From 76957cb3d621bf664311908e5962e151c633c285 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 1 Mar 2008 12:11:40 +0100 Subject: ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1 The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But currently 4k/2k is configured. This patch fixes this issue. Thanks to Thomas Kindler for pointing this out. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 5ef1005..599f5ce 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -975,9 +975,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set transmit enable & receive enable */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); - /* set receive fifo to 4k and tx fifo to 2k */ mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; + + /* set rx-/tx-fifo size */ + mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; /* set speed */ if (speed == _1000BASET) { -- cgit v1.1