From d8bd643141af4710d7f1b69bbab6b760de0af0a1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 27 Mar 2008 08:47:26 +0100 Subject: ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clear Signed-off-by: Stefan Roese --- cpu/ppc4xx/interrupts.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 698bcb5..8620e2b 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -218,15 +218,16 @@ static void uic_interrupt(u32 uic_base, int vec_base) } else { set_dcr(uic_base + UIC_ER, get_dcr(uic_base + UIC_ER) & - ~(0x80000000 >> vec)); + ~(0x80000000 >> (vec & 0x1f))); printf("Masking bogus interrupt vector %d" " (UIC_BASE=0x%x)\n", vec, uic_base); } /* - * After servicing the interrupt, we have to remove the status indicator. + * After servicing the interrupt, we have to remove the + * status indicator */ - set_dcr(uic_base + UIC_SR, (0x80000000 >> vec)); + set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f))); } /* -- cgit v1.1 From 4c9e855734c523900322a7c3cdd9099b4f51b51d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 Mar 2008 16:20:49 +0100 Subject: ppc4xx: Add AMCC Glacier 406GT eval board support This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index d990250..4541a14 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -275,6 +275,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; + u32 eth_cfg = 0; out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -308,6 +309,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) hw_p->print_speed = 1; /* print speed message again next time */ #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ + mfsdr(SDR0_ETH_CFG, eth_cfg); + eth_cfg &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, eth_cfg); +#endif + return; } @@ -494,11 +502,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) u32 zmiifer; /* ZMII0_FER reg. */ u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ + int mode; zmiifer = 0; rmiifer = 0; rmiifer1 = 0; +#if defined(CONFIG_460EX) + mode = 9; +#else + mode = 10; +#endif + /* TODO: * NOTE: 460GT has 2 RGMII bridge cores: * emac0 ------ RGMII0_BASE @@ -520,7 +535,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) * Right now only 2*RGMII is supported. Please extend when needed. * sr - 2008-02-19 */ - switch (9) { + switch (mode) { case 1: /* 1 MII - 460EX */ /* GMC0 EMAC4_0, ZMII Bridge */ @@ -836,10 +851,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = CONFIG_PHY1_ADDR; break; #endif -#if defined (CONFIG_440GX) +#if defined (CONFIG_PHY2_ADDR) case 2: reg = CONFIG_PHY2_ADDR; break; +#endif +#if defined (CONFIG_PHY3_ADDR) case 3: reg = CONFIG_PHY3_ADDR; break; @@ -1131,7 +1148,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx); + mtdcr (malrxctp8r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); #else @@ -1160,6 +1177,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ +#if defined (CONFIG_460GT) + case 2: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (malrxctp16r, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); + break; + case 3: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp3r, hw_p->tx_phys); + mtdcr (malrxctp24r, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); + break; +#endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ @@ -1866,14 +1903,22 @@ int ppc_4xx_eth_initialize (bd_t * bis) case 2: memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], bis->bi_enet2addr, 6); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x300; +#else hw_addr[eth_num] = 0x400; +#endif break; #endif #ifdef CONFIG_HAS_ETH3 case 3: memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], bis->bi_enet3addr, 6); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x400; +#else hw_addr[eth_num] = 0x600; +#endif break; #endif } -- cgit v1.1 From 9ad31989de12ce5c67b07c4867ead47465655c4b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 Mar 2008 16:35:12 +0100 Subject: ppc4xx: Fix compilation warning in 4xx_enet.c Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 4541a14..21ba922 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -274,8 +274,7 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; - uint32_t failsafe = 10000; - u32 eth_cfg = 0; + u32 val = 10000; out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -291,8 +290,8 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) /* wait for reset */ while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { udelay (1000); /* Delay 1 MS so as not to hammer the register */ - failsafe--; - if (failsafe == 0) + val--; + if (val == 0) break; } @@ -311,9 +310,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - eth_cfg &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); - mtsdr(SDR0_ETH_CFG, eth_cfg); + mfsdr(SDR0_ETH_CFG, val); + val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, val); #endif return; -- cgit v1.1 From f66e2c8b25c04b79e5fb385bc8989c2de7f63991 Mon Sep 17 00:00:00 2001 From: Mike Nuss Date: Wed, 20 Feb 2008 11:54:20 -0500 Subject: ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after startup to change the speed of the clocks. This patch adds the option CFG_PLL_RECONFIG. If this option is set to 667, the CPU initialization code will reconfigure the PLL to run the system with a CPU frequency of 667MHz and PLB frequency of 166MHz, without the need for an external EEPROM. Signed-off-by: Mike Nuss Acked-by: Stefan Roese --- cpu/ppc4xx/cpu_init.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 5d15e2f..b35f1f0 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -99,10 +99,107 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif /* CFG_INIT_DCACHE_CS */ +#ifndef CFG_PLL_RECONFIG +#define CFG_PLL_RECONFIG 0 +#endif + +void reconfigure_pll(u32 new_cpu_freq) +{ +#if defined(CONFIG_440EPX) + int reset_needed = 0; + u32 reg, temp; + u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ + fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ + fbdv, target_fbdv, lfbdv, target_lfbdv, + perdv0, target_perdv0, /* CLK_PERD */ + spcid0, target_spcid0; /* CLK_SPCID */ + + /* Reconfigure clocks if necessary. + * See PPC440EPx User's Manual, sections 8.2 and 14 */ + if (new_cpu_freq == 667) { + target_prbdv0 = 2; + target_fwdva = 2; + target_fwdvb = 4; + target_fbdv = 20; + target_lfbdv = 1; + target_perdv0 = 4; + target_spcid0 = 4; + + mfcpr(clk_primbd, reg); + temp = (reg & PRBDV_MASK) >> 24; + prbdv0 = temp ? temp : 8; + if (prbdv0 != target_prbdv0) { + reg &= ~PRBDV_MASK; + reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); + mtcpr(clk_primbd, reg); + reset_needed = 1; + } + + mfcpr(clk_plld, reg); + + temp = (reg & PLLD_FWDVA_MASK) >> 16; + fwdva = temp ? temp : 16; + + temp = (reg & PLLD_FWDVB_MASK) >> 8; + fwdvb = temp ? temp : 8; + + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + + if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { + reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | + PLLD_FBDV_MASK | PLLD_LFBDV_MASK); + reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | + ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | + ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | + (target_lfbdv == 64 ? 0 : target_lfbdv); + mtcpr(clk_plld, reg); + reset_needed = 1; + } + + mfcpr(clk_perd, reg); + perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; + if (perdv0 != target_perdv0) { + reg &= ~CPR0_PERD_PERDV0_MASK; + reg |= (target_perdv0 << 24); + mtcpr(clk_perd, reg); + reset_needed = 1; + } + + mfcpr(clk_spcid, reg); + temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; + spcid0 = temp ? temp : 4; + if (spcid0 != target_spcid0) { + reg &= ~CPR0_SPCID_SPCIDV0_MASK; + reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); + mtcpr(clk_spcid, reg); + reset_needed = 1; + } + + /* Set reload inhibit so configuration will persist across + * processor resets */ + mfcpr(clk_icfg, reg); + reg &= ~CPR0_ICFG_RLI_MASK; + reg |= 1 << 31; + mtcpr(clk_icfg, reg); + } + + /* Reset processor if configuration changed */ + if (reset_needed) { + __asm__ __volatile__ ("sync; isync"); + mtspr(dbcr0, 0x20000000); + } +#endif +} + /* * Breath some life into the CPU... * - * Set up the memory map, + * Reconfigure PLL if necessary, + * set up the memory map, * initialize a bunch of registers */ void @@ -111,6 +208,7 @@ cpu_init_f (void) #if defined(CONFIG_WATCHDOG) unsigned long val; #endif + reconfigure_pll(CFG_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) /* -- cgit v1.1 From f766cdf89b3a2a7634b8c5869f606150e332036c Mon Sep 17 00:00:00 2001 From: Markus Brunner Date: Thu, 27 Mar 2008 10:46:25 +0100 Subject: ppc4xx: PPC405EP Set EMAC noise filter bits This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359 which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set. Signed-off-by: Markus Brunner Signed-off-by: Stefan Roese --- cpu/ppc4xx/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index b35f1f0..42eabfe 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -233,6 +233,7 @@ cpu_init_f (void) #if defined (CFG_GPIO0_TCR) out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ #endif +#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */ #if defined (CONFIG_405EP) /* @@ -245,7 +246,6 @@ cpu_init_f (void) */ mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ -#endif /* CONFIG_405EP */ #if defined(CFG_4xx_GPIO_TABLE) gpio_set_chip_configuration(); -- cgit v1.1 From eb14ebe813a0cb5d47905228da446a5ad692473b Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sun, 30 Mar 2008 20:33:04 -0500 Subject: ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup Signed-off-by: Larry Johnson --- cpu/ppc4xx/denali_spd_ddr2.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 60f89c9..e20c9eb 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1093,10 +1093,10 @@ long int initdram(int board_type) program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - /*------------------------------------------------------------------ + /* * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia - * board SDRAM, but may be overly concervate. - *-----------------------------------------------------------------*/ + * board SDRAM, but may be overly conservative. + */ mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | DDR0_07_TFAW_ENCODE(13) | DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | @@ -1181,26 +1181,29 @@ long int initdram(int board_type) denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE); + /* + * Map the first 1 MiB of memory in the TLB, and perform the data eye + * search. + */ + program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); denali_sdram_register_dump(); - remove_tlb(CFG_SDRAM_BASE, dram_size); + remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE); #endif #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) program_tlb(0, CFG_SDRAM_BASE, dram_size, 0); sync(); - eieio(); /* Zero the memory */ debug("Zeroing SDRAM..."); - dcbz_area(CFG_SDRAM_BASE, dram_size); +#if defined(CFG_MEM_TOP_HIDE) + dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE); +#else +#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file +#endif dflush(); debug("Completed\n"); sync(); - eieio(); remove_tlb(CFG_SDRAM_BASE, dram_size); #if defined(CONFIG_DDR_ECC) @@ -1211,7 +1214,6 @@ long int initdram(int board_type) u32 val; sync(); - eieio(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); @@ -1229,7 +1231,6 @@ long int initdram(int board_type) print_mcsr(); #endif sync(); - eieio(); } #endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ -- cgit v1.1 From e54ec0f016803e4d9524ff71f7971bda0c51b287 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 3 Apr 2008 14:50:34 +0200 Subject: ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3 This patch fixes a problem with the RGMII setup of the 460GT. The 460GT has 2 RGMII instances and we need to configure the 2nd RGMII instance for the EMAC2+3 channels. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 21ba922..007cb4f 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -717,6 +717,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #ifdef CONFIG_4xx_DCACHE static u32 last_used_ea = 0; #endif +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + int rgmii_channel; +#endif EMAC_4XX_HW_PST hw_p = dev->priv; @@ -1022,12 +1027,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) + if (devnum >= 2) + rgmii_channel = devnum - 2; + else + rgmii_channel = devnum; + if (speed == 1000) - reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); + reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); else if (speed == 100) - reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); + reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); else if (speed == 10) - reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); + reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); else { printf("Error in RGMII Speed\n"); return -1; -- cgit v1.1