From 5c5128b60555aa6a793eac9e507d5c984bd5f3ec Mon Sep 17 00:00:00 2001 From: Lily Zhang Date: Fri, 25 Dec 2009 16:21:56 +0800 Subject: ENGR00119591 Fix SPI-NOR reset issue Add the workaround for ENGcm09397: reconfigure eCSPI SS signal as GPIO before reset. Signed-off-by: Lily Zhang --- cpu/arm_cortexa8/mx51/interrupts.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c index 9758bef..5212a42 100644 --- a/cpu/arm_cortexa8/mx51/interrupts.c +++ b/cpu/arm_cortexa8/mx51/interrupts.c @@ -24,6 +24,7 @@ */ #include +#include #include /* nothing really to do with interrupts, just starts up a counter. */ @@ -34,5 +35,13 @@ int interrupt_init(void) void reset_cpu(ulong addr) { + /* workaround for ENGcm09397 - Fix SPI NOR reset issue*/ + /* de-select SS0 of instance: eCSPI1 */ + writel(0x3, IOMUXC_BASE_ADDR + 0x218); + writel(0x85, IOMUXC_BASE_ADDR + 0x608); + /* de-select SS1 of instance: ecspi1 */ + writel(0x3, IOMUXC_BASE_ADDR + 0x21C); + writel(0x85, IOMUXC_BASE_ADDR + 0x60C); + __REG16(WDOG1_BASE_ADDR) = 4; } -- cgit v1.1