From 4a065abf926f128beb36d93449defa0d690e7fef Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 18 Sep 2008 19:04:26 +0900 Subject: sh: Add support watchdog for SH4A core Add support watchdog for SH4A core (SH7763, SH7780 and SH7785). And fix some compile warning. Signed-off-by: Nobuhiro Iwamatsu --- cpu/sh4/watchdog.c | 53 +++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 16 deletions(-) (limited to 'cpu') diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c index 346e217..f692429 100644 --- a/cpu/sh4/watchdog.c +++ b/cpu/sh4/watchdog.c @@ -17,34 +17,55 @@ #include #include +#include #define WDT_BASE WTCNT -static unsigned char cnt_read (void){ - return *((volatile unsigned char *)(WDT_BASE + 0x00)); +#define WDT_WD (1 << 6) +#define WDT_RST_P (0) +#define WDT_RST_M (1 << 5) +#define WDT_ENABLE (1 << 7) + +#if defined(CONFIG_WATCHDOG) +static unsigned char csr_read(void) +{ + return inb(WDT_BASE + 0x04); } -static unsigned char csr_read (void){ - return *((volatile unsigned char *)(WDT_BASE + 0x04)); +static void cnt_write(unsigned char value) +{ + outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00); } -static void cnt_write (unsigned char value){ - while (csr_read() & (1 << 5)) { - /* delay */ - } - *((volatile unsigned short *)(WDT_BASE + 0x00)) - = ((unsigned short) value) | 0x5A00; +static void csr_write(unsigned char value) +{ + outl((unsigned short)value | 0xA500, WDT_BASE + 0x04); } -static void csr_write (unsigned char value){ - *((volatile unsigned short *)(WDT_BASE + 0x04)) - = ((unsigned short) value) | 0xA500; +void watchdog_reset(void) +{ + outl(0x55000000, WDT_BASE + 0x08); } +int watchdog_init(void) +{ + /* Set overflow time*/ + cnt_write(0); + /* Power on reset */ + csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE); + + return 0; +} -int watchdog_init (void){ return 0; } +int watchdog_disable(void) +{ + csr_write(csr_read() & ~WDT_ENABLE); + return 0; +} +#endif -void reset_cpu (unsigned long ignored) +void reset_cpu(unsigned long ignored) { - while(1); + while (1) + ; } -- cgit v1.1 From 5fdc215f0b351b0c36cc3f8a0fa5850f24454bed Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 22 Sep 2008 22:23:06 +0200 Subject: Fix DPRAM memory leak when CFG_ALLOC_DPRAM is defined, which eventually leads to a machine check. This change assures that DPRAM is allocated only once in that case. Signed-off-by: Gary Jennejohn Signed-off-by: Wolfgang Denk --- cpu/mpc8xx/scc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 09a3db1..09a6348 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -215,12 +215,14 @@ static int scc_init (struct eth_device *dev, bd_t * bis) rxIdx = 0; txIdx = 0; + if (!rtx) { #ifdef CFG_ALLOC_DPRAM - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + - dpram_alloc_align (sizeof (RTXBD), 8)); + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + + dpram_alloc_align (sizeof (RTXBD), 8)); #else - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); -#endif /* 0 */ + rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); +#endif + } #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) /* Configure port A pins for Txd and Rxd. -- cgit v1.1 From d26154c9a692586b66eb6d1f8e1b67c75e40ea70 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 11 Sep 2008 21:35:36 +0400 Subject: mpc83xx: spd_sdram: fix ddr sdram base address assignment bug The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 76f2474..f4a0e90 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -274,7 +274,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + ecm->bar = CFG_DDR_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); -- cgit v1.1 From bac6a1d1fa1cd80aa57881fa9c2152b853cd0ed4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 7 Oct 2008 10:28:46 -0500 Subject: 85xx: Remove setting of *cache-line-size in device trees ePAPR says if the *cache-block-size is the same as *cache-line-size than we don't need the *cache-line-size property. Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bc1550d..037a60f 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -152,7 +152,6 @@ static inline void ft_fixup_l2cache(void *blob) } fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); - fdt_setprop_cell(blob, off, "cache-line-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); @@ -181,7 +180,6 @@ static inline void ft_fixup_cache(void *blob) dnum_sets = dsize / (dline_size * dnum_ways); fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); - fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); @@ -192,7 +190,6 @@ static inline void ft_fixup_cache(void *blob) inum_sets = isize / (iline_size * inum_ways); fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); - fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); fdt_setprop_cell(blob, off, "i-cache-size", isize); fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); -- cgit v1.1 From c0391111c33c22fabeddf8f4ca801ec7645b4f5c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Sat, 27 Sep 2008 14:40:57 +0800 Subject: Fix the incorrect DDR clk freq reporting on 8536DS On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin --- cpu/mpc85xx/cpu.c | 3 ++- cpu/mpc85xx/speed.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 67e81c0..f15b0a8 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -85,7 +85,8 @@ int checkcpu (void) struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 1cda1e3..485ba20 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_DDR_CLK_FREQ { - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } -- cgit v1.1 From f8a00dea841d5d75de1f8e8107e90ee1beeddf5f Mon Sep 17 00:00:00 2001 From: Adam Graham Date: Mon, 6 Oct 2008 10:16:13 -0700 Subject: ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT. Signed-off-by: Adam Graham Signed-off-by: Victor Gallardo Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 83b9883..47ab39b 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void) #endif } +/* + * Reset and relock memory DLL after SDRAM_CLKTR change + */ +static inline void relock_memory_DLL(void) +{ + u32 reg; + + mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE); + + do { + mfsdram(SDRAM_MCSTAT, reg); + } while (!(reg & SDRAM_MCSTAT_MIC_COMP)); + + mfsdram(SDRAM_MCOPT2, reg); + mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE); +} + static int ecc_check_status_reg(void) { u32 ecc_status; @@ -981,6 +998,8 @@ u32 DQS_autocalibration(void) mtsdram(SDRAM_CLKTR, clkp << 30); + relock_memory_DLL(); + putc('\b'); putc(slash[loopi++ % 8]); @@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void) mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30); + relock_memory_DLL(); + mfsdram(SDRAM_RQDC, rqdc_reg); rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); mtsdram(SDRAM_RQDC, rqdc_reg | -- cgit v1.1 From 1ed7a7f0f571b13d46530f8f8b9aff3957f15a96 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 25 Sep 2008 20:54:37 +0200 Subject: i.MX31: switch to CFG_HZ=1000 Switch to the standard CFG_HZ=1000 value, while at it, minor white-space cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads, provides 2% or 0.4% precision depending on the CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s boot-delay. Signed-off-by: Guennadi Liakhovetski --- cpu/arm1136/mx31/interrupts.c | 79 +++++++++++++++++++++++++++---------------- 1 file changed, 50 insertions(+), 29 deletions(-) (limited to 'cpu') diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c index 6e08c71..cd57071 100644 --- a/cpu/arm1136/mx31/interrupts.c +++ b/cpu/arm1136/mx31/interrupts.c @@ -27,30 +27,49 @@ #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ /* General purpose timers registers */ -#define GPTCR __REG(TIMER_BASE) /* Control register */ -#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ -#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ -#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ +#define GPTCR __REG(TIMER_BASE) /* Control register */ +#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ +#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ +#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ /* General purpose timers bitfields */ -#define GPTCR_SWR (1<<15) /* Software reset */ -#define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ -#define GPTCR_TEN (1) /* Timer enable */ +#define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_FRR (1 << 9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_TEN 1 /* Timer enable */ + +/* "time" is measured in 1 / CFG_HZ seconds, "tick" is internal timer period */ +#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ +#define TICK_TO_TIME(t) ((t) * CFG_HZ / CONFIG_MX31_CLK32) +#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CFG_HZ) +#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \ + 999999) / 1000000) +#else +/* ~2% error */ +#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CFG_HZ / 2) / CFG_HZ) +#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) +#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME) +#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME) +#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK) +#endif static ulong timestamp; static ulong lastinc; /* nothing really to do with interrupts, just starts up a counter. */ +/* The 32768Hz 32-bit timer overruns in 131072 seconds */ int interrupt_init (void) { int i; /* setup GP Timer 1 */ GPTCR = GPTCR_SWR; - for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */ + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ GPTPR = 0; /* 32Khz */ - GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; return 0; } @@ -67,7 +86,7 @@ void reset_timer(void) reset_timer_masked(); } -ulong get_timer_masked (void) +unsigned long long get_ticks (void) { ulong now = GPTCNT; /* current tick value */ @@ -80,6 +99,17 @@ ulong get_timer_masked (void) return timestamp; } +ulong get_timer_masked (void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CFG_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return TICK_TO_TIME(get_ticks()); +} + ulong get_timer (ulong base) { return get_timer_masked () - base; @@ -87,29 +117,20 @@ ulong get_timer (ulong base) void set_timer (ulong t) { + timestamp = TIME_TO_TICK(t); } /* delay x useconds AND perserve advance timstamp value */ void udelay (unsigned long usec) { - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; + unsigned long long tmp; + ulong tmo; + + tmo = US_TO_TICK(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; } void reset_cpu (ulong addr) -- cgit v1.1 From dffd2446fb041f38ef034b0fcf41e51e5e489159 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Tue, 30 Sep 2008 10:55:57 +0200 Subject: 85xx: Using proper I2C source clock divider for MPC8544 Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 485ba20..70dfad0 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 3; - else gd->i2c1_clk = sys_info.freqSystemBus / 2; + else + gd->i2c1_clk = sys_info.freqSystemBus / 3; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; -- cgit v1.1 From 5c7cbcd34d0ee566875a4fd0f2a3e5a62bba921c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 19 Aug 2008 15:05:34 -0500 Subject: 86xx: remove redudant code with lib_ppc/interrupts.c For some reason we duplicated the majority of code in lib_ppc/interrupts.c Not know how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala --- cpu/mpc86xx/interrupts.c | 131 +++-------------------------------------------- 1 file changed, 7 insertions(+), 124 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index f16744b..fa2cfac 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -35,78 +35,23 @@ #include #include #include -#include -#include -unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ -unsigned long timestamp; - - -static __inline__ unsigned long get_msr(void) -{ - unsigned long msr; - - asm volatile ("mfmsr %0":"=r" (msr):); - - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - asm volatile ("mtmsr %0"::"r" (msr)); -} - -static __inline__ unsigned long get_dec(void) -{ - unsigned long val; - - asm volatile ("mfdec %0":"=r" (val):); - - return val; -} - -static __inline__ void set_dec(unsigned long val) -{ - if (val) - asm volatile ("mtdec %0"::"r" (val)); -} - -/* interrupt is not supported yet */ int interrupt_init_cpu(unsigned long *decrementer_count) { - return 0; -} - -int interrupt_init(void) -{ - int ret; - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_pic.gcr = MPC86xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); - immr->im_pic.gcr = MPC86xx_PICGCR_MODE; - - /* call cpu specific function from $(CPU)/interrupts.c */ - ret = interrupt_init_cpu(&decrementer_count); + volatile ccsr_pic_t *pic = &immr->im_pic; - if (ret) - return ret; + pic->gcr = MPC86xx_PICGCR_RST; + while (pic->gcr & MPC86xx_PICGCR_RST) + ; + pic->gcr = MPC86xx_PICGCR_MODE; - decrementer_count = get_tbclk() / CFG_HZ; + *decrementer_count = get_tbclk() / CFG_HZ; debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n", (get_tbclk() / 1000000), - decrementer_count); - - set_dec(decrementer_count); - - set_msr(get_msr() | MSR_EE); - - debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", - get_msr(), - get_dec()); + *decrementer_count); #ifdef CONFIG_INTERRUPTS - volatile ccsr_pic_t *pic = &immr->im_pic; pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1); @@ -132,25 +77,6 @@ int interrupt_init(void) return 0; } -void enable_interrupts(void) -{ - set_msr(get_msr() | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int disable_interrupts(void) -{ - ulong msr = get_msr(); - - set_msr(msr & ~MSR_EE); - return (msr & MSR_EE) != 0; -} - -void increment_timestamp(void) -{ - timestamp++; -} - /* * timer_interrupt - gets called when the decrementer overflows, * with interrupts disabled. @@ -161,50 +87,9 @@ void timer_interrupt_cpu(struct pt_regs *regs) /* nothing to do here */ } -void timer_interrupt(struct pt_regs *regs) -{ - /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu(regs); - - timestamp++; - - /* Restore Decrementer Count */ - set_dec(decrementer_count); - -#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) - if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) - WATCHDOG_RESET(); -#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ - -#ifdef CONFIG_STATUS_LED - status_led_tick(timestamp); -#endif /* CONFIG_STATUS_LED */ - -#ifdef CONFIG_SHOW_ACTIVITY - board_show_activity(timestamp); -#endif /* CONFIG_SHOW_ACTIVITY */ - -} - -void reset_timer(void) -{ - timestamp = 0; -} - -ulong get_timer(ulong base) -{ - return timestamp - base; -} - -void set_timer(ulong t) -{ - timestamp = t; -} - /* * Install and free a interrupt handler. Not implemented yet. */ - void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { } @@ -218,8 +103,6 @@ void irq_free_handler(int vec) */ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - printf("\nInterrupt-unsupported:\n"); - return 0; } -- cgit v1.1 From 392438406041415fe64ab8748ec5ab5ad01d1cf7 Mon Sep 17 00:00:00 2001 From: Nick Spence Date: Thu, 28 Aug 2008 14:09:15 -0700 Subject: mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence --- cpu/mpc86xx/start.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 03f2128..90a1b83 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -895,9 +895,9 @@ lock_ram_in_cache: */ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ + li r4, ((CFG_INIT_RAM_END & ~31) + \ (CFG_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r2 + mtctr r4 1: dcbz r0, r3 addi r3, r3, 32 @@ -930,9 +930,9 @@ unlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ + li r4, ((CFG_INIT_RAM_END & ~31) + \ (CFG_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r2 + mtctr r4 1: icbi r0, r3 addi r3, r3, 32 bdnz 1b -- cgit v1.1 From 9724555755a6f1066636481b41f7094e0ce93a69 Mon Sep 17 00:00:00 2001 From: Selvamuthukumar Date: Thu, 9 Oct 2008 10:29:14 +0530 Subject: mpc83xx: wait till UPM completes the write to array Reference manual states that MxMR[MAD] increment is the indication of write to UPM array is complete. Honour that. Also, make the dummy write explicit. also fix the comment. Signed-off-by: Selvamuthukumar Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 5862acd..99ab216 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -124,8 +124,8 @@ int checkcpu(void) * The 'dummy' variable is used to increment the MAD. 'dummy' is * supposed to be a pointer to the memory of the device being * programmed by the UPM. The data in the MDR is written into - * memory and the MAD is incremented every time there's a read - * from 'dummy'. Unfortunately, the current prototype for this + * memory and the MAD is incremented every time there's a write + * to 'dummy'. Unfortunately, the current prototype for this * function doesn't allow for passing the address of this * device, and changing the prototype will break a number lots * of other code, so we need to use a round-about way of finding @@ -174,8 +174,9 @@ void upmconfig (uint upm, uint *table, uint size) for (i = 0; i < size; i++) { lbus->mdr = table[i]; __asm__ __volatile__ ("sync"); - *dummy; /* Write the value to memory and increment MAD */ + *dummy = 0; /* Write the value to memory and increment MAD */ __asm__ __volatile__ ("sync"); + while(((*mxmr & 0x3f) != ((i + 1) & 0x3f))); } /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ -- cgit v1.1 From 42653b826adb319a1df06e24ef26096b2a5d9d2a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Oct 2008 21:58:49 -0500 Subject: Revert "85xx: Using proper I2C source clock divider for MPC8544" This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. The fix introduced by this patch is not correct. The problem is that the documentation is not correct for the MPC8544 with regards to which bit in PORDEVSR2 is for the SEC_CFG. Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 70dfad0..485ba20 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 2; - else gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; -- cgit v1.1 From bf29e0ea0af03d593c64614136acc723a7a022a2 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Fri, 17 Oct 2008 12:54:18 +0200 Subject: ppc4xx: PPC44x MQ initialization Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f1d7684..995d5fe 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated, /* * Set optimal value for Memory Queue HB/LL Configuration registers */ - mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | - SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); - mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | - SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) | + SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE | + SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL); + mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) | + SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE | + SDRAM_CONF1LL_RPLM); mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); #endif } -- cgit v1.1 From fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d Mon Sep 17 00:00:00 2001 From: Lepcha Suchit Date: Thu, 16 Oct 2008 13:38:00 -0500 Subject: 83xx NAND boot: wait for LTESR[CC] At least some revisions of the 8313, and possibly other chips, do not wait for all pages of the initial 4K NAND region to be loaded before beginning execution; thus, we wait for it before branching out of the first NAND page. This fixes warm reset problems when booting from NAND on 8313erdb. Signed-off-by: Scott Wood Acked-by: Kim Phillips --- cpu/mpc83xx/start.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 14bfbda..6ff6682 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -167,6 +167,18 @@ boot_warm: /* time t 5 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ +#ifdef CONFIG_NAND_SPL + /* The FCM begins execution after only the first page + * is loaded. Wait for the rest before branching + * to another flash page. + */ + addi r7, r3, 0x50b0 +1: dcbi 0, r7 + lwz r6, 0(r7) + andi. r6, r6, 1 + beq 1b +#endif + bl init_e300_core #ifdef CFG_FLASHBOOT -- cgit v1.1 From c68a05feeb88de9fcf158e67ff6423c4cc988f88 Mon Sep 17 00:00:00 2001 From: richardretanubun Date: Mon, 29 Sep 2008 18:28:23 -0400 Subject: Adds two more ethernet interface to 83xx Added as a convenience for other platforms that uses MPC8360 (has 8 UCC). Six eth interface is chosen because the platform I am using combines UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth. Signed-off-by: Richard Retanubun Signed-off-by: Ben Warren --- cpu/mpc83xx/fdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 39bd9dc..3e3e1c8 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -52,7 +52,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_crypto_node(blob, 0x0204); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ + defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) fdt_fixup_ethernet(blob); #endif -- cgit v1.1 From 799b784aa00cb03a352847ab9f9acdde79b72d21 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:34:45 +0200 Subject: i2c: add CONFIG_I2C_MULTI_BUS for soft_i2c and mpc8260 i2c driver. Signed-off-by: Heiko Schocher --- cpu/mpc8260/i2c.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index c3af7b6..335177f 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -36,6 +36,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_I2C_MULTI_BUS) +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; +#endif /* CONFIG_I2C_MULTI_BUS */ + /* uSec to wait between polls of the i2c */ #define DELAY_US 100 /* uSec to wait for the CPM to start processing the buffer */ @@ -765,4 +769,36 @@ i2c_reg_write(uchar chip, uchar reg, uchar val) i2c_write(chip, reg, 1, &val, 1); } +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Functions for multiple I2C bus handling + */ +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= CFG_MAX_I2C_BUS) + return -1; + i2c_bus_num = bus; + + return 0; +} +/* TODO: add 100/400k switching */ +unsigned int i2c_get_bus_speed(void) +{ + return CFG_I2C_SPEED; +} + +int i2c_set_bus_speed(unsigned int speed) +{ + if (speed != CFG_I2C_SPEED) + return -1; + + return 0; +} + +#endif /* CONFIG_I2C_MULTI_BUS */ #endif /* CONFIG_HARD_I2C */ -- cgit v1.1 From 67b23a322848d828a5e45c0567b72762bfde7abf Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:39:47 +0200 Subject: I2C: adding new "i2c bus" Command to the I2C Subsystem. With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by: Heiko Schocher --- cpu/mpc8260/i2c.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index 335177f..a96fbf8 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -780,10 +780,23 @@ unsigned int i2c_get_bus_num(void) int i2c_set_bus_num(unsigned int bus) { +#if defined(CONFIG_I2C_MUX) + if (bus < CFG_MAX_I2C_BUS) { + i2c_bus_num = bus; + } else { + int ret; + + ret = i2x_mux_select_mux(bus); + if (ret == 0) + i2c_bus_num = bus; + else + return ret; + } +#else if (bus >= CFG_MAX_I2C_BUS) return -1; i2c_bus_num = bus; - +#endif return 0; } /* TODO: add 100/400k switching */ -- cgit v1.1 From 71edc271816ec82cf0550dd6980be2da3cc2ad9e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 13 Oct 2008 14:12:55 -0500 Subject: 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx version Signed-off-by: Kumar Gala --- cpu/74xx_7xx/cache.S | 10 +++++----- cpu/mpc86xx/cache.S | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index eac4544..62a6683 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -52,7 +52,7 @@ _GLOBAL(invalidate_l1_data_cache) /* * Flush data cache. */ -_GLOBAL(flush_data_cache) +_GLOBAL(flush_dcache) lis r3,0 lis r5,CACHE_LINE_SIZE flush: @@ -303,12 +303,12 @@ _GLOBAL(dcache_enable) /* * Disable data cache(s) - L1 and optionally L2 - * Calls flush_data_cache and l2cache_disable_no_flush. + * Calls flush_dcache and l2cache_disable_no_flush. * LR saved in r4 */ _GLOBAL(dcache_disable) mflr r4 /* save link register */ - bl flush_data_cache /* uses r3 and r5 */ + bl flush_dcache /* uses r3 and r5 */ sync mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK @@ -389,11 +389,11 @@ _GLOBAL(l2cache_enable) /* * Disable L2 cache - * Calls flush_data_cache. LR is saved in r4 + * Calls flush_dcache. LR is saved in r4 */ _GLOBAL(l2cache_disable) mflr r4 /* save link register */ - bl flush_data_cache /* uses r3 and r5 */ + bl flush_dcache /* uses r3 and r5 */ sync mtlr r4 /* restore link register */ l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index 80ff688..dd38806 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -53,7 +53,7 @@ _GLOBAL(invalidate_l1_data_cache) /* * Flush data cache. */ -_GLOBAL(flush_data_cache) +_GLOBAL(flush_dcache) lis r3,0 lis r5,CACHE_LINE_SIZE flush: @@ -290,12 +290,12 @@ _GLOBAL(dcache_enable) /* * Disable data cache(s) - L1 and optionally L2 - * Calls flush_data_cache and l2cache_disable_no_flush. + * Calls flush_dcache and l2cache_disable_no_flush. * LR saved in r4 */ _GLOBAL(dcache_disable) mflr r4 /* save link register */ - bl flush_data_cache /* uses r3 and r5 */ + bl flush_dcache /* uses r3 and r5 */ sync mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK @@ -363,11 +363,11 @@ _GLOBAL(l2cache_enable) /* * Disable L2 cache - * Calls flush_data_cache. LR is saved in r4 + * Calls flush_dcache. LR is saved in r4 */ _GLOBAL(l2cache_disable) mflr r4 /* save link register */ - bl flush_data_cache /* uses r3 and r5 */ + bl flush_dcache /* uses r3 and r5 */ sync mtlr r4 /* restore link register */ l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ -- cgit v1.1 From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/74xx_7xx/cache.S | 4 +- cpu/74xx_7xx/cpu.c | 20 +- cpu/74xx_7xx/interrupts.c | 2 +- cpu/74xx_7xx/kgdb.S | 10 +- cpu/74xx_7xx/speed.c | 4 +- cpu/74xx_7xx/start.S | 176 ++++++------- cpu/arm1136/cpu.c | 2 +- cpu/arm1136/mx31/interrupts.c | 10 +- cpu/arm1136/mx31/serial.c | 12 +- cpu/arm1136/omap24xx/interrupts.c | 18 +- cpu/arm1136/start.S | 16 +- cpu/arm1176/s3c64xx/interrupts.c | 4 +- cpu/arm1176/start.S | 26 +- cpu/arm720t/cpu.c | 2 +- cpu/arm720t/interrupts.c | 18 +- cpu/arm720t/lpc2292/flash.c | 4 +- cpu/arm720t/serial.c | 2 +- cpu/arm720t/serial_netarm.c | 2 +- cpu/arm720t/start.S | 12 +- cpu/arm920t/at91rm9200/i2c.c | 6 +- cpu/arm920t/at91rm9200/interrupts.c | 8 +- cpu/arm920t/at91rm9200/lowlevel_init.S | 2 +- cpu/arm920t/at91rm9200/spi.c | 4 +- cpu/arm920t/at91rm9200/usb.c | 4 +- cpu/arm920t/cpu.c | 2 +- cpu/arm920t/imx/interrupts.c | 2 +- cpu/arm920t/interrupts.c | 2 +- cpu/arm920t/s3c24x0/i2c.c | 8 +- cpu/arm920t/s3c24x0/interrupts.c | 2 +- cpu/arm920t/s3c24x0/usb.c | 4 +- cpu/arm920t/start.S | 12 +- cpu/arm925t/cpu.c | 2 +- cpu/arm925t/interrupts.c | 18 +- cpu/arm925t/start.S | 12 +- cpu/arm926ejs/at91/spi.c | 8 +- cpu/arm926ejs/at91/timer.c | 2 +- cpu/arm926ejs/at91/usb.c | 4 +- cpu/arm926ejs/cpu.c | 2 +- cpu/arm926ejs/davinci/i2c.c | 2 +- cpu/arm926ejs/davinci/nand.c | 48 ++-- cpu/arm926ejs/davinci/timer.c | 8 +- cpu/arm926ejs/omap/timer.c | 18 +- cpu/arm926ejs/start.S | 12 +- cpu/arm926ejs/versatile/timer.c | 20 +- cpu/arm946es/cpu.c | 2 +- cpu/arm946es/interrupts.c | 6 +- cpu/arm946es/start.S | 12 +- cpu/arm_intcm/cpu.c | 2 +- cpu/arm_intcm/start.S | 12 +- cpu/at32ap/at32ap700x/clk.c | 24 +- cpu/at32ap/at32ap700x/gpio.c | 4 +- cpu/at32ap/cache.c | 8 +- cpu/at32ap/cpu.c | 10 +- cpu/at32ap/hsdramc.c | 4 +- cpu/at32ap/interrupts.c | 4 +- cpu/at32ap/start.S | 2 +- cpu/blackfin/interrupts.c | 2 +- cpu/blackfin/start.S | 8 +- cpu/blackfin/traps.c | 4 +- cpu/i386/interrupts.c | 2 +- cpu/i386/sc520.c | 12 +- cpu/i386/sc520_asm.S | 12 +- cpu/i386/start.S | 4 +- cpu/i386/timer.c | 4 +- cpu/ixp/cpu.c | 6 +- cpu/ixp/interrupts.c | 4 +- cpu/ixp/npe/include/npe.h | 6 +- cpu/ixp/npe/npe.c | 12 +- cpu/ixp/serial.c | 12 +- cpu/ixp/start.S | 22 +- cpu/ixp/timer.c | 2 +- cpu/leon2/interrupts.c | 8 +- cpu/leon2/prom.c | 50 ++-- cpu/leon2/serial.c | 2 +- cpu/leon2/start.S | 36 +-- cpu/leon3/cpu_init.c | 20 +- cpu/leon3/interrupts.c | 8 +- cpu/leon3/prom.c | 52 ++-- cpu/leon3/serial.c | 2 +- cpu/leon3/start.S | 34 +-- cpu/lh7a40x/cpu.c | 2 +- cpu/lh7a40x/interrupts.c | 10 +- cpu/lh7a40x/start.S | 12 +- cpu/mcf5227x/cpu_init.c | 58 ++--- cpu/mcf5227x/interrupts.c | 8 +- cpu/mcf5227x/speed.c | 4 +- cpu/mcf5227x/start.S | 28 +-- cpu/mcf523x/cpu.c | 2 +- cpu/mcf523x/cpu_init.c | 72 +++--- cpu/mcf523x/interrupts.c | 8 +- cpu/mcf523x/speed.c | 2 +- cpu/mcf523x/start.S | 40 +-- cpu/mcf52x2/cpu.c | 14 +- cpu/mcf52x2/cpu_init.c | 356 +++++++++++++-------------- cpu/mcf52x2/interrupts.c | 14 +- cpu/mcf52x2/speed.c | 12 +- cpu/mcf52x2/start.S | 76 +++--- cpu/mcf532x/cpu.c | 2 +- cpu/mcf532x/cpu_init.c | 50 ++-- cpu/mcf532x/interrupts.c | 8 +- cpu/mcf532x/speed.c | 4 +- cpu/mcf532x/start.S | 38 +-- cpu/mcf5445x/cpu_init.c | 56 ++--- cpu/mcf5445x/dspi.c | 32 +-- cpu/mcf5445x/interrupts.c | 8 +- cpu/mcf5445x/pci.c | 62 ++--- cpu/mcf5445x/speed.c | 14 +- cpu/mcf5445x/start.S | 80 +++--- cpu/mcf547x_8x/cpu.c | 2 +- cpu/mcf547x_8x/cpu_init.c | 52 ++-- cpu/mcf547x_8x/interrupts.c | 8 +- cpu/mcf547x_8x/pci.c | 38 +-- cpu/mcf547x_8x/slicetimer.c | 18 +- cpu/mcf547x_8x/speed.c | 2 +- cpu/mcf547x_8x/start.S | 34 +-- cpu/microblaze/exception.c | 2 +- cpu/microblaze/interrupts.c | 22 +- cpu/microblaze/start.S | 14 +- cpu/microblaze/timer.c | 12 +- cpu/mips/au1x00_eth.c | 2 +- cpu/mips/au1x00_serial.c | 2 +- cpu/mips/cache.S | 16 +- cpu/mips/cpu.c | 2 +- cpu/mips/start.S | 12 +- cpu/mpc512x/cpu.c | 6 +- cpu/mpc512x/cpu_init.c | 10 +- cpu/mpc512x/i2c.c | 4 +- cpu/mpc512x/interrupts.c | 2 +- cpu/mpc512x/iopin.c | 2 +- cpu/mpc512x/serial.c | 18 +- cpu/mpc512x/speed.c | 4 +- cpu/mpc512x/start.S | 56 ++--- cpu/mpc5xx/cpu.c | 18 +- cpu/mpc5xx/cpu_init.c | 48 ++-- cpu/mpc5xx/interrupts.c | 12 +- cpu/mpc5xx/serial.c | 12 +- cpu/mpc5xx/speed.c | 4 +- cpu/mpc5xx/spi.c | 16 +- cpu/mpc5xx/start.S | 42 ++-- cpu/mpc5xxx/cpu.c | 2 +- cpu/mpc5xxx/cpu_init.c | 120 ++++----- cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S | 8 +- cpu/mpc5xxx/i2c.c | 6 +- cpu/mpc5xxx/interrupts.c | 2 +- cpu/mpc5xxx/pci_mpc5200.c | 10 +- cpu/mpc5xxx/serial.c | 4 +- cpu/mpc5xxx/speed.c | 8 +- cpu/mpc5xxx/start.S | 62 ++--- cpu/mpc5xxx/usb.c | 4 +- cpu/mpc8220/cpu.c | 2 +- cpu/mpc8220/cpu_init.c | 64 ++--- cpu/mpc8220/dramSetup.c | 14 +- cpu/mpc8220/interrupts.c | 2 +- cpu/mpc8220/pci.c | 4 +- cpu/mpc8220/speed.c | 14 +- cpu/mpc8220/start.S | 34 +-- cpu/mpc824x/cpu.c | 12 +- cpu/mpc824x/cpu_init.c | 234 +++++++++--------- cpu/mpc824x/drivers/epic/epic1.c | 4 +- cpu/mpc824x/drivers/i2c/i2c.c | 4 +- cpu/mpc824x/interrupts.c | 4 +- cpu/mpc824x/start.S | 90 +++---- cpu/mpc8260/commproc.c | 18 +- cpu/mpc8260/cpu.c | 20 +- cpu/mpc8260/cpu_init.c | 106 ++++---- cpu/mpc8260/ether_fcc.c | 24 +- cpu/mpc8260/ether_scc.c | 16 +- cpu/mpc8260/i2c.c | 36 +-- cpu/mpc8260/interrupts.c | 12 +- cpu/mpc8260/kgdb.S | 8 +- cpu/mpc8260/pci.c | 100 ++++---- cpu/mpc8260/serial_scc.c | 14 +- cpu/mpc8260/serial_smc.c | 14 +- cpu/mpc8260/speed.c | 4 +- cpu/mpc8260/spi.c | 20 +- cpu/mpc8260/start.S | 118 ++++----- cpu/mpc8260/traps.c | 4 +- cpu/mpc83xx/cpu.c | 16 +- cpu/mpc83xx/cpu_init.c | 202 +++++++-------- cpu/mpc83xx/ecc.c | 4 +- cpu/mpc83xx/fdt.c | 6 +- cpu/mpc83xx/interrupts.c | 4 +- cpu/mpc83xx/nand_init.c | 40 +-- cpu/mpc83xx/pci.c | 8 +- cpu/mpc83xx/qe_io.c | 2 +- cpu/mpc83xx/serdes.c | 2 +- cpu/mpc83xx/spd_sdram.c | 28 +-- cpu/mpc83xx/speed.c | 2 +- cpu/mpc83xx/start.S | 246 +++++++++--------- cpu/mpc83xx/traps.c | 4 +- cpu/mpc85xx/commproc.c | 16 +- cpu/mpc85xx/cpu.c | 18 +- cpu/mpc85xx/cpu_init.c | 88 +++---- cpu/mpc85xx/ddr-gen1.c | 4 +- cpu/mpc85xx/ddr-gen2.c | 2 +- cpu/mpc85xx/ddr-gen3.c | 4 +- cpu/mpc85xx/ether_fcc.c | 26 +- cpu/mpc85xx/fdt.c | 6 +- cpu/mpc85xx/interrupts.c | 4 +- cpu/mpc85xx/mp.c | 10 +- cpu/mpc85xx/mpc8536_serdes.c | 4 +- cpu/mpc85xx/pci.c | 62 ++--- cpu/mpc85xx/qe_io.c | 2 +- cpu/mpc85xx/serial_scc.c | 8 +- cpu/mpc85xx/speed.c | 6 +- cpu/mpc85xx/start.S | 48 ++-- cpu/mpc85xx/tlb.c | 2 +- cpu/mpc85xx/traps.c | 2 +- cpu/mpc86xx/cache.S | 4 +- cpu/mpc86xx/cpu.c | 30 +-- cpu/mpc86xx/cpu_init.c | 92 +++---- cpu/mpc86xx/ddr-8641.c | 4 +- cpu/mpc86xx/fdt.c | 4 +- cpu/mpc86xx/interrupts.c | 4 +- cpu/mpc86xx/speed.c | 2 +- cpu/mpc86xx/start.S | 100 ++++---- cpu/mpc8xx/commproc.c | 12 +- cpu/mpc8xx/cpu.c | 32 +-- cpu/mpc8xx/cpu_init.c | 126 +++++----- cpu/mpc8xx/fec.c | 40 +-- cpu/mpc8xx/i2c.c | 44 ++-- cpu/mpc8xx/interrupts.c | 16 +- cpu/mpc8xx/kgdb.S | 8 +- cpu/mpc8xx/lcd.c | 50 ++-- cpu/mpc8xx/scc.c | 8 +- cpu/mpc8xx/serial.c | 50 ++-- cpu/mpc8xx/speed.c | 28 +-- cpu/mpc8xx/spi.c | 40 +-- cpu/mpc8xx/start.S | 22 +- cpu/mpc8xx/upatch.c | 22 +- cpu/mpc8xx/video.c | 10 +- cpu/mpc8xxx/ddr/ddr.h | 14 +- cpu/nios/asmi.c | 6 +- cpu/nios/interrupts.c | 20 +- cpu/nios/serial.c | 8 +- cpu/nios/spi.c | 24 +- cpu/nios/start.S | 16 +- cpu/nios2/cpu.c | 8 +- cpu/nios2/epcs.c | 4 +- cpu/nios2/interrupts.c | 22 +- cpu/nios2/serial.c | 8 +- cpu/nios2/start.S | 24 +- cpu/nios2/sysid.c | 6 +- cpu/ppc4xx/40x_spd_sdram.c | 10 +- cpu/ppc4xx/44x_spd_ddr.c | 22 +- cpu/ppc4xx/44x_spd_ddr2.c | 80 +++--- cpu/ppc4xx/4xx_enet.c | 20 +- cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 8 +- cpu/ppc4xx/4xx_pci.c | 44 ++-- cpu/ppc4xx/4xx_pcie.c | 144 +++++------ cpu/ppc4xx/4xx_uart.c | 44 ++-- cpu/ppc4xx/cache.S | 4 +- cpu/ppc4xx/commproc.c | 12 +- cpu/ppc4xx/cpu.c | 6 +- cpu/ppc4xx/cpu_init.c | 100 ++++---- cpu/ppc4xx/denali_data_eye.c | 2 +- cpu/ppc4xx/denali_spd_ddr2.c | 22 +- cpu/ppc4xx/ecc.c | 4 +- cpu/ppc4xx/ecc.h | 6 +- cpu/ppc4xx/gpio.c | 8 +- cpu/ppc4xx/i2c.c | 24 +- cpu/ppc4xx/ndfc.c | 10 +- cpu/ppc4xx/sdram.c | 46 ++-- cpu/ppc4xx/sdram.h | 20 +- cpu/ppc4xx/start.S | 344 +++++++++++++------------- cpu/ppc4xx/usb.c | 4 +- cpu/ppc4xx/usb_ohci.c | 6 +- cpu/ppc4xx/usbdev.h | 44 ++-- cpu/pxa/cpu.c | 2 +- cpu/pxa/i2c.c | 8 +- cpu/pxa/interrupts.c | 6 +- cpu/pxa/mmc.c | 10 +- cpu/pxa/pxafb.c | 30 +-- cpu/pxa/start.S | 40 +-- cpu/pxa/usb.c | 4 +- cpu/s3c44b0/interrupts.c | 6 +- cpu/s3c44b0/start.S | 4 +- cpu/sa1100/cpu.c | 2 +- cpu/sa1100/interrupts.c | 6 +- cpu/sa1100/start.S | 14 +- cpu/sh2/start.S | 4 +- cpu/sh2/time.c | 4 +- cpu/sh3/start.S | 4 +- cpu/sh3/time.c | 4 +- cpu/sh4/start.S | 4 +- cpu/sh4/time.c | 4 +- 286 files changed, 3365 insertions(+), 3365 deletions(-) (limited to 'cpu') diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index 62a6683..66c7298 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -292,7 +292,7 @@ _GLOBAL(dcache_enable) mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 mflr r5 bl l2cache_enable /* uses r3 and r4 */ sync @@ -318,7 +318,7 @@ _GLOBAL(dcache_disable) andc r3, r3, r5 /* no enable, no invalidate */ mtspr HID0, r3 sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 bl l2cache_disable_no_flush /* uses r3 */ #endif mtlr r4 /* restore link register */ diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index c007abc..3c17277 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -256,16 +256,16 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) __asm__ __volatile__ ("isync"); __asm__ __volatile__ ("sync"); -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, - * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, + * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid * address. Better pick an address known to be invalid on your - * system and assign it to CFG_RESET_ADDRESS. + * system and assign it to CONFIG_SYS_RESET_ADDRESS. */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif soft_restart(addr); while(1); /* not reached */ @@ -277,18 +277,18 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * For the 7400 the TB clock runs at 1/4 the cpu bus speed. */ -#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK) +#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SYS_CONFIG_BUS_CLK) unsigned long get_tbclk(void) { return (gd->bus_clk / 4); } -#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/ +#else /* ! CONFIG_AMIGAONEG3SE and !CONFIG_SYS_CONFIG_BUS_CLK*/ unsigned long get_tbclk (void) { - return CFG_BUS_HZ / 4; + return CONFIG_SYS_BUS_HZ / 4; } -#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/ +#endif /* CONFIG_AMIGAONEG3SE or CONFIG_SYS_CONFIG_BUS_CLK*/ /* ------------------------------------------------------------------------- */ #if defined(CONFIG_WATCHDOG) #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) diff --git a/cpu/74xx_7xx/interrupts.c b/cpu/74xx_7xx/interrupts.c index f0ea485..0ea1aec 100644 --- a/cpu/74xx_7xx/interrupts.c +++ b/cpu/74xx_7xx/interrupts.c @@ -48,7 +48,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER)); puts("interrupt_init: setting decrementer_count\n"); #endif - *decrementer_count = get_tbclk() / CFG_HZ; + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; return (0); } diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S index 4f23122..ad487cd 100644 --- a/cpu/74xx_7xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -43,7 +43,7 @@ kgdb_flush_cache_all: addis r4,r0,0x0040 kgdb_flush_loop: lwz r5,0(r3) - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE cmp 0,0,r3,r4 bne kgdb_flush_loop SYNC @@ -55,21 +55,21 @@ kgdb_flush_loop: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 + li r5,CONFIG_SYS_CACHELINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT + srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE + addi r6,r6,CONFIG_SYS_CACHELINE_SIZE bdnz 2b SYNC blr diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index d8c40ce..bc33a67 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -127,8 +127,8 @@ int get_clocks (void) { ulong clock = 0; -#ifdef CFG_BUS_CLK - gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */ +#ifdef CONFIG_SYS_BUS_CLK + gd->bus_clk = CONFIG_SYS_BUS_CLK; /* bus clock is a fixed frequency */ #else gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ #endif diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 42b0f72..07bbe01 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -209,7 +209,7 @@ boot_warm: bl invalidate_bats sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l @@ -225,12 +225,12 @@ boot_warm: */ #endif -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 /* invalidate the L2 cache */ bl l2cache_invalidate sync #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* do early init */ bl board_asm_init #endif @@ -238,8 +238,8 @@ boot_warm: /* * Calculate absolute address in FLASH and jump there *------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr @@ -280,15 +280,15 @@ in_flash: bl l1dcache_enable sync #endif -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK bl lock_ram_in_cache sync #endif /* set up the stack pointer in our newly created * cache-ram (r1) */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -343,146 +343,146 @@ setup_bats: addis r0, r0, 0x0000 /* IBAT 0 */ - addis r4, r0, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - addis r3, r0, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l + addis r4, r0, CONFIG_SYS_IBAT0L@h + ori r4, r4, CONFIG_SYS_IBAT0L@l + addis r3, r0, CONFIG_SYS_IBAT0U@h + ori r3, r3, CONFIG_SYS_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 isync /* DBAT 0 */ - addis r4, r0, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - addis r3, r0, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l + addis r4, r0, CONFIG_SYS_DBAT0L@h + ori r4, r4, CONFIG_SYS_DBAT0L@l + addis r3, r0, CONFIG_SYS_DBAT0U@h + ori r3, r3, CONFIG_SYS_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 isync /* IBAT 1 */ - addis r4, r0, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - addis r3, r0, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l + addis r4, r0, CONFIG_SYS_IBAT1L@h + ori r4, r4, CONFIG_SYS_IBAT1L@l + addis r3, r0, CONFIG_SYS_IBAT1U@h + ori r3, r3, CONFIG_SYS_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 isync /* DBAT 1 */ - addis r4, r0, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - addis r3, r0, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l + addis r4, r0, CONFIG_SYS_DBAT1L@h + ori r4, r4, CONFIG_SYS_DBAT1L@l + addis r3, r0, CONFIG_SYS_DBAT1U@h + ori r3, r3, CONFIG_SYS_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 isync /* IBAT 2 */ - addis r4, r0, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - addis r3, r0, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l + addis r4, r0, CONFIG_SYS_IBAT2L@h + ori r4, r4, CONFIG_SYS_IBAT2L@l + addis r3, r0, CONFIG_SYS_IBAT2U@h + ori r3, r3, CONFIG_SYS_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 isync /* DBAT 2 */ - addis r4, r0, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - addis r3, r0, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l + addis r4, r0, CONFIG_SYS_DBAT2L@h + ori r4, r4, CONFIG_SYS_DBAT2L@l + addis r3, r0, CONFIG_SYS_DBAT2U@h + ori r3, r3, CONFIG_SYS_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 isync /* IBAT 3 */ - addis r4, r0, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - addis r3, r0, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l + addis r4, r0, CONFIG_SYS_IBAT3L@h + ori r4, r4, CONFIG_SYS_IBAT3L@l + addis r3, r0, CONFIG_SYS_IBAT3U@h + ori r3, r3, CONFIG_SYS_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 isync /* DBAT 3 */ - addis r4, r0, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - addis r3, r0, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l + addis r4, r0, CONFIG_SYS_DBAT3L@h + ori r4, r4, CONFIG_SYS_DBAT3L@l + addis r3, r0, CONFIG_SYS_DBAT3U@h + ori r3, r3, CONFIG_SYS_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 isync #ifdef CONFIG_HIGH_BATS /* IBAT 4 */ - addis r4, r0, CFG_IBAT4L@h - ori r4, r4, CFG_IBAT4L@l - addis r3, r0, CFG_IBAT4U@h - ori r3, r3, CFG_IBAT4U@l + addis r4, r0, CONFIG_SYS_IBAT4L@h + ori r4, r4, CONFIG_SYS_IBAT4L@l + addis r3, r0, CONFIG_SYS_IBAT4U@h + ori r3, r3, CONFIG_SYS_IBAT4U@l mtspr IBAT4L, r4 mtspr IBAT4U, r3 isync /* DBAT 4 */ - addis r4, r0, CFG_DBAT4L@h - ori r4, r4, CFG_DBAT4L@l - addis r3, r0, CFG_DBAT4U@h - ori r3, r3, CFG_DBAT4U@l + addis r4, r0, CONFIG_SYS_DBAT4L@h + ori r4, r4, CONFIG_SYS_DBAT4L@l + addis r3, r0, CONFIG_SYS_DBAT4U@h + ori r3, r3, CONFIG_SYS_DBAT4U@l mtspr DBAT4L, r4 mtspr DBAT4U, r3 isync /* IBAT 5 */ - addis r4, r0, CFG_IBAT5L@h - ori r4, r4, CFG_IBAT5L@l - addis r3, r0, CFG_IBAT5U@h - ori r3, r3, CFG_IBAT5U@l + addis r4, r0, CONFIG_SYS_IBAT5L@h + ori r4, r4, CONFIG_SYS_IBAT5L@l + addis r3, r0, CONFIG_SYS_IBAT5U@h + ori r3, r3, CONFIG_SYS_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 isync /* DBAT 5 */ - addis r4, r0, CFG_DBAT5L@h - ori r4, r4, CFG_DBAT5L@l - addis r3, r0, CFG_DBAT5U@h - ori r3, r3, CFG_DBAT5U@l + addis r4, r0, CONFIG_SYS_DBAT5L@h + ori r4, r4, CONFIG_SYS_DBAT5L@l + addis r3, r0, CONFIG_SYS_DBAT5U@h + ori r3, r3, CONFIG_SYS_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 isync /* IBAT 6 */ - addis r4, r0, CFG_IBAT6L@h - ori r4, r4, CFG_IBAT6L@l - addis r3, r0, CFG_IBAT6U@h - ori r3, r3, CFG_IBAT6U@l + addis r4, r0, CONFIG_SYS_IBAT6L@h + ori r4, r4, CONFIG_SYS_IBAT6L@l + addis r3, r0, CONFIG_SYS_IBAT6U@h + ori r3, r3, CONFIG_SYS_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 isync /* DBAT 6 */ - addis r4, r0, CFG_DBAT6L@h - ori r4, r4, CFG_DBAT6L@l - addis r3, r0, CFG_DBAT6U@h - ori r3, r3, CFG_DBAT6U@l + addis r4, r0, CONFIG_SYS_DBAT6L@h + ori r4, r4, CONFIG_SYS_DBAT6L@l + addis r3, r0, CONFIG_SYS_DBAT6U@h + ori r3, r3, CONFIG_SYS_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 isync /* IBAT 7 */ - addis r4, r0, CFG_IBAT7L@h - ori r4, r4, CFG_IBAT7L@l - addis r3, r0, CFG_IBAT7U@h - ori r3, r3, CFG_IBAT7U@l + addis r4, r0, CONFIG_SYS_IBAT7L@h + ori r4, r4, CONFIG_SYS_IBAT7L@l + addis r3, r0, CONFIG_SYS_IBAT7U@h + ori r3, r3, CONFIG_SYS_IBAT7U@l mtspr IBAT7L, r4 mtspr IBAT7U, r3 isync /* DBAT 7 */ - addis r4, r0, CFG_DBAT7L@h - ori r4, r4, CFG_DBAT7L@l - addis r3, r0, CFG_DBAT7U@h - ori r3, r3, CFG_DBAT7U@l + addis r4, r0, CONFIG_SYS_DBAT7L@h + ori r4, r4, CONFIG_SYS_DBAT7L@l + addis r3, r0, CONFIG_SYS_DBAT7U@h + ori r3, r3, CONFIG_SYS_DBAT7U@l mtspr DBAT7L, r4 mtspr DBAT7U, r3 isync @@ -612,16 +612,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -639,11 +639,11 @@ relocate_code: bl board_relocate_rom sync mr r3, r10 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ #else cmplw cr1,r3,r4 addi r0,r5,3 @@ -851,14 +851,14 @@ trap_reloc: blr -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ + (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r2 1: dcbz r0, r3 @@ -876,10 +876,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + li r2, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ + (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r2 1: icbi r0, r3 addi r3, r3, 32 diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index c27f8cd..0486163 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -89,7 +89,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c index cd57071..b36c58c 100644 --- a/cpu/arm1136/mx31/interrupts.c +++ b/cpu/arm1136/mx31/interrupts.c @@ -38,16 +38,16 @@ #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ #define GPTCR_TEN 1 /* Timer enable */ -/* "time" is measured in 1 / CFG_HZ seconds, "tick" is internal timer period */ +/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION /* ~0.4% error - measured with stop-watch on 100s boot-delay */ -#define TICK_TO_TIME(t) ((t) * CFG_HZ / CONFIG_MX31_CLK32) -#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CFG_HZ) +#define TICK_TO_TIME(t) ((t) * CONFIG_SYS_HZ / CONFIG_MX31_CLK32) +#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CONFIG_SYS_HZ) #define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \ 999999) / 1000000) #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CFG_HZ / 2) / CFG_HZ) +#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) #define TICK_TO_TIME(t) ((t) / TICK_PER_TIME) #define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME) @@ -104,7 +104,7 @@ ulong get_timer_masked (void) /* * get_ticks() returns a long long (64 bit), it wraps in * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CFG_HZ wraps in + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ return TICK_TO_TIME(get_ticks()); diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c index f498599..e025e94 100644 --- a/cpu/arm1136/mx31/serial.c +++ b/cpu/arm1136/mx31/serial.c @@ -25,18 +25,18 @@ #define __REG(x) (*((volatile u32 *)(x))) -#ifdef CFG_MX31_UART1 +#ifdef CONFIG_SYS_MX31_UART1 #define UART_PHYS 0x43f90000 -#elif defined(CFG_MX31_UART2) +#elif defined(CONFIG_SYS_MX31_UART2) #define UART_PHYS 0x43f94000 -#elif defined(CFG_MX31_UART3) +#elif defined(CONFIG_SYS_MX31_UART3) #define UART_PHYS 0x5000c000 -#elif defined(CFG_MX31_UART4) +#elif defined(CONFIG_SYS_MX31_UART4) #define UART_PHYS 0x43fb0000 -#elif defined(CFG_MX31_UART5) +#elif defined(CONFIG_SYS_MX31_UART5) #define UART_PHYS 0x43fb4000 #else -#error "define CFG_MX31_UARTx to use the mx31 UART driver" +#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" #endif /* Register definitions */ diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c index b9a8b93..fb02a49 100644 --- a/cpu/arm1136/omap24xx/interrupts.c +++ b/cpu/arm1136/omap24xx/interrupts.c @@ -37,7 +37,7 @@ #define TIMER_LOAD_VAL 0 /* macro to read the 32 bit timer */ -#define READ_TIMER (*((volatile ulong *)(CFG_TIMERBASE+TCRR))) +#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR))) static ulong timestamp; static ulong lastinc; @@ -48,9 +48,9 @@ int interrupt_init (void) int32_t val; /* Start the counter ticking up */ - *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ - *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */ + *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ + val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ reset_timer_masked(); /* init the timestamp and lastinc value */ @@ -81,10 +81,10 @@ void udelay (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -125,10 +125,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } endtime = get_timer_masked () + tmo; @@ -154,6 +154,6 @@ unsigned long long get_ticks(void) ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 51b664d..e622338 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -178,8 +178,8 @@ stack_setup: #ifdef CONFIG_ONENAND_IPL sub sp, r0, #128 /* leave 32 words for abort-stack */ #else - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -290,8 +290,8 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -323,8 +323,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) - sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack + sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr @@ -341,8 +341,8 @@ cpu_init_crit: sub r13, r13, #4 @ space on current stack for scratch reg. str r0, [r13] @ save R0's value. ldr r0, _armboot_start @ get data regions start - sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool - sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack + sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool + sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack str lr, [r0] @ save caller lr in position 0 of saved stack mrs r0, spsr @ get the spsr str lr, [r0, #4] @ save spsr in position 1 of saved stack diff --git a/cpu/arm1176/s3c64xx/interrupts.c b/cpu/arm1176/s3c64xx/interrupts.c index e34369f..83f3806 100644 --- a/cpu/arm1176/s3c64xx/interrupts.c +++ b/cpu/arm1176/s3c64xx/interrupts.c @@ -150,7 +150,7 @@ void reset_timer(void) ulong get_timer_masked(void) { unsigned long long res = get_ticks(); - do_div (res, (timer_load_val / (100 * CFG_HZ))); + do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ))); return res; } @@ -161,7 +161,7 @@ ulong get_timer(ulong base) void set_timer(ulong t) { - timestamp = t * (timer_load_val / (100 * CFG_HZ)); + timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ)); } void udelay(unsigned long usec) diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index 991277f..cb891df 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -37,8 +37,8 @@ #endif #include -#if !defined(CONFIG_ENABLE_MMU) && !defined(CFG_PHY_UBOOT_BASE) -#define CFG_PHY_UBOOT_BASE CFG_UBOOT_BASE +#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) +#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE #endif /* @@ -105,7 +105,7 @@ _TEXT_BASE: * by scsuh. */ _TEXT_PHY_BASE: - .word CFG_PHY_UBOOT_BASE + .word CONFIG_SYS_PHY_UBOOT_BASE .globl _armboot_start _armboot_start: @@ -209,7 +209,7 @@ enable_mmu: /* Set the TTB register */ ldr r0, _mmu_table_base - ldr r1, =CFG_PHY_UBOOT_BASE + ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE ldr r2, =0xfff00000 bic r0, r0, r2 orr r1, r0, r1 @@ -242,11 +242,11 @@ skip_hw_init: /* Set up the stack */ stack_setup: #ifdef CONFIG_MEMORY_UPPER_CODE - ldr sp, =(CFG_UBOOT_BASE + CFG_UBOOT_SIZE - 0xc) + ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc) #else ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ sub sp, r0, #12 /* leave 3 words for abort-stack */ #endif @@ -357,9 +357,9 @@ phy_last_jump: stmia sp, {r0 - r12} ldr r2, _armboot_start - sub r2, r2, #(CFG_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) /* set base 2 words into abort stack */ - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) /* get values for "aborted" pc and cpsr (into parm regs) */ ldmia r2, {r2 - r3} /* grab pointer to old stack */ @@ -377,9 +377,9 @@ phy_last_jump: /* setup our mode stack (enter in banked mode) */ ldr r13, _armboot_start /* move past malloc pool */ - sub r13, r13, #(CFG_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) /* move to reserved a couple spots for abort stack */ - sub r13, r13, #(CFG_GBL_DATA_SIZE + 8) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) /* save caller lr in position 0 of saved stack */ str lr, [r13] @@ -407,9 +407,9 @@ phy_last_jump: /* get data regions start */ ldr r0, _armboot_start /* move past malloc pool */ - sub r0, r0, #(CFG_MALLOC_LEN) + sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) /* move past gbl and a couple spots for abort stack */ - sub r0, r0, #(CFG_GBL_DATA_SIZE + 8) + sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) /* save caller lr in position 0 of saved stack */ str lr, [r0] /* get the spsr */ diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 60c1aa9..5ac8f59 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -41,7 +41,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 9854016..39ed345 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -95,7 +95,7 @@ static void timer_isr( void *data) { unsigned int *pTime = (unsigned int *)data; (*pTime)++; - if ( !(*pTime % (CFG_HZ/4))) { + if ( !(*pTime % (CONFIG_SYS_HZ/4))) { /* toggle LED 0 */ PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1); } @@ -118,7 +118,7 @@ int interrupt_init (void) IRQEN = 0; /* operate timer 2 in non-prescale mode */ - TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) | + TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) | NETARM_GEN_TCTL_ENABLE | NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); @@ -166,9 +166,9 @@ int interrupt_init (void) /* * Load Timer data register with count down value. - * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ + * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ */ - PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ)); + PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ)); /* * Enable global interrupt @@ -181,7 +181,7 @@ int interrupt_init (void) #elif defined(CONFIG_LPC2292) PUT32(T0IR, 0); /* disable all timer0 interrupts */ PUT32(T0TCR, 0); /* disable timer0 */ - PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ); + PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ); PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ @@ -223,7 +223,7 @@ void udelay (unsigned long usec) ulong tmo; tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 1000; tmo += get_timer (0); @@ -268,10 +268,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 1000; } else { - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -294,7 +294,7 @@ void udelay (unsigned long usec) { u32 ticks; - ticks = (usec * CFG_HZ) / 1000000; + ticks = (usec * CONFIG_SYS_HZ) / 1000000; ticks += get_timer (0); diff --git a/cpu/arm720t/lpc2292/flash.c b/cpu/arm720t/lpc2292/flash.c index e5c8697..3d2dc32 100644 --- a/cpu/arm720t/lpc2292/flash.c +++ b/cpu/arm720t/lpc2292/flash.c @@ -85,7 +85,7 @@ int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) command[1] = flash_addr; command[2] = COPY_BUFFER_LOCATION; command[3] = 512; - command[4] = CFG_SYS_CLK_FREQ >> 10; + command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10; iap_entry(command, result); if (result[0] != IAP_RET_CMD_SUCCESS) { printf("IAP copy failed\n"); @@ -132,7 +132,7 @@ int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last) command[0] = IAP_CMD_ERASE; command[1] = s_first; command[2] = s_last; - command[3] = CFG_SYS_CLK_FREQ >> 10; + command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10; iap_entry(command, result); if (result[0] != IAP_RET_CMD_SUCCESS) { printf("IAP erase failed\n"); diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 1b0e147..54a9b31 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -85,7 +85,7 @@ void serial_putc (const char c) if (c == '\n') serial_putc ('\r'); - tmo = get_timer (0) + 1 * CFG_HZ; + tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; while (IO_SYSFLG1 & SYSFLG1_UTXFF) if (get_timer (0) > tmo) break; diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c index a593cbc..1a1b2db 100644 --- a/cpu/arm720t/serial_netarm.c +++ b/cpu/arm720t/serial_netarm.c @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; /* wait until transmitter is ready for another character */ #define TXWAITRDY(registers) \ { \ - ulong tmo = get_timer(0) + 1 * CFG_HZ; \ + ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \ while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ if (get_timer(0) > tmo) \ break; \ diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 8423e4f..022b873 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -166,8 +166,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -444,8 +444,8 @@ lock_loop: add r8, sp, #S_PC ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -477,8 +477,8 @@ lock_loop: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c index 90f95df..b68c5dd 100644 --- a/cpu/arm920t/at91rm9200/i2c.c +++ b/cpu/arm920t/at91rm9200/i2c.c @@ -120,7 +120,7 @@ int i2c_read (unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len) { -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* we only allow one address byte */ if (alen > 1) return 1; @@ -139,7 +139,7 @@ int i2c_write(unsigned char chip, unsigned int addr, int alen, unsigned char *buffer, int len) { -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW int i; unsigned char *buf; @@ -210,7 +210,7 @@ int i2c_set_bus_speed(unsigned int speed) unsigned int i2c_get_bus_speed(void) { - return CFG_I2C_SPEED; + return CONFIG_SYS_I2C_SPEED; } #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c index 1054602..5f0703c 100644 --- a/cpu/arm920t/at91rm9200/interrupts.c +++ b/cpu/arm920t/at91rm9200/interrupts.c @@ -35,8 +35,8 @@ #include /*#include */ -/* the number of clocks per CFG_HZ */ -#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ) +/* the number of clocks per CONFIG_SYS_HZ */ +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) /* macro to read the 16 bit timer */ #define READ_TIMER (tmr->TC_CV & 0x0000ffff) @@ -126,7 +126,7 @@ void udelay_masked (unsigned long usec) ulong endtime; signed long diff; - tmo = CFG_HZ_CLOCK / 1000; + tmo = CONFIG_SYS_HZ_CLOCK / 1000; tmo *= usec; tmo /= 1000; @@ -155,7 +155,7 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 98363eb..66b07da 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -79,7 +79,7 @@ lowlevel_init: /* Get the CKGR Base Address */ ldr r1, =AT91C_BASE_CKGR /* Main oscillator Enable register */ -#ifdef CFG_USE_MAIN_OSCILLATOR +#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */ #else ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ diff --git a/cpu/arm920t/at91rm9200/spi.c b/cpu/arm920t/at91rm9200/spi.c index 265d185..f3cb5d8 100644 --- a/cpu/arm920t/at91rm9200/spi.c +++ b/cpu/arm920t/at91rm9200/spi.c @@ -137,11 +137,11 @@ unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && - ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + ((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT)); AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; pDesc->state = IDLE; - if (timeout >= CFG_SPI_WRITE_TOUT){ + if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){ printf("Error Timeout\n\r"); return DATAFLASH_ERROR; } diff --git a/cpu/arm920t/at91rm9200/usb.c b/cpu/arm920t/at91rm9200/usb.c index c121de6..72355dc 100644 --- a/cpu/arm920t/at91rm9200/usb.c +++ b/cpu/arm920t/at91rm9200/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) # ifdef CONFIG_AT91RM9200 #include @@ -50,4 +50,4 @@ int usb_cpu_init_fail(void) } # endif /* CONFIG_AT91RM9200 */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index f93bf57..1b9cde6 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -95,7 +95,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c index c61d3bc..ddcfb34 100644 --- a/cpu/arm920t/imx/interrupts.c +++ b/cpu/arm920t/imx/interrupts.c @@ -112,7 +112,7 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index c9cd066..09c54db 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -42,7 +42,7 @@ void do_irq (struct pt_regs *pt_regs) /* ASSUMED to be a timer interrupt */ /* Just clear it - count handled in */ /* integratorap.c */ - *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0; #else #error do_irq() not defined for this cpu type #endif diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c index 374b683..fba5cd1 100644 --- a/cpu/arm920t/s3c24x0/i2c.c +++ b/cpu/arm920t/s3c24x0/i2c.c @@ -384,7 +384,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) xaddr[3] = addr & 0xFF; } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -397,7 +397,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if (alen > 0) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif if ((ret = i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, @@ -423,7 +423,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -436,7 +436,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if (alen > 0) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif return (i2c_transfer (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 7ad9fcb..11e6804 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -179,7 +179,7 @@ ulong get_tbclk (void) #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ defined(CONFIG_VCMA9) - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; #else # error "tbclk not configured" #endif diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index 421ebb4..9ccf575 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) # if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) #if defined(CONFIG_S3C2400) @@ -69,4 +69,4 @@ int usb_cpu_init_fail (void) } # endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ -#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 5d0fec6..17977c2 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -202,8 +202,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -316,8 +316,8 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Calling r0-r12 ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE) - sub r2, r2, #(CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r3} @ get pc, cpsr add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -350,8 +350,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE) - sub r13, r13, #(CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c index d85b7fa..b9f0931 100644 --- a/cpu/arm925t/cpu.c +++ b/cpu/arm925t/cpu.c @@ -95,7 +95,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c index 208a25bd..3ef4554 100644 --- a/cpu/arm925t/interrupts.c +++ b/cpu/arm925t/interrupts.c @@ -39,7 +39,7 @@ #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) +#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8)) static ulong timestamp; static ulong lastdec; @@ -50,9 +50,9 @@ int interrupt_init (void) int32_t val; /* Start the decrementer ticking down from 0xffffffff */ - *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); - *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; + *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); + *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; /* init the timestamp and lastdec value */ reset_timer_masked(); @@ -86,10 +86,10 @@ void udelay (unsigned long usec) if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -145,10 +145,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -178,6 +178,6 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S index 5ddda54..c48014d 100644 --- a/cpu/arm925t/start.S +++ b/cpu/arm925t/start.S @@ -190,8 +190,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -295,8 +295,8 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -328,8 +328,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/cpu/arm926ejs/at91/spi.c b/cpu/arm926ejs/at91/spi.c index c9fe6d8..3eb252c 100644 --- a/cpu/arm926ejs/at91/spi.c +++ b/cpu/arm926ejs/at91/spi.c @@ -48,7 +48,7 @@ void AT91F_SpiInit(void) ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(0)); -#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1 +#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 /* Configure CS1 */ writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | @@ -57,7 +57,7 @@ void AT91F_SpiInit(void) AT91_BASE_SPI + AT91_SPI_CSR(1)); #endif -#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3 +#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 /* Configure CS3 */ writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | @@ -144,11 +144,11 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && - ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); + ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT)); writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); pDesc->state = IDLE; - if (timeout >= CFG_SPI_WRITE_TOUT) { + if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) { printf("Error Timeout\n\r"); return DATAFLASH_ERROR; } diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index c79ec7e..fec545b 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -130,7 +130,7 @@ ulong get_tbclk(void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm926ejs/at91/usb.c b/cpu/arm926ejs/at91/usb.c index 2a92f73..7cb082d 100644 --- a/cpu/arm926ejs/at91/usb.c +++ b/cpu/arm926ejs/at91/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) #include #include @@ -59,4 +59,4 @@ int usb_cpu_init_fail(void) return usb_cpu_stop(); } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 56c6289..48a2c0b 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -95,7 +95,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c index af9dc03..d220a4c 100644 --- a/cpu/arm926ejs/davinci/i2c.c +++ b/cpu/arm926ejs/davinci/i2c.c @@ -104,7 +104,7 @@ void i2c_init(int speed, int slaveadd) } psc = 2; - div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ + div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ REG(I2C_SCLH) = div - REG(I2C_SCLL); diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index f7cf0c9..014e2b0 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -44,14 +44,14 @@ #include #include -#ifdef CFG_USE_NAND +#ifdef CONFIG_SYS_USE_NAND #if !defined(CONFIG_NAND_LEGACY) #include #include #include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { @@ -87,11 +87,11 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) #endif } -#ifdef CFG_NAND_HW_ECC -#ifdef CFG_DAVINCI_BROKEN_ECC +#ifdef CONFIG_SYS_NAND_HW_ECC +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC /* Linux-compatible ECC uses MTD defaults. */ /* These layouts are not compatible with Linux or RBL/UBL. */ -#ifdef CFG_NAND_LARGEPAGE +#ifdef CONFIG_SYS_NAND_LARGEPAGE static struct nand_ecclayout davinci_nand_ecclayout = { .eccbytes = 12, .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, @@ -103,7 +103,7 @@ static struct nand_ecclayout davinci_nand_ecclayout = { {.offset = 60, .length = 4} } }; -#elif defined(CFG_NAND_SMALLPAGE) +#elif defined(CONFIG_SYS_NAND_SMALLPAGE) static struct nand_ecclayout davinci_nand_ecclayout = { .eccbytes = 3, .eccpos = {0, 1, 2}, @@ -113,9 +113,9 @@ static struct nand_ecclayout davinci_nand_ecclayout = { } }; #else -#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!" #endif -#endif /* CFG_DAVINCI_BROKEN_ECC */ +#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { @@ -154,7 +154,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { u_int32_t tmp; -#ifdef CFG_DAVINCI_BROKEN_ECC +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC /* * This is not how you should read ECCs on large page Davinci devices. * The region parameter gets you ECCs for flash chips on different chip @@ -191,11 +191,11 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u *ecc_code++ = tmp; *ecc_code++ = tmp >> 8; *ecc_code++ = tmp >> 16; -#endif /* CFG_DAVINCI_BROKEN_ECC */ +#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ return(0); } -#ifdef CFG_DAVINCI_BROKEN_ECC +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) { u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); @@ -312,12 +312,12 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in return(-1); } } -#endif /* CFG_DAVINCI_BROKEN_ECC */ +#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) { struct nand_chip *this = mtd->priv; -#ifdef CFG_DAVINCI_BROKEN_ECC +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC int block_count = 0, i, rc; block_count = (this->ecc.size/512); @@ -366,10 +366,10 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char * return -1; } } -#endif /* CFG_DAVINCI_BROKEN_ECC */ +#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ return(0); } -#endif /* CFG_NAND_HW_ECC */ +#endif /* CONFIG_SYS_NAND_HW_ECC */ static int nand_davinci_dev_ready(struct mtd_info *mtd) { @@ -431,32 +431,32 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; nand->chip_delay = 0; nand->select_chip = nand_davinci_select_chip; -#ifdef CFG_NAND_USE_FLASH_BBT +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->options = NAND_USE_FLASH_BBT; #endif -#ifdef CFG_NAND_HW_ECC +#ifdef CONFIG_SYS_NAND_HW_ECC nand->ecc.mode = NAND_ECC_HW; -#ifdef CFG_DAVINCI_BROKEN_ECC +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC nand->ecc.layout = &davinci_nand_ecclayout; -#ifdef CFG_NAND_LARGEPAGE +#ifdef CONFIG_SYS_NAND_LARGEPAGE nand->ecc.size = 2048; nand->ecc.bytes = 12; -#elif defined(CFG_NAND_SMALLPAGE) +#elif defined(CONFIG_SYS_NAND_SMALLPAGE) nand->ecc.size = 512; nand->ecc.bytes = 3; #else -#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!" +#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!" #endif #else nand->ecc.size = 512; nand->ecc.bytes = 3; -#endif /* CFG_DAVINCI_BROKEN_ECC */ +#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ nand->ecc.calculate = nand_davinci_calculate_ecc; nand->ecc.correct = nand_davinci_correct_data; nand->ecc.hwctl = nand_davinci_enable_hwecc; #else nand->ecc.mode = NAND_ECC_SOFT; -#endif /* CFG_NAND_HW_ECC */ +#endif /* CONFIG_SYS_NAND_HW_ECC */ /* Set address of hardware control function */ nand->cmd_ctrl = nand_davinci_hwcontrol; @@ -472,4 +472,4 @@ int board_nand_init(struct nand_chip *nand) #else #error "U-Boot legacy NAND support not available for DaVinci chips" #endif -#endif /* CFG_USE_NAND */ +#endif /* CONFIG_SYS_USE_NAND */ diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c index 6c670f0..773735a 100644 --- a/cpu/arm926ejs/davinci/timer.c +++ b/cpu/arm926ejs/davinci/timer.c @@ -54,9 +54,9 @@ typedef volatile struct { u_int32_t wdtcr; } davinci_timer; -davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; +davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE; -#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) #define TIM_CLK_DIV 16 static ulong timestamp; @@ -117,7 +117,7 @@ void udelay(unsigned long usec) ulong endtime; signed long diff; - tmo = CFG_HZ_CLOCK / 1000; + tmo = CONFIG_SYS_HZ_CLOCK / 1000; tmo *= usec; tmo /= (1000 * TIM_CLK_DIV); @@ -144,5 +144,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - return CFG_HZ; + return CONFIG_SYS_HZ; } diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c index a2a9133..49e74ab 100644 --- a/cpu/arm926ejs/omap/timer.c +++ b/cpu/arm926ejs/omap/timer.c @@ -41,7 +41,7 @@ #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) +#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8)) static ulong timestamp; static ulong lastdec; @@ -51,9 +51,9 @@ int timer_init (void) int32_t val; /* Start the decrementer ticking down from 0xffffffff */ - *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); - *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; + *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); + *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; /* init the timestamp and lastdec value */ reset_timer_masked(); @@ -87,10 +87,10 @@ void udelay (unsigned long usec) if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -140,10 +140,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -172,6 +172,6 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index a61fa18..ed4932a 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -165,8 +165,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -276,8 +276,8 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -310,8 +310,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c index f01f318..9ac867e 100755 --- a/cpu/arm926ejs/versatile/timer.c +++ b/cpu/arm926ejs/versatile/timer.c @@ -41,7 +41,7 @@ #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) +#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) static ulong timestamp; static ulong lastdec; @@ -62,9 +62,9 @@ int timer_init (void) ulong tmr_ctrl_val; /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* * The Timer Control Register has one Undefined/Shouldn't Use Bit @@ -78,11 +78,11 @@ int timer_init (void) * Tmr Siz : 16 Bit Counter * Tmr in Wrapping Mode */ - tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* init the timestamp and lastdec value */ reset_timer_masked(); @@ -116,10 +116,10 @@ void udelay (unsigned long usec) if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -169,10 +169,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -201,6 +201,6 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index 4c63a8d..44c589a 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -95,7 +95,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c index a2c3646..c13d309 100644 --- a/cpu/arm946es/interrupts.c +++ b/cpu/arm946es/interrupts.c @@ -121,10 +121,10 @@ void udelay_masked (unsigned long usec) if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ_CLOCK; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ_CLOCK; + tmo = usec * CONFIG_SYS_HZ_CLOCK; tmo /= (1000*1000); } @@ -151,7 +151,7 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S index 9e97f53..7972b00 100644 --- a/cpu/arm946es/start.S +++ b/cpu/arm946es/start.S @@ -157,8 +157,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -264,8 +264,8 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -298,8 +298,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c index e2309f8..ccf7fd5 100644 --- a/cpu/arm_intcm/cpu.c +++ b/cpu/arm_intcm/cpu.c @@ -43,7 +43,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S index d5778a0..ee0804a 100644 --- a/cpu/arm_intcm/start.S +++ b/cpu/arm_intcm/start.S @@ -155,8 +155,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -240,8 +240,8 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -274,8 +274,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c index b3aa034..2b1cd36 100644 --- a/cpu/at32ap/at32ap700x/clk.c +++ b/cpu/at32ap/at32ap700x/clk.c @@ -38,10 +38,10 @@ void clk_init(void) #ifdef CONFIG_PLL /* Initialize the PLL */ - sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) - | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) - | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) - | SM_BF(PLLOPT, CFG_PLL0_OPT) + sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1) + | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1) + | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT) | SM_BF(PLLOSC, 0) | SM_BIT(PLLEN))); @@ -51,14 +51,14 @@ void clk_init(void) /* Set up clocks for the CPU and all peripheral buses */ cksel = 0; - if (CFG_CLKDIV_CPU) - cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); - if (CFG_CLKDIV_HSB) - cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); - if (CFG_CLKDIV_PBA) - cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); - if (CFG_CLKDIV_PBB) - cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); + if (CONFIG_SYS_CLKDIV_CPU) + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1); + if (CONFIG_SYS_CLKDIV_HSB) + cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1); + if (CONFIG_SYS_CLKDIV_PBA) + cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1); + if (CONFIG_SYS_CLKDIV_PBB) + cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1); sm_writel(PM_CKSEL, cksel); #ifdef CONFIG_PLL diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c index 56ba2f9..91bb636 100644 --- a/cpu/at32ap/at32ap700x/gpio.c +++ b/cpu/at32ap/at32ap700x/gpio.c @@ -33,8 +33,8 @@ */ void gpio_enable_ebi(void) { -#ifdef CFG_HSDRAMC -#ifndef CFG_SDRAM_16BIT +#ifdef CONFIG_SYS_HSDRAMC +#ifndef CONFIG_SYS_SDRAM_16BIT gpio_select_periph_A(GPIO_PIN_PE0, 0); gpio_select_periph_A(GPIO_PIN_PE1, 0); gpio_select_periph_A(GPIO_PIN_PE2, 0); diff --git a/cpu/at32ap/cache.c b/cpu/at32ap/cache.c index 41fb5aa..16a0565 100644 --- a/cpu/at32ap/cache.c +++ b/cpu/at32ap/cache.c @@ -28,7 +28,7 @@ void dcache_clean_range(volatile void *start, size_t size) { unsigned long v, begin, end, linesz; - linesz = CFG_DCACHE_LINESZ; + linesz = CONFIG_SYS_DCACHE_LINESZ; /* You asked for it, you got it */ begin = (unsigned long)start & ~(linesz - 1); @@ -44,7 +44,7 @@ void dcache_invalidate_range(volatile void *start, size_t size) { unsigned long v, begin, end, linesz; - linesz = CFG_DCACHE_LINESZ; + linesz = CONFIG_SYS_DCACHE_LINESZ; /* You asked for it, you got it */ begin = (unsigned long)start & ~(linesz - 1); @@ -58,7 +58,7 @@ void dcache_flush_range(volatile void *start, size_t size) { unsigned long v, begin, end, linesz; - linesz = CFG_DCACHE_LINESZ; + linesz = CONFIG_SYS_DCACHE_LINESZ; /* You asked for it, you got it */ begin = (unsigned long)start & ~(linesz - 1); @@ -74,7 +74,7 @@ void icache_invalidate_range(volatile void *start, size_t size) { unsigned long v, begin, end, linesz; - linesz = CFG_ICACHE_LINESZ; + linesz = CONFIG_SYS_ICACHE_LINESZ; /* You asked for it, you got it */ begin = (unsigned long)start & ~(linesz - 1); diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 1a13702..f92d3e2 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -32,12 +32,12 @@ #include "hsmc3.h" /* Sanity checks */ -#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \ - || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \ - || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB) +#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \ + || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \ + || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB) # error Constraint fCPU >= fHSB >= fPB{A,B} violated #endif -#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1)) +#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1)) # error Invalid PLL multiplier and/or divider #endif @@ -47,7 +47,7 @@ int cpu_init(void) { extern void _evba(void); - gd->cpu_hz = CFG_OSC0_HZ; + gd->cpu_hz = CONFIG_SYS_OSC0_HZ; /* TODO: Move somewhere else, but needs to be run before we * increase the clock frequency. */ diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index 992612b..f74121c 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -21,7 +21,7 @@ */ #include -#ifdef CFG_HSDRAMC +#ifdef CONFIG_SYS_HSDRAMC #include #include @@ -117,4 +117,4 @@ unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) return sdram_size; } -#endif /* CFG_HSDRAMC */ +#endif /* CONFIG_SYS_HSDRAMC */ diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c index 160838e..75cc39e 100644 --- a/cpu/at32ap/interrupts.c +++ b/cpu/at32ap/interrupts.c @@ -82,7 +82,7 @@ void set_timer(unsigned long t) unsigned long long ticks = t; unsigned long lo, hi, hi_new; - ticks = (ticks * get_tbclk()) / CFG_HZ; + ticks = (ticks * get_tbclk()) / CONFIG_SYS_HZ; hi = ticks >> 32; lo = ticks & 0xffffffffUL; @@ -137,7 +137,7 @@ void timer_init(void) sysreg_write(COUNT, 0); - tmp = (u64)CFG_HZ << 32; + tmp = (u64)CONFIG_SYS_HZ << 32; tmp += gd->cpu_hz / 2; do_div(tmp, gd->cpu_hz); tb_factor = (u32)tmp; diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S index 907e9b1..d37a46e 100644 --- a/cpu/at32ap/start.S +++ b/cpu/at32ap/start.S @@ -188,7 +188,7 @@ at32ap_low_level_init: .align 2 .type sp_init,@object sp_init: - .long CFG_INIT_SP_ADDR + .long CONFIG_SYS_INIT_SP_ADDR got_init: .long 3b - _GLOBAL_OFFSET_TABLE_ diff --git a/cpu/blackfin/interrupts.c b/cpu/blackfin/interrupts.c index 80c5505..d4dd636 100644 --- a/cpu/blackfin/interrupts.c +++ b/cpu/blackfin/interrupts.c @@ -48,7 +48,7 @@ ulong get_tbclk(void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S index 30212e9..8303292 100644 --- a/cpu/blackfin/start.S +++ b/cpu/blackfin/start.S @@ -145,12 +145,12 @@ ENTRY(_start) r6 = 0 (x); p1 = r0; - p2.l = LO(CFG_MONITOR_BASE); - p2.h = HI(CFG_MONITOR_BASE); + p2.l = LO(CONFIG_SYS_MONITOR_BASE); + p2.h = HI(CONFIG_SYS_MONITOR_BASE); p3 = 0x04; - p4.l = LO(CFG_MONITOR_BASE + CFG_MONITOR_LEN); - p4.h = HI(CFG_MONITOR_BASE + CFG_MONITOR_LEN); + p4.l = LO(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN); + p4.h = HI(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN); .Lloop1: r1 = [p1 ++ p3]; [p2 ++ p3] = r1; diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c index 4474fe5..2eb45b5 100644 --- a/cpu/blackfin/traps.c +++ b/cpu/blackfin/traps.c @@ -229,8 +229,8 @@ static void decode_address(char *buf, unsigned long address) if (!address) sprintf(buf, "<0x%p> /* Maybe null pointer? */", address); - else if (address >= CFG_MONITOR_BASE && - address < CFG_MONITOR_BASE + CFG_MONITOR_LEN) + else if (address >= CONFIG_SYS_MONITOR_BASE && + address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) sprintf(buf, "<0x%p> /* somewhere in u-boot */", address); else sprintf(buf, "<0x%p> /* unknown address */", address); diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c index f340119..f6dbcca 100644 --- a/cpu/i386/interrupts.c +++ b/cpu/i386/interrupts.c @@ -509,7 +509,7 @@ int disable_interrupts(void) } -#ifdef CFG_RESET_GENERIC +#ifdef CONFIG_SYS_RESET_GENERIC void __attribute__ ((regparm(0))) generate_gpf(void); asm(".globl generate_gpf\n" diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 640b255..8bcb979 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -113,7 +113,7 @@ void init_sc520(void) write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ - if (CFG_SC520_HIGH_SPEED) { + if (CONFIG_SYS_SC520_HIGH_SPEED) { write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); @@ -145,7 +145,7 @@ unsigned long init_sc520_dram(void) u32 dram_present=0; u32 dram_ctrl; -#ifdef CFG_SDRAM_DRCTMCTL +#ifdef CONFIG_SYS_SDRAM_DRCTMCTL /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, * after we are running a stack in RAM, we have troubles. Besides, @@ -156,9 +156,9 @@ unsigned long init_sc520_dram(void) #else int val; - int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY; - int refresh_rate = CFG_SDRAM_REFRESH_RATE; - int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY; + int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; + int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; + int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY; /* set SDRAM speed here */ @@ -393,7 +393,7 @@ void pci_sc520_init(struct pci_controller *hose) #endif -#ifdef CFG_TIMER_SC520 +#ifdef CONFIG_SYS_TIMER_SC520 void reset_timer(void) diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index 34322ea..59ed2b8 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -460,21 +460,21 @@ emptybank: incl %edi loop cleanuplp -#if defined CFG_SDRAM_DRCTMCTL +#if defined CONFIG_SYS_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ movl $DRCTMCTL, %edi - movb $CFG_SDRAM_DRCTMCTL,%al + movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al movb (%edi), %al #else -#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T) +#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) /* set the CAS latency now since it is hard to do * when we run from the RAM */ movl $DRCTMCTL, %edi /* DRAM timing register */ movb (%edi), %al -#ifdef CFG_SDRAM_CAS_LATENCY_2T +#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T andb $0xef, %al #endif -#ifdef CFG_SDRAM_CAS_LATENCY_3T +#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T orb $0x10, %al #endif movb %al, (%edi) @@ -540,7 +540,7 @@ bank0: movl (%edi), %eax done: movl %ebx, %eax -#if CFG_SDRAM_ECC_ENABLE +#if CONFIG_SYS_SDRAM_ECC_ENABLE /* A nominal memory test: just a byte at each address line */ movl %eax, %ecx shrl $0x1, %ecx diff --git a/cpu/i386/start.S b/cpu/i386/start.S index 264ac09..f5ad833 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -67,7 +67,7 @@ mem_init_ret: * (we need atleast bss start+bss size+stack size) */ movl $_i386boot_bss_start, %ecx /* BSS start */ addl $_i386boot_bss_size, %ecx /* BSS size */ - addl $CFG_STACK_SIZE, %ecx + addl $CONFIG_SYS_STACK_SIZE, %ecx cmpl %ecx, %eax jae mem_ok @@ -88,7 +88,7 @@ mem_ok: /* create a stack after the bss */ movl $_i386boot_bss_start, %eax addl $_i386boot_bss_size, %eax - addl $CFG_STACK_SIZE, %eax + addl $CONFIG_SYS_STACK_SIZE, %eax movl %eax, %esp pushl $0 diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c index 486d927..46db23f 100644 --- a/cpu/i386/timer.c +++ b/cpu/i386/timer.c @@ -72,9 +72,9 @@ int timer_init(void) } -#ifdef CFG_TIMER_GENERIC +#ifdef CONFIG_SYS_TIMER_GENERIC -/* the unit for these is CFG_HZ */ +/* the unit for these is CONFIG_SYS_HZ */ /* FixMe: implement these */ void reset_timer (void) diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 2c7d5a0..402188e 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -81,7 +81,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif @@ -198,7 +198,7 @@ void pci_init(void) void bootcount_store (ulong a) { - volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR); + volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR); save_addr[0] = a; save_addr[1] = BOOTCOUNT_MAGIC; @@ -206,7 +206,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { - volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR); + volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR); if (save_addr[1] != BOOTCOUNT_MAGIC) return 0; diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c index 84fe937..621f31b 100644 --- a/cpu/ixp/interrupts.c +++ b/cpu/ixp/interrupts.c @@ -40,8 +40,8 @@ */ #define FREQ 66666666 -#define CLOCK_TICK_RATE (((FREQ / CFG_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CFG_HZ) -#define LATCH ((CLOCK_TICK_RATE + CFG_HZ/2) / CFG_HZ) /* For divider */ +#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) +#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ struct _irq_handler { void *m_data; diff --git a/cpu/ixp/npe/include/npe.h b/cpu/ixp/npe/include/npe.h index e53458d..3d6f727 100644 --- a/cpu/ixp/npe/include/npe.h +++ b/cpu/ixp/npe/include/npe.h @@ -27,10 +27,10 @@ /* * defines... */ -#define CFG_NPE_NUMS 1 +#define CONFIG_SYS_NPE_NUMS 1 #ifdef CONFIG_HAS_ETH1 -#undef CFG_NPE_NUMS -#define CFG_NPE_NUMS 2 +#undef CONFIG_SYS_NPE_NUMS +#define CONFIG_SYS_NPE_NUMS 2 #endif #define NPE_NUM_PORTS 3 diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 892096b..bd77fed 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -51,7 +51,7 @@ static int npe_exists[NPE_NUM_PORTS]; static int npe_used[NPE_NUM_PORTS]; /* A little extra so we can align to cacheline. */ -static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CFG_CACHELINE_SIZE - 1]; +static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1]; static u8 *npe_alloc_end; static u8 *npe_alloc_free; @@ -60,7 +60,7 @@ static void *npe_alloc(int size) static int count = 0; void *p = NULL; - size = (size + (CFG_CACHELINE_SIZE-1)) & ~(CFG_CACHELINE_SIZE-1); + size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1); count++; if ((npe_alloc_free + size) < npe_alloc_end) { @@ -399,7 +399,7 @@ static int npe_init(struct eth_device *dev, bd_t * bis) npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1)); + CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); /* initialize mbuf pool */ init_rx_mbufs(p_npe); @@ -568,7 +568,7 @@ int npe_initialize(bd_t * bis) int eth_num = 0; struct npe *p_npe = NULL; - for (eth_num = 0; eth_num < CFG_NPE_NUMS; eth_num++) { + for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) { /* See if we can actually bring up the interface, otherwise, skip it */ switch (eth_num) { @@ -673,8 +673,8 @@ int npe_initialize(bd_t * bis) npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CFG_CACHELINE_SIZE - 1) - & ~(CFG_CACHELINE_SIZE - 1)); + CONFIG_SYS_CACHELINE_SIZE - 1) + & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); if (!npe_csr_load()) return 0; diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c index 4549631..dd26af4 100644 --- a/cpu/ixp/serial.c +++ b/cpu/ixp/serial.c @@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; void serial_setbrg (void) { unsigned int quot = 0; - int uart = CFG_IXP425_CONSOLE; + int uart = CONFIG_SYS_IXP425_CONSOLE; if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0)) quot = SERIAL_CLOCK / gd->baudrate; @@ -85,9 +85,9 @@ int serial_init (void) void serial_putc (const char c) { /* wait for room in the tx FIFO on UART */ - while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0); + while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0); - THR(CFG_IXP425_CONSOLE) = c; + THR(CONFIG_SYS_IXP425_CONSOLE) = c; /* If \n, also do \r */ if (c == '\n') @@ -101,7 +101,7 @@ void serial_putc (const char c) */ int serial_tstc (void) { - return LSR(CFG_IXP425_CONSOLE) & LSR_DR; + return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR; } /* @@ -111,9 +111,9 @@ int serial_tstc (void) */ int serial_getc (void) { - while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR)); + while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)); - return (char) RBR(CFG_IXP425_CONSOLE) & 0xff; + return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; } void diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S index d4c8e33..196ba5d 100644 --- a/cpu/ixp/start.S +++ b/cpu/ixp/start.S @@ -154,7 +154,7 @@ reset: CPWAIT r0 /* set EXP CS0 to the optimum timing */ - ldr r1, =CFG_EXP_CS0 + ldr r1, =CONFIG_SYS_EXP_CS0 ldr r2, =IXP425_EXP_CS0 str r1, [r2] @@ -165,7 +165,7 @@ reset: orr r1, r1, #0x80000000 str r1, [r2] #endif - mov r1, #CFG_SDR_CONFIG + mov r1, #CONFIG_SYS_SDR_CONFIG ldr r2, =IXP425_SDR_CONFIG str r1, [r2] @@ -181,7 +181,7 @@ reset: DELAY_FOR 0x4000, r0 /* set SDRAM internal refresh val */ - ldr r1, =CFG_SDRAM_REFRESH_CNT + ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT str r1, [r3] DELAY_FOR 0x4000, r0 @@ -199,7 +199,7 @@ reset: bne 111b /* set mode register in sdram */ - mov r1, #CFG_SDR_MODE_CONFIG + mov r1, #CONFIG_SYS_SDR_MODE_CONFIG str r1, [r4] DELAY_FOR 0x4000, r0 @@ -211,7 +211,7 @@ reset: /* copy */ mov r0, #0 mov r4, r0 - add r2, r0, #CFG_MONITOR_LEN + add r2, r0, #CONFIG_SYS_MONITOR_LEN mov r1, #0x10000000 mov r5, r1 @@ -283,8 +283,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -345,8 +345,8 @@ _start_armboot: .word start_armboot add r8, sp, #S_PC ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ @@ -382,8 +382,8 @@ _start_armboot: .word start_armboot .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c index 920f34e..09d8ad5 100644 --- a/cpu/ixp/timer.c +++ b/cpu/ixp/timer.c @@ -44,7 +44,7 @@ void ixp425_udelay(unsigned long usec) * This function has a max usec, but since it is called from udelay * we should not have to worry... be happy */ - unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; + unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; diff --git a/cpu/leon2/interrupts.c b/cpu/leon2/interrupts.c index 35b375c..9b0da96 100644 --- a/cpu/leon2/interrupts.c +++ b/cpu/leon2/interrupts.c @@ -98,8 +98,8 @@ static void leon2_ic_enable(unsigned int irq) void handler_irq(int irq, struct pt_regs *regs) { if (irq_handlers[irq].handler) { - if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) || - ((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE) + if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) || + ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE) ) { printf("handler_irq: bad handler: %x, irq number %d\n", (unsigned int)irq_handlers[irq].handler, irq); @@ -163,8 +163,8 @@ void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", (ulong) handler, (ulong) irq_handlers[irq].handler); - if (((unsigned int)handler > CFG_RAM_END) || - ((unsigned int)handler < CFG_RAM_BASE) + if (((unsigned int)handler > CONFIG_SYS_RAM_END) || + ((unsigned int)handler < CONFIG_SYS_RAM_BASE) ) { printf("irq_install_handler: bad handler: %x, irq number %d\n", (unsigned int)handler, irq); diff --git a/cpu/leon2/prom.c b/cpu/leon2/prom.c index b031995..1a6c7f7 100644 --- a/cpu/leon2/prom.c +++ b/cpu/leon2/prom.c @@ -45,14 +45,14 @@ extern struct linux_romvec *kernel_arg_promvec; /* for __va */ extern int __prom_start; #define PAGE_OFFSET 0xf0000000 -#define phys_base CFG_SDRAM_BASE +#define phys_base CONFIG_SYS_SDRAM_BASE #define PROM_OFFS 8192 #define PROM_SIZE_MASK (PROM_OFFS-1) #define __va(x) ( \ (void *)( ((unsigned long)(x))-PROM_OFFS+ \ - (CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \ + (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \ ) -#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE)) +#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE)) struct property { char *name; @@ -540,13 +540,13 @@ static struct leon_prom_info PROM_DATA spi = { __va(&spi.totphys), { NULL, - (char *)CFG_SDRAM_BASE, + (char *)CONFIG_SYS_SDRAM_BASE, 0, }, __va(&spi.avail), { NULL, - (char *)CFG_SDRAM_BASE, + (char *)CONFIG_SYS_SDRAM_BASE, 0, }, NULL, /* prommap_p */ @@ -654,7 +654,7 @@ static void PROM_TEXT leon_reboot(char *bcommand) /* get physical address */ struct leon_prom_info *pspi = - (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); unsigned int *srmmu_ctx_table; @@ -707,7 +707,7 @@ static void PROM_TEXT leon_reboot_physical(char *bcommand) srmmu_set_mmureg(0); /* Hardcoded start address */ - reset = CFG_MONITOR_BASE; + reset = CONFIG_SYS_MONITOR_BASE; /* flush data cache */ sparc_dcache_flush_all(); @@ -762,7 +762,7 @@ static int PROM_TEXT no_nextnode(int node) { /* get physical address */ struct leon_prom_info *pspi = - (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -777,7 +777,7 @@ static int PROM_TEXT no_child(int node) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -792,7 +792,7 @@ static struct property PROM_TEXT *find_property(int node, char *name) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -811,7 +811,7 @@ static int PROM_TEXT no_proplen(int node, char *name) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -827,7 +827,7 @@ static int PROM_TEXT no_getprop(int node, char *name, char *value) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -850,7 +850,7 @@ static char PROM_TEXT *no_nextprop(int node, char *name) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); struct property *prop; /* convert into virtual address */ @@ -906,7 +906,7 @@ void leon_prom_init(struct leon_prom_info *pspi) pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000; /* Set Available main memory size */ - pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE; + pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE; pspi->avail.num_bytes = pspi->totphys.num_bytes; #undef nodes @@ -951,7 +951,7 @@ extern unsigned short bss_start, bss_end; int prom_init(void) { struct leon_prom_info *pspi = (void *) - ((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET); + ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET); /* disable mmu */ srmmu_set_mmureg(0x00000000); @@ -977,7 +977,7 @@ void prepare_bootargs(char *bootargs) /* if no bootargs set, skip copying ==> default bootline */ if (bootargs && (*bootargs != '\0')) { pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) + - CFG_PROM_OFFSET); + CONFIG_SYS_PROM_OFFSET); src = bootargs; dst = &pspi->arg[0]; left = 255; /* max len */ @@ -994,7 +994,7 @@ void srmmu_init_cpu(unsigned int entry) { sparc_srmmu_setup *psrmmu_tables = (void *) ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) + - CFG_PROM_OFFSET); + CONFIG_SYS_PROM_OFFSET); /* Make context 0 (kernel's context) point * to our prepared memory mapping @@ -1010,21 +1010,21 @@ void srmmu_init_cpu(unsigned int entry) #define PTE 2 #define ACC_SU_ALL 0x1c psrmmu_tables->pgd_table[0xf0] = - (CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE; + (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf1] = - ((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf2] = - ((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf3] = - ((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf4] = - ((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf5] = - ((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf6] = - ((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf7] = - ((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE; /* convert rom vec pointer to virtual address */ kernel_arg_promvec = (struct linux_romvec *) diff --git a/cpu/leon2/serial.c b/cpu/leon2/serial.c index ce9457f..4f41b8e 100644 --- a/cpu/leon2/serial.c +++ b/cpu/leon2/serial.c @@ -57,7 +57,7 @@ int serial_init(void) regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2; #endif - regs->UART_Scaler = CFG_LEON2_UART1_SCALER; + regs->UART_Scaler = CONFIG_SYS_LEON2_UART1_SCALER; /* Let bit 11 be unchanged (debug bit for GRMON) */ tmp = READ_WORD(regs->UART_Control); diff --git a/cpu/leon2/start.S b/cpu/leon2/start.S index f23f499..9b5d83e 100644 --- a/cpu/leon2/start.S +++ b/cpu/leon2/start.S @@ -68,7 +68,7 @@ ARGPUSH = (WINDOWSIZE + 4) MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) /* Number of register windows */ -#ifndef CFG_SPARC_NWINDOWS +#ifndef CONFIG_SYS_SPARC_NWINDOWS #error Must define number of SPARC register windows, default is 8 #endif @@ -280,16 +280,16 @@ leon2_init_ioport: leon2_init_mctrl: /* memory config register 1 */ - set CFG_GRLIB_MEMCFG1, %g2 + set CONFIG_SYS_GRLIB_MEMCFG1, %g2 ld [%g1], %g3 ! and %g3, 0x300, %g3 or %g2, %g3, %g2 st %g2, [%g1 + LEON2_MCFG1] - set CFG_GRLIB_MEMCFG2, %g2 ! Load memory config register 2 + set CONFIG_SYS_GRLIB_MEMCFG2, %g2 ! Load memory config register 2 #if !( defined(TSIM) || !defined(BZIMAGE)) st %g2, [%g1 + LEON2_MCFG2] ! only for prom version, else done by "dumon -i" #endif - set CFG_GRLIB_MEMCFG3, %g2 ! Init FT register + set CONFIG_SYS_GRLIB_MEMCFG3, %g2 ! Init FT register st %g2, [%g1 + LEON2_ECTRL] ld [%g1 + LEON2_ECTRL], %g2 srl %g2, 30, %g2 @@ -310,7 +310,7 @@ leon2_init_psr: nop leon2_init_stackp: - set CFG_INIT_SP_OFFSET, %fp + set CONFIG_SYS_INIT_SP_OFFSET, %fp andn %fp, 0x0f, %fp sub %fp, 64, %sp @@ -327,7 +327,7 @@ cpu_init_unreloc: reloc: set TEXT_START,%g2 set DATA_END,%g3 - set CFG_RELOC_MONITOR_BASE,%g4 + set CONFIG_SYS_RELOC_MONITOR_BASE,%g4 reloc_loop: ldd [%g2],%l0 ldd [%g2+8],%l2 @@ -373,10 +373,10 @@ fixup_got: set __got_end,%g3 /* * new got offset = (old GOT-PTR (read with ld) - - * CFG_RELOC_MONITOR_BASE(from define) ) + + * CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) + * Destination Address (from define) */ - set CFG_RELOC_MONITOR_BASE,%g2 + set CONFIG_SYS_RELOC_MONITOR_BASE,%g2 set TEXT_START, %g1 add %g4,%g2,%g4 sub %g4,%g1,%g4 @@ -397,7 +397,7 @@ got_loop: prom_relocate: set __prom_start, %g2 set __prom_end, %g3 - set CFG_PROM_OFFSET, %g4 + set CONFIG_SYS_PROM_OFFSET, %g4 prom_relocate_loop: ldd [%g2],%l0 @@ -413,7 +413,7 @@ prom_relocate_loop: * the new trap table address */ - set CFG_RELOC_MONITOR_BASE, %g2 + set CONFIG_SYS_RELOC_MONITOR_BASE, %g2 wr %g0, %g2, %tbr /* call relocate*/ @@ -421,14 +421,14 @@ prom_relocate_loop: /* Call relocated init functions */ jump: set cpu_init_f2,%o1 - set CFG_RELOC_MONITOR_BASE,%o2 + set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 add %o1,%o2,%o1 sub %o1,%g1,%o1 call %o1 clr %o0 set board_init_f,%o1 - set CFG_RELOC_MONITOR_BASE,%o2 + set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 add %o1,%o2,%o1 sub %o1,%g1,%o1 call %o1 @@ -454,7 +454,7 @@ _irq_entry: WRITE_PAUSE mov %l7, %o0 ! irq level set handler_irq, %o1 - set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2 + set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2 add %o1, %o2, %o1 call %o1 add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr @@ -472,7 +472,7 @@ _window_overflow: mov %wim, %l3 ! Calculate next WIM mov %g1, %l7 srl %l3, 1, %g1 - sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4 + sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4 or %l4, %g1, %g1 save ! Get into window to be saved. @@ -509,7 +509,7 @@ _window_underflow: mov %wim, %l3 ! Calculate next WIM sll %l3, 1, %l4 - srl %l3, (CFG_SPARC_NWINDOWS-1), %l5 + srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5 or %l5, %l4, %l5 mov %l5, %wim nop; nop; nop @@ -578,7 +578,7 @@ trap_setup: */ srl %t_wim, 0x1, %g2 ! begin computation of new %wim - set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 sll %t_wim, %g3, %t_wim ! NWINDOWS-1 or %t_wim, %g2, %g2 @@ -612,7 +612,7 @@ ret_trap_entry: mov 2, %g1 sll %g1, %t_psr, %g1 - set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS + set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS srl %g1, %g2, %g2 or %g1, %g2, %g1 @@ -622,7 +622,7 @@ ret_trap_entry: sll %g2, 0x1, %g1 /* We have to grab a window before returning. */ - set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 srl %g2, %g3, %g2 or %g1, %g2, %g1 diff --git a/cpu/leon3/cpu_init.c b/cpu/leon3/cpu_init.c index 4fe7d4b..be22ec2 100644 --- a/cpu/leon3/cpu_init.c +++ b/cpu/leon3/cpu_init.c @@ -159,9 +159,9 @@ int init_memory_ctrl() mctrl = (ambapp_dev_mctrl *) base; /* config MCTRL memory controller */ - mctrl->mcfg1 = CFG_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300); - mctrl->mcfg2 = CFG_GRLIB_MEMCFG2; - mctrl->mcfg3 = CFG_GRLIB_MEMCFG3; + mctrl->mcfg1 = CONFIG_SYS_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300); + mctrl->mcfg2 = CONFIG_SYS_GRLIB_MEMCFG2; + mctrl->mcfg3 = CONFIG_SYS_GRLIB_MEMCFG3; not_found_mctrl = 0; } @@ -171,9 +171,9 @@ int init_memory_ctrl() mctrl = (ambapp_dev_mctrl *) base; /* config MCTRL memory controller */ - mctrl->mcfg1 = CFG_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300); - mctrl->mcfg2 = CFG_GRLIB_FT_MEMCFG2; - mctrl->mcfg3 = CFG_GRLIB_FT_MEMCFG3; + mctrl->mcfg1 = CONFIG_SYS_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300); + mctrl->mcfg2 = CONFIG_SYS_GRLIB_FT_MEMCFG2; + mctrl->mcfg3 = CONFIG_SYS_GRLIB_FT_MEMCFG3; not_found_mctrl = 0; } @@ -183,7 +183,7 @@ int init_memory_ctrl() sdctrl = (ambapp_dev_sdctrl *) base; /* config memory controller */ - sdctrl->sdcfg = CFG_GRLIB_SDRAM; + sdctrl->sdcfg = CONFIG_SYS_GRLIB_SDRAM; not_found_mctrl = 0; } @@ -192,8 +192,8 @@ int init_memory_ctrl() ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1); /* Config DDR2 memory controller */ - ddr2spa->cfg1 = CFG_GRLIB_DDR2_CFG1; - ddr2spa->cfg3 = CFG_GRLIB_DDR2_CFG3; + ddr2spa->cfg1 = CONFIG_SYS_GRLIB_DDR2_CFG1; + ddr2spa->cfg3 = CONFIG_SYS_GRLIB_DDR2_CFG3; not_found_mctrl = 0; } @@ -202,7 +202,7 @@ int init_memory_ctrl() ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1); /* Config DDR memory controller */ - ddrspa->ctrl = CFG_GRLIB_DDR_CFG; + ddrspa->ctrl = CONFIG_SYS_GRLIB_DDR_CFG; not_found_mctrl = 0; } diff --git a/cpu/leon3/interrupts.c b/cpu/leon3/interrupts.c index 2692632..ac6aca5 100644 --- a/cpu/leon3/interrupts.c +++ b/cpu/leon3/interrupts.c @@ -104,8 +104,8 @@ static void leon3_ic_enable(unsigned int irq) void handler_irq(int irq, struct pt_regs *regs) { if (irq_handlers[irq].handler) { - if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) || - ((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE) + if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) || + ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE) ) { printf("handler_irq: bad handler: %x, irq number %d\n", (unsigned int)irq_handlers[irq].handler, irq); @@ -165,8 +165,8 @@ void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", (ulong) handler, (ulong) irq_handlers[irq].handler); - if (((unsigned int)handler > CFG_RAM_END) || - ((unsigned int)handler < CFG_RAM_BASE) + if (((unsigned int)handler > CONFIG_SYS_RAM_END) || + ((unsigned int)handler < CONFIG_SYS_RAM_BASE) ) { printf("irq_install_handler: bad handler: %x, irq number %d\n", (unsigned int)handler, irq); diff --git a/cpu/leon3/prom.c b/cpu/leon3/prom.c index 9fa2d04..18d2fb2 100644 --- a/cpu/leon3/prom.c +++ b/cpu/leon3/prom.c @@ -49,14 +49,14 @@ ambapp_dev_gptimer *gptimer; /* for __va */ extern int __prom_start; #define PAGE_OFFSET 0xf0000000 -#define phys_base CFG_SDRAM_BASE +#define phys_base CONFIG_SYS_SDRAM_BASE #define PROM_OFFS 8192 #define PROM_SIZE_MASK (PROM_OFFS-1) #define __va(x) ( \ (void *)( ((unsigned long)(x))-PROM_OFFS+ \ - (CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \ + (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \ ) -#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE)) +#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-TEXT_BASE)) struct property { char *name; @@ -545,13 +545,13 @@ static struct leon_prom_info PROM_DATA spi = { __va(&spi.totphys), { NULL, - (char *)CFG_SDRAM_BASE, + (char *)CONFIG_SYS_SDRAM_BASE, 0, }, __va(&spi.avail), { NULL, - (char *)CFG_SDRAM_BASE, + (char *)CONFIG_SYS_SDRAM_BASE, 0, }, NULL, /* prommap_p */ @@ -659,7 +659,7 @@ static void PROM_TEXT leon_reboot(char *bcommand) /* get physical address */ struct leon_prom_info *pspi = - (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); unsigned int *srmmu_ctx_table; @@ -712,7 +712,7 @@ static void PROM_TEXT leon_reboot_physical(char *bcommand) srmmu_set_mmureg(0); /* Hardcoded start address */ - reset = CFG_MONITOR_BASE; + reset = CONFIG_SYS_MONITOR_BASE; /* flush data cache */ sparc_dcache_flush_all(); @@ -742,7 +742,7 @@ static int PROM_TEXT leon_nbputchar(int c) /* get physical address */ struct leon_prom_info *pspi = - (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); uart = (ambapp_dev_apbuart *) SPARC_BYPASS_READ(&pspi->reloc_funcs.leon3_apbuart); @@ -778,7 +778,7 @@ static int PROM_TEXT no_nextnode(int node) { /* get physical address */ struct leon_prom_info *pspi = - (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -793,7 +793,7 @@ static int PROM_TEXT no_child(int node) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -808,7 +808,7 @@ static struct property PROM_TEXT *find_property(int node, char *name) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -827,7 +827,7 @@ static int PROM_TEXT no_proplen(int node, char *name) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -843,7 +843,7 @@ static int PROM_TEXT no_getprop(int node, char *name, char *value) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); /* convert into virtual address */ pspi = (struct leon_prom_info *) @@ -866,7 +866,7 @@ static char PROM_TEXT *no_nextprop(int node, char *name) { /* get physical address */ struct leon_prom_info *pspi = (struct leon_prom_info *) - (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables)); struct property *prop; /* convert into virtual address */ @@ -922,7 +922,7 @@ void leon_prom_init(struct leon_prom_info *pspi) pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000; /* Set Available main memory size */ - pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE; + pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE; pspi->avail.num_bytes = pspi->totphys.num_bytes; /* Set the pointer to the Console UART in romvec */ @@ -982,7 +982,7 @@ extern unsigned short bss_start, bss_end; int prom_init(void) { struct leon_prom_info *pspi = (void *) - ((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET); + ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET); /* disable mmu */ srmmu_set_mmureg(0x00000000); @@ -1008,7 +1008,7 @@ void prepare_bootargs(char *bootargs) /* if no bootargs set, skip copying ==> default bootline */ if (bootargs && (*bootargs != '\0')) { pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) + - CFG_PROM_OFFSET); + CONFIG_SYS_PROM_OFFSET); src = bootargs; dst = &pspi->arg[0]; left = 255; /* max len */ @@ -1025,7 +1025,7 @@ void srmmu_init_cpu(unsigned int entry) { sparc_srmmu_setup *psrmmu_tables = (void *) ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) + - CFG_PROM_OFFSET); + CONFIG_SYS_PROM_OFFSET); /* Make context 0 (kernel's context) point * to our prepared memory mapping @@ -1041,21 +1041,21 @@ void srmmu_init_cpu(unsigned int entry) #define PTE 2 #define ACC_SU_ALL 0x1c psrmmu_tables->pgd_table[0xf0] = - (CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE; + (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf1] = - ((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf2] = - ((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf3] = - ((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf4] = - ((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf5] = - ((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf6] = - ((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE; psrmmu_tables->pgd_table[0xf7] = - ((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE; + ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE; /* convert rom vec pointer to virtual address */ kernel_arg_promvec = (struct linux_romvec *) diff --git a/cpu/leon3/serial.c b/cpu/leon3/serial.c index 27d5cd3..4b2fcb8 100644 --- a/cpu/leon3/serial.c +++ b/cpu/leon3/serial.c @@ -58,7 +58,7 @@ int serial_init(void) * * Receiver & transmitter enable */ - leon3_apbuart->scaler = CFG_GRLIB_APBUART_SCALER; + leon3_apbuart->scaler = CONFIG_SYS_GRLIB_APBUART_SCALER; /* Let bit 11 be unchanged (debug bit for GRMON) */ tmp = READ_WORD(leon3_apbuart->ctrl); diff --git a/cpu/leon3/start.S b/cpu/leon3/start.S index d421898..7afe10e 100644 --- a/cpu/leon3/start.S +++ b/cpu/leon3/start.S @@ -68,7 +68,7 @@ ARGPUSH = (WINDOWSIZE + 4) MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) /* Number of register windows */ -#ifndef CFG_SPARC_NWINDOWS +#ifndef CONFIG_SYS_SPARC_NWINDOWS #error Must define number of SPARC register windows, default is 8 #endif @@ -251,7 +251,7 @@ wininit: mov %g3, %wim stackp: - set CFG_INIT_SP_OFFSET, %fp + set CONFIG_SYS_INIT_SP_OFFSET, %fp andn %fp, 0x0f, %fp sub %fp, 64, %sp @@ -268,7 +268,7 @@ cpu_init_unreloc: reloc: set TEXT_START,%g2 set DATA_END,%g3 - set CFG_RELOC_MONITOR_BASE,%g4 + set CONFIG_SYS_RELOC_MONITOR_BASE,%g4 reloc_loop: ldd [%g2],%l0 ldd [%g2+8],%l2 @@ -314,10 +314,10 @@ fixup_got: set __got_end,%g3 /* * new got offset = (old GOT-PTR (read with ld) - - * CFG_RELOC_MONITOR_BASE(from define) ) + + * CONFIG_SYS_RELOC_MONITOR_BASE(from define) ) + * Destination Address (from define) */ - set CFG_RELOC_MONITOR_BASE,%g2 + set CONFIG_SYS_RELOC_MONITOR_BASE,%g2 set TEXT_START, %g1 add %g4,%g2,%g4 sub %g4,%g1,%g4 @@ -338,7 +338,7 @@ got_loop: prom_relocate: set __prom_start, %g2 set __prom_end, %g3 - set CFG_PROM_OFFSET, %g4 + set CONFIG_SYS_PROM_OFFSET, %g4 prom_relocate_loop: ldd [%g2],%l0 @@ -354,7 +354,7 @@ prom_relocate_loop: * the new trap table address */ - set CFG_RELOC_MONITOR_BASE, %g2 + set CONFIG_SYS_RELOC_MONITOR_BASE, %g2 wr %g0, %g2, %tbr nop nop @@ -368,22 +368,22 @@ snoop_detect: sethi %hi(0x00800000), %o0 lda [%g0] 2, %o1 and %o0, %o1, %o0 - sethi %hi(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o1 - st %o0, [%lo(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE)+%o1] + sethi %hi(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o1 + st %o0, [%lo(leon3_snooping_avail+CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE)+%o1] /* call relocate*/ nop /* Call relocated init functions */ jump: set cpu_init_f2,%o1 - set CFG_RELOC_MONITOR_BASE,%o2 + set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 add %o1,%o2,%o1 sub %o1,%g1,%o1 call %o1 clr %o0 set board_init_f,%o1 - set CFG_RELOC_MONITOR_BASE,%o2 + set CONFIG_SYS_RELOC_MONITOR_BASE,%o2 add %o1,%o2,%o1 sub %o1,%g1,%o1 call %o1 @@ -409,7 +409,7 @@ _irq_entry: WRITE_PAUSE mov %l7, %o0 ! irq level set handler_irq, %o1 - set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2 + set (CONFIG_SYS_RELOC_MONITOR_BASE-TEXT_BASE), %o2 add %o1, %o2, %o1 call %o1 add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr @@ -427,7 +427,7 @@ _window_overflow: mov %wim, %l3 ! Calculate next WIM mov %g1, %l7 srl %l3, 1, %g1 - sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4 + sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1) , %l4 or %l4, %g1, %g1 save ! Get into window to be saved. @@ -464,7 +464,7 @@ _window_underflow: mov %wim, %l3 ! Calculate next WIM sll %l3, 1, %l4 - srl %l3, (CFG_SPARC_NWINDOWS-1), %l5 + srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5 or %l5, %l4, %l5 mov %l5, %wim nop; nop; nop @@ -533,7 +533,7 @@ trap_setup: */ srl %t_wim, 0x1, %g2 ! begin computation of new %wim - set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 sll %t_wim, %g3, %t_wim ! NWINDOWS-1 or %t_wim, %g2, %g2 @@ -567,7 +567,7 @@ ret_trap_entry: mov 2, %g1 sll %g1, %t_psr, %g1 - set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS + set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS srl %g1, %g2, %g2 or %g1, %g2, %g1 @@ -577,7 +577,7 @@ ret_trap_entry: sll %g2, 0x1, %g1 /* We have to grab a window before returning. */ - set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 srl %g2, %g3, %g2 or %g1, %g2, %g1 diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index 578eb73..8ff3a36 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -94,7 +94,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c index d01787f..5acfe1a 100644 --- a/cpu/lh7a40x/interrupts.c +++ b/cpu/lh7a40x/interrupts.c @@ -59,7 +59,7 @@ int interrupt_init (void) /* * 10ms period with 508.469kHz clock = 5084 */ - timer_load_val = CFG_HZ/100; + timer_load_val = CONFIG_SYS_HZ/100; } /* load value for 10 ms timeout */ @@ -98,12 +98,12 @@ void udelay (unsigned long usec) /* normalize */ if (usec >= 1000) { tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 1000; } else { if (usec > 1) { - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } else @@ -152,11 +152,11 @@ void udelay_masked (unsigned long usec) /* normalize */ if (usec >= 1000) { tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 1000; } else { if (usec > 1) { - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } else { tmo = 1; diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S index e4655d6..11252ce 100644 --- a/cpu/lh7a40x/start.S +++ b/cpu/lh7a40x/start.S @@ -172,8 +172,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -285,8 +285,8 @@ cpu_init_crit: sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r3} @ get pc, cpsr add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -318,8 +318,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c index cf29559..0f1dd1f 100644 --- a/cpu/mcf5227x/cpu_init.c +++ b/cpu/mcf5227x/cpu_init.c @@ -58,40 +58,40 @@ void cpu_init_f(void) scm1->pacrg = 0; scm1->pacri = 0; -#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) - fbcs->csar0 = CFG_CS0_BASE; - fbcs->cscr0 = CFG_CS0_CTRL; - fbcs->csmr0 = CFG_CS0_MASK; +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif -#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) - fbcs->csar1 = CFG_CS1_BASE; - fbcs->cscr1 = CFG_CS1_CTRL; - fbcs->csmr1 = CFG_CS1_MASK; +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) - fbcs->csar2 = CFG_CS2_BASE; - fbcs->cscr2 = CFG_CS2_CTRL; - fbcs->csmr2 = CFG_CS2_MASK; +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) - fbcs->csar3 = CFG_CS3_BASE; - fbcs->cscr3 = CFG_CS3_CTRL; - fbcs->csmr3 = CFG_CS3_MASK; +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) - fbcs->csar4 = CFG_CS4_BASE; - fbcs->cscr4 = CFG_CS4_CTRL; - fbcs->csmr4 = CFG_CS4_MASK; +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) - fbcs->csar5 = CFG_CS5_BASE; - fbcs->cscr5 = CFG_CS5_CTRL; - fbcs->csmr5 = CFG_CS5_MASK; +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif #ifdef CONFIG_FSL_I2C @@ -107,12 +107,12 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - u32 oscillator = CFG_RTC_OSCILLATOR; + u32 oscillator = CONFIG_SYS_RTC_OSCILLATOR; - rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; + rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; #endif return (0); @@ -123,7 +123,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_uart &= (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); diff --git a/cpu/mcf5227x/interrupts.c b/cpu/mcf5227x/interrupts.c index 9572a7b..85828a6 100644 --- a/cpu/mcf5227x/interrupts.c +++ b/cpu/mcf5227x/interrupts.c @@ -31,7 +31,7 @@ int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ intp->imrh0 |= 0xFFFFFFFF; @@ -44,9 +44,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; - intp->imrh0 &= ~CFG_TMRINTR_MASK; + intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; + intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; } #endif diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c index 0baf9bc..74b9059 100644 --- a/cpu/mcf5227x/speed.c +++ b/cpu/mcf5227x/speed.c @@ -99,14 +99,14 @@ int get_clocks(void) /* serial mode */ } else { /* Normal Mode */ - vco = pfdr * CFG_INPUT_CLKSRC; + vco = pfdr * CONFIG_SYS_INPUT_CLKSRC; gd->vco_clk = vco; } if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ } else { - gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; gd->cpu_clk = vco / temp; /* cpu clock */ diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index 1b47c97..becaab7 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -29,9 +29,9 @@ #endif /* last three long word reserved for cache status */ -#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) -#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) -#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) #define _START _start #define _FAULT _fault @@ -132,10 +132,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CFG_FLASH_BASE, %d0 + move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -156,7 +156,7 @@ _start: /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -187,7 +187,7 @@ relocate_code: move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CFG_MONITOR_BASE, %a1 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 @@ -202,7 +202,7 @@ relocate_code: * initialization, now running from RAM. */ move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 jmp (%a1) in_ram: @@ -212,9 +212,9 @@ clear_bss: * Now clear BSS segment */ move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 6: clr.l (%a1)+ cmp.l %a1,%d1 @@ -224,11 +224,11 @@ clear_bss: * fix got table in RAM */ move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a1,%a5 /* * fix got pointer register a5 */ move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 7: move.l (%a1),%d1 @@ -240,7 +240,7 @@ clear_bss: /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ @@ -276,7 +276,7 @@ icache_enable: move.l #0x01200000, %d0 /* Invalid cache */ movec %d0, %CACR - move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 + move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 movec %d0, %ACR0 move.l #0x81600610, %d0 /* Enable cache */ diff --git a/cpu/mcf523x/cpu.c b/cpu/mcf523x/cpu.c index bdc152f..1ce90fd 100644 --- a/cpu/mcf523x/cpu.c +++ b/cpu/mcf523x/cpu.c @@ -98,7 +98,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CFG_CLK / CFG_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); wdog_module |= (wdog_module / 8192); wdp->mr = wdog_module; diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c index 8ab5b8e..6520944 100644 --- a/cpu/mcf523x/cpu_init.c +++ b/cpu/mcf523x/cpu_init.c @@ -49,69 +49,69 @@ void cpu_init_f(void) wdog->cr = 0; #endif - scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); /* Port configuration */ gpio->par_cs = 0; -#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) - fbcs->csar0 = CFG_CS0_BASE; - fbcs->cscr0 = CFG_CS0_CTRL; - fbcs->csmr0 = CFG_CS0_MASK; +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif -#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS1; - fbcs->csar1 = CFG_CS1_BASE; - fbcs->cscr1 = CFG_CS1_CTRL; - fbcs->csmr1 = CFG_CS1_MASK; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS2; - fbcs->csar2 = CFG_CS2_BASE; - fbcs->cscr2 = CFG_CS2_CTRL; - fbcs->csmr2 = CFG_CS2_MASK; + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS3; - fbcs->csar3 = CFG_CS3_BASE; - fbcs->cscr3 = CFG_CS3_CTRL; - fbcs->csmr3 = CFG_CS3_MASK; + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS4; - fbcs->csar4 = CFG_CS4_BASE; - fbcs->cscr4 = CFG_CS4_CTRL; - fbcs->csmr4 = CFG_CS4_MASK; + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS5; - fbcs->csar5 = CFG_CS5_BASE; - fbcs->cscr5 = CFG_CS5_CTRL; - fbcs->csmr5 = CFG_CS5_MASK; + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif -#if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL)) +#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS6; - fbcs->csar6 = CFG_CS6_BASE; - fbcs->cscr6 = CFG_CS6_CTRL; - fbcs->csmr6 = CFG_CS6_MASK; + fbcs->csar6 = CONFIG_SYS_CS6_BASE; + fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; + fbcs->csmr6 = CONFIG_SYS_CS6_MASK; #endif -#if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL)) +#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) gpio->par_cs |= GPIO_PAR_CS_CS7; - fbcs->csar7 = CFG_CS7_BASE; - fbcs->cscr7 = CFG_CS7_CTRL; - fbcs->csmr7 = CFG_CS7_MASK; + fbcs->csar7 = CONFIG_SYS_CS7_BASE; + fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; + fbcs->csmr7 = CONFIG_SYS_CS7_MASK; #endif #ifdef CONFIG_FSL_I2C - CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR; - CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET; + CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; + CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; #endif icache_enable(); @@ -130,7 +130,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); break; diff --git a/cpu/mcf523x/interrupts.c b/cpu/mcf523x/interrupts.c index 125c53b..db5ccdf 100644 --- a/cpu/mcf523x/interrupts.c +++ b/cpu/mcf523x/interrupts.c @@ -28,7 +28,7 @@ int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ intp->imrl0 |= 0x1; @@ -40,10 +40,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; intp->imrl0 &= ~INTC_IPRL_INT0; - intp->imrl0 &= ~CFG_TMRINTR_MASK; + intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK; } #endif diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c index 1bda2d4..6096ba4 100644 --- a/cpu/mcf523x/speed.c +++ b/cpu/mcf523x/speed.c @@ -42,7 +42,7 @@ int get_clocks(void) while (!(pll->synsr & PLL_SYNSR_LOCK)); - gd->bus_clk = CFG_CLK; + gd->bus_clk = CONFIG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); #ifdef CONFIG_FSL_I2C diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S index 2b638df..b70b83b 100644 --- a/cpu/mcf523x/start.S +++ b/cpu/mcf523x/start.S @@ -127,10 +127,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CFG_FLASH_BASE, %d0 + move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -143,14 +143,14 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 move.l %d0, (%a1) move.l %d0, (%a2) /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -181,7 +181,7 @@ relocate_code: move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CFG_MONITOR_BASE, %a1 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 @@ -196,7 +196,7 @@ relocate_code: * initialization, now running from RAM. */ move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 jmp (%a1) in_ram: @@ -206,9 +206,9 @@ clear_bss: * Now clear BSS segment */ move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 6: clr.l (%a1)+ cmp.l %a1,%d1 @@ -218,11 +218,11 @@ clear_bss: * fix got table in RAM */ move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a1,%a5 /* * fix got pointer register a5 */ move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 7: move.l (%a1),%d1 @@ -234,7 +234,7 @@ clear_bss: /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ @@ -270,16 +270,16 @@ icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ nop - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ movec %d0, %ACR0 /* Enable cache */ - move.l #(CFG_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ + move.l #(CONFIG_SYS_FLASH_BASE + 0xc000), %d0 /* Setup cache mask */ movec %d0, %ACR1 /* Enable cache */ move.l #0x80400100, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ nop - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 moveq #1, %d0 move.l %d0, (%a1) rts @@ -292,14 +292,14 @@ icache_disable: movec %d0, %ACR0 movec %d0, %ACR1 - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 moveq #0, %d0 move.l %d0, (%a1) rts .globl icache_status icache_status: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 move.l (%a1), %d0 rts @@ -312,7 +312,7 @@ icache_invalid: .globl dcache_enable dcache_enable: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 moveq #1, %d0 move.l %d0, (%a1) rts @@ -320,14 +320,14 @@ dcache_enable: /* No dcache, just a dummy function */ .globl dcache_disable dcache_disable: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 moveq #0, %d0 move.l %d0, (%a1) rts .globl dcache_status dcache_status: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 move.l (%a1), %d0 rts diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index c25670d..32d6c40 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -66,11 +66,11 @@ int checkcpu(void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CFG_CLK)); + cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CFG_CLK)); + pin, prn, strmhz(buf, CONFIG_SYS_CLK)); return 0; } @@ -174,7 +174,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ wdt->wdog_wrrr = - ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; wdt->wdog_wcr = 0; /* reset watchdog counter */ puts("WATCHDOG:enabled\n"); @@ -202,7 +202,7 @@ int checkcpu(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", - strmhz(buf, CFG_CLK)); + strmhz(buf, CONFIG_SYS_CLK)); return 0; }; @@ -236,7 +236,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ wdt->wmr = - ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; wdt->wsr = 0x5555; /* reset watchdog counter */ wdt->wsr = 0xAAAA; @@ -278,7 +278,7 @@ int checkcpu(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", - strmhz(buf, CFG_CLK)); + strmhz(buf, CONFIG_SYS_CLK)); return 0; } @@ -300,7 +300,7 @@ int checkcpu(void) unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", - strmhz(buf, CFG_CLK)); + strmhz(buf, CONFIG_SYS_CLK)); if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 68aefe9..7bb358e 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -72,20 +72,20 @@ void cpu_init_f(void) * Setup chip selects... */ - mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); - mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); - mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); + mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1); + mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1); + mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1); - mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); - mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); - mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); + mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0); + mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0); + mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0); #ifdef CONFIG_FSL_I2C - CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR; - CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET; -#ifdef CFG_I2C2_OFFSET - CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR; - CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET; + CONFIG_SYS_I2C_PINMUX_REG = CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; + CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; +#ifdef CONFIG_SYS_I2C2_OFFSET + CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; + CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; #endif #endif @@ -102,7 +102,7 @@ int cpu_init_r(void) void uart_port_conf(void) { /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: break; case 1: @@ -138,7 +138,7 @@ int cpu_init_r(void) void uart_port_conf(void) { /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD); @@ -169,59 +169,59 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR); + volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - sysctrl->sc_scr = CFG_SCR; - sysctrl->sc_spr = CFG_SPR; + sysctrl->sc_scr = CONFIG_SYS_SCR; + sysctrl->sc_spr = CONFIG_SYS_SPR; /* Setup Ports: */ - gpio->gpio_pacnt = CFG_PACNT; - gpio->gpio_paddr = CFG_PADDR; - gpio->gpio_padat = CFG_PADAT; - gpio->gpio_pbcnt = CFG_PBCNT; - gpio->gpio_pbddr = CFG_PBDDR; - gpio->gpio_pbdat = CFG_PBDAT; - gpio->gpio_pdcnt = CFG_PDCNT; + gpio->gpio_pacnt = CONFIG_SYS_PACNT; + gpio->gpio_paddr = CONFIG_SYS_PADDR; + gpio->gpio_padat = CONFIG_SYS_PADAT; + gpio->gpio_pbcnt = CONFIG_SYS_PBCNT; + gpio->gpio_pbddr = CONFIG_SYS_PBDDR; + gpio->gpio_pbdat = CONFIG_SYS_PBDAT; + gpio->gpio_pdcnt = CONFIG_SYS_PDCNT; /* Memory Controller: */ - csctrl->cs_br0 = CFG_BR0_PRELIM; - csctrl->cs_or0 = CFG_OR0_PRELIM; + csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM; + csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM; -#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - csctrl->cs_br1 = CFG_BR1_PRELIM; - csctrl->cs_or1 = CFG_OR1_PRELIM; +#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) + csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM; + csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM; #endif -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - csctrl->cs_br2 = CFG_BR2_PRELIM; - csctrl->cs_or2 = CFG_OR2_PRELIM; +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) + csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM; + csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM; #endif -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - csctrl->cs_br3 = CFG_BR3_PRELIM; - csctrl->cs_or3 = CFG_OR3_PRELIM; +#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) + csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM; + csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM; #endif -#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - csctrl->cs_br4 = CFG_BR4_PRELIM; - csctrl->cs_or4 = CFG_OR4_PRELIM; +#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) + csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM; + csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM; #endif -#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - csctrl->cs_br5 = CFG_BR5_PRELIM; - csctrl->cs_or5 = CFG_OR5_PRELIM; +#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) + csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM; + csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM; #endif -#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - csctrl->cs_br6 = CFG_BR6_PRELIM; - csctrl->cs_or6 = CFG_OR6_PRELIM; +#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) + csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM; + csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM; #endif -#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - csctrl->cs_br7 = CFG_BR7_PRELIM; - csctrl->cs_or7 = CFG_OR7_PRELIM; +#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) + csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM; + csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM; #endif #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ @@ -244,7 +244,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); @@ -282,57 +282,57 @@ void cpu_init_f(void) /* Memory Controller: */ /* Flash */ - csctrl_reg->ar0 = CFG_AR0_PRELIM; - csctrl_reg->cr0 = CFG_CR0_PRELIM; - csctrl_reg->mr0 = CFG_MR0_PRELIM; + csctrl_reg->ar0 = CONFIG_SYS_AR0_PRELIM; + csctrl_reg->cr0 = CONFIG_SYS_CR0_PRELIM; + csctrl_reg->mr0 = CONFIG_SYS_MR0_PRELIM; -#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM)) - csctrl_reg->ar1 = CFG_AR1_PRELIM; - csctrl_reg->cr1 = CFG_CR1_PRELIM; - csctrl_reg->mr1 = CFG_MR1_PRELIM; +#if (defined(CONFIG_SYS_AR1_PRELIM) && defined(CONFIG_SYS_CR1_PRELIM) && defined(CONFIG_SYS_MR1_PRELIM)) + csctrl_reg->ar1 = CONFIG_SYS_AR1_PRELIM; + csctrl_reg->cr1 = CONFIG_SYS_CR1_PRELIM; + csctrl_reg->mr1 = CONFIG_SYS_MR1_PRELIM; #endif -#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM)) - csctrl_reg->ar2 = CFG_AR2_PRELIM; - csctrl_reg->cr2 = CFG_CR2_PRELIM; - csctrl_reg->mr2 = CFG_MR2_PRELIM; +#if (defined(CONFIG_SYS_AR2_PRELIM) && defined(CONFIG_SYS_CR2_PRELIM) && defined(CONFIG_SYS_MR2_PRELIM)) + csctrl_reg->ar2 = CONFIG_SYS_AR2_PRELIM; + csctrl_reg->cr2 = CONFIG_SYS_CR2_PRELIM; + csctrl_reg->mr2 = CONFIG_SYS_MR2_PRELIM; #endif -#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM)) - csctrl_reg->ar3 = CFG_AR3_PRELIM; - csctrl_reg->cr3 = CFG_CR3_PRELIM; - csctrl_reg->mr3 = CFG_MR3_PRELIM; +#if (defined(CONFIG_SYS_AR3_PRELIM) && defined(CONFIG_SYS_CR3_PRELIM) && defined(CONFIG_SYS_MR3_PRELIM)) + csctrl_reg->ar3 = CONFIG_SYS_AR3_PRELIM; + csctrl_reg->cr3 = CONFIG_SYS_CR3_PRELIM; + csctrl_reg->mr3 = CONFIG_SYS_MR3_PRELIM; #endif -#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM)) - csctrl_reg->ar4 = CFG_AR4_PRELIM; - csctrl_reg->cr4 = CFG_CR4_PRELIM; - csctrl_reg->mr4 = CFG_MR4_PRELIM; +#if (defined(CONFIG_SYS_AR4_PRELIM) && defined(CONFIG_SYS_CR4_PRELIM) && defined(CONFIG_SYS_MR4_PRELIM)) + csctrl_reg->ar4 = CONFIG_SYS_AR4_PRELIM; + csctrl_reg->cr4 = CONFIG_SYS_CR4_PRELIM; + csctrl_reg->mr4 = CONFIG_SYS_MR4_PRELIM; #endif -#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM)) - csctrl_reg->ar5 = CFG_AR5_PRELIM; - csctrl_reg->cr5 = CFG_CR5_PRELIM; - csctrl_reg->mr5 = CFG_MR5_PRELIM; +#if (defined(CONFIG_SYS_AR5_PRELIM) && defined(CONFIG_SYS_CR5_PRELIM) && defined(CONFIG_SYS_MR5_PRELIM)) + csctrl_reg->ar5 = CONFIG_SYS_AR5_PRELIM; + csctrl_reg->cr5 = CONFIG_SYS_CR5_PRELIM; + csctrl_reg->mr5 = CONFIG_SYS_MR5_PRELIM; #endif -#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM)) - csctrl_reg->ar6 = CFG_AR6_PRELIM; - csctrl_reg->cr6 = CFG_CR6_PRELIM; - csctrl_reg->mr6 = CFG_MR6_PRELIM; +#if (defined(CONFIG_SYS_AR6_PRELIM) && defined(CONFIG_SYS_CR6_PRELIM) && defined(CONFIG_SYS_MR6_PRELIM)) + csctrl_reg->ar6 = CONFIG_SYS_AR6_PRELIM; + csctrl_reg->cr6 = CONFIG_SYS_CR6_PRELIM; + csctrl_reg->mr6 = CONFIG_SYS_MR6_PRELIM; #endif -#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM)) - csctrl_reg->ar7 = CFG_AR7_PRELIM; - csctrl_reg->cr7 = CFG_CR7_PRELIM; - csctrl_reg->mr7 = CFG_MR7_PRELIM; +#if (defined(CONFIG_SYS_AR7_PRELIM) && defined(CONFIG_SYS_CR7_PRELIM) && defined(CONFIG_SYS_MR7_PRELIM)) + csctrl_reg->ar7 = CONFIG_SYS_AR7_PRELIM; + csctrl_reg->cr7 = CONFIG_SYS_CR7_PRELIM; + csctrl_reg->mr7 = CONFIG_SYS_MR7_PRELIM; #endif #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ #ifdef CONFIG_FSL_I2C - CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR; - CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET; + CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; + CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; #endif /* enable instruction cache now */ @@ -352,7 +352,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_uart |= UART0_ENABLE_MASK; break; @@ -384,155 +384,155 @@ void cpu_init_f(void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); + MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; MCFGPIO_PBCDPAR = 0xc0; /* Set up the GPIO ports */ -#ifdef CFG_PEPAR - MCFGPIO_PEPAR = CFG_PEPAR; +#ifdef CONFIG_SYS_PEPAR + MCFGPIO_PEPAR = CONFIG_SYS_PEPAR; #endif -#ifdef CFG_PFPAR - MCFGPIO_PFPAR = CFG_PFPAR; +#ifdef CONFIG_SYS_PFPAR + MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; #endif -#ifdef CFG_PJPAR - MCFGPIO_PJPAR = CFG_PJPAR; +#ifdef CONFIG_SYS_PJPAR + MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; #endif -#ifdef CFG_PSDPAR - MCFGPIO_PSDPAR = CFG_PSDPAR; +#ifdef CONFIG_SYS_PSDPAR + MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; #endif -#ifdef CFG_PASPAR - MCFGPIO_PASPAR = CFG_PASPAR; +#ifdef CONFIG_SYS_PASPAR + MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; #endif -#ifdef CFG_PEHLPAR - MCFGPIO_PEHLPAR = CFG_PEHLPAR; +#ifdef CONFIG_SYS_PEHLPAR + MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; #endif -#ifdef CFG_PQSPAR - MCFGPIO_PQSPAR = CFG_PQSPAR; +#ifdef CONFIG_SYS_PQSPAR + MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; #endif -#ifdef CFG_PTCPAR - MCFGPIO_PTCPAR = CFG_PTCPAR; +#ifdef CONFIG_SYS_PTCPAR + MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR; #endif -#ifdef CFG_PTDPAR - MCFGPIO_PTDPAR = CFG_PTDPAR; +#ifdef CONFIG_SYS_PTDPAR + MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif -#ifdef CFG_PUAPAR - MCFGPIO_PUAPAR = CFG_PUAPAR; +#ifdef CONFIG_SYS_PUAPAR + MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; #endif -#ifdef CFG_DDRUA - MCFGPIO_DDRUA = CFG_DDRUA; +#ifdef CONFIG_SYS_DDRUA + MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; #endif /* This is probably a bad place to setup chip selects, but everyone else is doing it! */ -#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \ - defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS) +#if defined(CONFIG_SYS_CS0_BASE) & defined(CONFIG_SYS_CS0_SIZE) & \ + defined(CONFIG_SYS_CS0_WIDTH) & defined(CONFIG_SYS_CS0_WS) - MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; + MCFCSM_CSAR0 = (CONFIG_SYS_CS0_BASE >> 16) & 0xFFFF; -#if (CFG_CS0_WIDTH == 8) -#define CFG_CS0_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS0_WIDTH == 16) -#define CFG_CS0_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS0_WIDTH == 32) -#define CFG_CS0_PS MCFCSM_CSCR_PS_32 +#if (CONFIG_SYS_CS0_WIDTH == 8) +#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_8 +#elif (CONFIG_SYS_CS0_WIDTH == 16) +#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_16 +#elif (CONFIG_SYS_CS0_WIDTH == 32) +#define CONFIG_SYS_CS0_PS MCFCSM_CSCR_PS_32 #else -#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" +#error "CONFIG_SYS_CS0_WIDTH: Fault - wrong bus with for CS0" #endif - MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) - | CFG_CS0_PS | MCFCSM_CSCR_AA; + MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CONFIG_SYS_CS0_WS) + | CONFIG_SYS_CS0_PS | MCFCSM_CSCR_AA; -#if (CFG_CS0_RO != 0) - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) +#if (CONFIG_SYS_CS0_RO != 0) + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; #else - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS0_SIZE - 1) | MCFCSM_CSMR_V; #endif #else #warning "Chip Select 0 are not initialized/used" #endif -#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ - defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS) +#if defined(CONFIG_SYS_CS1_BASE) & defined(CONFIG_SYS_CS1_SIZE) & \ + defined(CONFIG_SYS_CS1_WIDTH) & defined(CONFIG_SYS_CS1_WS) - MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; + MCFCSM_CSAR1 = (CONFIG_SYS_CS1_BASE >> 16) & 0xFFFF; -#if (CFG_CS1_WIDTH == 8) -#define CFG_CS1_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS1_WIDTH == 16) -#define CFG_CS1_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS1_WIDTH == 32) -#define CFG_CS1_PS MCFCSM_CSCR_PS_32 +#if (CONFIG_SYS_CS1_WIDTH == 8) +#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_8 +#elif (CONFIG_SYS_CS1_WIDTH == 16) +#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_16 +#elif (CONFIG_SYS_CS1_WIDTH == 32) +#define CONFIG_SYS_CS1_PS MCFCSM_CSCR_PS_32 #else -#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" +#error "CONFIG_SYS_CS1_WIDTH: Fault - wrong bus with for CS1" #endif - MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) - | CFG_CS1_PS | MCFCSM_CSCR_AA; + MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CONFIG_SYS_CS1_WS) + | CONFIG_SYS_CS1_PS | MCFCSM_CSCR_AA; -#if (CFG_CS1_RO != 0) - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) +#if (CONFIG_SYS_CS1_RO != 0) + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1) | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; #else - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS1_SIZE - 1) | MCFCSM_CSMR_V; #endif #else #warning "Chip Select 1 are not initialized/used" #endif -#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ - defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS) +#if defined(CONFIG_SYS_CS2_BASE) & defined(CONFIG_SYS_CS2_SIZE) & \ + defined(CONFIG_SYS_CS2_WIDTH) & defined(CONFIG_SYS_CS2_WS) - MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; + MCFCSM_CSAR2 = (CONFIG_SYS_CS2_BASE >> 16) & 0xFFFF; -#if (CFG_CS2_WIDTH == 8) -#define CFG_CS2_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS2_WIDTH == 16) -#define CFG_CS2_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS2_WIDTH == 32) -#define CFG_CS2_PS MCFCSM_CSCR_PS_32 +#if (CONFIG_SYS_CS2_WIDTH == 8) +#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_8 +#elif (CONFIG_SYS_CS2_WIDTH == 16) +#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_16 +#elif (CONFIG_SYS_CS2_WIDTH == 32) +#define CONFIG_SYS_CS2_PS MCFCSM_CSCR_PS_32 #else -#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" +#error "CONFIG_SYS_CS2_WIDTH: Fault - wrong bus with for CS2" #endif - MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) - | CFG_CS2_PS | MCFCSM_CSCR_AA; + MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CONFIG_SYS_CS2_WS) + | CONFIG_SYS_CS2_PS | MCFCSM_CSCR_AA; -#if (CFG_CS2_RO != 0) - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) +#if (CONFIG_SYS_CS2_RO != 0) + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1) | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; #else - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS2_SIZE - 1) | MCFCSM_CSMR_V; #endif #else #warning "Chip Select 2 are not initialized/used" #endif -#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ - defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS) +#if defined(CONFIG_SYS_CS3_BASE) & defined(CONFIG_SYS_CS3_SIZE) & \ + defined(CONFIG_SYS_CS3_WIDTH) & defined(CONFIG_SYS_CS3_WS) - MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; + MCFCSM_CSAR3 = (CONFIG_SYS_CS3_BASE >> 16) & 0xFFFF; -#if (CFG_CS3_WIDTH == 8) -#define CFG_CS3_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS3_WIDTH == 16) -#define CFG_CS3_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS3_WIDTH == 32) -#define CFG_CS3_PS MCFCSM_CSCR_PS_32 +#if (CONFIG_SYS_CS3_WIDTH == 8) +#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_8 +#elif (CONFIG_SYS_CS3_WIDTH == 16) +#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_16 +#elif (CONFIG_SYS_CS3_WIDTH == 32) +#define CONFIG_SYS_CS3_PS MCFCSM_CSCR_PS_32 #else -#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" +#error "CONFIG_SYS_CS3_WIDTH: Fault - wrong bus with for CS1" #endif - MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) - | CFG_CS3_PS | MCFCSM_CSCR_AA; + MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CONFIG_SYS_CS3_WS) + | CONFIG_SYS_CS3_PS | MCFCSM_CSCR_AA; -#if (CFG_CS3_RO != 0) - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) +#if (CONFIG_SYS_CS3_RO != 0) + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1) | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; #else - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CONFIG_SYS_CS3_SIZE - 1) | MCFCSM_CSMR_V; #endif #else @@ -556,7 +556,7 @@ int cpu_init_r(void) void uart_port_conf(void) { /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: MCFGPIO_PUAPAR &= 0xFc; MCFGPIO_PUAPAR |= 0x03; @@ -589,12 +589,12 @@ void cpu_init_f(void) * which is their primary function. * ~Jeremy */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT); + mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); /* * dBug Compliance: @@ -636,13 +636,13 @@ void cpu_init_f(void) * Setup chip selects... */ - mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); - mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); - mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); + mbar_writeShort(MCFSIM_CSAR1, CONFIG_SYS_CSAR1); + mbar_writeShort(MCFSIM_CSCR1, CONFIG_SYS_CSCR1); + mbar_writeLong(MCFSIM_CSMR1, CONFIG_SYS_CSMR1); - mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); - mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); - mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); + mbar_writeShort(MCFSIM_CSAR0, CONFIG_SYS_CSAR0); + mbar_writeShort(MCFSIM_CSCR0, CONFIG_SYS_CSCR0); + mbar_writeLong(MCFSIM_CSMR0, CONFIG_SYS_CSMR0); /* enable instruction cache now */ icache_enable(); @@ -659,7 +659,7 @@ int cpu_init_r(void) void uart_port_conf(void) { /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: break; case 1: diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index b8fb7bb..0181e4b 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -51,10 +51,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE); + volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); intp->int_icr1 &= ~INT_ICR1_TMR3MASK; - intp->int_icr1 |= CFG_TMRINTR_PRI; + intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI; } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ @@ -62,7 +62,7 @@ void dtimer_intr_setup(void) #if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ intp->imrl0 |= 0x1; @@ -74,11 +74,11 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; intp->imrl0 &= 0xFFFFFFFE; - intp->imrl0 &= ~CFG_TMRINTR_MASK; + intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK; } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ @@ -95,7 +95,7 @@ int interrupt_init(void) void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI); + mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index 4cb8f93..fe51fb4 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -39,11 +39,11 @@ int get_clocks (void) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; -#ifndef CFG_PLL_BYPASS +#ifndef CONFIG_SYS_PLL_BYPASS #ifdef CONFIG_M5249 /* Setup the PLL to run at the specified speed */ -#ifdef CFG_FAST_CLK +#ifdef CONFIG_SYS_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ @@ -51,7 +51,7 @@ int get_clocks (void) #endif /* CONFIG_M5249 */ #ifdef CONFIG_M5253 - pllcr = CFG_PLLCR; + pllcr = CONFIG_SYS_PLLCR; #endif /* CONFIG_M5253 */ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ @@ -60,7 +60,7 @@ int get_clocks (void) pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CFG_PLL_BYPASS */ +#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ @@ -76,7 +76,7 @@ int get_clocks (void) ; #endif - gd->cpu_clk = CFG_CLK; + gd->cpu_clk = CONFIG_SYS_CLK; #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; #else @@ -85,7 +85,7 @@ int get_clocks (void) #ifdef CONFIG_FSL_I2C gd->i2c1_clk = gd->bus_clk; -#ifdef CFG_I2C2_OFFSET +#ifdef CONFIG_SYS_I2C2_OFFSET gd->i2c2_clk = gd->bus_clk; #endif #endif diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 2e8ecfb..da45bcb 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -56,7 +56,7 @@ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) +#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) .long _start - TEXT_BASE #else .long _START @@ -103,9 +103,9 @@ _vectors: .text -#if defined(CFG_INT_FLASH_BASE) && \ +#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ (defined(CONFIG_M5282) || defined(CONFIG_M5281)) - #if (TEXT_BASE == CFG_INT_FLASH_BASE) + #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ .long 0xFFFFFFFF /* all sectors protected */ .long 0x00000000 /* supervisor/User restriction */ @@ -120,44 +120,44 @@ _start: move.w #0x2700,%sr #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) - move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR /*** The 5249 has MBAR2 as well ***/ -#ifdef CFG_MBAR2 - move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */ +#ifdef CONFIG_SYS_MBAR2 + move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */ movec %d0, #0xc0e /* Set MBAR2 */ #endif - move.l #(CFG_INIT_RAM_ADDR + 1), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ - move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #if defined(CONFIG_M5282) -#if (TEXT_BASE == CFG_INT_FLASH_BASE) +#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ - move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1 - move.l #(CFG_INIT_RAM_ADDR), %a2 + move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 _copy_flash: move.l (%a0)+, (%a2)+ cmp.l %a0, %a1 bgt.s _copy_flash - jmp CFG_INIT_RAM_ADDR + jmp CONFIG_SYS_INIT_RAM_ADDR _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 + move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -165,9 +165,9 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 + move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR -#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ +#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ #endif #endif @@ -175,22 +175,22 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) - move.l #CFG_INT_FLASH_BASE, %d0 +#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 #else - move.l #CFG_FLASH_BASE, %d0 + move.l #CONFIG_SYS_FLASH_BASE, %d0 #endif movec %d0, %VBR #endif #ifdef CONFIG_M5275 /* Initialize IPSBAR */ - move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 /* movec %d0, %MBAR */ /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #endif @@ -204,7 +204,7 @@ _after_flashbar_copy: #endif /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -235,7 +235,7 @@ relocate_code: move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CFG_MONITOR_BASE, %a1 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 /* copy the code to RAM */ @@ -249,7 +249,7 @@ relocate_code: * initialization, now running from RAM. */ move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 jmp (%a1) in_ram: @@ -259,9 +259,9 @@ clear_bss: * Now clear BSS segment */ move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 6: clr.l (%a1)+ cmp.l %a1,%d1 @@ -271,11 +271,11 @@ clear_bss: * fix got table in RAM */ move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a1,%a5 /* * fix got pointer register a5 */ move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 7: move.l (%a1),%d1 @@ -290,27 +290,27 @@ clear_bss: /* quick and dirty */ move.l %a0,%d1 - add.l #(icache_state - CFG_MONITOR_BASE),%d1 + add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1 move.l %a0,%a1 - add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1 + add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1 move.l %d1,(%a1) move.l %a0,%a1 - add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1 + add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1 move.l %d1,(%a1) move.l %a0,%a1 - add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1 + add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1 move.l %d1,(%a1) #endif /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ - defined(CFG_HALT_BEFOR_RAM_JUMP) +#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ + defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) halt #endif jsr (%a1) @@ -344,14 +344,14 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ nop - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 moveq #1, %d0 move.l %d0, (%a1) rts diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 260d6e6..8c496a2 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -117,7 +117,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); #ifdef CONFIG_M5329 wdp->mr = (wdog_module / 8192); #else diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c index 93086f7..d348e29 100644 --- a/cpu/mcf532x/cpu_init.c +++ b/cpu/mcf532x/cpu_init.c @@ -63,46 +63,46 @@ void cpu_init_f(void) /* Port configuration */ gpio->par_cs = 0; -#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) - fbcs->csar0 = CFG_CS0_BASE; - fbcs->cscr0 = CFG_CS0_CTRL; - fbcs->csmr0 = CFG_CS0_MASK; +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif -#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ gpio->par_cs |= GPIO_PAR_CS1; - fbcs->csar1 = CFG_CS1_BASE; - fbcs->cscr1 = CFG_CS1_CTRL; - fbcs->csmr1 = CFG_CS1_MASK; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) gpio->par_cs |= GPIO_PAR_CS2; - fbcs->csar2 = CFG_CS2_BASE; - fbcs->cscr2 = CFG_CS2_CTRL; - fbcs->csmr2 = CFG_CS2_MASK; + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) gpio->par_cs |= GPIO_PAR_CS3; - fbcs->csar3 = CFG_CS3_BASE; - fbcs->cscr3 = CFG_CS3_CTRL; - fbcs->csmr3 = CFG_CS3_MASK; + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CFG_CS4_BASE; - fbcs->cscr4 = CFG_CS4_CTRL; - fbcs->csmr4 = CFG_CS4_MASK; + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CFG_CS5_BASE; - fbcs->cscr5 = CFG_CS5_CTRL; - fbcs->csmr5 = CFG_CS5_MASK; + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif #ifdef CONFIG_FSL_I2C @@ -125,7 +125,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); break; diff --git a/cpu/mcf532x/interrupts.c b/cpu/mcf532x/interrupts.c index ff50d7d..d6c8205 100644 --- a/cpu/mcf532x/interrupts.c +++ b/cpu/mcf532x/interrupts.c @@ -28,7 +28,7 @@ int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ intp->imrh0 |= 0xFFFFFFFF; @@ -41,9 +41,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; - intp->imrh0 &= ~CFG_TMRINTR_MASK; + intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; + intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; } #endif diff --git a/cpu/mcf532x/speed.c b/cpu/mcf532x/speed.c index a11e425..1e40374 100644 --- a/cpu/mcf532x/speed.c +++ b/cpu/mcf532x/speed.c @@ -197,7 +197,7 @@ int clock_pll(int fsys, int flags) */ /* software workaround for SDRAM opeartion after exiting LIMP mode errata */ - *sdram_workaround = CFG_SDRAM_BASE; + *sdram_workaround = CONFIG_SYS_SDRAM_BASE; /* wait for DQS logic to relock */ for (i = 0; i < 0x200; i++) ; @@ -210,7 +210,7 @@ int clock_pll(int fsys, int flags) */ int get_clocks(void) { - gd->bus_clk = clock_pll(CFG_CLK / 1000, 0) * 1000; + gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); #ifdef CONFIG_FSL_I2C diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index c806f7a..7a3eb5f 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -127,10 +127,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CFG_FLASH_BASE, %d0 + move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -142,14 +142,14 @@ _start: /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 move.l %d0, (%a1) move.l %d0, (%a2) /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -180,7 +180,7 @@ relocate_code: move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CFG_MONITOR_BASE, %a1 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 @@ -195,7 +195,7 @@ relocate_code: * initialization, now running from RAM. */ move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 jmp (%a1) in_ram: @@ -205,9 +205,9 @@ clear_bss: * Now clear BSS segment */ move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 6: clr.l (%a1)+ cmp.l %a1,%d1 @@ -217,11 +217,11 @@ clear_bss: * fix got table in RAM */ move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a1,%a5 /* * fix got pointer register a5 */ move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 7: move.l (%a1),%d1 @@ -233,7 +233,7 @@ clear_bss: /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ @@ -268,14 +268,14 @@ _int_handler: icache_enable: move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 + move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0x80000200, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable cache */ nop - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 moveq #1, %d0 move.l %d0, (%a1) rts @@ -288,14 +288,14 @@ icache_disable: movec %d0, %ACR0 movec %d0, %ACR1 - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 moveq #0, %d0 move.l %d0, (%a1) rts .globl icache_status icache_status: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 move.l (%a1), %d0 rts @@ -307,7 +307,7 @@ icache_invalid: .globl dcache_enable dcache_enable: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 moveq #1, %d0 move.l %d0, (%a1) rts @@ -315,14 +315,14 @@ dcache_enable: /* No dcache, just a dummy function */ .globl dcache_disable dcache_disable: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 moveq #0, %d0 move.l %d0, (%a1) rts .globl dcache_status dcache_status: - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 move.l (%a1), %d0 rts diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 51a9e90..50b4561 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -62,42 +62,42 @@ void cpu_init_f(void) GPIO_PAR_FBCTL_TS_TS; #if !defined(CONFIG_CF_SBF) -#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) - fbcs->csar0 = CFG_CS0_BASE; - fbcs->cscr0 = CFG_CS0_CTRL; - fbcs->csmr0 = CFG_CS0_MASK; +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif #endif -#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ - fbcs->csar1 = CFG_CS1_BASE; - fbcs->cscr1 = CFG_CS1_CTRL; - fbcs->csmr1 = CFG_CS1_MASK; + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) - fbcs->csar2 = CFG_CS2_BASE; - fbcs->cscr2 = CFG_CS2_CTRL; - fbcs->csmr2 = CFG_CS2_MASK; +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) - fbcs->csar3 = CFG_CS3_BASE; - fbcs->cscr3 = CFG_CS3_CTRL; - fbcs->csmr3 = CFG_CS3_MASK; +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) - fbcs->csar4 = CFG_CS4_BASE; - fbcs->cscr4 = CFG_CS4_CTRL; - fbcs->csmr4 = CFG_CS4_MASK; +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) - fbcs->csar5 = CFG_CS5_BASE; - fbcs->cscr5 = CFG_CS5_CTRL; - fbcs->csmr5 = CFG_CS5_MASK; +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif #ifdef CONFIG_FSL_I2C @@ -113,11 +113,11 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; + rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; #endif return (0); @@ -128,7 +128,7 @@ void uart_port_conf(void) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_uart = (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c index 959d6bd..6d3ebab 100644 --- a/cpu/mcf5445x/dspi.c +++ b/cpu/mcf5445x/dspi.c @@ -47,29 +47,29 @@ void dspi_init(void) DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; -#ifdef CFG_DSPI_DCTAR0 - dspi->dctar0 = CFG_DSPI_DCTAR0; +#ifdef CONFIG_SYS_DSPI_DCTAR0 + dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0; #endif -#ifdef CFG_DSPI_DCTAR1 - dspi->dctar1 = CFG_DSPI_DCTAR1; +#ifdef CONFIG_SYS_DSPI_DCTAR1 + dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1; #endif -#ifdef CFG_DSPI_DCTAR2 - dspi->dctar2 = CFG_DSPI_DCTAR2; +#ifdef CONFIG_SYS_DSPI_DCTAR2 + dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2; #endif -#ifdef CFG_DSPI_DCTAR3 - dspi->dctar3 = CFG_DSPI_DCTAR3; +#ifdef CONFIG_SYS_DSPI_DCTAR3 + dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3; #endif -#ifdef CFG_DSPI_DCTAR4 - dspi->dctar4 = CFG_DSPI_DCTAR4; +#ifdef CONFIG_SYS_DSPI_DCTAR4 + dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4; #endif -#ifdef CFG_DSPI_DCTAR5 - dspi->dctar5 = CFG_DSPI_DCTAR5; +#ifdef CONFIG_SYS_DSPI_DCTAR5 + dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5; #endif -#ifdef CFG_DSPI_DCTAR6 - dspi->dctar6 = CFG_DSPI_DCTAR6; +#ifdef CONFIG_SYS_DSPI_DCTAR6 + dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6; #endif -#ifdef CFG_DSPI_DCTAR7 - dspi->dctar7 = CFG_DSPI_DCTAR7; +#ifdef CONFIG_SYS_DSPI_DCTAR7 + dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7; #endif } diff --git a/cpu/mcf5445x/interrupts.c b/cpu/mcf5445x/interrupts.c index 9572a7b..85828a6 100644 --- a/cpu/mcf5445x/interrupts.c +++ b/cpu/mcf5445x/interrupts.c @@ -31,7 +31,7 @@ int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ intp->imrh0 |= 0xFFFFFFFF; @@ -44,9 +44,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; - intp->imrh0 &= ~CFG_TMRINTR_MASK; + intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; + intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; } #endif diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c index 0398469..c4a3b05 100644 --- a/cpu/mcf5445x/pci.c +++ b/cpu/mcf5445x/pci.c @@ -31,9 +31,9 @@ #if defined(CONFIG_PCI) /* System RAM mapped over PCI */ -#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) +#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) #define cfg_read(val, addr, type, op) *val = op((type)(addr)); #define cfg_write(val, addr, type, op) op((type *)(addr), (val)); @@ -80,9 +80,9 @@ void pci_mcf5445x_init(struct pci_controller *hose) pci->tcr1 |= PCI_TCR1_P; /* Initiator windows */ - pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16); - pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16); - pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16); + pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); + pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); + pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); pci->iwcr = PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | @@ -97,34 +97,34 @@ void pci_mcf5445x_init(struct pci_controller *hose) pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); pci->cr2 = 0; -#ifdef CFG_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); - pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR0 + pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); + pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; barEn |= PCI_TCR2_B0E; #endif -#ifdef CFG_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); - pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR1 + pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); + pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; barEn |= PCI_TCR2_B1E; #endif -#ifdef CFG_PCI_BAR2 - pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2); - pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR2 + pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2); + pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN; barEn |= PCI_TCR2_B2E; #endif -#ifdef CFG_PCI_BAR3 - pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3); - pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR3 + pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3); + pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN; barEn |= PCI_TCR2_B3E; #endif -#ifdef CFG_PCI_BAR4 - pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4); - pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR4 + pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4); + pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN; barEn |= PCI_TCR2_B4E; #endif -#ifdef CFG_PCI_BAR5 - pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5); - pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR5 + pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5); + pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN; barEn |= PCI_TCR2_B5E; #endif @@ -138,20 +138,20 @@ void pci_mcf5445x_init(struct pci_controller *hose) hose->first_busno = 0; hose->last_busno = 0xff; - pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); - pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, PCI_REGION_IO); + pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, - CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, + pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, + CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose->region_count = 3; hose->cfg_addr = &(pci->car); - hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; + hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c index 6711a1d..9c0c077 100644 --- a/cpu/mcf5445x/speed.c +++ b/cpu/mcf5445x/speed.c @@ -94,7 +94,7 @@ int get_clocks(void) u16 fbpll_mask; #ifdef CONFIG_M54455EVB - volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3); + volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3); #endif u8 bootmode; @@ -145,7 +145,7 @@ int get_clocks(void) if (bootmode == 0) { /* RCON mode */ - vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC; + vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* invaild range, re-set in PCR */ @@ -154,7 +154,7 @@ int get_clocks(void) j = (pll->pcr & 0xFF000000) >> 24; for (i = j; i < 0xFF; i++) { - vco = i * CFG_INPUT_CLKSRC; + vco = i * CONFIG_SYS_INPUT_CLKSRC; if (vco >= CLOCK_PLL_FVCO_MIN) { bus = vco / temp; if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) @@ -172,25 +172,25 @@ int get_clocks(void) gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 2) { /* Normal mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* Default value */ pcrvalue = (pll->pcr & 0x00FFFFFF); pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24; pll->pcr = pcrvalue; - vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 3) { /* serial mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC; + vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; gd->vco_clk = vco; /* Vco clock */ } if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ } else { - gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; gd->cpu_clk = vco / temp; /* cpu clock */ diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 2a6019b..61e43ff 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -29,9 +29,9 @@ #endif /* last three long word reserved for cache status */ -#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) -#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) -#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) #define _START _start #define _FAULT _fault @@ -47,8 +47,8 @@ rte; #if defined(CONFIG_CF_SBF) -#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR) -#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) #endif .text @@ -149,18 +149,18 @@ asm_sbf_img_hdr: .long TEXT_BASE /* image to be relocated at */ asm_dram_init: - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* init Rambar */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CFG_CS0_BASE), (%a1) + move.l #(CONFIG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CFG_CS0_CTRL), (%a1) + move.l #(CONFIG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CFG_CS0_MASK), (%a1) + move.l #(CONFIG_SYS_CS0_MASK), (%a1) /* * Dram Initialization @@ -168,7 +168,7 @@ asm_dram_init: */ /* mscr sdram */ move.l #0xFC0A4074, %a1 - move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1) + move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) nop /* SDRAM Chip 0 and 1 */ @@ -177,8 +177,8 @@ asm_dram_init: /* calculate the size */ move.l #0x13, %d1 - move.l #(CFG_SDRAM_SIZE), %d2 -#ifdef CFG_SDRAM_BASE1 + move.l #(CONFIG_SYS_SDRAM_SIZE), %d2 +#ifdef CONFIG_SYS_SDRAM_BASE1 lsr.l #1, %d2 #endif @@ -189,20 +189,20 @@ dramsz_loop: bne dramsz_loop /* SDRAM Chip 0 and 1 */ - move.l #(CFG_SDRAM_BASE), (%a1) + move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) or.l %d1, (%a1) -#ifdef CFG_SDRAM_BASE1 - move.l #(CFG_SDRAM_BASE1), (%a2) +#ifdef CONFIG_SYS_SDRAM_BASE1 + move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2) or.l %d1, (%a2) #endif nop /* dram cfg1 and cfg2 */ move.l #0xFC0B8008, %a1 - move.l #(CFG_SDRAM_CFG1), (%a1) + move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1) nop move.l #0xFC0B800C, %a2 - move.l #(CFG_SDRAM_CFG2), (%a2) + move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2) nop move.l #0xFC0B8000, %a1 /* Mode */ @@ -210,13 +210,13 @@ dramsz_loop: #ifdef CONFIG_M54455EVB /* Issue PALL */ - move.l #(CFG_SDRAM_CTRL + 2), (%a2) + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) nop /* Issue LEMR */ - move.l #(CFG_SDRAM_EMOD + 0x408), (%a1) + move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) nop - move.l #(CFG_SDRAM_MODE + 0x300), (%a1) + move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) nop move.l #1000, %d0 @@ -227,24 +227,24 @@ wait1000: #endif /* Issue PALL */ - move.l #(CFG_SDRAM_CTRL + 2), (%a2) + move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) nop /* Perform two refresh cycles */ - move.l #(CFG_SDRAM_CTRL + 4), %d0 + move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0 nop move.l %d0, (%a2) move.l %d0, (%a2) nop #ifdef CONFIG_M54455EVB - move.l #(CFG_SDRAM_MODE + 0x200), (%a1) + move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1) nop #elif defined(CONFIG_M54451EVB) /* Issue LEMR */ - move.l #(CFG_SDRAM_MODE), (%a2) + move.l #(CONFIG_SYS_SDRAM_MODE), (%a2) nop - move.l #(CFG_SDRAM_EMOD), (%a2) + move.l #(CONFIG_SYS_SDRAM_EMOD), (%a2) nop #endif @@ -254,7 +254,7 @@ wait500: subq.l #1, %d0 bne wait500 - move.l #(CFG_SDRAM_CTRL), %d0 + move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 and.l #0x7FFFFFFF, %d0 #ifdef CONFIG_M54455EVB or.l #0x10000c00, %d0 @@ -290,8 +290,8 @@ wait500: move.l (%a1)+, %d5 move.l (%a1), %a4 - move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0 - move.l #(CFG_SBFHDR_SIZE), %d4 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 move.l #0xFC05C02C, %a1 /* dspi status */ @@ -381,10 +381,10 @@ _start: move.l #TEXT_BASE, %d0 movec %d0, %VBR #else - move.l #CFG_FLASH_BASE, %d0 + move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif @@ -408,7 +408,7 @@ _start: /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -439,7 +439,7 @@ relocate_code: move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CFG_MONITOR_BASE, %a1 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 @@ -454,7 +454,7 @@ relocate_code: * initialization, now running from RAM. */ move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 jmp (%a1) in_ram: @@ -464,9 +464,9 @@ clear_bss: * Now clear BSS segment */ move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 6: clr.l (%a1)+ cmp.l %a1,%d1 @@ -476,11 +476,11 @@ clear_bss: * fix got table in RAM */ move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a1,%a5 /* * fix got pointer register a5 */ move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 7: move.l (%a1),%d1 @@ -492,7 +492,7 @@ clear_bss: /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ @@ -531,7 +531,7 @@ icache_enable: move.l #0x00040100, %d0 /* Invalidate icache */ movec %d0, %CACR - move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */ + move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */ movec %d0, %ACR2 move.l #0x04088020, %d0 /* Enable bcache and icache */ diff --git a/cpu/mcf547x_8x/cpu.c b/cpu/mcf547x_8x/cpu.c index ab4ad28..f9a3544 100644 --- a/cpu/mcf547x_8x/cpu.c +++ b/cpu/mcf547x_8x/cpu.c @@ -133,7 +133,7 @@ int watchdog_init(void) volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); gptmr->pre = CONFIG_WATCHDOG_TIMEOUT; - gptmr->cnt = CFG_TIMER_PRESCALER * 1000; + gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000; gptmr->mode = GPT_TMS_SGPIO; gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN; diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c index 11154c6..9a0e040 100644 --- a/cpu/mcf547x_8x/cpu_init.c +++ b/cpu/mcf547x_8x/cpu_init.c @@ -52,40 +52,40 @@ void cpu_init_f(void) xlbarb->pri = 0; xlbarb->prien = 0xff; -#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) - fbcs->csar0 = CFG_CS0_BASE; - fbcs->cscr0 = CFG_CS0_CTRL; - fbcs->csmr0 = CFG_CS0_MASK; +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) + fbcs->csar0 = CONFIG_SYS_CS0_BASE; + fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; + fbcs->csmr0 = CONFIG_SYS_CS0_MASK; #endif -#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) - fbcs->csar1 = CFG_CS1_BASE; - fbcs->cscr1 = CFG_CS1_CTRL; - fbcs->csmr1 = CFG_CS1_MASK; +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) + fbcs->csar1 = CONFIG_SYS_CS1_BASE; + fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; + fbcs->csmr1 = CONFIG_SYS_CS1_MASK; #endif -#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) - fbcs->csar2 = CFG_CS2_BASE; - fbcs->cscr2 = CFG_CS2_CTRL; - fbcs->csmr2 = CFG_CS2_MASK; +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) + fbcs->csar2 = CONFIG_SYS_CS2_BASE; + fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; + fbcs->csmr2 = CONFIG_SYS_CS2_MASK; #endif -#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) - fbcs->csar3 = CFG_CS3_BASE; - fbcs->cscr3 = CFG_CS3_CTRL; - fbcs->csmr3 = CFG_CS3_MASK; +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) + fbcs->csar3 = CONFIG_SYS_CS3_BASE; + fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; + fbcs->csmr3 = CONFIG_SYS_CS3_MASK; #endif -#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) - fbcs->csar4 = CFG_CS4_BASE; - fbcs->cscr4 = CFG_CS4_CTRL; - fbcs->csmr4 = CFG_CS4_MASK; +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) + fbcs->csar4 = CONFIG_SYS_CS4_BASE; + fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; + fbcs->csmr4 = CONFIG_SYS_CS4_MASK; #endif -#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) - fbcs->csar5 = CFG_CS5_BASE; - fbcs->cscr5 = CFG_CS5_CTRL; - fbcs->csmr5 = CFG_CS5_MASK; +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) + fbcs->csar5 = CONFIG_SYS_CS5_BASE; + fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; + fbcs->csmr5 = CONFIG_SYS_CS5_MASK; #endif #ifdef CONFIG_FSL_I2C @@ -110,10 +110,10 @@ int cpu_init_r(void) void uart_port_conf(void) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile u8 *pscsicr = (u8 *) (CFG_UART_BASE + 0x40); + volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); /* Setup Ports: */ - switch (CFG_UART_PORT) { + switch (CONFIG_SYS_UART_PORT) { case 0: gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; diff --git a/cpu/mcf547x_8x/interrupts.c b/cpu/mcf547x_8x/interrupts.c index d684ffe..76be876 100644 --- a/cpu/mcf547x_8x/interrupts.c +++ b/cpu/mcf547x_8x/interrupts.c @@ -28,7 +28,7 @@ int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ intp->imrh0 |= 0xFFFFFFFF; @@ -42,9 +42,9 @@ int interrupt_init(void) #if defined(CONFIG_SLTTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; - intp->imrh0 &= ~CFG_TMRINTR_MASK; + intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; + intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; } #endif diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c index 70378b0..f5c2536 100644 --- a/cpu/mcf547x_8x/pci.c +++ b/cpu/mcf547x_8x/pci.c @@ -31,9 +31,9 @@ #if defined(CONFIG_PCI) /* System RAM mapped over PCI */ -#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE -#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) +#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) #define cfg_read(val, addr, type, op) *val = op((type)(addr)); #define cfg_write(val, addr, type, op) op((type *)(addr), (val)); @@ -107,9 +107,9 @@ void pci_mcf547x_8x_init(struct pci_controller *hose) pci->tcr1 = PCI_TCR1_P; /* Initiator windows */ - pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16); - pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16); - pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16); + pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); + pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); + pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); pci->iwcr = PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | @@ -124,13 +124,13 @@ void pci_mcf547x_8x_init(struct pci_controller *hose) pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); pci->cr2 = 0; -#ifdef CFG_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); - pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR0 + pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); + pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; #endif -#ifdef CFG_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); - pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN; +#ifdef CONFIG_SYS_PCI_BAR1 + pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); + pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; #endif /* Deassert reset bit */ @@ -141,20 +141,20 @@ void pci_mcf547x_8x_init(struct pci_controller *hose) hose->first_busno = 0; hose->last_busno = 0xff; - pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); - pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, PCI_REGION_IO); + pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, - CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, + pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, + CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose->region_count = 3; hose->cfg_addr = &(pci->car); - hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; + hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, diff --git a/cpu/mcf547x_8x/slicetimer.c b/cpu/mcf547x_8x/slicetimer.c index 494f98f..67e8189 100644 --- a/cpu/mcf547x_8x/slicetimer.c +++ b/cpu/mcf547x_8x/slicetimer.c @@ -31,22 +31,22 @@ DECLARE_GLOBAL_DATA_PTR; static ulong timestamp; #if defined(CONFIG_SLTTMR) -#ifndef CFG_UDELAY_BASE +#ifndef CONFIG_SYS_UDELAY_BASE # error "uDelay base not defined!" #endif -#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) +#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK) # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" #endif extern void dtimer_intr_setup(void); void udelay(unsigned long usec) { - volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE); + volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); u32 now, freq; /* 1 us period */ - freq = CFG_TIMER_PRESCALER; + freq = CONFIG_SYS_TIMER_PRESCALER; timerp->cr = 0; /* Disable */ timerp->tcnt = usec * freq; @@ -62,10 +62,10 @@ void udelay(unsigned long usec) void dtimer_interrupt(void *not_used) { - volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); + volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); /* check for timer interrupt asserted */ - if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { + if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { timerp->sr |= SLT_SR_ST; timestamp++; return; @@ -74,7 +74,7 @@ void dtimer_interrupt(void *not_used) void timer_init(void) { - volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); + volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); timestamp = 0; @@ -83,10 +83,10 @@ void timer_init(void) timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ /* initialize and enable timer interrupt */ - irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); + irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); /* Interrupt every ms */ - timerp->tcnt = 1000 * CFG_TIMER_PRESCALER; + timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER; dtimer_intr_setup(); diff --git a/cpu/mcf547x_8x/speed.c b/cpu/mcf547x_8x/speed.c index 28fe657..2cee488 100644 --- a/cpu/mcf547x_8x/speed.c +++ b/cpu/mcf547x_8x/speed.c @@ -37,7 +37,7 @@ int get_clocks(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bus_clk = CFG_CLK; + gd->bus_clk = CONFIG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); #ifdef CONFIG_FSL_I2C diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S index 87355f9..41fc694 100644 --- a/cpu/mcf547x_8x/start.S +++ b/cpu/mcf547x_8x/start.S @@ -29,9 +29,9 @@ #endif /* last three long word reserved for cache status */ -#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) -#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) -#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) #define _START _start #define _FAULT _fault @@ -132,16 +132,16 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CFG_FLASH_BASE, %d0 + move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR0 - move.l #(CFG_INIT_RAM1_ADDR + CFG_INIT_RAM1_CTRL), %d0 + move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 movec %d0, %RAMBAR1 - move.l #CFG_MBAR, %d0 /* set MBAR address */ + move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ move.c %d0, %MBAR /* invalidate and disable cache */ @@ -164,7 +164,7 @@ _start: /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ - move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -195,7 +195,7 @@ relocate_code: move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CFG_MONITOR_BASE, %a1 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 @@ -210,7 +210,7 @@ relocate_code: * initialization, now running from RAM. */ move.l %a0, %a1 - add.l #(in_ram - CFG_MONITOR_BASE), %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 jmp (%a1) in_ram: @@ -220,9 +220,9 @@ clear_bss: * Now clear BSS segment */ move.l %a0, %a1 - add.l #(_sbss - CFG_MONITOR_BASE),%a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a0, %d1 - add.l #(_ebss - CFG_MONITOR_BASE),%d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 6: clr.l (%a1)+ cmp.l %a1,%d1 @@ -232,11 +232,11 @@ clear_bss: * fix got table in RAM */ move.l %a0, %a1 - add.l #(__got_start - CFG_MONITOR_BASE),%a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 move.l %a1,%a5 /* * fix got pointer register a5 */ move.l %a0, %a2 - add.l #(__got_end - CFG_MONITOR_BASE),%a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 7: move.l (%a1),%d1 @@ -248,7 +248,7 @@ clear_bss: /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 - add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ @@ -281,7 +281,7 @@ _int_handler: /* cache functions */ .globl icache_enable icache_enable: - move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 + move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 movec %d0, %ACR2 /* Enable cache */ move.l #0x020C8100, %d0 /* Setup cache mask */ @@ -322,7 +322,7 @@ icache_status: dcache_enable: bsr icache_disable - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 + move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 movec %d0, %ACR0 /* Enable cache */ move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c index d76b05a..0365de3 100644 --- a/cpu/microblaze/exception.c +++ b/cpu/microblaze/exception.c @@ -65,7 +65,7 @@ void _hw_exception_handler (void) hang (); } -#ifdef CFG_USR_EXCEP +#ifdef CONFIG_SYS_USR_EXCEP void _exception_handler (void) { puts ("User vector_exception\n"); diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index 26e88cb..a6021c9 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -45,19 +45,19 @@ int disable_interrupts (void) return 0; } -#ifdef CFG_INTC_0 -#ifdef CFG_TIMER_0 +#ifdef CONFIG_SYS_INTC_0 +#ifdef CONFIG_SYS_TIMER_0 extern void timer_init (void); #endif -#ifdef CFG_FSL_2 +#ifdef CONFIG_SYS_FSL_2 extern void fsl_init2 (void); #endif -static struct irq_action vecs[CFG_INTC_0_NUM]; +static struct irq_action vecs[CONFIG_SYS_INTC_0_NUM]; /* mapping structure to interrupt controller */ -microblaze_intc_t *intc = (microblaze_intc_t *) (CFG_INTC_0_ADDR); +microblaze_intc_t *intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR); /* default handler */ void def_hdlr (void) @@ -100,7 +100,7 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg) { struct irq_action *act; /* irq out of range */ - if ((irq < 0) || (irq > CFG_INTC_0_NUM)) { + if ((irq < 0) || (irq > CONFIG_SYS_INTC_0_NUM)) { puts ("IRQ out of range\n"); return; } @@ -135,17 +135,17 @@ int interrupts_init (void) { int i; /* initialize irq list */ - for (i = 0; i < CFG_INTC_0_NUM; i++) { + for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) { vecs[i].handler = (interrupt_handler_t *) def_hdlr; vecs[i].arg = (void *)i; vecs[i].count = 0; } /* initialize intc controller */ intc_init (); -#ifdef CFG_TIMER_0 +#ifdef CONFIG_SYS_TIMER_0 timer_init (); #endif -#ifdef CFG_FSL_2 +#ifdef CONFIG_SYS_FSL_2 fsl_init2 (); #endif enable_interrupts (); @@ -191,7 +191,7 @@ void interrupt_handler (void) #endif #if defined(CONFIG_CMD_IRQ) -#ifdef CFG_INTC_0 +#ifdef CONFIG_SYS_INTC_0 int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; @@ -201,7 +201,7 @@ int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "Nr Routine Arg Count\n" "-----------------------------\n"); - for (i = 0; i < CFG_INTC_0_NUM; i++) { + for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) { if (act->handler != (interrupt_handler_t*) def_hdlr) { printf ("%02d %08x %08x %d\n", i, (int)act->handler, (int)act->arg, act->count); diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S index 8740284..2e9a08d 100644 --- a/cpu/microblaze/start.S +++ b/cpu/microblaze/start.S @@ -30,7 +30,7 @@ .global _start _start: mts rmsr, r0 /* disable cache */ - addi r1, r0, CFG_INIT_SP_OFFSET + addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET addi r1, r1, -4 /* Decrement SP to top of memory */ /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/ addi r6, r0, 0xb0000000 /* hex b000 opcode imm */ @@ -45,9 +45,9 @@ _start: swi r6, r0, 0x14 /* interrupt */ swi r6, r0, 0x24 /* hardware exception */ -#ifdef CFG_RESET_ADDRESS +#ifdef CONFIG_SYS_RESET_ADDRESS /* reset address */ - addik r6, r0, CFG_RESET_ADDRESS + addik r6, r0, CONFIG_SYS_RESET_ADDRESS sw r6, r1, r0 lhu r7, r1, r0 shi r7, r0, 0x2 @@ -56,11 +56,11 @@ _start: * Copy U-Boot code to TEXT_BASE * solve problem with sbrk_base */ -#if (CFG_RESET_ADDRESS != TEXT_BASE) +#if (CONFIG_SYS_RESET_ADDRESS != TEXT_BASE) addi r4, r0, __end addi r5, r0, __text_start rsub r4, r5, r4 /* size = __end - __text_start */ - addi r6, r0, CFG_RESET_ADDRESS /* source address */ + addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */ addi r7, r0, 0 /* counter */ 4: lw r8, r6, r7 @@ -71,7 +71,7 @@ _start: #endif #endif -#ifdef CFG_USR_EXCEP +#ifdef CONFIG_SYS_USR_EXCEP /* user_vector_exception */ addik r6, r0, _exception_handler sw r6, r1, r0 @@ -80,7 +80,7 @@ _start: shi r6, r0, 0xe #endif -#ifdef CFG_INTC_0 +#ifdef CONFIG_SYS_INTC_0 /* interrupt_handler */ addik r6, r0, _interrupt_handler sw r6, r1, r0 diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c index b350453..a91eabc 100644 --- a/cpu/microblaze/timer.c +++ b/cpu/microblaze/timer.c @@ -33,7 +33,7 @@ void reset_timer (void) timestamp = 0; } -#ifdef CFG_TIMER_0 +#ifdef CONFIG_SYS_TIMER_0 ulong get_timer (ulong base) { return (timestamp - base); @@ -50,9 +50,9 @@ void set_timer (ulong t) timestamp = t; } -#ifdef CFG_INTC_0 -#ifdef CFG_TIMER_0 -microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR); +#ifdef CONFIG_SYS_INTC_0 +#ifdef CONFIG_SYS_TIMER_0 +microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); void timer_isr (void *arg) { @@ -62,12 +62,12 @@ void timer_isr (void *arg) void timer_init (void) { - tmr->loadreg = CFG_TIMER_0_PRELOAD; + tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD; tmr->control = TIMER_INTERRUPT | TIMER_RESET; tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT; reset_timer (); - install_interrupt_handler (CFG_TIMER_0_IRQ, timer_isr, (void *)tmr); + install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr); } #endif #endif diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index d0cf8e0..8ddc06a 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,7 +23,7 @@ */ #include -#if defined(CFG_DISCOVER_PHY) +#if defined(CONFIG_SYS_DISCOVER_PHY) #error "PHY not supported yet" /* We just assume that we are running 100FD for now */ /* We all use switches, right? ;-) */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index e8baab5..c25ba5a 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -76,7 +76,7 @@ void serial_setbrg (void) sd = (*sys_powerctrl & 0x03) + 2; /* calulate 2x baudrate and round */ - divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); + divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); if (divisorx2 & 0x01) divisorx2 = divisorx2 + 1; diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index ee5d411..ff4f11c 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -208,9 +208,9 @@ LEAF(mips_init_dcache) */ NESTED(mips_cache_reset, 0, ra) move RA, ra - li t2, CFG_ICACHE_SIZE - li t3, CFG_DCACHE_SIZE - li t4, CFG_CACHELINE_SIZE + li t2, CONFIG_SYS_ICACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE + li t4, CONFIG_SYS_CACHELINE_SIZE move t5, t4 li v0, MIPS_MAX_CACHE_SIZE @@ -302,7 +302,7 @@ LEAF(dcache_enable) jr ra END(dcache_enable) -#ifdef CFG_INIT_RAM_LOCK_MIPS +#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS /******************************************************************************* * * mips_cache_lock - lock RAM area pointed to by a0 in cache. @@ -311,9 +311,9 @@ LEAF(dcache_enable) * */ #if defined(CONFIG_PURPLE) -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2) +# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2) #else -# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE) +# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE) #endif .globl mips_cache_lock .ent mips_cache_lock @@ -321,11 +321,11 @@ mips_cache_lock: li a1, CKSEG0 - CACHE_LOCK_SIZE addu a0, a1 li a2, CACHE_LOCK_SIZE - li a3, CFG_CACHELINE_SIZE + li a3, CONFIG_SYS_CACHELINE_SIZE move a1, a2 icacheop(a0,a1,a2,a3,0x1d) jr ra .end mips_cache_lock -#endif /* CFG_INIT_RAM_LOCK_MIPS */ +#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */ diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 0f58d25..38d8697 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -51,7 +51,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) void flush_cache(ulong start_addr, ulong size) { - unsigned long lsize = CFG_CACHELINE_SIZE; + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; unsigned long addr = start_addr & ~(lsize - 1); unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 09e4aab..6a22302 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -274,14 +274,14 @@ reset: /* Set up temporary stack. */ -#ifdef CFG_INIT_RAM_LOCK_MIPS - li a0, CFG_INIT_SP_OFFSET +#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS + li a0, CONFIG_SYS_INIT_SP_OFFSET la t9, mips_cache_lock jalr t9 nop #endif - li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET + li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET la sp, 0(t0) la t9, board_init_f @@ -303,7 +303,7 @@ reset: relocate_code: move sp, a0 /* Set new stack pointer */ - li t0, CFG_MONITOR_BASE + li t0, CONFIG_SYS_MONITOR_BASE la t3, in_ram lw t2, -12(t3) /* t2 <-- uboot_end_data */ move t1, a2 @@ -311,10 +311,10 @@ relocate_code: /* * Fix $gp: * - * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address */ move t6, gp - sub gp, CFG_MONITOR_BASE + sub gp, CONFIG_SYS_MONITOR_BASE add gp, a2 /* gp now adjusted */ sub t6, gp, t6 /* t6 <-- relocation offset */ diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index d432d99..9b59738 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; int checkcpu (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ulong clock = gd->cpu_clk; u32 pvr = get_pvr (); u32 spridr = immr->sysconf.spridr; @@ -75,7 +75,7 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { ulong msr; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* Interrupts and MMU off */ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); @@ -122,7 +122,7 @@ void watchdog_reset (void) int re_enable = disable_interrupts (); /* Reset watchdog */ - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; immr->wdt.swsrr = 0x556c; immr->wdt.swsrr = 0xaa39; diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c index d6949f6..fa753c8 100644 --- a/cpu/mpc512x/cpu_init.c +++ b/cpu/mpc512x/cpu_init.c @@ -37,23 +37,23 @@ void cpu_init_f (volatile immap_t * im) u32 ips_div; /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); /* system performance tweaking */ -#ifdef CFG_ACR_PIPE_DEP +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif -#ifdef CFG_ACR_RPTCNT +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | - (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); #endif /* RSR - Reset Status Register - clear all status */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 56ba443..77a6f0d 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -#define immr ((immap_t *)CFG_IMMR) +#define immr ((immap_t *)CONFIG_SYS_IMMR) /* by default set I2C bus 0 active */ static unsigned int bus_num = 0; @@ -422,7 +422,7 @@ unsigned int i2c_get_bus_speed (void) int i2c_set_bus_speed (unsigned int speed) { - if (speed != CFG_I2C_SPEED) + if (speed != CONFIG_SYS_I2C_SPEED) return -1; return 0; diff --git a/cpu/mpc512x/interrupts.c b/cpu/mpc512x/interrupts.c index 8cc241c..ef7c773 100644 --- a/cpu/mpc512x/interrupts.c +++ b/cpu/mpc512x/interrupts.c @@ -37,7 +37,7 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { - *decrementer_count = get_tbclk () / CFG_HZ; + *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; return 0; } diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c index 3d7042d..78f4fa1e 100644 --- a/cpu/mpc512x/iopin.c +++ b/cpu/mpc512x/iopin.c @@ -29,7 +29,7 @@ void iopin_initialize(iopin_t *ioregs_init, int len) { short i, j, p; u_long *reg; - immap_t *im = (immap_t *)CFG_IMMR; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; reg = (u_long *)&(im->io_ctrl.regs[0]); diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 8a21404..7db87a8 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; static void fifo_init (volatile psc512x_t *psc) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; /* reset Rx & Tx fifo slice */ psc->rfcmd = PSC_FIFO_RESET_SLICE; @@ -60,7 +60,7 @@ static void fifo_init (volatile psc512x_t *psc) int serial_init(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; unsigned long baseclk; int div; @@ -106,7 +106,7 @@ int serial_init(void) void serial_putc (const char c) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; if (c == '\n') @@ -121,7 +121,7 @@ void serial_putc (const char c) void serial_putc_raw (const char c) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; /* Wait for last character to go. */ @@ -141,7 +141,7 @@ void serial_puts (const char *s) int serial_getc (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; /* Wait for a character to arrive. */ @@ -153,7 +153,7 @@ int serial_getc (void) int serial_tstc (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; return !(psc->rfstat & PSC_FIFO_EMPTY); @@ -161,7 +161,7 @@ int serial_tstc (void) void serial_setbrg (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; unsigned long baseclk, div; @@ -174,7 +174,7 @@ void serial_setbrg (void) void serial_setrts(int s) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; if (s) { @@ -189,7 +189,7 @@ void serial_setrts(int s) int serial_getcts(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; return (psc->ip & 0x1) ? 0 : 1; diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index e62477b..baf6215 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -62,13 +62,13 @@ static int sys_dividors[][2] = { int get_clocks (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u8 spmf; u8 cpmf; u8 sys_div; u8 ips_div; u8 pci_div; - u32 ref_clk = CFG_MPC512X_CLKIN; + u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN; u32 spll; u32 sys_clk; u32 core_clk; diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index fb8acb5..26f3c52 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -192,8 +192,8 @@ boot_cold: /* Set IMMR area to our preferred location */ lis r4, CONFIG_DEFAULT_IMMR@h - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l + lis r3, CONFIG_SYS_IMMR@h + ori r3, r3, CONFIG_SYS_IMMR@l stw r3, IMMRBAR(r4) mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ @@ -208,18 +208,18 @@ boot_cold: */ /* Boot CS/CS0 window range */ - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l + lis r3, CONFIG_SYS_IMMR@h + ori r3, r3, CONFIG_SYS_IMMR@l - lis r4, START_REG(CFG_FLASH_BASE) - ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) + lis r4, START_REG(CONFIG_SYS_FLASH_BASE) + ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE) stw r4, LPCS0AW(r3) /* * The SRAM window has a fixed size (256K), so only the start address * is necessary */ - lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00 stw r4, SRAMBAR(r3) /* @@ -234,11 +234,11 @@ boot_cold: * Set configuration of the Boot/CS0, the SRAM window does not have a * config register so no params can be set for it */ - lis r3, (CFG_IMMR + LPC_OFFSET)@h - ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l + lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h + ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l - lis r4, CFG_CS0_CFG@h - ori r4, r4, CFG_CS0_CFG@l + lis r4, CONFIG_SYS_CS0_CFG@h + ori r4, r4, CONFIG_SYS_CS0_CFG@l stw r4, CS0_CONFIG(r3) /* Master enable all CS's */ @@ -246,15 +246,15 @@ boot_cold: ori r4, r4, CS_CTRL_ME@l stw r4, CS_CTRL(r3) - lis r4, (CFG_MONITOR_BASE)@h - ori r4, r4, (CFG_MONITOR_BASE)@l + lis r4, (CONFIG_SYS_MONITOR_BASE)@h + ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET mtlr r5 blr in_flash: - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -268,7 +268,7 @@ in_flash: GET_GOT /* initialize GOT access */ /* r3: IMMR */ - lis r3, CFG_IMMR@h + lis r3, CONFIG_SYS_IMMR@h /* run low-level CPU init code (in Flash) */ bl cpu_init_f @@ -353,12 +353,12 @@ cpu_early_init: SYNC mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ - lis r3, CFG_IMMR@h + lis r3, CONFIG_SYS_IMMR@h #if defined(CONFIG_WATCHDOG) /* Initialise the watchdog and reset it */ /*--------------------------------------*/ - lis r4, CFG_WATCHDOG_VALUE + lis r4, CONFIG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3) @@ -386,18 +386,18 @@ cpu_early_init: /* Initialize the Hardware Implementation-dependent Registers */ /* HID0 also contains cache control */ /*------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l SYNC mtspr HID0, r3 - lis r3, CFG_HID2@h - ori r3, r3, CFG_HID2@l + lis r3, CONFIG_SYS_HID2@h + ori r3, r3, CONFIG_SYS_HID2@l SYNC mtspr HID2, r3 sync @@ -499,16 +499,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) * + Destination Address * * Offset: diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c index 4bef90c..7fffebc 100644 --- a/cpu/mpc5xx/cpu.c +++ b/cpu/mpc5xx/cpu.c @@ -80,7 +80,7 @@ void watchdog_reset (void) { int re_enable = disable_interrupts (); - reset_5xx_watchdog ((immap_t *) CFG_IMMR); + reset_5xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); if (re_enable) enable_interrupts (); } @@ -103,14 +103,14 @@ void reset_5xx_watchdog (volatile immap_t * immr) */ unsigned long get_tbclk (void) { - volatile immap_t *immr = (volatile immap_t *) CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *) CONFIG_SYS_IMMR; ulong oscclk, factor; if (immr->im_clkrst.car_sccr & SCCR_TBS) { return (gd->cpu_clk / 16); } - factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; + factor = (((CONFIG_SYS_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; oscclk = gd->cpu_clk / factor; @@ -141,7 +141,7 @@ int dcache_status (void) int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { #if defined(CONFIG_PATI) - volatile ulong *addr = (ulong *) CFG_RESET_ADDRESS; + volatile ulong *addr = (ulong *) CONFIG_SYS_RESET_ADDRESS; *addr = 1; #else ulong addr; @@ -155,15 +155,15 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address + * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. * "(ulong)-1" used to be a good choice for many systems... */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*) (void)) addr) (); #endif /* #if defined(CONFIG_PATI) */ diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c index 5bbb798..cb4bf84 100644 --- a/cpu/mpc5xx/cpu_init.c +++ b/cpu/mpc5xx/cpu_init.c @@ -41,74 +41,74 @@ void cpu_init_f (volatile immap_t * immr) /* SYPCR - contains watchdog control. This will enable watchdog */ /* if CONFIG_WATCHDOG is set */ - immr->im_siu_conf.sc_sypcr = CFG_SYPCR; + immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; #if defined(CONFIG_WATCHDOG) reset_5xx_watchdog (immr); #endif /* SIUMCR - contains debug pin configuration */ - immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; + immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; /* Initialize timebase. Unlock TBSCRK */ immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CFG_TBSCR; + immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; /* Full IMB bus speed */ - immr->im_uimb.uimb_umcr = CFG_UMCR; + immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR; /* Time base and decrementer will be enables (TBE) */ /* in init_timebase() in time.c called from board_init_f(). */ /* Initialize the PIT. Unlock PISCRK */ immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; #if !defined(CONFIG_PATI) /* PATI sest PLL in start.S */ /* PLL (CPU clock) settings */ immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - /* If CFG_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CFG_PLPRCR over car_plprcr, - * otherwise OR in CFG_PLPRCR so we do not change the currentMF + /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to + * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, + * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF * field value. */ -#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) - reg = CFG_PLPRCR; /* reset control bits */ +#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) + reg = CONFIG_SYS_PLPRCR; /* reset control bits */ #else reg = immr->im_clkrst.car_plprcr; reg &= PLPRCR_MF_MSK; /* isolate MF field */ - reg |= CFG_PLPRCR; /* reset control bits */ + reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ #endif immr->im_clkrst.car_plprcr = reg; #endif /* !defined(CONFIG_PATI) */ - /* System integration timers. CFG_MASK has EBDF configuration */ + /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */ immr->im_clkrstk.cark_sccrk = KAPWR_KEY; reg = immr->im_clkrst.car_sccr; reg &= SCCR_MASK; - reg |= CFG_SCCR; + reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg; /* Memory Controller */ - memctl->memc_br0 = CFG_BR0_PRELIM; - memctl->memc_or0 = CFG_OR0_PRELIM; + memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; -#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; +#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; #endif } diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c index a4f47c7..167543f 100644 --- a/cpu/mpc5xx/interrupts.c +++ b/cpu/mpc5xx/interrupts.c @@ -52,11 +52,11 @@ static struct interrupt_action irq_vecs[NR_IRQS]; int interrupt_init_cpu (ulong *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int vec; /* Decrementer used here for status led */ - *decrementer_count = get_tbclk () / CFG_HZ; + *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; /* Disable all interrupts */ immr->im_siu_conf.sc_simask = 0; @@ -74,7 +74,7 @@ int interrupt_init_cpu (ulong *decrementer_count) */ void external_interrupt (struct pt_regs *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int irq; ulong simask, newmask; ulong vec, v_bit; @@ -130,7 +130,7 @@ void external_interrupt (struct pt_regs *regs) void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* SIU interrupt */ if (irq_vecs[vec].handler != NULL) { printf ("SIU interrupt %d 0x%x\n", @@ -148,7 +148,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void irq_free_handler (int vec) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* SIU interrupt */ #if 0 printf ("Free CPM interrupt for vector %d\n", @@ -165,7 +165,7 @@ void irq_free_handler (int vec) */ void timer_interrupt_cpu (struct pt_regs *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #if 0 printf ("*** Timer Interrupt *** "); diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c index 39f57a1..88c6db8 100644 --- a/cpu/mpc5xx/serial.c +++ b/cpu/mpc5xx/serial.c @@ -48,7 +48,7 @@ static int ready_to_send(void); int serial_init (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; serial_setbrg(); @@ -65,7 +65,7 @@ int serial_init (void) void serial_putc(const char c) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* Test for completition */ if(ready_to_send()) { @@ -87,7 +87,7 @@ void serial_putc(const char c) int serial_getc(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile short status; unsigned char tmp; @@ -115,7 +115,7 @@ int serial_getc(void) int serial_tstc() { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; short status; /* New data character ? */ @@ -129,7 +129,7 @@ int serial_tstc() void serial_setbrg (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; short scxbr; /* Set baudrate */ @@ -151,7 +151,7 @@ void serial_puts (const char *s) int ready_to_send(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile short status; do { diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c index 7b7c5b9..ea5c1de 100644 --- a/cpu/mpc5xx/speed.c +++ b/cpu/mpc5xx/speed.c @@ -38,14 +38,14 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #ifndef CONFIG_5xx_GCLK_FREQ uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK); uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT); ulong vcoout; - vcoout = (CFG_OSC_CLK / (divf + 1)) * (mf + 1) * 2; + vcoout = (CONFIG_SYS_OSC_CLK / (divf + 1)) * (mf + 1) * 2; if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); } else { diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c index 3c187be..3ca15ea 100644 --- a/cpu/mpc5xx/spi.c +++ b/cpu/mpc5xx/spi.c @@ -111,7 +111,7 @@ void spi_init_f (void) volatile immap_t *immr; volatile qsmcm5xx_t *qsmcm; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */ @@ -128,7 +128,7 @@ void spi_init_f (void) * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI) * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO) * -------------------------------------------- */ - qsmcm->qsmcm_pqspar = 0x3 | (CFG_SPI_CS_USED << 3); + qsmcm->qsmcm_pqspar = 0x3 | (CONFIG_SYS_SPI_CS_USED << 3); /* -------------------------------------------- * DDRQS[00] = 0 reserved @@ -160,7 +160,7 @@ void spi_init_f (void) * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output * PORTQS[15] = 0 [0x0001] -> SPIMISO Input * -------------------------------------------- */ - qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3); + qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3); /* -------------------------------------------- * Controll Register 0 * SPCR0[00] = 1 (0x8000) Master @@ -235,7 +235,7 @@ ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) volatile immap_t *immr; volatile qsmcm5xx_t *qsmcm; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; for(i=0;i<32;i++) { qsmcm->qsmcm_recram[i]=0x0000; @@ -308,7 +308,7 @@ ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) volatile immap_t *immr; volatile qsmcm5xx_t *qsmcm; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; for(i=0;i<32;i++) { @@ -364,15 +364,15 @@ ssize_t spi_xfer (size_t count) int i; int tm; ushort status; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; DPRINT (("*** spi_xfer entered count %d***\n",count)); /* Set CS for device */ for(i=0;i<(count-1);i++) - qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ + qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ - qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ + qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */ qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8; DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count)); diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 0637003..f2ffe84 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -87,7 +87,7 @@ version_string: .globl _start _start: mfspr r3, 638 - li r4, CFG_ISB /* Set ISB bit */ + li r4, CONFIG_SYS_ISB /* Set ISB bit */ or r3, r3, r4 mtspr 638, r3 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ @@ -121,12 +121,12 @@ boot_warm: /* the external flash access on PATI fails if programming the PLL to 40MHz. * Copy the PLL programming code to the internal RAM and execute it *----------------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET - lis r4, CFG_INIT_RAM_ADDR@h - ori r4, r4, CFG_INIT_RAM_ADDR@l + lis r4, CONFIG_SYS_INIT_RAM_ADDR@h + ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l mtlr r4 addis r5,0,0x0 ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2) @@ -144,8 +144,8 @@ boot_warm: * Calculate absolute address in FLASH and jump there *----------------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr @@ -155,9 +155,9 @@ in_flash: /* Initialize some SPRs that are hard to access from C */ /*----------------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ - lis r2, CFG_INIT_SP_ADDR@h - ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ + lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */ + lis r2, CONFIG_SYS_INIT_SP_ADDR@h + ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ /* Note: R0 is still 0 here */ stwu r0, -4(r1) /* Clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -173,8 +173,8 @@ in_flash: /* Set up debug mode entry */ - lis r2, CFG_DER@h - ori r2, r2, CFG_DER@l + lis r2, CONFIG_SYS_DER@h + ori r2, r2, CONFIG_SYS_DER@l mtspr DER, r2 /* Let the C-code set up the rest */ @@ -385,15 +385,15 @@ relocate_code: mr r10, r5 /* Save copy of monitor destination Address in SRAM */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -581,15 +581,15 @@ trap_reloc: #if defined(CONFIG_PATI) /* Program the PLL */ pll_prog_code_start: - lis r4, (CFG_IMMR + 0x002fc384)@h - ori r4, r4, (CFG_IMMR + 0x002fc384)@l + lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h + ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l lis r3, (0x55ccaa33)@h ori r3, r3, (0x55ccaa33)@l stw r3, 0(r4) - lis r4, (CFG_IMMR + 0x002fc284)@h - ori r4, r4, (CFG_IMMR + 0x002fc284)@l - lis r3, CFG_PLPRCR@h - ori r3, r3, CFG_PLPRCR@l + lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h + ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l + lis r3, CONFIG_SYS_PLPRCR@h + ori r3, r3, CONFIG_SYS_PLPRCR@l stw r3, 0(r4) addis r3,0,0x0 ori r3,r3,0xA000 diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 1326c3c..9c6ab76 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -118,7 +118,7 @@ unsigned long get_tbclk (void) #if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd) { - int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4; + int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4; char * cpu_path = "/cpus/" OF_CPU; #ifdef CONFIG_MPC5xxx_FEC char * eth_path = "/" OF_SOC "/ethernet@3000"; diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index bc6201e..14bd417 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -35,11 +35,11 @@ DECLARE_GLOBAL_DATA_PTR; void cpu_init_f (void) { unsigned long addecr = (1 << 25); /* Boot_CS */ -#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) addecr |= (1 << 22); /* SDRAM enable */ #endif /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -47,95 +47,95 @@ void cpu_init_f (void) /* * Memory Controller: configure chip selects and enable them */ -#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE) - *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START); - *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START, - CFG_BOOTCS_SIZE); +#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE) + *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CONFIG_SYS_BOOTCS_START); + *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START, + CONFIG_SYS_BOOTCS_SIZE); #endif -#if defined(CFG_BOOTCS_CFG) - *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG; +#if defined(CONFIG_SYS_BOOTCS_CFG) + *(vu_long *)MPC5XXX_BOOTCS_CFG = CONFIG_SYS_BOOTCS_CFG; #endif -#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE) - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START); - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE); +#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) + *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_CS0_START); + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE); /* CS0 and BOOT_CS cannot be enabled at once. */ /* addecr |= (1 << 16); */ #endif -#if defined(CFG_CS0_CFG) - *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG; +#if defined(CONFIG_SYS_CS0_CFG) + *(vu_long *)MPC5XXX_CS0_CFG = CONFIG_SYS_CS0_CFG; #endif -#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE) - *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START); - *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE); +#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) + *(vu_long *)MPC5XXX_CS1_START = START_REG(CONFIG_SYS_CS1_START); + *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE); addecr |= (1 << 17); #endif -#if defined(CFG_CS1_CFG) - *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG; +#if defined(CONFIG_SYS_CS1_CFG) + *(vu_long *)MPC5XXX_CS1_CFG = CONFIG_SYS_CS1_CFG; #endif -#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE) - *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START); - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE); +#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE) + *(vu_long *)MPC5XXX_CS2_START = START_REG(CONFIG_SYS_CS2_START); + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE); addecr |= (1 << 18); #endif -#if defined(CFG_CS2_CFG) - *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG; +#if defined(CONFIG_SYS_CS2_CFG) + *(vu_long *)MPC5XXX_CS2_CFG = CONFIG_SYS_CS2_CFG; #endif -#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE) - *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START); - *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE); +#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) + *(vu_long *)MPC5XXX_CS3_START = START_REG(CONFIG_SYS_CS3_START); + *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE); addecr |= (1 << 19); #endif -#if defined(CFG_CS3_CFG) - *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG; +#if defined(CONFIG_SYS_CS3_CFG) + *(vu_long *)MPC5XXX_CS3_CFG = CONFIG_SYS_CS3_CFG; #endif -#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE) - *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START); - *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE); +#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) + *(vu_long *)MPC5XXX_CS4_START = START_REG(CONFIG_SYS_CS4_START); + *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE); addecr |= (1 << 20); #endif -#if defined(CFG_CS4_CFG) - *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG; +#if defined(CONFIG_SYS_CS4_CFG) + *(vu_long *)MPC5XXX_CS4_CFG = CONFIG_SYS_CS4_CFG; #endif -#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE) - *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START); - *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE); +#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) + *(vu_long *)MPC5XXX_CS5_START = START_REG(CONFIG_SYS_CS5_START); + *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE); addecr |= (1 << 21); #endif -#if defined(CFG_CS5_CFG) - *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG; +#if defined(CONFIG_SYS_CS5_CFG) + *(vu_long *)MPC5XXX_CS5_CFG = CONFIG_SYS_CS5_CFG; #endif #if defined(CONFIG_MPC5200) addecr |= 1; -#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE) - *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START); - *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE); +#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) + *(vu_long *)MPC5XXX_CS6_START = START_REG(CONFIG_SYS_CS6_START); + *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE); addecr |= (1 << 26); #endif -#if defined(CFG_CS6_CFG) - *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG; +#if defined(CONFIG_SYS_CS6_CFG) + *(vu_long *)MPC5XXX_CS6_CFG = CONFIG_SYS_CS6_CFG; #endif -#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE) - *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START); - *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE); +#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) + *(vu_long *)MPC5XXX_CS7_START = START_REG(CONFIG_SYS_CS7_START); + *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE); addecr |= (1 << 27); #endif -#if defined(CFG_CS7_CFG) - *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG; +#if defined(CONFIG_SYS_CS7_CFG) + *(vu_long *)MPC5XXX_CS7_CFG = CONFIG_SYS_CS7_CFG; #endif -#if defined(CFG_CS_BURST) - *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST; +#if defined(CONFIG_SYS_CS_BURST) + *(vu_long *)MPC5XXX_CS_BURST = CONFIG_SYS_CS_BURST; #endif -#if defined(CFG_CS_DEADCYCLE) - *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE; +#if defined(CONFIG_SYS_CS_DEADCYCLE) + *(vu_long *)MPC5XXX_CS_DEADCYCLE = CONFIG_SYS_CS_DEADCYCLE; #endif #endif /* CONFIG_MPC5200 */ @@ -144,8 +144,8 @@ void cpu_init_f (void) *(vu_long *)MPC5XXX_CS_CTRL = (1 << 24); /* Setup pin multiplexing */ -#if defined(CFG_GPS_PORT_CONFIG) - *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG; +#if defined(CONFIG_SYS_GPS_PORT_CONFIG) + *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CONFIG_SYS_GPS_PORT_CONFIG; #endif #if defined(CONFIG_MPC5200) @@ -154,28 +154,28 @@ void cpu_init_f (void) /* Enable snooping for RAM */ *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); - *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d; + *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_SYS_SDRAM_BASE | 0x1d; -# if defined(CFG_IPBCLK_EQUALS_XLBCLK) +# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) /* Motorola reports IPB should better run at 133 MHz. */ *(vu_long *)MPC5XXX_ADDECR |= 1; /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ addecr = *(vu_long *)MPC5XXX_CDM_CFG; addecr &= ~0x103; -# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2) +# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ addecr |= 0x01; # else /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ addecr |= 0x02; -# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */ +# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ *(vu_long *)MPC5XXX_CDM_CFG = addecr; -# endif /* CFG_IPBCLK_EQUALS_XLBCLK */ +# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ /* Configure the XLB Arbiter */ *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; -# if defined(CFG_XLB_PIPELINING) +# if defined(CONFIG_SYS_XLB_PIPELINING) /* Enable piplining */ *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31); # endif diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S index a07c776..d140c7e 100644 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -23,7 +23,7 @@ scEthernetRecv_Entry: /* Task 0 */ .long 0x00000000 .long 0x00000000 .long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long CFG_MBAR +.long CONFIG_SYS_MBAR .globl scEthernetXmit_Entry scEthernetXmit_Entry: /* Task 1 */ .long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ @@ -33,7 +33,7 @@ scEthernetXmit_Entry: /* Task 1 */ .long 0x00000000 .long 0x00000000 .long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long CFG_MBAR +.long CONFIG_SYS_MBAR .globl scEthernetRecv_TDT @@ -151,7 +151,7 @@ scEthernetRecv_VarTab: /* Task 0 Variable Table */ .long 0x00000000 /* var[6] */ .long 0x00000000 /* var[7] */ .long 0x00000000 /* var[8] */ -.long (CFG_MBAR + 0x8800) /* var[9] */ +.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */ .long 0x00000008 /* var[10] */ .long 0x0000000c /* var[11] */ .long 0x80000000 /* var[12] */ @@ -190,7 +190,7 @@ scEthernetXmit_VarTab: /* Task 1 Variable Table */ .long 0x00000000 /* var[8] */ .long 0x00000000 /* var[9] */ .long 0x00000000 /* var[10] */ -.long (CFG_MBAR + 0x8800) /* var[11] */ +.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */ .long 0x00000000 /* var[12] */ .long 0x80000000 /* var[13] */ .long 0x10000000 /* var[14] */ diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c index 0f02e78..4d16bbe 100644 --- a/cpu/mpc5xxx/i2c.c +++ b/cpu/mpc5xxx/i2c.c @@ -30,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -#if (CFG_I2C_MODULE == 2) +#if (CONFIG_SYS_I2C_MODULE == 2) #define I2C_BASE MPC5XXX_I2C2 -#elif (CFG_I2C_MODULE == 1) +#elif (CONFIG_SYS_I2C_MODULE == 1) #define I2C_BASE MPC5XXX_I2C1 #else -#error CFG_I2C_MODULE is not properly configured +#error CONFIG_SYS_I2C_MODULE is not properly configured #endif #define I2C_TIMEOUT 100 diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index 8816dd1..6035771 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -229,7 +229,7 @@ int mpc5xxx_get_irq(struct pt_regs *regs) int interrupt_init_cpu(ulong * decrementer_count) { - *decrementer_count = get_tbclk() / CFG_HZ; + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; mpc5xxx_init_irq(); diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c index 2f01d5c..a3251ab 100644 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -31,8 +31,8 @@ #include /* System RAM mapped over PCI */ -#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE #define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024) /* PCIIWCR bit fields */ @@ -125,11 +125,11 @@ void pci_mpc5xxx_init (struct pci_controller *hose) /* Set cache line size */ *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) | - (CFG_CACHELINE_SIZE / 4); + (CONFIG_SYS_CACHELINE_SIZE / 4); /* Map MBAR to PCI space */ - *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1; + *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR; + *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1; /* Map RAM to PCI space */ *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index 430d63f..a8a384a 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -106,7 +106,7 @@ int serial_init (void) /* select clock sources */ #if defined(CONFIG_MGT5100) psc->psc_clock_select = 0xdd00; - baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; + baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; #elif defined(CONFIG_MPC5200) psc->psc_clock_select = 0; baseclk = (gd->ipb_clk + 16) / 32; @@ -247,7 +247,7 @@ void serial_setbrg(void) unsigned long baseclk, div; #if defined(CONFIG_MGT5100) - baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; + baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; #elif defined(CONFIG_MPC5200) baseclk = (gd->ipb_clk + 16) / 32; #endif diff --git a/cpu/mpc5xxx/speed.c b/cpu/mpc5xxx/speed.c index 7847adc..0e3e552 100644 --- a/cpu/mpc5xxx/speed.c +++ b/cpu/mpc5xxx/speed.c @@ -47,15 +47,15 @@ int get_clocks (void) { ulong val, vco; -#if !defined(CFG_MPC5XXX_CLKIN) -#error clock measuring not implemented yet - define CFG_MPC5XXX_CLKIN +#if !defined(CONFIG_SYS_MPC5XXX_CLKIN) +#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN #endif val = *(vu_long *)MPC5XXX_CDM_PORCFG; if (val & (1 << 6)) { - vco = CFG_MPC5XXX_CLKIN * 12; + vco = CONFIG_SYS_MPC5XXX_CLKIN * 12; } else { - vco = CFG_MPC5XXX_CLKIN * 16; + vco = CONFIG_SYS_MPC5XXX_CLKIN * 16; } if (val & (1 << 5)) { gd->bus_clk = vco / 8; diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 9b1bd48..defe77d 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -106,19 +106,19 @@ boot_warm: /* Move CSBoot and adjust instruction pointer */ /*--------------------------------------------------------------*/ -#if defined(CFG_LOWBOOT) -# if defined(CFG_RAMBOOT) -# error CFG_LOWBOOT is incompatible with CFG_RAMBOOT -# endif /* CFG_RAMBOOT */ +#if defined(CONFIG_SYS_LOWBOOT) +# if defined(CONFIG_SYS_RAMBOOT) +# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT +# endif /* CONFIG_SYS_RAMBOOT */ # if defined(CONFIG_MGT5100) -# error CFG_LOWBOOT is incompatible with MGT5100 +# error CONFIG_SYS_LOWBOOT is incompatible with MGT5100 # endif /* CONFIG_MGT5100 */ - lis r4, CFG_DEFAULT_MBAR@h - lis r3, START_REG(CFG_BOOTCS_START)@h - ori r3, r3, START_REG(CFG_BOOTCS_START)@l + lis r4, CONFIG_SYS_DEFAULT_MBAR@h + lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h + ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l stw r3, 0x4(r4) /* CS0 start */ - lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l + lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l stw r3, 0x8(r4) /* CS0 stop */ lis r3, 0x02010000@h ori r3, r3, 0x02010000@l @@ -130,20 +130,20 @@ boot_warm: blr lowboot_reentry: - lis r3, START_REG(CFG_BOOTCS_START)@h - ori r3, r3, START_REG(CFG_BOOTCS_START)@l + lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h + ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l stw r3, 0x4c(r4) /* Boot start */ - lis r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h - ori r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l + lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h + ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l stw r3, 0x50(r4) /* Boot stop */ lis r3, 0x02000001@h ori r3, r3, 0x02000001@l stw r3, 0x54(r4) /* Boot enable, CS0 disable */ -#endif /* CFG_LOWBOOT */ +#endif /* CONFIG_SYS_LOWBOOT */ -#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) - lis r3, CFG_MBAR@h - ori r3, r3, CFG_MBAR@l +#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) + lis r3, CONFIG_SYS_MBAR@h + ori r3, r3, CONFIG_SYS_MBAR@l #if defined(CONFIG_MPC5200) /* MBAR is mirrored into the MBAR SPR */ mtspr MBAR,r3 @@ -152,9 +152,9 @@ lowboot_reentry: #if defined(CONFIG_MGT5100) rlwinm r3, r3, 17, 15, 31 #endif - lis r4, CFG_DEFAULT_MBAR@h + lis r4, CONFIG_SYS_DEFAULT_MBAR@h stw r3, 0(r4) -#endif /* CFG_DEFAULT_MBAR */ +#endif /* CONFIG_SYS_DEFAULT_MBAR */ /* Initialise the MPC5xxx processor core */ /*--------------------------------------------------------------*/ @@ -165,9 +165,9 @@ lowboot_reentry: /*--------------------------------------------------------------*/ /* set up stack in on-chip SRAM */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - ori r1, r3, CFG_INIT_SP_OFFSET + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -400,13 +400,13 @@ init_5xxx_core: /* HID0 also contains cache control */ /*--------------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l SYNC mtspr HID0, r3 @@ -582,16 +582,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ diff --git a/cpu/mpc5xxx/usb.c b/cpu/mpc5xxx/usb.c index ed467ab..8f2b66a 100644 --- a/cpu/mpc5xxx/usb.c +++ b/cpu/mpc5xxx/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) #include @@ -51,4 +51,4 @@ int usb_cpu_init_fail(void) return 0; } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c index be274cd..5b3fdd3 100644 --- a/cpu/mpc8220/cpu.c +++ b/cpu/mpc8220/cpu.c @@ -42,7 +42,7 @@ int checkcpu (void) printf (CPU_ID_STR); - printf (" (JTAG ID %08lx)", *(vu_long *) (CFG_MBAR + 0x50)); + printf (" (JTAG ID %08lx)", *(vu_long *) (CONFIG_SYS_MBAR + 0x50)); printf (" at %s MHz\n", strmhz (buf, clock)); diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c index 0daac5b..8f52c7d 100644 --- a/cpu/mpc8220/cpu_init.c +++ b/cpu/mpc8220/cpu_init.c @@ -39,7 +39,7 @@ void cpu_init_f (void) volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB; /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -49,54 +49,54 @@ void cpu_init_f (void) portcfg->pcfg1 = 0; portcfg->pcfg2 = 0; portcfg->pcfg3 = 0; - portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG; - portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG; + portcfg->pcfg2 = CONFIG_SYS_GP1_PORT2_CONFIG; + portcfg->pcfg3 = CONFIG_SYS_PCI_PORT3_CONFIG | CONFIG_SYS_GP2_PORT3_CONFIG; /* * Flexbus Controller: configure chip selects and enable them */ -#if defined (CFG_CS0_BASE) - flexbus->csar0 = CFG_CS0_BASE; +#if defined (CONFIG_SYS_CS0_BASE) + flexbus->csar0 = CONFIG_SYS_CS0_BASE; /* Sorcery-C can hang-up after CTRL reg initialization */ -#if defined (CFG_CS0_CTRL) - flexbus->cscr0 = CFG_CS0_CTRL; +#if defined (CONFIG_SYS_CS0_CTRL) + flexbus->cscr0 = CONFIG_SYS_CS0_CTRL; #endif - flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1; + flexbus->csmr0 = ((CONFIG_SYS_CS0_MASK - 1) & 0xffff0000) | 1; __asm__ volatile ("sync"); #endif -#if defined (CFG_CS1_BASE) - flexbus->csar1 = CFG_CS1_BASE; - flexbus->cscr1 = CFG_CS1_CTRL; - flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1; +#if defined (CONFIG_SYS_CS1_BASE) + flexbus->csar1 = CONFIG_SYS_CS1_BASE; + flexbus->cscr1 = CONFIG_SYS_CS1_CTRL; + flexbus->csmr1 = ((CONFIG_SYS_CS1_MASK - 1) & 0xffff0000) | 1; __asm__ volatile ("sync"); #endif -#if defined (CFG_CS2_BASE) - flexbus->csar2 = CFG_CS2_BASE; - flexbus->cscr2 = CFG_CS2_CTRL; - flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG; +#if defined (CONFIG_SYS_CS2_BASE) + flexbus->csar2 = CONFIG_SYS_CS2_BASE; + flexbus->cscr2 = CONFIG_SYS_CS2_CTRL; + flexbus->csmr2 = ((CONFIG_SYS_CS2_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CONFIG_SYS_CS2_PORT3_CONFIG; __asm__ volatile ("sync"); #endif -#if defined (CFG_CS3_BASE) - flexbus->csar3 = CFG_CS3_BASE; - flexbus->cscr3 = CFG_CS3_CTRL; - flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG; +#if defined (CONFIG_SYS_CS3_BASE) + flexbus->csar3 = CONFIG_SYS_CS3_BASE; + flexbus->cscr3 = CONFIG_SYS_CS3_CTRL; + flexbus->csmr3 = ((CONFIG_SYS_CS3_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CONFIG_SYS_CS3_PORT3_CONFIG; __asm__ volatile ("sync"); #endif -#if defined (CFG_CS4_BASE) - flexbus->csar4 = CFG_CS4_BASE; - flexbus->cscr4 = CFG_CS4_CTRL; - flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG; +#if defined (CONFIG_SYS_CS4_BASE) + flexbus->csar4 = CONFIG_SYS_CS4_BASE; + flexbus->cscr4 = CONFIG_SYS_CS4_CTRL; + flexbus->csmr4 = ((CONFIG_SYS_CS4_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CONFIG_SYS_CS4_PORT3_CONFIG; __asm__ volatile ("sync"); #endif -#if defined (CFG_CS5_BASE) - flexbus->csar5 = CFG_CS5_BASE; - flexbus->cscr5 = CFG_CS5_CTRL; - flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1; - portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG; +#if defined (CONFIG_SYS_CS5_BASE) + flexbus->csar5 = CONFIG_SYS_CS5_BASE; + flexbus->cscr5 = CONFIG_SYS_CS5_CTRL; + flexbus->csmr5 = ((CONFIG_SYS_CS5_MASK - 1) & 0xffff0000) | 1; + portcfg->pcfg3 |= CONFIG_SYS_CS5_PORT3_CONFIG; __asm__ volatile ("sync"); #endif diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c index 08e3172..52cf133 100644 --- a/cpu/mpc8220/dramSetup.c +++ b/cpu/mpc8220/dramSetup.c @@ -34,9 +34,9 @@ characteristics to initialize the dram on MPC8220 DECLARE_GLOBAL_DATA_PTR; -#define SPD_SIZE CFG_SDRAM_SPD_SIZE -#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */ -#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS +#define SPD_SIZE CONFIG_SYS_SDRAM_SPD_SIZE +#define DRAM_SPD (CONFIG_SYS_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */ +#define TOTAL_BANK CONFIG_SYS_SDRAM_TOTAL_BANKS int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse) { @@ -103,7 +103,7 @@ int readSpdData (u8 * spdData) /* Enable Port Configuration for SDA and SDL signals */ pcfg = (volatile pcfg8220_t *) (MMAP_PCFG); __asm__ ("sync"); - pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG; + pcfg->pcfg3 &= ~CONFIG_SYS_I2C_PORT3_CONFIG; __asm__ ("sync"); /* Points the structure to I2c mbar memory offset */ @@ -144,7 +144,7 @@ int readSpdData (u8 * spdData) break; } - pi2cReg->adr = CFG_I2C_SLAVE<<1; + pi2cReg->adr = CONFIG_SYS_I2C_SLAVE<<1; pi2cReg->cr = I2C_CTL_EN; /* Set Enable */ @@ -541,7 +541,7 @@ u32 dramSetup (void) } /* Set up the Drive Strength register */ - sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH; + sysconf->sdramds = CONFIG_SYS_SDRAM_DRIVE_STRENGTH; /* ********************** Cfg 1 ************************* */ @@ -679,7 +679,7 @@ u32 dramSetup (void) /* Set up mode value for CAS latency */ -#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */ +#if (CONFIG_SYS_SDRAM_CAS_LATENCY==5) /* CL=2.5 */ mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD); #else diff --git a/cpu/mpc8220/interrupts.c b/cpu/mpc8220/interrupts.c index 036378c..78e9917 100644 --- a/cpu/mpc8220/interrupts.c +++ b/cpu/mpc8220/interrupts.c @@ -34,7 +34,7 @@ int interrupt_init_cpu (ulong * decrementer_count) { - *decrementer_count = get_tbclk () / CFG_HZ; + *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; return (0); } diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c index 4ef214e..a78a828 100644 --- a/cpu/mpc8220/pci.c +++ b/cpu/mpc8220/pci.c @@ -33,8 +33,8 @@ #if defined(CONFIG_PCI) /* System RAM mapped over PCI */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) #define cfg_read(val, addr, type, op) *val = op((type)(addr)); diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c index 200a762..c01ca0c 100644 --- a/cpu/mpc8220/speed.c +++ b/cpu/mpc8220/speed.c @@ -67,25 +67,25 @@ int get_clocks (void) u32 hid1; int i, size, pci2bus; -#if !defined(CFG_MPC8220_CLKIN) -#error clock measuring not implemented yet - define CFG_MPC8220_CLKIN +#if !defined(CONFIG_SYS_MPC8220_CLKIN) +#error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN #endif - gd->inp_clk = CFG_MPC8220_CLKIN; + gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN; /* Read XLB to PCI(INP) clock multiplier */ pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT; /* XLB bus clock */ - gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus; + gd->bus_clk = CONFIG_SYS_MPC8220_CLKIN * pci2bus; /* PCI clock is same as input clock */ - gd->pci_clk = CFG_MPC8220_CLKIN; + gd->pci_clk = CONFIG_SYS_MPC8220_CLKIN; /* FlexBus is temporary set as the same as input clock */ /* will do dynamic in the future */ - gd->flb_clk = CFG_MPC8220_CLKIN; + gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN; /* CPU Clock - Read HID1 */ asm volatile ("mfspr %0, 1009":"=r" (hid1):); @@ -97,7 +97,7 @@ int get_clocks (void) for (i = 0; i < size; i++) if (hid1 == bus2core[i].hid1) { gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1; - gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; + gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; break; } diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index b5145ca..373be2c 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -105,16 +105,16 @@ boot_warm: /* replace default MBAR base address from 0x80000000 to 0xf0000000 */ -#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT) - lis r3, CFG_MBAR@h - ori r3, r3, CFG_MBAR@l +#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT) + lis r3, CONFIG_SYS_MBAR@h + ori r3, r3, CONFIG_SYS_MBAR@l /* MBAR is mirrored into the MBAR SPR */ mtspr MBAR,r3 mtspr SPRN_SPRG7W,r3 - lis r4, CFG_DEFAULT_MBAR@h + lis r4, CONFIG_SYS_DEFAULT_MBAR@h stw r3, 0(r4) -#endif /* CFG_DEFAULT_MBAR */ +#endif /* CONFIG_SYS_DEFAULT_MBAR */ /* Initialise the MPC8220 processor core */ /*--------------------------------------------------------------*/ @@ -125,9 +125,9 @@ boot_warm: /*--------------------------------------------------------------*/ /* set up stack in on-chip SRAM */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - ori r1, r3, CFG_INIT_SP_OFFSET + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -361,13 +361,13 @@ init_8220_core: /* HID0 also contains cache control */ /*--------------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l SYNC mtspr HID0, r3 @@ -458,7 +458,7 @@ init_8220_core: .globl icache_enable icache_enable: lis r4, 0 - ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */ + ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */ rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ /* @@ -547,16 +547,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c index 0a45cc8..08f6a94 100644 --- a/cpu/mpc824x/cpu.c +++ b/cpu/mpc824x/cpu.c @@ -109,17 +109,17 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, - * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, + * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid * address. Better pick an address known to be invalid on - * your system and assign it to CFG_RESET_ADDRESS. + * your system and assign it to CONFIG_SYS_RESET_ADDRESS. * "(ulong)-1" used to be a good choice for many systems... */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*)(void)) addr) (); return 1; diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index 7871031..395f776 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -25,32 +25,32 @@ #include #include -#ifndef CFG_BANK0_ROW -#define CFG_BANK0_ROW 0 +#ifndef CONFIG_SYS_BANK0_ROW +#define CONFIG_SYS_BANK0_ROW 0 #endif -#ifndef CFG_BANK1_ROW -#define CFG_BANK1_ROW 0 +#ifndef CONFIG_SYS_BANK1_ROW +#define CONFIG_SYS_BANK1_ROW 0 #endif -#ifndef CFG_BANK2_ROW -#define CFG_BANK2_ROW 0 +#ifndef CONFIG_SYS_BANK2_ROW +#define CONFIG_SYS_BANK2_ROW 0 #endif -#ifndef CFG_BANK3_ROW -#define CFG_BANK3_ROW 0 +#ifndef CONFIG_SYS_BANK3_ROW +#define CONFIG_SYS_BANK3_ROW 0 #endif -#ifndef CFG_BANK4_ROW -#define CFG_BANK4_ROW 0 +#ifndef CONFIG_SYS_BANK4_ROW +#define CONFIG_SYS_BANK4_ROW 0 #endif -#ifndef CFG_BANK5_ROW -#define CFG_BANK5_ROW 0 +#ifndef CONFIG_SYS_BANK5_ROW +#define CONFIG_SYS_BANK5_ROW 0 #endif -#ifndef CFG_BANK6_ROW -#define CFG_BANK6_ROW 0 +#ifndef CONFIG_SYS_BANK6_ROW +#define CONFIG_SYS_BANK6_ROW 0 #endif -#ifndef CFG_BANK7_ROW -#define CFG_BANK7_ROW 0 +#ifndef CONFIG_SYS_BANK7_ROW +#define CONFIG_SYS_BANK7_ROW 0 #endif -#ifndef CFG_DBUS_SIZE2 -#define CFG_DBUS_SIZE2 0 +#ifndef CONFIG_SYS_DBUS_SIZE2 +#define CONFIG_SYS_DBUS_SIZE2 0 #endif /* @@ -163,150 +163,150 @@ cpu_init_f (void) #endif CONFIG_WRITE_WORD(PICR2, val); - CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); -#ifndef CFG_RAMBOOT - CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | - (CFG_BANK0_ROW) | - (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | - (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | - (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | - (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | - (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | - (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | - (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | - (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); + CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR); +#ifndef CONFIG_SYS_RAMBOOT + CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | + (CONFIG_SYS_BANK0_ROW) | + (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | + (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | + (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | + (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | + (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | + (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | + (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | + (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)); #endif -#if defined(CFG_ASRISE) && defined(CFG_ASFALL) - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT | - CFG_ASRISE << MCCR2_ASRISE_SHIFT | - CFG_ASFALL << MCCR2_ASFALL_SHIFT); +#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL) + CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT | + CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT | + CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT); #else - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); + CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT); #endif #if defined(CONFIG_MPC8240) CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT) | - (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); + (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | + (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)); #elif defined(CONFIG_MPC8245) CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT)); + (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT)); #else #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) #endif /* this is gross. We think these should all be the same, and various boards - * should define CFG_ACTORW to 0 if they don't want to set it, or even, if + * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if * its not set, we define it to zero in this file */ #if defined(CONFIG_CU824) || defined(CONFIG_PN62) CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | MCCR4_BIT21 | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); + (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CONFIG_SYS_BSTOPRE & 0x0003) <> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); #elif defined(CONFIG_MPC8240) CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | MCCR4_BIT21 | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <> 6) <> 6) <> 6) <> 6) <> MICR_ADDR_SHIFT) | - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMSAR1, - ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MSAR2, - ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMSAR2, - ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MEAR1, - ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMEAR1, - ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MEAR2, - ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMEAR2, - ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - - CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); -#ifdef CFG_DLL_MAX_DELAY - CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */ + ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + + CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR); +#ifdef CONFIG_SYS_DLL_MAX_DELAY + CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */ #endif -#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL) - CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL); +#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL) + CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL); #endif -#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD) - CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */ +#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD) + CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */ #endif /* setup & hold time */ CONFIG_WRITE_BYTE(MBER, - CFG_BANK0_ENABLE | - (CFG_BANK1_ENABLE << 1) | - (CFG_BANK2_ENABLE << 2) | - (CFG_BANK3_ENABLE << 3) | - (CFG_BANK4_ENABLE << 4) | - (CFG_BANK5_ENABLE << 5) | - (CFG_BANK6_ENABLE << 6) | - (CFG_BANK7_ENABLE << 7)); - -#ifdef CFG_PGMAX - CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX); + CONFIG_SYS_BANK0_ENABLE | + (CONFIG_SYS_BANK1_ENABLE << 1) | + (CONFIG_SYS_BANK2_ENABLE << 2) | + (CONFIG_SYS_BANK3_ENABLE << 3) | + (CONFIG_SYS_BANK4_ENABLE << 4) | + (CONFIG_SYS_BANK5_ENABLE << 5) | + (CONFIG_SYS_BANK6_ENABLE << 6) | + (CONFIG_SYS_BANK7_ENABLE << 7)); + +#ifdef CONFIG_SYS_PGMAX + CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX); #endif /* ! Wait 200us before initialize other registers */ diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c index f89deed..ecbb42d 100644 --- a/cpu/mpc824x/drivers/epic/epic1.c +++ b/cpu/mpc824x/drivers/epic/epic1.c @@ -311,7 +311,7 @@ ULONG sysEUMBBARRead { ULONG temp; - temp = *(ULONG *) (CFG_EUMB_ADDR + regNum); + temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum); return ( LONGSWAP(temp)); } @@ -331,7 +331,7 @@ void sysEUMBBARWrite ) { - *(ULONG *) (CFG_EUMB_ADDR + regNum) = LONGSWAP(regVal); + *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal); return ; } diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c index 3add687..854345e 100644 --- a/cpu/mpc824x/drivers/i2c/i2c.c +++ b/cpu/mpc824x/drivers/i2c/i2c.c @@ -31,9 +31,9 @@ #ifdef CONFIG_HARD_I2C #include -#define TIMEOUT (CFG_HZ/4) +#define TIMEOUT (CONFIG_SYS_HZ/4) -#define I2C_Addr ((unsigned *)(CFG_EUMB_ADDR + 0x3000)) +#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000)) #define I2CADR &I2C_Addr[0] #define I2CFDR &I2C_Addr[1] diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c index 4359ecc..139c52c 100644 --- a/cpu/mpc824x/interrupts.c +++ b/cpu/mpc824x/interrupts.c @@ -31,7 +31,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) { - *decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ; + *decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ; /* * It's all broken at the moment and I currently don't need @@ -57,7 +57,7 @@ void external_interrupt (struct pt_regs *regs) { register unsigned long temp; - pci_readl (CFG_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); + pci_readl (CONFIG_SYS_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); sync (); /* i'm not convinced this is needed, but dink source has it */ temp &= 0xff; /*get vector */ diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 784edc3..b5d7eb1 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -157,8 +157,8 @@ in_flash: /* Allocate Initial RAM in data cache. */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l li r2, 128 mtctr r2 1: @@ -180,8 +180,8 @@ in_flash: * Thisk the stack pointer *somewhere* sensible. Doesnt * matter much where as we'll move it when we relocate */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -475,21 +475,21 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ -#ifdef CFG_RAMBOOT - lis r4, CFG_SDRAM_BASE@h /* Source Address */ - ori r4, r4, CFG_SDRAM_BASE@l +#ifdef CONFIG_SYS_RAMBOOT + lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_SDRAM_BASE@l #else - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l #endif lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -531,8 +531,8 @@ relocate_code: /* Unlock the data cache and invalidate locked area */ xor r0, r0, r0 mtspr 1011, r0 - lis r4, CFG_INIT_RAM_ADDR@h - ori r4, r4, CFG_INIT_RAM_ADDR@l + lis r4, CONFIG_SYS_INIT_RAM_ADDR@h + ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l li r0, 128 mtctr r0 41: @@ -709,66 +709,66 @@ trap_reloc: /* Setup the BAT registers. */ setup_bats: - lis r4, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - lis r3, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l + lis r4, CONFIG_SYS_IBAT0L@h + ori r4, r4, CONFIG_SYS_IBAT0L@l + lis r3, CONFIG_SYS_IBAT0U@h + ori r3, r3, CONFIG_SYS_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 isync - lis r4, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - lis r3, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l + lis r4, CONFIG_SYS_DBAT0L@h + ori r4, r4, CONFIG_SYS_DBAT0L@l + lis r3, CONFIG_SYS_DBAT0U@h + ori r3, r3, CONFIG_SYS_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 isync - lis r4, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - lis r3, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l + lis r4, CONFIG_SYS_IBAT1L@h + ori r4, r4, CONFIG_SYS_IBAT1L@l + lis r3, CONFIG_SYS_IBAT1U@h + ori r3, r3, CONFIG_SYS_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 isync - lis r4, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - lis r3, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l + lis r4, CONFIG_SYS_DBAT1L@h + ori r4, r4, CONFIG_SYS_DBAT1L@l + lis r3, CONFIG_SYS_DBAT1U@h + ori r3, r3, CONFIG_SYS_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 isync - lis r4, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - lis r3, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l + lis r4, CONFIG_SYS_IBAT2L@h + ori r4, r4, CONFIG_SYS_IBAT2L@l + lis r3, CONFIG_SYS_IBAT2U@h + ori r3, r3, CONFIG_SYS_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 isync - lis r4, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - lis r3, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l + lis r4, CONFIG_SYS_DBAT2L@h + ori r4, r4, CONFIG_SYS_DBAT2L@l + lis r3, CONFIG_SYS_DBAT2U@h + ori r3, r3, CONFIG_SYS_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 isync - lis r4, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - lis r3, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l + lis r4, CONFIG_SYS_IBAT3L@h + ori r4, r4, CONFIG_SYS_IBAT3L@l + lis r3, CONFIG_SYS_IBAT3U@h + ori r3, r3, CONFIG_SYS_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 isync - lis r4, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - lis r3, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l + lis r4, CONFIG_SYS_DBAT3L@h + ori r4, r4, CONFIG_SYS_DBAT3L@l + lis r3, CONFIG_SYS_DBAT3U@h + ori r3, r3, CONFIG_SYS_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 isync diff --git a/cpu/mpc8260/commproc.c b/cpu/mpc8260/commproc.c index 8777e77..94f6bc2 100644 --- a/cpu/mpc8260/commproc.c +++ b/cpu/mpc8260/commproc.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; void m8260_cpm_reset(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile ulong count; /* Reclaim the DP memory for our use. @@ -54,7 +54,7 @@ m8260_cpm_reset(void) uint m8260_cpm_dpalloc(uint size, uint align) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint retloc; uint align_mask, off; uint savebase; @@ -110,7 +110,7 @@ m8260_cpm_hostalloc(uint size, uint align) void m8260_cpm_setbrg(uint brg, uint rate) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *bp; uint cd = BRG_UART_CLK / rate; @@ -133,7 +133,7 @@ m8260_cpm_setbrg(uint brg, uint rate) void m8260_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *bp; /* This is good enough to get SMCs running..... @@ -158,7 +158,7 @@ m8260_cpm_fastbrg(uint brg, uint rate, int div16) void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *bp; if (brg < 4) { @@ -181,7 +181,7 @@ m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) void post_word_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); *save_addr = a; } @@ -189,7 +189,7 @@ void post_word_store (ulong a) ulong post_word_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); return *save_addr; } @@ -201,7 +201,7 @@ ulong post_word_load (void) void bootcount_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); save_addr[0] = a; save_addr[1] = BOOTCOUNT_MAGIC; @@ -210,7 +210,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_BOOTCOUNT_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); if (save_addr[1] != BOOTCOUNT_MAGIC) return 0; diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index efb8ed6..9f834d3 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -61,7 +61,7 @@ extern int get_cpu_str_f (char *buf); int checkcpu (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong clock = gd->cpu_clk; uint pvr = get_pvr (); uint immr, rev, m, k; @@ -88,7 +88,7 @@ int checkcpu (void) rev = pvr & 0xff; immr = immap->im_memctl.memc_immr; - if ((immr & IMMR_ISB_MSK) != CFG_IMMR) + if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR) return -1; /* whoops! someone moved the IMMR */ #if defined(CONFIG_GET_CPU_STR_F) @@ -178,7 +178,7 @@ int checkcpu (void) void upmconfig (uint upm, uint * table, uint size) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */ uint i; @@ -241,7 +241,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { ulong msr, addr; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */ @@ -255,15 +255,15 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*)(void)) addr) (); return 1; @@ -293,7 +293,7 @@ void watchdog_reset (void) { int re_enable = disable_interrupts (); - reset_8260_watchdog ((immap_t *) CFG_IMMR); + reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR); if (re_enable) enable_interrupts (); } diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 36fc1eb..1d52773 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -114,7 +114,7 @@ void cpu_init_f (volatile immap_t * immr) extern void m8260_cpm_reset (void); /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -124,45 +124,45 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrst.car_rsr = RSR_ALLBITS; /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ - immr->im_clkrst.car_rmr = CFG_RMR; + immr->im_clkrst.car_rmr = CONFIG_SYS_RMR; /* BCR - Bus Configuration Register (4-25) */ -#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE) +#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE) if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010); + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010); } else { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010); + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010); } #else - immr->im_siu_conf.sc_bcr = CFG_BCR; + immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR; #endif /* SIUMCR - contains debug pin configuration (4-31) */ -#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH) +#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH) cpu_clk = board_get_cpu_clk_f (); if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000); + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000); } else { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000); + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000); } #else - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; + immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; #endif config_8260_ioports (immr); /* initialize time counter status and control register (4-40) */ - immr->im_sit.sit_tmcntsc = CFG_TMCNTSC; + immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC; /* initialize the PIT (4-42) */ - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; #if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ /* System clock control register (9-8) */ sccr = immr->im_clkrst.car_sccr & (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK); immr->im_clkrst.car_sccr = sccr | - (CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); + (CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) ); #endif /* !CONFIG_COGENT */ /* @@ -174,71 +174,71 @@ void cpu_init_f (volatile immap_t * immr) * has been determined */ -#if defined(CFG_OR0_REMAP) - memctl->memc_or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->memc_or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ /* the PS came from the HRCW, don´t change it */ - memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK); - memctl->memc_or0 = CFG_OR0_PRELIM; + memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CONFIG_SYS_BR0_PRELIM, BRx_PS_MSK); + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->memc_or6 = CFG_OR6_PRELIM; - memctl->memc_br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; + memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->memc_or7 = CFG_OR7_PRELIM; - memctl->memc_br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; + memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif -#if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM) - memctl->memc_or8 = CFG_OR8_PRELIM; - memctl->memc_br8 = CFG_BR8_PRELIM; +#if defined(CONFIG_SYS_BR8_PRELIM) && defined(CONFIG_SYS_OR8_PRELIM) + memctl->memc_or8 = CONFIG_SYS_OR8_PRELIM; + memctl->memc_br8 = CONFIG_SYS_BR8_PRELIM; #endif -#if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM) - memctl->memc_or9 = CFG_OR9_PRELIM; - memctl->memc_br9 = CFG_BR9_PRELIM; +#if defined(CONFIG_SYS_BR9_PRELIM) && defined(CONFIG_SYS_OR9_PRELIM) + memctl->memc_or9 = CONFIG_SYS_OR9_PRELIM; + memctl->memc_br9 = CONFIG_SYS_BR9_PRELIM; #endif -#if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM) - memctl->memc_or10 = CFG_OR10_PRELIM; - memctl->memc_br10 = CFG_BR10_PRELIM; +#if defined(CONFIG_SYS_BR10_PRELIM) && defined(CONFIG_SYS_OR10_PRELIM) + memctl->memc_or10 = CONFIG_SYS_OR10_PRELIM; + memctl->memc_br10 = CONFIG_SYS_BR10_PRELIM; #endif -#if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM) - memctl->memc_or11 = CFG_OR11_PRELIM; - memctl->memc_br11 = CFG_BR11_PRELIM; +#if defined(CONFIG_SYS_BR11_PRELIM) && defined(CONFIG_SYS_OR11_PRELIM) + memctl->memc_or11 = CONFIG_SYS_OR11_PRELIM; + memctl->memc_br11 = CONFIG_SYS_BR11_PRELIM; #endif m8260_cpm_reset (); @@ -251,7 +251,7 @@ int cpu_init_r (void) { volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base; - immr->im_cpm.cp_rccr = CFG_RCCR; + immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; return (0); } diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 37bf445..3ab57eb 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -73,8 +73,8 @@ static struct ether_fcc_info_s PROFF_FCC1, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, - CFG_CMXFCR_MASK1, - CFG_CMXFCR_VALUE1 + CONFIG_SYS_CMXFCR_MASK1, + CONFIG_SYS_CMXFCR_VALUE1 }, #endif @@ -84,8 +84,8 @@ static struct ether_fcc_info_s PROFF_FCC2, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, - CFG_CMXFCR_MASK2, - CFG_CMXFCR_VALUE2 + CONFIG_SYS_CMXFCR_MASK2, + CONFIG_SYS_CMXFCR_VALUE2 }, #endif @@ -95,8 +95,8 @@ static struct ether_fcc_info_s PROFF_FCC3, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, - CFG_CMXFCR_MASK3, - CFG_CMXFCR_VALUE3 + CONFIG_SYS_CMXFCR_MASK3, + CONFIG_SYS_CMXFCR_VALUE3 }, #endif }; @@ -225,7 +225,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8260_t *cp = &(immr->im_cpm); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -246,7 +246,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */ - immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; /* 28.9 - (6): FDSR: Ethernet Syn */ immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555; @@ -296,10 +296,10 @@ static int fec_init(struct eth_device* dev, bd_t *bis) */ pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); /* protocol-specific area */ @@ -366,7 +366,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* write GFMR: disable tx/rx */ immr->im_fcc[info->ether_index].fcc_gfmr &= @@ -646,7 +646,7 @@ swap16 (unsigned short x) void eth_loopback_test (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8260_t *cp = &(immr->im_cpm); int c, nclosed; ulong runtime, nmsec; diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index 633d053..c65f0e0 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -77,8 +77,8 @@ #define TX_BUF_CNT 2 -#if !defined(CFG_SCC_TOUT_LOOP) - #define CFG_SCC_TOUT_LOOP 1000000 +#if !defined(CONFIG_SYS_SCC_TOUT_LOOP) + #define CONFIG_SYS_SCC_TOUT_LOOP 1000000 #endif static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; @@ -111,7 +111,7 @@ int eth_send(volatile void *packet, int length) } for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CFG_SCC_TOUT_LOOP) { + if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { puts ("scc: tx buffer not ready\n"); goto out; } @@ -123,7 +123,7 @@ int eth_send(volatile void *packet, int length) BD_ENET_TX_WRAP); for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CFG_SCC_TOUT_LOOP) { + if (i >= CONFIG_SYS_SCC_TOUT_LOOP) { puts ("scc: tx error\n"); goto out; } @@ -187,7 +187,7 @@ int eth_rx(void) int eth_init(bd_t *bis) { int i; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; scc_enet_t *pram_ptr; uint dpaddr; @@ -203,7 +203,7 @@ int eth_init(bd_t *bis) /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ immr->im_cpmux.cmx_uar = 0; immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | - CFG_CMXSCR_VALUE); + CONFIG_SYS_CMXSCR_VALUE); /* 24.21 (6) write RBASE and TBASE to parameter RAM */ @@ -340,7 +340,7 @@ int eth_init(bd_t *bis) void eth_halt(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); } @@ -348,7 +348,7 @@ void eth_halt(void) #if 0 void restart(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); } diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index a96fbf8..a934193 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -54,12 +54,12 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; /*----------------------------------------------------------------------- * Set default values */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xFE #endif /*----------------------------------------------------------------------- */ @@ -176,7 +176,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval, */ static int i2c_setrate(int hz, int speed) { - immap_t *immap = (immap_t *)CFG_IMMR ; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; int brgval, modval, /* 0-3 */ @@ -219,7 +219,7 @@ static int i2c_setrate(int hz, int speed) void i2c_init(int speed, int slaveadd) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; volatile iic_t *iip; @@ -227,7 +227,7 @@ void i2c_init(int speed, int slaveadd) volatile I2C_BD *rxbd, *txbd; uint dpaddr; -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ @@ -270,7 +270,7 @@ void i2c_init(int speed, int slaveadd) * divide BRGCLK by 1) */ PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ; + i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ; /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; @@ -309,7 +309,7 @@ void i2c_init(int speed, int slaveadd) static void i2c_newio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile iic_t *iip; uint dpaddr; @@ -494,7 +494,7 @@ int i2c_receive(i2c_state_t *state, static int i2c_doio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile iic_t *iip; volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; volatile I2C_BD *txbd, *rxbd; @@ -667,7 +667,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address @@ -679,7 +679,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); @@ -716,7 +716,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address @@ -728,7 +728,7 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); @@ -781,7 +781,7 @@ unsigned int i2c_get_bus_num(void) int i2c_set_bus_num(unsigned int bus) { #if defined(CONFIG_I2C_MUX) - if (bus < CFG_MAX_I2C_BUS) { + if (bus < CONFIG_SYS_MAX_I2C_BUS) { i2c_bus_num = bus; } else { int ret; @@ -793,7 +793,7 @@ int i2c_set_bus_num(unsigned int bus) return ret; } #else - if (bus >= CFG_MAX_I2C_BUS) + if (bus >= CONFIG_SYS_MAX_I2C_BUS) return -1; i2c_bus_num = bus; #endif @@ -802,12 +802,12 @@ int i2c_set_bus_num(unsigned int bus) /* TODO: add 100/400k switching */ unsigned int i2c_get_bus_speed(void) { - return CFG_I2C_SPEED; + return CONFIG_SYS_I2C_SPEED; } int i2c_set_bus_speed(unsigned int speed) { - if (speed != CFG_I2C_SPEED) + if (speed != CONFIG_SYS_I2C_SPEED) return -1; return 0; diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c index bf0d4d0..a7700c4 100644 --- a/cpu/mpc8260/interrupts.c +++ b/cpu/mpc8260/interrupts.c @@ -82,7 +82,7 @@ static u_char irq_to_siubit[] = { static void m8260_mask_irq (unsigned int irq_nr) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int bit, word; volatile uint *simr; @@ -96,7 +96,7 @@ static void m8260_mask_irq (unsigned int irq_nr) static void m8260_unmask_irq (unsigned int irq_nr) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int bit, word; volatile uint *simr; @@ -110,7 +110,7 @@ static void m8260_unmask_irq (unsigned int irq_nr) static void m8260_mask_and_ack (unsigned int irq_nr) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int bit, word; volatile uint *simr, *sipnr; @@ -126,7 +126,7 @@ static void m8260_mask_and_ack (unsigned int irq_nr) static int m8260_get_irq (struct pt_regs *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int irq; unsigned long bits; @@ -142,9 +142,9 @@ static int m8260_get_irq (struct pt_regs *regs) int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ; /* Initialize the default interrupt mapping priorities */ immr->im_intctl.ic_sicr = 0; diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index dae87bb..c5936c7 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -50,21 +50,21 @@ kgdb_flush_cache_all: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 + li r5,CONFIG_SYS_CACHELINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT + srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE + addi r6,r6,CONFIG_SYS_CACHELINE_SIZE bdnz 2b SYNC blr diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 8230364..378d6c5 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -70,23 +70,23 @@ DECLARE_GLOBAL_DATA_PTR; * This window is set up using the first set of Inbound ATU registers */ -#ifndef CFG_PCI_SLV_MEM_LOCAL -#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ #else -#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL +#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL #endif -#ifndef CFG_PCI_SLV_MEM_BUS +#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ #else -#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS +#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS #endif -#ifndef CFG_PICMR0_MASK_ATTRIB +#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ PICMR_PREFETCH_EN) #else -#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB +#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB #endif /* @@ -97,29 +97,29 @@ DECLARE_GLOBAL_DATA_PTR; */ /* PCIBR0 */ -#ifndef CFG_PCI_MSTR0_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ #else -#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL +#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL #endif -#ifndef CFG_PCIMSK0_MASK +#ifndef CONFIG_SYS_PCIMSK0_MASK #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ #else -#define PCIMSK0_MASK CFG_PCIMSK0_MASK +#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK #endif /* PCIBR1 */ -#ifndef CFG_PCI_MSTR1_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ #else -#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL +#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL #endif -#ifndef CFG_PCIMSK1_MASK +#ifndef CONFIG_SYS_PCIMSK1_MASK #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ #else -#define PCIMSK1_MASK CFG_PCIMSK1_MASK +#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK #endif /* @@ -128,34 +128,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_MEM_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ #else -#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL #endif -#ifndef CFG_PCI_MSTR_MEM_BUS +#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ #else -#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS +#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS #endif -#ifndef CFG_CPU_PCI_MEM_START +#ifndef CONFIG_SYS_CPU_PCI_MEM_START #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL #else -#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START +#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START #endif -#ifndef CFG_PCI_MSTR_MEM_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ #else -#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE +#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE #endif -#ifndef CFG_POCMR0_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) #else -#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB +#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB #endif /* @@ -164,34 +164,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_MEMIO_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ #else -#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL +#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL #endif -#ifndef CFG_PCI_MSTR_MEMIO_BUS +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ #else -#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS +#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS #endif -#ifndef CFG_CPU_PCI_MEMIO_START +#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL #else -#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START +#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START #endif -#ifndef CFG_PCI_MSTR_MEMIO_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ #else -#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE +#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE #endif -#ifndef CFG_POCMR1_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) #else -#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB +#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB #endif /* @@ -200,34 +200,34 @@ DECLARE_GLOBAL_DATA_PTR; * in the bridge. */ -#ifndef CFG_PCI_MSTR_IO_LOCAL +#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ #else -#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL +#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL #endif -#ifndef CFG_PCI_MSTR_IO_BUS +#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ #else -#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS +#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS #endif -#ifndef CFG_CPU_PCI_IO_START +#ifndef CONFIG_SYS_CPU_PCI_IO_START #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL #else -#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START +#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START #endif -#ifndef CFG_PCI_MSTR_IO_SIZE +#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ #else -#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE +#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE #endif -#ifndef CFG_POCMR2_MASK_ATTRIB +#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) #else -#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB +#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB #endif /* PCI bus configuration registers. @@ -245,11 +245,11 @@ void pci_mpc8250_init (struct pci_controller *hose) { u16 tempShort; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; pci_dev_t host_devno = PCI_BDF (0, 0, 0); - pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, - CFG_IMMR + PCI_CFG_DATA_REG); + pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG, + CONFIG_SYS_IMMR + PCI_CFG_DATA_REG); /* * Setting required to enable local bus for PCI (SIUMCR [LBPC]). @@ -413,8 +413,8 @@ void pci_mpc8250_init (struct pci_controller *hose) gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); #else pci_set_region (hose->regions + 0, - CFG_SDRAM_BASE, - CFG_SDRAM_BASE, + CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); #endif diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c index 3a6eaf0..4ab6a28 100644 --- a/cpu/mpc8260/serial_scc.c +++ b/cpu/mpc8260/serial_scc.c @@ -84,7 +84,7 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -201,7 +201,7 @@ serial_putc(const char c) if (c == '\n') serial_putc ('\r'); - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; @@ -233,7 +233,7 @@ serial_getc(void) volatile immap_t *im; unsigned char c; - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; @@ -257,7 +257,7 @@ serial_tstc() volatile scc_uart_t *up; volatile immap_t *im; - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC]; rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; @@ -321,7 +321,7 @@ serial_tstc() void kgdb_serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -440,7 +440,7 @@ putDebugChar(const char c) if (c == '\n') putDebugChar ('\r'); - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase]; @@ -472,7 +472,7 @@ getDebugChar(void) volatile immap_t *im; unsigned char c; - im = (immap_t *)CFG_IMMR; + im = (immap_t *)CONFIG_SYS_IMMR; up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC]; rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase]; diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c index f3dffeb..a6efa66 100644 --- a/cpu/mpc8260/serial_smc.c +++ b/cpu/mpc8260/serial_smc.c @@ -76,7 +76,7 @@ static unsigned char brg_map[] = { int serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -186,7 +186,7 @@ serial_putc(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (c == '\n') serial_putc ('\r'); @@ -220,7 +220,7 @@ serial_getc(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; unsigned char c; up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); @@ -243,7 +243,7 @@ serial_tstc() { volatile cbd_t *rbdf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); @@ -289,7 +289,7 @@ serial_tstc() void kgdb_serial_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -401,7 +401,7 @@ putDebugChar(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (c == '\n') putDebugChar ('\r'); @@ -435,7 +435,7 @@ getDebugChar(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; unsigned char c; up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]); diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c index 8d280fb..0e1c2b0 100644 --- a/cpu/mpc8260/speed.c +++ b/cpu/mpc8260/speed.c @@ -107,7 +107,7 @@ corecnf_t corecnf_tab[] = { int get_clocks (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong clkin; ulong sccr, dfbrg; ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; @@ -191,7 +191,7 @@ int get_clocks (void) int prt_8260_clks (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong sccr, dfbrg; ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf; corecnf_t *cp; diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c index c1a607c..f5d2ac3 100644 --- a/cpu/mpc8260/spi.c +++ b/cpu/mpc8260/spi.c @@ -63,8 +63,8 @@ * The value 0x2000 makes it far enough from the start of the data * area (as well as from the stack pointer). * --------------------------------------------------------------- */ -#ifndef CFG_SPI_INIT_OFFSET -#define CFG_SPI_INIT_OFFSET 0x2000 +#ifndef CONFIG_SYS_SPI_INIT_OFFSET +#define CONFIG_SYS_SPI_INIT_OFFSET 0x2000 #endif #define CPM_SPI_BASE 0x100 @@ -119,11 +119,11 @@ ssize_t spi_xfer (size_t); * Initially we place the RX and TX buffers at a fixed location in DPRAM! * ---------------------------------------------------------------------- */ static uchar *rxbuf = - (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase - [CFG_SPI_INIT_OFFSET]; + (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase + [CONFIG_SYS_SPI_INIT_OFFSET]; static uchar *txbuf = - (uchar *)&((immap_t *)CFG_IMMR)->im_dprambase - [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; + (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase + [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; /* ************************************************************************** * @@ -143,7 +143,7 @@ void spi_init_f (void) volatile cpm8260_t *cp; volatile cbd_t *tbdf, *rbdf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8260_t *) &immr->im_cpm; *(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI; @@ -200,7 +200,7 @@ void spi_init_f (void) /* Allocate space for one transmit and one receive buffer * descriptor in the DP ram */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8); #else dpaddr = CPM_SPI_BASE; @@ -279,7 +279,7 @@ void spi_init_r (void) volatile cpm8260_t *cp; volatile cbd_t *tbdf, *rbdf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8260_t *) &immr->im_cpm; spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; @@ -365,7 +365,7 @@ ssize_t spi_xfer (size_t count) DPRINT (("*** spi_xfer entered ***\n")); - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8260_t *) &immr->im_cpm; spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 7f5dc81..da0c516 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -127,14 +127,14 @@ version_string: .text .globl _hrcw_table _hrcw_table: - _HRCW_TABLE_ENTRY(CFG_HRCW_MASTER) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6) - _HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7) /* * After configuration, a system reset exception is executed using the * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP] @@ -172,8 +172,8 @@ _start_warm: b boot_warm boot_cold: -#if defined(CONFIG_MPC8260ADS) && defined(CFG_DEFAULT_IMMR) - lis r3, CFG_DEFAULT_IMMR@h +#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR) + lis r3, CONFIG_SYS_DEFAULT_IMMR@h nop lwz r4, 0(r3) nop @@ -183,7 +183,7 @@ boot_cold: nop stw r4, 0(r3) nop -#endif /* CONFIG_MPC8260ADS && CFG_DEFAULT_IMMR */ +#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */ boot_warm: mfmsr r5 /* save msr contents */ @@ -195,24 +195,24 @@ boot_warm: bl cogent_init_8260 #endif /* CONFIG_COGENT */ -#if defined(CFG_DEFAULT_IMMR) - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l - lis r4, CFG_DEFAULT_IMMR@h +#if defined(CONFIG_SYS_DEFAULT_IMMR) + lis r3, CONFIG_SYS_IMMR@h + ori r3, r3, CONFIG_SYS_IMMR@l + lis r4, CONFIG_SYS_DEFAULT_IMMR@h stw r3, 0x1A8(r4) -#endif /* CFG_DEFAULT_IMMR */ +#endif /* CONFIG_SYS_DEFAULT_IMMR */ /* Initialise the MPC8260 processor core */ /*--------------------------------------------------------------*/ bl init_8260_core -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR+IM_REGBASE)@h + lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h lwz r4, IM_OR0@l(r3) li r5, 0x7fff and r4, r4, r5 @@ -221,20 +221,20 @@ boot_warm: /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr in_flash: -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* initialize some things that are hard to access from C */ /*--------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* set up stack in internal DPRAM */ - ori r1, r3, CFG_INIT_SP_OFFSET + lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */ + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -458,18 +458,18 @@ cogent_init_8260: /* Taken from page 14 of CMA282 manual */ /*--------------------------------------------------------------*/ - lis r4, (CFG_IMMR+IM_REGBASE)@h - lis r3, CFG_IMMR@h + lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h + lis r3, CONFIG_SYS_IMMR@h stw r3, IM_IMMR@l(r4) lwz r3, IM_IMMR@l(r4) stw r3, 0(r0) - lis r3, CFG_SYPCR@h - ori r3, r3, CFG_SYPCR@l + lis r3, CONFIG_SYS_SYPCR@h + ori r3, r3, CONFIG_SYS_SYPCR@l stw r3, IM_SYPCR@l(r4) lwz r3, IM_SYPCR@l(r4) stw r3, 4(r0) - lis r3, CFG_SCCR@h - ori r3, r3, CFG_SCCR@l + lis r3, CONFIG_SYS_SCCR@h + ori r3, r3, CONFIG_SYS_SCCR@l stw r3, IM_SCCR@l(r4) lwz r3, IM_SCCR@l(r4) stw r3, 8(r0) @@ -521,10 +521,10 @@ init_8260_core: /* Initialise the SYPCR early, and reset the watchdog (if req) */ /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR+IM_REGBASE)@h + lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h #if !defined(CONFIG_COGENT) - lis r4, CFG_SYPCR@h - ori r4, r4, CFG_SYPCR@l + lis r4, CONFIG_SYS_SYPCR@h + ori r4, r4, CONFIG_SYS_SYPCR@l stw r4, IM_SYPCR@l(r3) #endif /* !CONFIG_COGENT */ #if defined(CONFIG_WATCHDOG) @@ -538,18 +538,18 @@ init_8260_core: /* HID0 also contains cache control */ /*--------------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, CONFIG_SYS_HID0_INIT@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, CONFIG_SYS_HID0_FINAL@l SYNC mtspr HID0, r3 - lis r3, CFG_HID2@h - ori r3, r3, CFG_HID2@l + lis r3, CONFIG_SYS_HID2@h + ori r3, r3, CONFIG_SYS_HID2@l mtspr HID2, r3 /* clear all BAT's */ @@ -619,29 +619,29 @@ init_8260_core: .globl init_debug init_debug: - lis r3, (CFG_IMMR+IM_REGBASE)@h + lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h /* Quick and dirty hack to enable the RAM and copy the */ /* vectors so that we can take exceptions. */ /*--------------------------------------------------------------*/ /* write Memory Refresh Prescaler */ - li r4, CFG_MPTPR + li r4, CONFIG_SYS_MPTPR sth r4, IM_MPTPR@l(r3) /* write 60x Refresh Timer */ - li r4, CFG_PSRT + li r4, CONFIG_SYS_PSRT stb r4, IM_PSRT@l(r3) /* init the 60x SDRAM Mode Register */ - lis r4, (CFG_PSDMR|PSDMR_OP_NORM)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l stw r4, IM_PSDMR@l(r3) /* write Precharge All Banks command */ - lis r4, (CFG_PSDMR|PSDMR_OP_PREA)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) /* write eight CBR Refresh commands */ - lis r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) stb r0, 0(0) @@ -652,13 +652,13 @@ init_debug: stb r0, 0(0) stb r0, 0(0) /* write Mode Register Write command */ - lis r4, (CFG_PSDMR|PSDMR_OP_MRW)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) /* write Normal Operation command and enable Refresh */ - lis r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h - ori r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l + lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h + ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l stw r4, IM_PSDMR@l(r3) stb r0, 0(0) /* RAM should now be operational */ @@ -687,7 +687,7 @@ init_debug: /* an exception is generated (before the instruction at that */ /* location completes). The vector for this exception is 0x1300 */ /*--------------------------------------------------------------*/ - lis r3, CFG_IMMR@h + lis r3, CONFIG_SYS_IMMR@h lwz r3, 0(r3) mtspr IABR, r3 @@ -695,9 +695,9 @@ init_debug: /* resides) to a known value - makes it easier to see where */ /* the stack has been written */ /*--------------------------------------------------------------*/ - lis r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h - ori r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l - li r4, ((CFG_INIT_SP_OFFSET - 4) / 4) + lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h + ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l + li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4) mtctr r4 lis r4, 0xdeadbeaf@h ori r4, r4, 0xdeadbeaf@l @@ -807,16 +807,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index b5d416c..6624544 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -111,7 +111,7 @@ _exception(int signr, struct pt_regs *regs) void dump_pci (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; printf ("PCI: err status %x err mask %x err ctrl %x\n", le32_to_cpu (immap->im_pci.pci_esr), @@ -135,7 +135,7 @@ MachineCheckException(struct pt_regs *regs) * the PCI exception handler. */ #ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; #ifdef DEBUG dump_pci(); #endif diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 99ab216..05c2f33 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -67,7 +67,7 @@ int checkcpu(void) CPU_TYPE_ENTRY(8379), }; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; puts("CPU: "); @@ -148,7 +148,7 @@ int checkcpu(void) void upmconfig (uint upm, uint *table, uint size) { #if defined(CONFIG_MPC834X) - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile lbus83xx_t *lbus = &immap->lbus; volatile uchar *dummy = NULL; const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ @@ -196,7 +196,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr; #endif - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef MPC83xx_RESET /* Interrupts and MMU off */ @@ -235,7 +235,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ - addr = CFG_RESET_ADDRESS; + addr = CONFIG_SYS_RESET_ADDRESS; printf("resetting the board."); printf("\n"); @@ -266,7 +266,7 @@ void watchdog_reset (void) int re_enable = disable_interrupts(); /* Reset the 83xx watchdog */ - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; immr->wdt.swsrr = 0x556c; immr->wdt.swsrr = 0xaa39; @@ -278,7 +278,7 @@ void watchdog_reset (void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 dmamr0 = swab32(dma->dmamr0); @@ -309,7 +309,7 @@ void dma_init(void) uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 byte_count = swab32(dma->dmabcr0); @@ -328,7 +328,7 @@ uint dma_check(void) int dma_xfer(void *dest, u32 count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile dma83xx_t *dma = &immap->dma; volatile u32 dmamr0; diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index ff01cf1..491c2e5 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -60,107 +60,107 @@ static void config_qe_ioports(void) void cpu_init_f (volatile immap_t * im) { /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); /* system performance tweaking */ -#ifdef CFG_ACR_PIPE_DEP +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif -#ifdef CFG_ACR_RPTCNT +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); #endif -#ifdef CFG_SPCR_OPT +#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other devices */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CFG_SPCR_OPT << SPCR_OPT_SHIFT); + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); #endif -#ifdef CFG_SPCR_TSECEP +#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | - (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT); + (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT); #endif -#ifdef CFG_SPCR_TSEC1EP +#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | - (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); + (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); #endif -#ifdef CFG_SPCR_TSEC2EP +#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | - (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); + (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); #endif -#ifdef CFG_SCCR_ENCCM +#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT); + (CONFIG_SYS_SCCR_ENCCM << SCCR_PCICM_SHIFT); #endif -#ifdef CFG_SCCR_PCICM +#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | - (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT); + (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT); #endif -#ifdef CFG_SCCR_TSECCM +#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | - (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT); + (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT); #endif -#ifdef CFG_SCCR_TSEC1CM +#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | - (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); + (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); #endif -#ifdef CFG_SCCR_TSEC2CM +#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | - (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); + (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); #endif -#ifdef CFG_SCCR_TSEC1ON +#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | - (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); + (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); #endif -#ifdef CFG_SCCR_TSEC2ON +#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | - (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); + (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); #endif -#ifdef CFG_SCCR_USBMPHCM +#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | - (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); + (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); #endif -#ifdef CFG_SCCR_USBDRCM +#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | - (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); + (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); #endif -#ifdef CFG_SCCR_SATACM +#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | - (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT); + (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT); #endif /* RSR - Reset Status Register - clear all status (4.6.1.3) */ @@ -178,30 +178,30 @@ void cpu_init_f (volatile immap_t * im) im->reset.rmr = (RMR_CSRE & (1<lbus.lcrr = CFG_LCRR; + im->lbus.lcrr = CONFIG_SYS_LCRR; /* Enable Time Base & Decrimenter ( so we will have udelay() )*/ im->sysconf.spcr |= SPCR_TBEN; /* System General Purpose Register */ -#ifdef CFG_SICRH +#ifdef CONFIG_SYS_SICRH #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH; + im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH; #else - im->sysconf.sicrh = CFG_SICRH; + im->sysconf.sicrh = CONFIG_SYS_SICRH; #endif #endif -#ifdef CFG_SICRL - im->sysconf.sicrl = CFG_SICRL; +#ifdef CONFIG_SYS_SICRL + im->sysconf.sicrl = CONFIG_SYS_SICRL; #endif /* DDR control driver register */ -#ifdef CFG_DDRCDR - im->sysconf.ddrcdr = CFG_DDRCDR; +#ifdef CONFIG_SYS_DDRCDR + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; #endif /* Output buffer impedance register */ -#ifdef CFG_OBIR - im->sysconf.obir = CFG_OBIR; +#ifdef CONFIG_SYS_OBIR + im->sysconf.obir = CONFIG_SYS_OBIR; #endif #ifdef CONFIG_QE @@ -218,88 +218,88 @@ void cpu_init_f (volatile immap_t * im) * has been determined */ -#if defined(CFG_BR0_PRELIM) \ - && defined(CFG_OR0_PRELIM) \ - && defined(CFG_LBLAWBAR0_PRELIM) \ - && defined(CFG_LBLAWAR0_PRELIM) - im->lbus.bank[0].br = CFG_BR0_PRELIM; - im->lbus.bank[0].or = CFG_OR0_PRELIM; - im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM; - im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM; +#if defined(CONFIG_SYS_BR0_PRELIM) \ + && defined(CONFIG_SYS_OR0_PRELIM) \ + && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \ + && defined(CONFIG_SYS_LBLAWAR0_PRELIM) + im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM; + im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM; + im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; + im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM; #else -#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined +#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined #endif -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - im->lbus.bank[1].br = CFG_BR1_PRELIM; - im->lbus.bank[1].or = CFG_OR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM; + im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM; #endif -#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM) - im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM; - im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM) + im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; + im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM; #endif -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - im->lbus.bank[2].br = CFG_BR2_PRELIM; - im->lbus.bank[2].or = CFG_OR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM; + im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM; #endif -#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM) - im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM; - im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM) + im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; + im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - im->lbus.bank[3].br = CFG_BR3_PRELIM; - im->lbus.bank[3].or = CFG_OR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM; + im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM; #endif -#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM) - im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM; - im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM) + im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; + im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - im->lbus.bank[4].br = CFG_BR4_PRELIM; - im->lbus.bank[4].or = CFG_OR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM; + im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM; #endif -#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM) - im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM; - im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM) + im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; + im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - im->lbus.bank[5].br = CFG_BR5_PRELIM; - im->lbus.bank[5].or = CFG_OR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM; + im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM; #endif -#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM) - im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM; - im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM) + im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM; + im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - im->lbus.bank[6].br = CFG_BR6_PRELIM; - im->lbus.bank[6].or = CFG_OR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM; + im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM; #endif -#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM) - im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM; - im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM) + im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM; + im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - im->lbus.bank[7].br = CFG_BR7_PRELIM; - im->lbus.bank[7].or = CFG_OR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM; + im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM; #endif -#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM) - im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM; - im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; +#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM) + im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM; + im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM; #endif -#ifdef CFG_GPIO1_PRELIM - im->gpio[0].dat = CFG_GPIO1_DAT; - im->gpio[0].dir = CFG_GPIO1_DIR; +#ifdef CONFIG_SYS_GPIO1_PRELIM + im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT; + im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR; #endif -#ifdef CFG_GPIO2_PRELIM - im->gpio[1].dat = CFG_GPIO2_DAT; - im->gpio[1].dir = CFG_GPIO2_DIR; +#ifdef CONFIG_SYS_GPIO2_PRELIM + im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; + im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; #endif } int cpu_init_r (void) { #ifdef CONFIG_QE - uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */ + uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ qe_init(qe_base); qe_reset(); #endif diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c index 5137ab6..5ab169f 100644 --- a/cpu/mpc83xx/ecc.c +++ b/cpu/mpc83xx/ecc.c @@ -20,7 +20,7 @@ #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) void ecc_print_status(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; printf("\nECC mode: %s\n\n", @@ -100,7 +100,7 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile u32 val; u64 *addr; diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 3e3e1c8..f890775 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; void ft_cpu_setup(void *blob, bd_t *bd) { - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int spridr = immr->sysconf.spridr; /* @@ -77,9 +77,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_qe_setup(blob); #endif -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CFG_NS16550_CLK, 1); + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 98ed21c..faffbaf 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -38,9 +38,9 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + *decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ; /* Enable e300 time base */ diff --git a/cpu/mpc83xx/nand_init.c b/cpu/mpc83xx/nand_init.c index e92f230..38e141a 100644 --- a/cpu/mpc83xx/nand_init.c +++ b/cpu/mpc83xx/nand_init.c @@ -37,7 +37,7 @@ void cpu_init_f (volatile immap_t * im) int i; /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ for (i = 0; i < sizeof(gd_t); i++) @@ -45,34 +45,34 @@ void cpu_init_f (volatile immap_t * im) /* system performance tweaking */ -#ifdef CFG_ACR_PIPE_DEP +#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); + (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif -#ifdef CFG_ACR_RPTCNT +#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); + (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT); #endif -#ifdef CFG_SPCR_OPT +#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other devices */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CFG_SPCR_OPT << SPCR_OPT_SHIFT); + (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); #endif /* Enable Time Base & Decrimenter (so we will have udelay()) */ im->sysconf.spcr |= SPCR_TBEN; /* DDR control driver register */ -#ifdef CFG_DDRCDR - im->sysconf.ddrcdr = CFG_DDRCDR; +#ifdef CONFIG_SYS_DDRCDR + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; #endif /* Output buffer impedance register */ -#ifdef CFG_OBIR - im->sysconf.obir = CFG_OBIR; +#ifdef CONFIG_SYS_OBIR + im->sysconf.obir = CONFIG_SYS_OBIR; #endif /* @@ -84,16 +84,16 @@ void cpu_init_f (volatile immap_t * im) * has been determined */ -#if defined(CFG_NAND_BR_PRELIM) \ - && defined(CFG_NAND_OR_PRELIM) \ - && defined(CFG_NAND_LBLAWBAR_PRELIM) \ - && defined(CFG_NAND_LBLAWAR_PRELIM) - im->lbus.bank[0].br = CFG_NAND_BR_PRELIM; - im->lbus.bank[0].or = CFG_NAND_OR_PRELIM; - im->sysconf.lblaw[0].bar = CFG_NAND_LBLAWBAR_PRELIM; - im->sysconf.lblaw[0].ar = CFG_NAND_LBLAWAR_PRELIM; +#if defined(CONFIG_SYS_NAND_BR_PRELIM) \ + && defined(CONFIG_SYS_NAND_OR_PRELIM) \ + && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ + && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) + im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM; + im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM; + im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; + im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; #else -#error CFG_NAND_BR_PRELIM, CFG_NAND_OR_PRELIM, CFG_NAND_LBLAWBAR_PRELIM & CFG_NAND_LBLAWAR_PRELIM must be defined +#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined #endif } diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index c3ec5f8..5b8eeb7 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -42,7 +42,7 @@ static int pci_num_buses; static void pci_init_bus(int bus, struct pci_region *reg) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile pot83xx_t *pot = immr->ios.pot; volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus]; struct pci_controller *hose = &pci_hose[bus]; @@ -94,8 +94,8 @@ static void pci_init_bus(int bus, struct pci_region *reg) hose->first_busno = 0; hose->last_busno = 0xff; - pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80, - CFG_IMMR + 0x8304 + bus * 0x80); + pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80, + CONFIG_SYS_IMMR + 0x8304 + bus * 0x80); pci_register_hose(hose); @@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) */ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; int i; if (num_buses > MAX_BUSES) { diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index ce91a07..db94f00 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -33,7 +33,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; /* Caculate pin location and 2bit mask and dir */ diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c index 020c4c8..630b111 100644 --- a/cpu/mpc83xx/serdes.c +++ b/cpu/mpc83xx/serdes.c @@ -44,7 +44,7 @@ void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) { - void *regs = (void *)CFG_IMMR + offset; + void *regs = (void *)CONFIG_SYS_IMMR + offset; u32 tmp; /* 1.0V corevdd */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index f4a0e90..359a915 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; void board_add_ram_info(int use_default) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; char buf[32]; @@ -57,9 +57,9 @@ void board_add_ram_info(int use_default) printf(", %s MHz)", strmhz(buf, gd->mem_clk)); -#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE) +#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE) puts("\nSDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); #endif } @@ -71,8 +71,8 @@ extern uint dma_check(void); extern int dma_xfer(void *dest, uint count, void *src); #endif -#ifndef CFG_READ_SPD -#define CFG_READ_SPD i2c_read +#ifndef CONFIG_SYS_READ_SPD +#define CONFIG_SYS_READ_SPD i2c_read #endif /* @@ -129,7 +129,7 @@ static void spd_debug(spd_eeprom_t *spd) long int spd_sdram() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; @@ -158,7 +158,7 @@ long int spd_sdram() unsigned int pvr = get_pvr(); /* Read SPD parameters with I2C */ - CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG spd_debug(&spd); #endif @@ -194,12 +194,12 @@ long int spd_sdram() return 0; } -#ifdef CFG_DDRCDR_VALUE +#ifdef CONFIG_SYS_DDRCDR_VALUE /* * Adjust DDR II IO voltage biasing. It just makes it work. */ if(spd.mem_type == SPD_MEMTYPE_DDR2) { - immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; } udelay(50000); #endif @@ -214,7 +214,7 @@ long int spd_sdram() } /* Setup DDR chip select register */ -#ifdef CFG_83XX_DDR_USES_CS0 +#ifdef CONFIG_SYS_83XX_DDR_USES_CS0 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[0] = ( 1 << 31 | (odt_rd_cfg << 20) @@ -274,7 +274,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CFG_DDR_SDRAM_BASE & 0xfffff000; + ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); @@ -724,8 +724,8 @@ long int spd_sdram() debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); } -#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ - ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; +#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); @@ -842,7 +842,7 @@ static __inline__ unsigned long get_tbms (void) /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ddr83xx_t *ddr= &immap->ddr; unsigned long t_start, t_end; register u64 *p; diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 76c569d..3a708d8 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -90,7 +90,7 @@ corecnf_t corecnf_tab[] = { */ int get_clocks(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 pci_sync_in; u8 spmf; u8 clkin_div; diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 14bfbda..565cc39 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -57,8 +57,8 @@ #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) #endif -#if !defined(CONFIG_NAND_SPL) && !defined(CFG_RAMBOOT) -#define CFG_FLASHBOOT +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_SYS_FLASHBOOT #endif /* @@ -93,8 +93,8 @@ .fill 8,1,(((w)>> 8)&0xff); \ .fill 8,1,(((w) )&0xff) - _HRCW_TABLE_ENTRY(CFG_HRCW_LOW) - _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) + _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) /* * Magic number and version string - put it after the HRCW since it @@ -111,10 +111,10 @@ version_string: #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined -#endif /* CFG_DEFAULT_IMMR */ -#ifndef CFG_IMMR -#define CFG_IMMR CONFIG_DEFAULT_IMMR -#endif /* CFG_IMMR */ +#endif /* CONFIG_SYS_DEFAULT_IMMR */ +#ifndef CONFIG_SYS_IMMR +#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR +#endif /* CONFIG_SYS_IMMR */ /* * After configuration, a system reset exception is executed using the @@ -160,8 +160,8 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l + lis r3, CONFIG_SYS_IMMR@h + ori r3, r3, CONFIG_SYS_IMMR@l stw r3, IMMRBAR(r4) /* Initialise the E300 processor core */ @@ -169,15 +169,15 @@ boot_warm: /* time t 5 */ bl init_e300_core -#ifdef CFG_FLASHBOOT +#ifdef CONFIG_SYS_FLASHBOOT /* Inflate flash location so it appears everywhere, calculate */ /* the absolute address in final location of the FLASH, jump */ /* there and deflate the flash size back to minimal size */ /*------------------------------------------------------------*/ bl map_flash_by_law1 - lis r4, (CFG_MONITOR_BASE)@h - ori r4, r4, (CFG_MONITOR_BASE)@l + lis r4, (CONFIG_SYS_MONITOR_BASE)@h + ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET mtlr r5 blr @@ -185,7 +185,7 @@ in_flash: #if 1 /* Remapping flash with LAW0. */ bl remap_flash_by_law0 #endif -#endif /* CFG_FLASHBOOT */ +#endif /* CONFIG_SYS_FLASHBOOT */ /* setup the bats */ bl setup_bats @@ -211,15 +211,15 @@ in_flash: /* enable the data cache */ bl dcache_enable sync -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK bl lock_ram_in_cache sync #endif /* set up the stack pointer in our newly created * cache-ram (r1) */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -234,7 +234,7 @@ in_flash: GET_GOT /* initialize GOT access */ /* r3: IMMR */ - lis r3, CFG_IMMR@h + lis r3, CONFIG_SYS_IMMR@h /* run low-level CPU init code (in Flash)*/ bl cpu_init_f @@ -456,11 +456,11 @@ init_e300_core: /* time t 10 */ mtspr SRR1, r3 /* Make SRR1 match MSR */ - lis r3, CFG_IMMR@h + lis r3, CONFIG_SYS_IMMR@h #if defined(CONFIG_WATCHDOG) /* Initialise the Wathcdog values and reset it (if req) */ /*------------------------------------------------------*/ - lis r4, CFG_WATCHDOG_VALUE + lis r4, CONFIG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3) @@ -499,18 +499,18 @@ init_e300_core: /* time t 10 */ /* - force invalidation of data and instruction caches */ /*------------------------------------------------------*/ - lis r3, CFG_HID0_INIT@h - ori r3, r3, (CFG_HID0_INIT | HID0_ICFI | HID0_DCFI)@l + lis r3, CONFIG_SYS_HID0_INIT@h + ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l SYNC mtspr HID0, r3 - lis r3, CFG_HID0_FINAL@h - ori r3, r3, (CFG_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l + lis r3, CONFIG_SYS_HID0_FINAL@h + ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l SYNC mtspr HID0, r3 - lis r3, CFG_HID2@h - ori r3, r3, CFG_HID2@l + lis r3, CONFIG_SYS_HID2@h + ori r3, r3, CONFIG_SYS_HID2@l SYNC mtspr HID2, r3 @@ -524,131 +524,131 @@ setup_bats: addis r0, r0, 0x0000 /* IBAT 0 */ - addis r4, r0, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - addis r3, r0, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l + addis r4, r0, CONFIG_SYS_IBAT0L@h + ori r4, r4, CONFIG_SYS_IBAT0L@l + addis r3, r0, CONFIG_SYS_IBAT0U@h + ori r3, r3, CONFIG_SYS_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 /* DBAT 0 */ - addis r4, r0, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - addis r3, r0, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l + addis r4, r0, CONFIG_SYS_DBAT0L@h + ori r4, r4, CONFIG_SYS_DBAT0L@l + addis r3, r0, CONFIG_SYS_DBAT0U@h + ori r3, r3, CONFIG_SYS_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 /* IBAT 1 */ - addis r4, r0, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - addis r3, r0, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l + addis r4, r0, CONFIG_SYS_IBAT1L@h + ori r4, r4, CONFIG_SYS_IBAT1L@l + addis r3, r0, CONFIG_SYS_IBAT1U@h + ori r3, r3, CONFIG_SYS_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 /* DBAT 1 */ - addis r4, r0, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - addis r3, r0, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l + addis r4, r0, CONFIG_SYS_DBAT1L@h + ori r4, r4, CONFIG_SYS_DBAT1L@l + addis r3, r0, CONFIG_SYS_DBAT1U@h + ori r3, r3, CONFIG_SYS_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 /* IBAT 2 */ - addis r4, r0, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - addis r3, r0, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l + addis r4, r0, CONFIG_SYS_IBAT2L@h + ori r4, r4, CONFIG_SYS_IBAT2L@l + addis r3, r0, CONFIG_SYS_IBAT2U@h + ori r3, r3, CONFIG_SYS_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 /* DBAT 2 */ - addis r4, r0, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - addis r3, r0, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l + addis r4, r0, CONFIG_SYS_DBAT2L@h + ori r4, r4, CONFIG_SYS_DBAT2L@l + addis r3, r0, CONFIG_SYS_DBAT2U@h + ori r3, r3, CONFIG_SYS_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 /* IBAT 3 */ - addis r4, r0, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - addis r3, r0, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l + addis r4, r0, CONFIG_SYS_IBAT3L@h + ori r4, r4, CONFIG_SYS_IBAT3L@l + addis r3, r0, CONFIG_SYS_IBAT3U@h + ori r3, r3, CONFIG_SYS_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 /* DBAT 3 */ - addis r4, r0, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - addis r3, r0, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l + addis r4, r0, CONFIG_SYS_DBAT3L@h + ori r4, r4, CONFIG_SYS_DBAT3L@l + addis r3, r0, CONFIG_SYS_DBAT3U@h + ori r3, r3, CONFIG_SYS_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 #ifdef CONFIG_HIGH_BATS /* IBAT 4 */ - addis r4, r0, CFG_IBAT4L@h - ori r4, r4, CFG_IBAT4L@l - addis r3, r0, CFG_IBAT4U@h - ori r3, r3, CFG_IBAT4U@l + addis r4, r0, CONFIG_SYS_IBAT4L@h + ori r4, r4, CONFIG_SYS_IBAT4L@l + addis r3, r0, CONFIG_SYS_IBAT4U@h + ori r3, r3, CONFIG_SYS_IBAT4U@l mtspr IBAT4L, r4 mtspr IBAT4U, r3 /* DBAT 4 */ - addis r4, r0, CFG_DBAT4L@h - ori r4, r4, CFG_DBAT4L@l - addis r3, r0, CFG_DBAT4U@h - ori r3, r3, CFG_DBAT4U@l + addis r4, r0, CONFIG_SYS_DBAT4L@h + ori r4, r4, CONFIG_SYS_DBAT4L@l + addis r3, r0, CONFIG_SYS_DBAT4U@h + ori r3, r3, CONFIG_SYS_DBAT4U@l mtspr DBAT4L, r4 mtspr DBAT4U, r3 /* IBAT 5 */ - addis r4, r0, CFG_IBAT5L@h - ori r4, r4, CFG_IBAT5L@l - addis r3, r0, CFG_IBAT5U@h - ori r3, r3, CFG_IBAT5U@l + addis r4, r0, CONFIG_SYS_IBAT5L@h + ori r4, r4, CONFIG_SYS_IBAT5L@l + addis r3, r0, CONFIG_SYS_IBAT5U@h + ori r3, r3, CONFIG_SYS_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 /* DBAT 5 */ - addis r4, r0, CFG_DBAT5L@h - ori r4, r4, CFG_DBAT5L@l - addis r3, r0, CFG_DBAT5U@h - ori r3, r3, CFG_DBAT5U@l + addis r4, r0, CONFIG_SYS_DBAT5L@h + ori r4, r4, CONFIG_SYS_DBAT5L@l + addis r3, r0, CONFIG_SYS_DBAT5U@h + ori r3, r3, CONFIG_SYS_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 /* IBAT 6 */ - addis r4, r0, CFG_IBAT6L@h - ori r4, r4, CFG_IBAT6L@l - addis r3, r0, CFG_IBAT6U@h - ori r3, r3, CFG_IBAT6U@l + addis r4, r0, CONFIG_SYS_IBAT6L@h + ori r4, r4, CONFIG_SYS_IBAT6L@l + addis r3, r0, CONFIG_SYS_IBAT6U@h + ori r3, r3, CONFIG_SYS_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 /* DBAT 6 */ - addis r4, r0, CFG_DBAT6L@h - ori r4, r4, CFG_DBAT6L@l - addis r3, r0, CFG_DBAT6U@h - ori r3, r3, CFG_DBAT6U@l + addis r4, r0, CONFIG_SYS_DBAT6L@h + ori r4, r4, CONFIG_SYS_DBAT6L@l + addis r3, r0, CONFIG_SYS_DBAT6U@h + ori r3, r3, CONFIG_SYS_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 /* IBAT 7 */ - addis r4, r0, CFG_IBAT7L@h - ori r4, r4, CFG_IBAT7L@l - addis r3, r0, CFG_IBAT7U@h - ori r3, r3, CFG_IBAT7U@l + addis r4, r0, CONFIG_SYS_IBAT7L@h + ori r4, r4, CONFIG_SYS_IBAT7L@l + addis r3, r0, CONFIG_SYS_IBAT7U@h + ori r3, r3, CONFIG_SYS_IBAT7U@l mtspr IBAT7L, r4 mtspr IBAT7U, r3 /* DBAT 7 */ - addis r4, r0, CFG_DBAT7L@h - ori r4, r4, CFG_DBAT7L@l - addis r3, r0, CFG_DBAT7U@h - ori r3, r3, CFG_DBAT7U@l + addis r4, r0, CONFIG_SYS_DBAT7L@h + ori r4, r4, CONFIG_SYS_DBAT7L@l + addis r3, r0, CONFIG_SYS_DBAT7U@h + ori r3, r3, CONFIG_SYS_DBAT7U@l mtspr DBAT7L, r4 mtspr DBAT7U, r3 #endif @@ -774,11 +774,11 @@ dcache_status: .globl flush_dcache flush_dcache: lis r3, 0 - lis r5, CFG_CACHELINE_SIZE + lis r5, CONFIG_SYS_CACHELINE_SIZE 1: cmp 0, 1, r3, r5 bge 2f lwz r5, 0(r3) - lis r5, CFG_CACHELINE_SIZE + lis r5, CONFIG_SYS_CACHELINE_SIZE addi r3, r3, 0x4 b 1b 2: blr @@ -820,16 +820,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__bss_start) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) * + Destination Address * * Offset: @@ -1073,14 +1073,14 @@ trap_reloc: blr #endif /* !CONFIG_NAND_SPL */ -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r4, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ + (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: dcbz r0, r3 @@ -1099,10 +1099,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r4, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ + (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: icbi r0, r3 dcbi r0, r3 @@ -1122,14 +1122,14 @@ unlock_ram_in_cache: mtspr HID0, r3 /* no invalidate, unlock */ blr #endif /* !CONFIG_NAND_SPL */ -#endif /* CFG_INIT_RAM_LOCK */ +#endif /* CONFIG_SYS_INIT_RAM_LOCK */ -#ifdef CFG_FLASHBOOT +#ifdef CONFIG_SYS_FLASHBOOT map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*----------------------------------------------------*/ - lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */ + lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ lwz r4, OR0@l(r3) li r5, 0x7fff /* r5 <= 0x00007FFFF */ and r4, r4, r5 @@ -1151,14 +1151,14 @@ map_flash_by_law1: * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */ - lis r4, (CFG_FLASH_BASE)@h - ori r4, r4, (CFG_FLASH_BASE)@l - stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ + lis r4, (CONFIG_SYS_FLASH_BASE)@h + ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */ + /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CFG_FLASH_SIZE + li r5, CONFIG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b @@ -1175,24 +1175,24 @@ remap_flash_by_law0: lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5 - lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h - ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l + lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h + ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4 - stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ lwz r4, OR0(r3) - lis r5, ~((CFG_FLASH_SIZE << 4) - 1) + lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) or r4, r4, r5 stw r4, OR0(r3) - lis r4, (CFG_FLASH_BASE)@h - ori r4, r4, (CFG_FLASH_BASE)@l - stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */ + lis r4, (CONFIG_SYS_FLASH_BASE)@h + ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */ + /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CFG_FLASH_SIZE + li r5, CONFIG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b @@ -1203,4 +1203,4 @@ remap_flash_by_law0: stw r4, LBLAWBAR1(r3) stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ blr -#endif /* CFG_FLASHBOOT */ +#endif /* CONFIG_SYS_FLASHBOOT */ diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c index dfd6c03..3b09a62 100644 --- a/cpu/mpc83xx/traps.c +++ b/cpu/mpc83xx/traps.c @@ -100,7 +100,7 @@ _exception(int signr, struct pt_regs *regs) void dump_pci (void) { /* - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; printf ("PCI: err status %x err mask %x err ctrl %x\n", le32_to_cpu (immap->im_pci.pci_esr), le32_to_cpu (immap->im_pci.pci_emr), @@ -124,7 +124,7 @@ MachineCheckException(struct pt_regs *regs) */ #ifdef CONFIG_PCI #if 0 - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; #ifdef DEBUG dump_pci(); #endif diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index b0ecd25..fff8dff 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -37,10 +37,10 @@ DECLARE_GLOBAL_DATA_PTR; void m8560_cpm_reset(void) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile ulong count; - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Reclaim the DP memory for our use. */ @@ -64,7 +64,7 @@ m8560_cpm_reset(void) uint m8560_cpm_dpalloc(uint size, uint align) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; uint retloc; uint align_mask, off; uint savebase; @@ -120,7 +120,7 @@ m8560_cpm_hostalloc(uint size, uint align) void m8560_cpm_setbrg(uint brg, uint rate) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... @@ -142,7 +142,7 @@ m8560_cpm_setbrg(uint brg, uint rate) void m8560_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... @@ -167,7 +167,7 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16) void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile uint *bp; if (brg < 4) { @@ -190,7 +190,7 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) void post_word_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); *save_addr = a; } @@ -198,7 +198,7 @@ void post_word_store (ulong a) ulong post_word_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); return *save_addr; } diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index f15b0a8..61162a8 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -84,7 +84,7 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else @@ -151,11 +151,11 @@ int checkcpu (void) break; } -#if defined(CFG_LBC_LCRR) - lcrr = CFG_LBC_LCRR; +#if defined(CONFIG_SYS_LBC_LCRR) + lcrr = CONFIG_SYS_LBC_LCRR; #else { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } @@ -200,7 +200,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ udelay(100); } @@ -256,7 +256,7 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; @@ -266,7 +266,7 @@ void dma_init(void) { } uint dma_check(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -285,7 +285,7 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->dar0 = (uint) dest; dma->sar0 = (uint) src; @@ -306,7 +306,7 @@ void upmconfig (uint upm, uint * table, uint size) { int i, mdr, mad, old_mad = 0; volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile u32 *brp,*orp; volatile u8* dummy = NULL; int upmmask; diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 783c5ba..3a8aef2 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -132,28 +132,28 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) { u32 temp; - set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, + set_tlb(0, CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 1, BOOKE_PAGESZ_4K, 0); - temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT); + out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CFG_CCSRBAR); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); } #endif /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -172,69 +172,69 @@ void cpu_init_early_f(void) void cpu_init_f (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); disable_tlb(14); disable_tlb(15); #ifdef CONFIG_CPM2 - config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); + config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); #endif /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary * addresses - these have to be modified later when FLASH size * has been determined */ -#if defined(CFG_OR0_REMAP) - memctl->or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ /* if cs1 is already set via debugger, leave cs0/cs1 alone */ if (! memctl->br1 & 1) { -#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; +#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) + memctl->br0 = CONFIG_SYS_BR0_PRELIM; + memctl->or0 = CONFIG_SYS_OR0_PRELIM; #endif -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->or1 = CONFIG_SYS_OR1_PRELIM; + memctl->br1 = CONFIG_SYS_BR1_PRELIM; #endif } -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->or2 = CFG_OR2_PRELIM; - memctl->br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->or2 = CONFIG_SYS_OR2_PRELIM; + memctl->br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->or3 = CFG_OR3_PRELIM; - memctl->br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->or3 = CONFIG_SYS_OR3_PRELIM; + memctl->br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->or4 = CFG_OR4_PRELIM; - memctl->br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->or4 = CONFIG_SYS_OR4_PRELIM; + memctl->br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->or5 = CFG_OR5_PRELIM; - memctl->br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->or5 = CONFIG_SYS_OR5_PRELIM; + memctl->br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->or6 = CFG_OR6_PRELIM; - memctl->br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->or6 = CONFIG_SYS_OR6_PRELIM; + memctl->br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->or7 = CFG_OR7_PRELIM; - memctl->br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->or7 = CONFIG_SYS_OR7_PRELIM; + memctl->br7 = CONFIG_SYS_BR7_PRELIM; #endif #if defined(CONFIG_CPM2) @@ -264,7 +264,7 @@ int cpu_init_r(void) puts ("L2: "); #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; uint l2srbar; @@ -317,13 +317,13 @@ int cpu_init_r(void) if (l2cache->l2ctl & 0x80000000) { puts("already enabled"); l2srbar = l2cache->l2srbar0; -#ifdef CFG_INIT_L2_ADDR - if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { - l2srbar = CFG_INIT_L2_ADDR; +#ifdef CONFIG_SYS_INIT_L2_ADDR + if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE) { + l2srbar = CONFIG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf("moving to 0x%08x", CFG_INIT_L2_ADDR); + printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); } -#endif /* CFG_INIT_L2_ADDR */ +#endif /* CONFIG_SYS_INIT_L2_ADDR */ puts("\n"); } else { asm("msync;isync"); @@ -335,7 +335,7 @@ int cpu_init_r(void) puts("disabled\n"); #endif #ifdef CONFIG_QE - uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ qe_init(qe_base); qe_reset(); #endif diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c index 2c11ee4..e24c9af 100644 --- a/cpu/mpc85xx/ddr-gen1.c +++ b/cpu/mpc85xx/ddr-gen1.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; if (ctrl_num != 0) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); @@ -79,7 +79,7 @@ ddr_enable_ecc(unsigned int dram_size) { uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_init(); diff --git a/cpu/mpc85xx/ddr-gen2.c b/cpu/mpc85xx/ddr-gen2.c index 130090c..655f99c 100644 --- a/cpu/mpc85xx/ddr-gen2.c +++ b/cpu/mpc85xx/ddr-gen2.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; if (ctrl_num) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index d7cc9db..e0654bb 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, switch (ctrl_num) { case 0: - ddr = (void *)CFG_MPC85xx_DDR_ADDR; + ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; break; case 1: - ddr = (void *)CFG_MPC85xx_DDR2_ADDR; + ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; break; default: printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index bd62aab..32ad469 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -74,8 +74,8 @@ static struct ether_fcc_info_s PROFF_FCC1, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, - CFG_CMXFCR_MASK1, - CFG_CMXFCR_VALUE1 + CONFIG_SYS_CMXFCR_MASK1, + CONFIG_SYS_CMXFCR_VALUE1 }, #endif @@ -85,8 +85,8 @@ static struct ether_fcc_info_s PROFF_FCC2, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, - CFG_CMXFCR_MASK2, - CFG_CMXFCR_VALUE2 + CONFIG_SYS_CMXFCR_MASK2, + CONFIG_SYS_CMXFCR_VALUE2 }, #endif @@ -96,8 +96,8 @@ static struct ether_fcc_info_s PROFF_FCC3, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, - CFG_CMXFCR_MASK3, - CFG_CMXFCR_VALUE3 + CONFIG_SYS_CMXFCR_MASK3, + CONFIG_SYS_CMXFCR_VALUE3 }, #endif }; @@ -230,7 +230,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -257,11 +257,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 1){ - cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 2){ - cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; } /* 28.9 - (6): FDSR: Ethernet Syn */ @@ -321,14 +321,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis) pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ /* localbus SDRAM should be preferred */ pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); pram_ptr->fen_genfcc.fcc_rbdstat = 0; pram_ptr->fen_genfcc.fcc_rbdlen = 0; pram_ptr->fen_genfcc.fcc_rdptr = 0; /* localbus SDRAM should be preferred */ pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); pram_ptr->fen_genfcc.fcc_tbdstat = 0; pram_ptr->fen_genfcc.fcc_tbdlen = 0; @@ -426,7 +426,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; /* write GFMR: disable tx/rx */ if(info->ether_index == 0) { diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 037a60f..3c8fbd8 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -83,7 +83,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) /* return size in kilobytes */ static inline u32 l2cache_size(void) { - volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; u32 ver = SVR_SOC_VER(get_svr()); @@ -224,9 +224,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_qe_setup(blob); #endif -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CFG_NS16550_CLK, 1); + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_CPM2 diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index d702ca6..4ef8395 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -34,14 +34,14 @@ int interrupt_init_cpu(unsigned long *decrementer_count) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); pic->gcr = MPC85xx_PICGCR_RST; while (pic->gcr & MPC85xx_PICGCR_RST) ; pic->gcr = MPC85xx_PICGCR_M; - *decrementer_count = get_tbclk() / CFG_HZ; + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; /* PIE is same as DIE, dec interrupt enable */ mtspr(SPRN_TCR, TCR_PIE); diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 4e09c9c..3338c1a 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -36,7 +36,7 @@ u32 get_my_id() int cpu_reset(int nr) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); (void)in_be32(&pic->pir); out_be32(&pic->pir, 0x0); @@ -87,7 +87,7 @@ int cpu_release(int nr, int argc, char *argv[]) return 1; } -#ifdef CFG_64BIT_STRTOUL +#ifdef CONFIG_SYS_64BIT_STRTOUL boot_addr = simple_strtoull(argv[0], NULL, 16); #else boot_addr = simple_strtoul(argv[0], NULL, 16); @@ -129,9 +129,9 @@ static void pq3_mp_up(unsigned long bootpg) u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_addr(); volatile u32 bpcr; - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/cpu/mpc85xx/mpc8536_serdes.c b/cpu/mpc85xx/mpc8536_serdes.c index ae091e6..d9ac466 100644 --- a/cpu/mpc85xx/mpc8536_serdes.c +++ b/cpu/mpc85xx/mpc8536_serdes.c @@ -54,8 +54,8 @@ void fsl_serdes_init(void) { - void *guts = (void *)(CFG_MPC85xx_GUTS_ADDR); - void *sd = (void *)CFG_MPC85xx_SERDES2_ADDR; + void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR; u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); u32 srds2_io_sel; u32 tmp; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index fdc4c83..112f18c 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -39,11 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u16 reg16; u32 dev; - volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); #ifdef CONFIG_MPC85XX_PCI2 - volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR); + volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR); #endif - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct pci_controller * hose; pci_hose = board_hose; @@ -54,8 +54,8 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = 0xff; pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); + (CONFIG_SYS_IMMR+0x8000), + (CONFIG_SYS_IMMR+0x8004)); /* * Hose scan. @@ -80,19 +80,19 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); } - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff; pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; + pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1)); + POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1)); - pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; + pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; pcix->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1)); + POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1)); pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; @@ -105,15 +105,15 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix->piwar3 = 0; pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = 2; @@ -152,8 +152,8 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = 0xff; pci_setup_indirect(hose, - (CFG_IMMR+0x9000), - (CFG_IMMR+0x9004)); + (CONFIG_SYS_IMMR+0x9000), + (CONFIG_SYS_IMMR+0x9004)); dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); @@ -165,19 +165,19 @@ pci_mpc85xx_init(struct pci_controller *board_hose) */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff; + pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff; pcix2->potear1 = 0x00000000; - pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; + pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff; pcix2->powbear1 = 0x00000000; pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1)); + POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1)); - pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; + pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff; pcix2->potear2 = 0x00000000; - pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; + pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff; pcix2->powbear2 = 0x00000000; pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1)); + POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1)); pcix2->pitar1 = 0x00000000; pcix2->piwbar1 = 0x00000000; @@ -190,15 +190,15 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix2->piwar3 = 0; pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); hose->region_count = 2; diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c index 21ea38b..72a29b7 100644 --- a/cpu/mpc85xx/qe_io.c +++ b/cpu/mpc85xx/qe_io.c @@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io); diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 7ee3cc8..05fb808 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -88,7 +88,7 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile ccsr_cpm_scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -201,7 +201,7 @@ serial_putc(const char c) { volatile scc_uart_t *up; volatile cbd_t *tbdf; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; if (c == '\n') serial_putc ('\r'); @@ -234,7 +234,7 @@ serial_getc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; unsigned char c; up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); @@ -258,7 +258,7 @@ serial_tstc() { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 70dfad0..d9f9a8c 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; @@ -67,10 +67,10 @@ int get_clocks (void) { sys_info_t sys_info; #ifdef CONFIG_MPC8544 - volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR; + volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; #endif #if defined(CONFIG_CPM2) - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; uint sccr, dfbrg; /* set VCO = 4 * BRG */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 10fe936..25d0390 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -172,12 +172,12 @@ _start_e500: mtspr BUCSR,r0 #endif -#if defined(CFG_INIT_DBCR) +#if defined(CONFIG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CFG_INIT_DBCR@l + lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CONFIG_SYS_INIT_DBCR@l mtspr DBCR0,r0 #endif @@ -210,11 +210,11 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l - lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h - ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l - lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l mtspr MAS0,r6 mtspr MAS1,r7 @@ -238,8 +238,8 @@ switch_as: /* Allocate Initial RAM in data cache. */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l mfspr r2, L1CFG0 andi. r2, r2, 0x1ff /* cache size * 1024 / (2 * L1 line size) */ @@ -249,17 +249,17 @@ switch_as: 1: dcbz r0,r3 dcbtls 0,r0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b /* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CFG_RAMBOOT +#ifdef CONFIG_SYS_RAMBOOT b _start_cont #else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3,CFG_MONITOR_BASE@h - ori r3,r3,CFG_MONITOR_BASE@l + lis r3,CONFIG_SYS_MONITOR_BASE@h + ori r3,r3,CONFIG_SYS_MONITOR_BASE@l addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 blr @@ -279,8 +279,8 @@ version_string: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + lis r1,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l li r0,0 stwu r0,-4(r1) @@ -778,16 +778,16 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ mr r3,r5 /* Destination Address */ - lis r4,CFG_MONITOR_BASE@h /* Source Address */ - ori r4,r4,CFG_MONITOR_BASE@l + lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4,r4,CONFIG_SYS_MONITOR_BASE@l lwz r5,GOT(__init_end) sub r5,r5,r4 - li r6,CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -996,20 +996,20 @@ trap_reloc: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CFG_INIT_RAM_ADDR & ~31)@h - ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l + lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync /* Invalidate the TLB entries for the cache */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l tlbivax 0,r3 addi r3,r3,0x1000 tlbivax 0,r3 diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 7ce7a14..a2d16ae 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -138,7 +138,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) * Starting at TLB1 8, use no more than 8 TLB1 entries. */ ram_tlb_index = 8; - ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; + ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 0eab694..1045cc1 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -290,7 +290,7 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); uint vect; diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index dd38806..0bb058b 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -279,7 +279,7 @@ _GLOBAL(dcache_enable) mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 mflr r5 bl l2cache_enable /* uses r3 and r4 */ sync @@ -305,7 +305,7 @@ _GLOBAL(dcache_disable) andc r3, r3, r5 /* no enable, no invalidate */ mtspr HID0, r3 sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 bl l2cache_disable_no_flush /* uses r3 */ #endif mtlr r4 /* restore link register */ diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 3a75af7..4cace98 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -41,7 +41,7 @@ checkcpu(void) uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; puts("Freescale PowerPC\n"); @@ -100,11 +100,11 @@ checkcpu(void) printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); -#if defined(CFG_LBC_LCRR) - lcrr = CFG_LBC_LCRR; +#if defined(CONFIG_SYS_LBC_LCRR) + lcrr = CONFIG_SYS_LBC_LCRR; #else { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; @@ -161,16 +161,16 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { #if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) -#ifdef CFG_RESET_ADDRESS - ulong addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + ulong addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, - * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, + * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid * address. Better pick an address known to be invalid on your - * system and assign it to CFG_RESET_ADDRESS. + * system and assign it to CONFIG_SYS_RESET_ADDRESS. */ - ulong addr = CFG_MONITOR_BASE - sizeof(ulong); + ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); #endif /* flush and disable I/D cache */ @@ -219,7 +219,7 @@ watchdog_reset(void) /* * This actually feed the hard enabled watchdog. */ - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_wdt_t *wdt = &immap->im_wdt; volatile ccsr_gur_t *gur = &immap->im_gur; u32 tmp = gur->pordevsr; @@ -237,7 +237,7 @@ watchdog_reset(void) void dma_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; dma->satr0 = 0x00040000; @@ -248,7 +248,7 @@ dma_init(void) uint dma_check(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; @@ -266,7 +266,7 @@ dma_check(void) int dma_xfer(void *dest, uint count, void *src) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; dma->dar0 = (uint) dest; @@ -288,7 +288,7 @@ dma_xfer(void *dest, uint count, void *src) */ void mpc86xx_reginfo(void) { - immap_t *immap = (immap_t *)CFG_IMMR; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; ccsr_lbc_t *lbc = &immap->im_lbc; print_bats(); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 1fda3fe..4ab88f0 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -43,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; void cpu_init_f(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -61,52 +61,52 @@ void cpu_init_f(void) * has been determined */ -#if defined(CFG_OR0_REMAP) - memctl->or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ -#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; +#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) + memctl->br0 = CONFIG_SYS_BR0_PRELIM; + memctl->or0 = CONFIG_SYS_OR0_PRELIM; #endif -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->or1 = CONFIG_SYS_OR1_PRELIM; + memctl->br1 = CONFIG_SYS_BR1_PRELIM; #endif -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->or2 = CFG_OR2_PRELIM; - memctl->br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->or2 = CONFIG_SYS_OR2_PRELIM; + memctl->br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->or3 = CFG_OR3_PRELIM; - memctl->br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->or3 = CONFIG_SYS_OR3_PRELIM; + memctl->br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->or4 = CFG_OR4_PRELIM; - memctl->br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->or4 = CONFIG_SYS_OR4_PRELIM; + memctl->br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->or5 = CFG_OR5_PRELIM; - memctl->br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->or5 = CONFIG_SYS_OR5_PRELIM; + memctl->br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->or6 = CFG_OR6_PRELIM; - memctl->br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->or6 = CONFIG_SYS_OR6_PRELIM; + memctl->br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->or7 = CFG_OR7_PRELIM; - memctl->br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->or7 = CONFIG_SYS_OR7_PRELIM; + memctl->br7 = CONFIG_SYS_BR7_PRELIM; #endif /* enable the timebase bit in HID0 */ @@ -127,22 +127,22 @@ int cpu_init_r(void) /* Set up BAT registers */ void setup_bats(void) { - write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L); - write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L); - write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L); - write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L); - write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L); - write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L); - write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L); - write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L); - write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L); - write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L); - write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L); - write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L); - write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L); - write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L); - write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L); - write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L); + write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); + write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); + write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); + write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); + write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); + write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); + write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); + write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); + write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); + write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); + write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); + write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); + write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); + write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); return; } diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c index f936182..51d0102 100644 --- a/cpu/mpc86xx/ddr-8641.c +++ b/cpu/mpc86xx/ddr-8641.c @@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, switch (ctrl_num) { case 0: - ddr = (void *)CFG_MPC86xx_DDR_ADDR; + ddr = (void *)CONFIG_SYS_MPC86xx_DDR_ADDR; break; case 1: - ddr = (void *)CFG_MPC86xx_DDR2_ADDR; + ddr = (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR; break; default: printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index 12d9052..1fef94f5 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -28,8 +28,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_ethernet(blob); #endif -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CFG_NS16550_CLK, 1); + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif } diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index fa2cfac..c78fc72 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -38,7 +38,7 @@ int interrupt_init_cpu(unsigned long *decrementer_count) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_pic_t *pic = &immr->im_pic; pic->gcr = MPC86xx_PICGCR_RST; @@ -46,7 +46,7 @@ int interrupt_init_cpu(unsigned long *decrementer_count) ; pic->gcr = MPC86xx_PICGCR_MODE; - *decrementer_count = get_tbclk() / CFG_HZ; + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n", (get_tbclk() / 1000000), *decrementer_count); diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index da5b58b..415ac9d 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -36,7 +36,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); void get_sys_info(sys_info_t *sysInfo) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 90a1b83..159f3e1 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -194,7 +194,7 @@ boot_warm: #endif 1: -#ifdef CFG_RAMBOOT +#ifdef CONFIG_SYS_RAMBOOT /* disable everything */ li r0, 0 mtspr HID0, r0 @@ -205,7 +205,7 @@ boot_warm: bl invalidate_bats sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 /* init the L2 cache */ lis r3, L2_INIT@h ori r3, r3, L2_INIT@l @@ -218,8 +218,8 @@ boot_warm: /* * Calculate absolute address in FLASH and jump there *------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr @@ -257,15 +257,15 @@ in_flash: bl icache_enable #endif -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK bl lock_ram_in_cache sync #endif /* set up the stack pointer in our newly created * cache-ram (r1) */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -278,7 +278,7 @@ in_flash: bl clear_tlbs sync -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) /* setup ccsrbar */ bl setup_ccsrbar #endif @@ -308,8 +308,8 @@ in_flash: stb r3, 0(r4) /* Get the address to jump to in r3*/ - lis r3, CFG_DIAG_ADDR@h - ori r3, r3, CFG_DIAG_ADDR@l + lis r3, CONFIG_SYS_DIAG_ADDR@h + ori r3, r3, CONFIG_SYS_DIAG_ADDR@l /* Load the LR with the branch address */ mtlr r3 @@ -367,37 +367,37 @@ invalidate_bats: .globl early_bats early_bats: /* IBAT 5 */ - lis r4, CFG_IBAT5L@h - ori r4, r4, CFG_IBAT5L@l - lis r3, CFG_IBAT5U@h - ori r3, r3, CFG_IBAT5U@l + lis r4, CONFIG_SYS_IBAT5L@h + ori r4, r4, CONFIG_SYS_IBAT5L@l + lis r3, CONFIG_SYS_IBAT5U@h + ori r3, r3, CONFIG_SYS_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 isync /* DBAT 5 */ - lis r4, CFG_DBAT5L@h - ori r4, r4, CFG_DBAT5L@l - lis r3, CFG_DBAT5U@h - ori r3, r3, CFG_DBAT5U@l + lis r4, CONFIG_SYS_DBAT5L@h + ori r4, r4, CONFIG_SYS_DBAT5L@l + lis r3, CONFIG_SYS_DBAT5U@h + ori r3, r3, CONFIG_SYS_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 isync /* IBAT 6 */ - lis r4, CFG_IBAT6L@h - ori r4, r4, CFG_IBAT6L@l - lis r3, CFG_IBAT6U@h - ori r3, r3, CFG_IBAT6U@l + lis r4, CONFIG_SYS_IBAT6L@h + ori r4, r4, CONFIG_SYS_IBAT6L@l + lis r3, CONFIG_SYS_IBAT6U@h + ori r3, r3, CONFIG_SYS_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 isync /* DBAT 6 */ - lis r4, CFG_DBAT6L@h - ori r4, r4, CFG_DBAT6L@l - lis r3, CFG_DBAT6U@h - ori r3, r3, CFG_DBAT6U@l + lis r4, CONFIG_SYS_DBAT6L@h + ori r4, r4, CONFIG_SYS_DBAT6L@l + lis r3, CONFIG_SYS_DBAT6U@h + ori r3, r3, CONFIG_SYS_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 isync @@ -621,16 +621,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -648,11 +648,11 @@ relocate_code: bl board_relocate_rom sync mr r3, r10 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ #else cmplw cr1,r3,r4 addi r0,r5,3 @@ -864,15 +864,15 @@ enable_ext_addr: isync blr -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) .globl setup_ccsrbar setup_ccsrbar: /* Special sequence needed to update CCSRBAR itself */ - lis r4, CFG_CCSRBAR_DEFAULT@h - ori r4, r4, CFG_CCSRBAR_DEFAULT@l + lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l - lis r5, CFG_CCSRBAR@h - ori r5, r5, CFG_CCSRBAR@l + lis r5, CONFIG_SYS_CCSRBAR@h + ori r5, r5, CONFIG_SYS_CCSRBAR@l srwi r6,r5,12 stw r6, 0(r4) isync @@ -882,21 +882,21 @@ setup_ccsrbar: lwz r5, 0(r5) isync - lis r3, CFG_CCSRBAR@h - lwz r5, CFG_CCSRBAR@l(r3) + lis r3, CONFIG_SYS_CCSRBAR@h + lwz r5, CONFIG_SYS_CCSRBAR@l(r3) isync blr #endif -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r4, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ + (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: dcbz r0, r3 @@ -928,10 +928,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CFG_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r4, ((CFG_INIT_RAM_END & ~31) + \ - (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ + (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: icbi r0, r3 addi r3, r3, 32 @@ -987,7 +987,7 @@ secondary_cpu_setup: sync bl enable_ext_addr -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 /* init the L2 cache */ addis r3, r0, L2_INIT@h ori r3, r3, L2_INIT@l diff --git a/cpu/mpc8xx/commproc.c b/cpu/mpc8xx/commproc.c index 07c763c..a87a0dc 100644 --- a/cpu/mpc8xx/commproc.c +++ b/cpu/mpc8xx/commproc.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM int dpram_init (void) { @@ -82,14 +82,14 @@ uint dpram_base_align (uint align) return (gd->dp_alloc_base + mask) & ~mask; } -#endif /* CFG_ALLOC_DPRAM */ +#endif /* CONFIG_SYS_ALLOC_DPRAM */ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) void post_word_store (ulong a) { volatile void *save_addr = - ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; + ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; *(volatile ulong *) save_addr = a; } @@ -97,7 +97,7 @@ void post_word_store (ulong a) ulong post_word_load (void) { volatile void *save_addr = - ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; + ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR; return *(volatile ulong *) save_addr; } @@ -109,7 +109,7 @@ ulong post_word_load (void) void bootcount_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + + (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_BOOTCOUNT_ADDR ); save_addr[0] = a; @@ -119,7 +119,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CFG_IMMR)->im_cpm.cp_dpmem + + (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_BOOTCOUNT_ADDR ); if (save_addr[1] != BOOTCOUNT_MAGIC) diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index ec6a3fd..420eaed 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -137,13 +137,13 @@ static int check_CPU (long clock, uint pvr, uint immr) printf ("unknown M%s (0x%08x)", id_str, k); -#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX) +#if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX) printf (" at %s MHz [%d.%d...%d.%d MHz]\n ", strmhz (buf, clock), - CFG_8xx_CPUCLK_MIN / 1000000, - ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, - CFG_8xx_CPUCLK_MAX / 1000000, - ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 + CONFIG_SYS_8xx_CPUCLK_MIN / 1000000, + ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000, + CONFIG_SYS_8xx_CPUCLK_MAX / 1000000, + ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000 ); #else printf (" at %s MHz: ", strmhz (buf, clock)); @@ -375,7 +375,7 @@ int checkcpu (void) int checkicache (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; u32 cacheon = rd_ic_cst () & IDC_ENABLED; @@ -422,7 +422,7 @@ int checkicache (void) int checkdcache (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; u32 cacheon = rd_dc_cst () & IDC_ENABLED; @@ -462,7 +462,7 @@ void upmconfig (uint upm, uint * table, uint size) { uint i; uint addr = 0; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; for (i = 0; i < size; i++) { @@ -480,7 +480,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong msr, addr; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ @@ -495,16 +495,16 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address - * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. + * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS. * "(ulong)-1" used to be a good choice for many systems... */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*)(void)) addr) (); return 1; @@ -525,7 +525,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) disable_interrupts (); /* make sure the watchdog is running */ - reset_8xx_watchdog ((immap_t *) CFG_IMMR); + reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); /* wait for watchdog reset */ while (1) {}; @@ -591,7 +591,7 @@ void watchdog_reset (void) { int re_enable = disable_interrupts (); - reset_8xx_watchdog ((immap_t *) CFG_IMMR); + reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR); if (re_enable) enable_interrupts (); } diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 5c43eca..eb0091b 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -27,12 +27,12 @@ #include #include -#if defined(CFG_RTCSC) || defined(CFG_RMDS) +#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) DECLARE_GLOBAL_DATA_PTR; #endif -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \ - defined(CFG_SMC_UCODE_PATCH) +#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ + defined(CONFIG_SYS_SMC_UCODE_PATCH) void cpm_load_patch (volatile immap_t * immr); #endif @@ -47,7 +47,7 @@ void cpu_init_f (volatile immap_t * immr) { #ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; -# ifdef CFG_PLPRCR +# ifdef CONFIG_SYS_PLPRCR ulong mfmask; # endif #endif @@ -55,7 +55,7 @@ void cpu_init_f (volatile immap_t * immr) /* SYPCR - contains watchdog control (11-9) */ - immr->im_siu_conf.sc_sypcr = CFG_SYPCR; + immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; #if defined(CONFIG_WATCHDOG) reset_8xx_watchdog (immr); @@ -63,27 +63,27 @@ void cpu_init_f (volatile immap_t * immr) /* SIUMCR - contains debug pin configuration (11-6) */ #ifndef CONFIG_SVM_SC8xx - immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; + immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; #else - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; + immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR; #endif /* initialize timebase status and control register (11-26) */ /* unlock TBSCRK */ immr->im_sitk.sitk_tbscrk = KAPWR_KEY; - immr->im_sit.sit_tbscr = CFG_TBSCR; + immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; /* initialize the PIT (11-31) */ immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; /* System integration timers. Don't change EBDF! (15-27) */ immr->im_clkrstk.cark_sccrk = KAPWR_KEY; reg = immr->im_clkrst.car_sccr; reg &= SCCR_MASK; - reg |= CFG_SCCR; + reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg; /* PLL (CPU clock) settings (15-30) */ @@ -92,25 +92,25 @@ void cpu_init_f (volatile immap_t * immr) #ifndef CONFIG_MBX /* MBX board does things different */ - /* If CFG_PLPRCR (set in the various *_config.h files) tries to - * set the MF field, then just copy CFG_PLPRCR over car_plprcr, - * otherwise OR in CFG_PLPRCR so we do not change the current MF + /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to + * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, + * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF * field value. * * For newer (starting MPC866) chips PLPRCR layout is different. */ -#ifdef CFG_PLPRCR +#ifdef CONFIG_SYS_PLPRCR if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) mfmask = PLPRCR_MFACT_MSK; else mfmask = PLPRCR_MF_MSK; - if ((CFG_PLPRCR & mfmask) != 0) - reg = CFG_PLPRCR; /* reset control bits */ + if ((CONFIG_SYS_PLPRCR & mfmask) != 0) + reg = CONFIG_SYS_PLPRCR; /* reset control bits */ else { reg = immr->im_clkrst.car_plprcr; reg &= mfmask; /* isolate MF-related fields */ - reg |= CFG_PLPRCR; /* reset control bits */ + reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ } immr->im_clkrst.car_plprcr = reg; #endif @@ -130,20 +130,20 @@ void cpu_init_f (volatile immap_t * immr) * when FLASH size has been determined * * Depending on the size of the memory region defined by - * CFG_OR0_REMAP some boards (wide address mask) allow to map the - * CFG_MONITOR_BASE, while others (narrower address mask) can't - * map CFG_MONITOR_BASE. + * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the + * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't + * map CONFIG_SYS_MONITOR_BASE. * - * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is - * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000. + * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is + * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. * * If BR0 wasn't loaded with address base 0xff000000, then BR0's * base address remains as 0x00000000. However, the address mask - * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped + * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped * into the Bank0. * * This is why CONFIG_IVMS8 and similar boards must load BR0 with - * CFG_BR0_PRELIM in advance. + * CONFIG_SYS_BR0_PRELIM in advance. * * [Thanks to Michael Liao for this explanation. * I owe him a free beer. - wd] @@ -165,60 +165,60 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) - memctl->memc_br0 = CFG_BR0_PRELIM; + memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; #endif -#if defined(CFG_OR0_REMAP) - memctl->memc_or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->memc_or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; #endif -#if defined(CFG_OR5_REMAP) - memctl->memc_or5 = CFG_OR5_REMAP; +#if defined(CONFIG_SYS_OR5_REMAP) + memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; #endif /* now restrict to preliminary range */ - memctl->memc_br0 = CFG_BR0_PRELIM; - memctl->memc_or0 = CFG_OR0_PRELIM; + memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; -#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; +#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; #endif #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ memctl->memc_br0 = 0; #endif -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - memctl->memc_or6 = CFG_OR6_PRELIM; - memctl->memc_br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) + memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; + memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - memctl->memc_or7 = CFG_OR7_PRELIM; - memctl->memc_br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) + memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; + memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif #endif /* ! CONFIG_MBX */ @@ -249,13 +249,13 @@ void cpu_init_f (volatile immap_t * immr) rpxlite_init (); #endif -#ifdef CFG_RCCR /* must be done before cpm_load_patch() */ +#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ /* write config value */ - immr->im_cpm.cp_rccr = CFG_RCCR; + immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; #endif -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \ - defined(CFG_SMC_UCODE_PATCH) +#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ + defined(CONFIG_SYS_SMC_UCODE_PATCH) cpm_load_patch (immr); /* load mpc8xx microcode patch */ #endif } @@ -265,21 +265,21 @@ void cpu_init_f (volatile immap_t * immr) */ int cpu_init_r (void) { -#if defined(CFG_RTCSC) || defined(CFG_RMDS) +#if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) bd_t *bd = gd->bd; volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); #endif -#ifdef CFG_RTCSC +#ifdef CONFIG_SYS_RTCSC /* Unlock RTSC register */ immr->im_sitk.sitk_rtcsck = KAPWR_KEY; /* write config value */ - immr->im_sit.sit_rtcsc = CFG_RTCSC; + immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC; #endif -#ifdef CFG_RMDS +#ifdef CONFIG_SYS_RMDS /* write config value */ - immr->im_cpm.cp_rmds = CFG_RMDS; + immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS; #endif return (0); } diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 37eb481..141425d 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* define WANT_MII when MII support is required */ -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) #define WANT_MII #else #undef WANT_MII @@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR; #error RMII support is unusable without a working PHY. #endif -#ifdef CFG_DISCOVER_PHY +#ifdef CONFIG_SYS_DISCOVER_PHY static int mii_discover_phy(struct eth_device *dev); #endif @@ -197,7 +197,7 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length) { int j, rc; struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); /* section 16.9.23.3 * Wait for ready @@ -248,7 +248,7 @@ static int fec_recv (struct eth_device *dev) { struct ether_fcc_info_s *efis = dev->priv; volatile fec_t *fecp = - (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); + (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); int length; for (;;) { @@ -339,7 +339,7 @@ static inline void fec_10Mbps(struct eth_device *dev) if ((unsigned int)fecidx >= 2) hang(); - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask; + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask; } static inline void fec_100Mbps(struct eth_device *dev) @@ -351,7 +351,7 @@ static inline void fec_100Mbps(struct eth_device *dev) if ((unsigned int)fecidx >= 2) hang(); - ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask; + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask; } #endif @@ -359,7 +359,7 @@ static inline void fec_100Mbps(struct eth_device *dev) static inline void fec_full_duplex(struct eth_device *dev) { struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ @@ -368,7 +368,7 @@ static inline void fec_full_duplex(struct eth_device *dev) static inline void fec_half_duplex(struct eth_device *dev) { struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ @@ -377,7 +377,7 @@ static inline void fec_half_duplex(struct eth_device *dev) static void fec_pin_init(int fecidx) { bd_t *bd = gd->bd; - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile fec_t *fecp; /* @@ -474,7 +474,7 @@ static void fec_pin_init(int fecidx) * Configure port A for MII. */ -#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY) +#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY) /* * On the ICU862 board the MII-MDC pin is routed to PD8 pin @@ -569,9 +569,9 @@ static int fec_reset(volatile fec_t *fecp) static int fec_init (struct eth_device *dev, bd_t * bd) { struct ether_fcc_info_s *efis = dev->priv; - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile fec_t *fecp = - (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); + (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset); int i; if (efis->ether_index == 0) { @@ -657,7 +657,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) txIdx = 0; if (!rtx) { -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + dpram_alloc_align (sizeof (RTXBD), 8)); #else @@ -721,7 +721,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; if (efis->phy_addr == -1) { -#ifdef CFG_DISCOVER_PHY +#ifdef CONFIG_SYS_DISCOVER_PHY /* * wait for the PHY to wake up after reset */ @@ -772,7 +772,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s *efis = dev->priv; - volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); + volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset); int i; /* avoid halt if initialized; mii gets stuck otherwise */ @@ -801,7 +801,7 @@ static void fec_halt(struct eth_device* dev) efis->initialized = 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* Make MII read/write commands for the FEC. */ @@ -846,7 +846,7 @@ mii_send(uint mii_cmd) volatile fec_t *ep; int cnt; - ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec); + ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec); ep->fec_mii_data = mii_cmd; /* command to phy */ @@ -868,7 +868,7 @@ mii_send(uint mii_cmd) } #endif -#if defined(CFG_DISCOVER_PHY) +#if defined(CONFIG_SYS_DISCOVER_PHY) static int mii_discover_phy(struct eth_device *dev) { #define MAX_PHY_PASSES 11 @@ -937,7 +937,7 @@ static int mii_discover_phy(struct eth_device *dev) } return phyaddr; } -#endif /* CFG_DISCOVER_PHY */ +#endif /* CONFIG_SYS_DISCOVER_PHY */ #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) @@ -948,7 +948,7 @@ static int mii_discover_phy(struct eth_device *dev) */ static void __mii_init(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile fec_t *fecp = &(immr->im_cpm.cp_fec); if (fec_reset(fecp) < 0) diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index f05b666..29c7c71 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -45,12 +45,12 @@ DECLARE_GLOBAL_DATA_PTR; /*----------------------------------------------------------------------- * Set default values */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xFE #endif /*----------------------------------------------------------------------- */ @@ -162,7 +162,7 @@ i2c_roundrate(int hz, int speed, int filter, int modval, static int i2c_setrate (int hz, int speed) { - immap_t *immap = (immap_t *) CFG_IMMR; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c; int brgval, modval, /* 0-3 */ @@ -207,7 +207,7 @@ i2c_setrate (int hz, int speed) void i2c_init(int speed, int slaveaddr) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; @@ -215,21 +215,21 @@ i2c_init(int speed, int slaveaddr) volatile I2C_BD *rxbd, *txbd; uint dpaddr; -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ i2c_init_board(); #endif -#ifdef CFG_I2C_UCODE_PATCH +#ifdef CONFIG_SYS_I2C_UCODE_PATCH iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; #else /* Disable relocation */ iip->iic_rpbase = 0; #endif -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = iip->iic_rbase; if (dpaddr == 0) { /* need to allocate dual port ram */ @@ -269,7 +269,7 @@ i2c_init(int speed, int slaveaddr) * divide BRGCLK by 1) */ PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ; + i2c_setrate (gd->cpu_clk, CONFIG_SYS_I2C_SPEED) ; /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; @@ -295,7 +295,7 @@ i2c_init(int speed, int slaveaddr) /* Set maximum receive size. */ iip->iic_mrblr = I2C_RXTX_LEN; -#ifdef CFG_I2C_UCODE_PATCH +#ifdef CONFIG_SYS_I2C_UCODE_PATCH /* * Initialize required parameters if using microcode patch. */ @@ -318,13 +318,13 @@ i2c_init(int speed, int slaveaddr) static void i2c_newio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; PRINTD(("[I2C] i2c_newio\n")); -#ifdef CFG_I2C_UCODE_PATCH +#ifdef CONFIG_SYS_I2C_UCODE_PATCH iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; #endif state->rx_idx = 0; @@ -492,7 +492,7 @@ i2c_receive(i2c_state_t *state, static int i2c_doio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CFG_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; @@ -501,7 +501,7 @@ static int i2c_doio(i2c_state_t *state) PRINTD(("[I2C] i2c_doio\n")); -#ifdef CFG_I2C_UCODE_PATCH +#ifdef CONFIG_SYS_I2C_UCODE_PATCH iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; #endif @@ -593,7 +593,7 @@ int i2c_probe(uchar chip) int rc; uchar buf[1]; - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_newio(&state); @@ -628,7 +628,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones like * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the @@ -639,7 +639,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); @@ -678,7 +678,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[2] = (addr >> 8) & 0xFF; xaddr[3] = addr & 0xFF; -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones like * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the @@ -689,7 +689,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); @@ -722,7 +722,7 @@ i2c_reg_read(uchar i2c_addr, uchar reg) { uchar buf; - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_read(i2c_addr, reg, 1, &buf, 1); @@ -732,7 +732,7 @@ i2c_reg_read(uchar i2c_addr, uchar reg) void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) { - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_write(i2c_addr, reg, 1, &val, 1); } diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c index 20e7012..5daa6b2 100644 --- a/cpu/mpc8xx/interrupts.c +++ b/cpu/mpc8xx/interrupts.c @@ -47,9 +47,9 @@ static void cpm_interrupt (void *regs); int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - *decrementer_count = get_tbclk () / CFG_HZ; + *decrementer_count = get_tbclk () / CONFIG_SYS_HZ; /* disable all interrupts */ immr->im_siu_conf.sc_simask = 0; @@ -67,7 +67,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ void external_interrupt (struct pt_regs *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int irq; ulong simask, newmask; ulong vec, v_bit; @@ -124,7 +124,7 @@ void external_interrupt (struct pt_regs *regs) */ static void cpm_interrupt (void *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; uint vec; /* @@ -165,7 +165,7 @@ static void cpm_error_interrupt (void *dummy) void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; if ((vec & CPMVEC_OFFSET) != 0) { /* CPM interrupt */ @@ -202,7 +202,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void irq_free_handler (int vec) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; if ((vec & CPMVEC_OFFSET) != 0) { /* CPM interrupt */ @@ -230,7 +230,7 @@ void irq_free_handler (int vec) static void cpm_interrupt_init (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Initialize the CPM interrupt controller. @@ -266,7 +266,7 @@ static void cpm_interrupt_init (void) */ void timer_interrupt_cpu (struct pt_regs *regs) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #if 0 printf ("*** Timer Interrupt *** "); diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S index 812baa3..2cc8fe6 100644 --- a/cpu/mpc8xx/kgdb.S +++ b/cpu/mpc8xx/kgdb.S @@ -52,21 +52,21 @@ kgdb_flush_cache_all: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 + li r5,CONFIG_SYS_CACHELINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT + srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE + addi r6,r6,CONFIG_SYS_CACHELINE_SIZE bdnz 2b SYNC blr diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c index 3c64a9b..4474e24 100644 --- a/cpu/mpc8xx/lcd.c +++ b/cpu/mpc8xx/lcd.c @@ -63,7 +63,7 @@ #define LCD_BPP LCD_COLOR4 vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 /* wbl, vpw, lcdac, wbf */ }; @@ -76,7 +76,7 @@ vidinfo_t panel_info = { * Hitachi SP19X001-. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 /* wbl, vpw, lcdac, wbf */ }; @@ -89,7 +89,7 @@ vidinfo_t panel_info = { * NEC NL6448AC33-18. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 144, 2, 0, 33 /* wbl, vpw, lcdac, wbf */ }; @@ -101,7 +101,7 @@ vidinfo_t panel_info = { * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 144, 2, 0, 33 /* wbl, vpw, lcdac, wbf */ }; @@ -113,7 +113,7 @@ vidinfo_t panel_info = { * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 144, 2, 0, 33 /* wbl, vpw, lcdac, wbf */ }; @@ -125,7 +125,7 @@ vidinfo_t panel_info = { * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, 3, 0, 0, 1, 1, 25, 1, 0, 33 /* wbl, vpw, lcdac, wbf */ }; @@ -138,7 +138,7 @@ vidinfo_t panel_info = { * not sure what it is....... */ vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 15, 4, 0, 3 }; #endif /* CONFIG_SHARP_16x9 */ @@ -152,7 +152,7 @@ vidinfo_t panel_info = { #define LCD_DF 12 vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 15, 4, 0, 3 /* wbl, vpw, lcdac, wbf */ }; @@ -165,7 +165,7 @@ vidinfo_t panel_info = { * Sharp LQ64D341 display, 640x480. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 128, 16, 0, 32 /* wbl, vpw, lcdac, wbf */ }; @@ -176,7 +176,7 @@ vidinfo_t panel_info = { * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. */ vidinfo_t panel_info = { - 400, 240, 143, 79, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, + 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 248, 4, 0, 35 /* wbl, vpw, lcdac, wbf */ }; @@ -188,7 +188,7 @@ vidinfo_t panel_info = { * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 171, 129, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW, + 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, 3, 0, 0, 1, 1, 160, 3, 0, 48 /* wbl, vpw, lcdac, wbf */ }; @@ -201,7 +201,7 @@ vidinfo_t panel_info = { * HLD1045 display, 640x480. Active, color, single scan. */ vidinfo_t panel_info = { - 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 160, 3, 0, 48 /* wbl, vpw, lcdac, wbf */ }; @@ -213,7 +213,7 @@ vidinfo_t panel_info = { * Prime View V16C6448AC */ vidinfo_t panel_info = { - 640, 480, 130, 98, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH, + 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, 3, 0, 0, 1, 1, 144, 2, 0, 35 /* wbl, vpw, lcdac, wbf */ }; @@ -235,7 +235,7 @@ vidinfo_t panel_info = { /* 1 - 4 grey levels, 2 bpp */ /* 2 - 16 grey levels, 4 bpp */ vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW, + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 }; #endif /* CONFIG_OPTREX_BW */ @@ -249,7 +249,7 @@ vidinfo_t panel_info = { #define LCD_DF 10 vidinfo_t panel_info = { - 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW, + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 }; #endif @@ -307,7 +307,7 @@ ulong calc_fbsize (void) void lcd_ctrl_init (void *lcdbase) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile lcd823_t *lcdp = &immr->im_lcd; uint lccrtmp; @@ -320,7 +320,7 @@ void lcd_ctrl_init (void *lcdbase) #ifdef CONFIG_RPXLITE /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ - panel_info.vl_dp = CFG_LOW; + panel_info.vl_dp = CONFIG_SYS_LOW; #endif lccrtmp = LCDBIT (LCCR_BNUM_BIT, @@ -436,14 +436,14 @@ void lcd_ctrl_init (void *lcdbase) static void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(immr->im_cpm); unsigned short colreg, *cmap_ptr; cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; colreg = *cmap_ptr; -#ifdef CFG_INVERT_COLORS +#ifdef CONFIG_SYS_INVERT_COLORS colreg ^= 0x0FFF; #endif @@ -459,7 +459,7 @@ lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(immr->im_cpm); unsigned short colreg, *cmap_ptr; @@ -468,7 +468,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) colreg = ((red & 0x0F) << 8) | ((green & 0x0F) << 4) | (blue & 0x0F) ; -#ifdef CFG_INVERT_COLORS +#ifdef CONFIG_SYS_INVERT_COLORS colreg ^= 0x0FFF; #endif *cmap_ptr = colreg; @@ -486,7 +486,7 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) static void lcd_initcolregs (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(immr->im_cpm); ushort regno; @@ -501,7 +501,7 @@ void lcd_initcolregs (void) void lcd_enable (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile lcd823_t *lcdp = &immr->im_lcd; /* Enable the LCD panel */ @@ -521,7 +521,7 @@ void lcd_enable (void) #if defined(CONFIG_LWMON) { uchar c = pic_read (0x60); -#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON) +#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) /* Enable LCD later in sysmon test, only if temperature is OK */ #else c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ @@ -586,7 +586,7 @@ void lcd_enable (void) #if defined (CONFIG_RBC823) void lcd_disable (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile lcd823_t *lcdp = &immr->im_lcd; #if defined(CONFIG_LWMON) diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 09a6348..effb967 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -191,7 +191,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) int i; scc_enet_t *pram_ptr; - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; #if defined(CONFIG_LWMON) reset_phy(); @@ -216,7 +216,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) txIdx = 0; if (!rtx) { -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + dpram_alloc_align (sizeof (RTXBD), 8)); #else @@ -552,7 +552,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) static void scc_halt (struct eth_device *dev) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); @@ -563,7 +563,7 @@ static void scc_halt (struct eth_device *dev) #if 0 void restart (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index ad02299..cae90dd 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -74,8 +74,8 @@ static void serial_setdivisor(volatile cpm8xx_t *cp) divisor=(50*1000*1000 + 8*9600)/16/9600; } -#ifdef CFG_BRGCLK_PRESCALE - divisor /= CFG_BRGCLK_PRESCALE; +#ifdef CONFIG_SYS_BRGCLK_PRESCALE + divisor /= CONFIG_SYS_BRGCLK_PRESCALE; #endif if(divisor<=0x1000) { @@ -94,7 +94,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp) static void smc_setbrg (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); /* Set up the baud rate generator. @@ -110,7 +110,7 @@ static void smc_setbrg (void) static int smc_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -124,7 +124,7 @@ static int smc_init (void) sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH +#ifdef CONFIG_SYS_SMC_UCODE_PATCH up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; #else /* Disable relocation */ @@ -140,15 +140,15 @@ static int smc_init (void) im->im_siu_conf.sc_sdcr = 1; /* clear error conditions */ -#ifdef CFG_SDSR - im->im_sdma.sdma_sdsr = CFG_SDSR; +#ifdef CONFIG_SYS_SDSR + im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; #else im->im_sdma.sdma_sdsr = 0x83; #endif /* clear SDMA interrupt mask */ -#ifdef CFG_SDMR - im->im_sdma.sdma_sdmr = CFG_SDMR; +#ifdef CONFIG_SYS_SDMR + im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; #else im->im_sdma.sdma_sdmr = 0x00; #endif @@ -193,7 +193,7 @@ static int smc_init (void) * the buffer descriptors. */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; #else dpaddr = CPM_SERIAL_BASE ; @@ -218,7 +218,7 @@ static int smc_init (void) up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = SMC_EB; up->smc_tfcr = SMC_EB; -#if defined (CFG_SMC_UCODE_PATCH) +#if defined (CONFIG_SYS_SMC_UCODE_PATCH) up->smc_rbptr = up->smc_rbase; up->smc_tbptr = up->smc_tbase; up->smc_rstate = 0; @@ -239,11 +239,11 @@ static int smc_init (void) sp->smc_smcm = 0; sp->smc_smce = 0xff; -#ifdef CFG_SPC1920_SMC1_CLK4 +#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4 /* clock source is PLD */ /* set freq to 19200 Baud */ - *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3; + *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3; /* configure clk4 as input */ im->im_ioport.iop_pdpar |= 0x800; im->im_ioport.iop_pddir &= ~0x800; @@ -288,7 +288,7 @@ smc_putc(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); #ifdef CONFIG_MODEM_SUPPORT @@ -300,7 +300,7 @@ smc_putc(const char c) smc_putc ('\r'); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH +#ifdef CONFIG_SYS_SMC_UCODE_PATCH up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; #endif @@ -336,12 +336,12 @@ smc_getc(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); unsigned char c; up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH +#ifdef CONFIG_SYS_SMC_UCODE_PATCH up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; #endif @@ -365,11 +365,11 @@ smc_tstc(void) { volatile cbd_t *rbdf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH +#ifdef CONFIG_SYS_SMC_UCODE_PATCH up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; #endif @@ -398,7 +398,7 @@ struct serial_device serial_smc_device = static void scc_setbrg (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); /* Set up the baud rate generator. @@ -414,7 +414,7 @@ scc_setbrg (void) static int scc_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -474,7 +474,7 @@ static int scc_init (void) /* Allocate space for two buffer descriptors in the DP ram. */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; #else dpaddr = CPM_SERIAL2_BASE ; @@ -580,7 +580,7 @@ scc_putc(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); #ifdef CONFIG_MODEM_SUPPORT @@ -625,7 +625,7 @@ scc_getc(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); unsigned char c; @@ -651,7 +651,7 @@ scc_tstc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC]; diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 070babc..f309f29 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG) +#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG) #define PITC_SHIFT 16 #define PITR_SHIFT 16 @@ -87,12 +87,12 @@ static __inline__ void set_msr(unsigned long msr) unsigned long measure_gclk(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; ulong timer2_val; ulong msr_val; -#ifdef CFG_8XX_XIN +#ifdef CONFIG_SYS_8XX_XIN /* dont use OSCM, only use EXTCLK/512 */ immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; #else @@ -137,7 +137,7 @@ unsigned long measure_gclk(void) immr->im_sit.sit_pitc = SPEED_PITC_INIT; immr->im_sitk.sitk_piscrk = KAPWR_KEY; - immr->im_sit.sit_piscr = CFG_PISCR; + immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; /* * Start measurement - disable interrupts, just in case @@ -164,9 +164,9 @@ unsigned long measure_gclk(void) timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); immr->im_sit.sit_piscr &= ~PISCR_PTE; -#if defined(CFG_8XX_XIN) +#if defined(CONFIG_SYS_8XX_XIN) /* not using OSCM, using XIN, so scale appropriately */ - return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L; + return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L; #else return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ #endif @@ -261,7 +261,7 @@ static long init_pll_866 (long clk); */ int get_clocks_866 (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; char tmp[64]; long cpuclk = 0; long sccr_reg; @@ -269,11 +269,11 @@ int get_clocks_866 (void) if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk)) + if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk)) cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; gd->cpu_clk = init_pll_866 (cpuclk); -#if defined(CFG_MEASURE_CPUCLK) +#if defined(CONFIG_SYS_MEASURE_CPUCLK) gd->cpu_clk = measure_gclk (); #endif @@ -301,12 +301,12 @@ int get_clocks_866 (void) */ int sdram_adjust_866 (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; long mamr; mamr = immr->im_memctl.memc_mamr; mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); + mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); immr->im_memctl.memc_mamr = mamr; return (0); @@ -320,7 +320,7 @@ static long init_pll_866 (long clk) { extern void plprcr_write_866 (long); - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; long n, plprcr; char mfi, mfn, mfd, s, pdf; long step_mfi, step_mfn; @@ -394,13 +394,13 @@ static long init_pll_866 (long clk) */ int adjust_sdram_tbs_8xx (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; long mamr; long sccr; mamr = immr->im_memctl.memc_mamr; mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT); + mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); immr->im_memctl.memc_mamr = mamr; if (gd->cpu_clk < 67000000) { diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c index e318ed0..b2ac23e 100644 --- a/cpu/mpc8xx/spi.c +++ b/cpu/mpc8xx/spi.c @@ -41,7 +41,7 @@ #include #include -#if (defined(CONFIG_SPI)) || (CONFIG_POST & CFG_POST_SPI) +#if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI) /* Warning: * You cannot enable DEBUG for early system initalization, i. e. when @@ -64,8 +64,8 @@ * The value 0xb00 makes it far enough from the start of the data * area (as well as from the stack pointer). * --------------------------------------------------------------- */ -#ifndef CFG_SPI_INIT_OFFSET -#define CFG_SPI_INIT_OFFSET 0xB00 +#ifndef CONFIG_SYS_SPI_INIT_OFFSET +#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 #endif #ifdef DEBUG @@ -118,11 +118,11 @@ ssize_t spi_xfer (size_t); * Initially we place the RX and TX buffers at a fixed location in DPRAM! * ---------------------------------------------------------------------- */ static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem - [CFG_SPI_INIT_OFFSET]; + (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem + [CONFIG_SYS_SPI_INIT_OFFSET]; static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem - [CFG_SPI_INIT_OFFSET+MAX_BUFFER]; + (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem + [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; /* ************************************************************************** * @@ -144,12 +144,12 @@ void spi_init_f (void) volatile iop8xx_t *iop; volatile cbd_t *tbdf, *rbdf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cpi = (cpic8xx_t *)&immr->im_cpic; iop = (iop8xx_t *) &immr->im_ioport; cp = (cpm8xx_t *) &immr->im_cpm; -#ifdef CFG_SPI_UCODE_PATCH +#ifdef CONFIG_SYS_SPI_UCODE_PATCH spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; #else spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; @@ -210,7 +210,7 @@ void spi_init_f (void) /* Allocate space for one transmit and one receive buffer * descriptor in the DP ram */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = dpram_alloc_align (sizeof(cbd_t)*2, 8); #else dpaddr = CPM_SPI_BASE; @@ -234,7 +234,7 @@ void spi_init_f (void) spi->spi_tbptr = spi->spi_tbase; /* 4 */ -#ifdef CFG_SPI_UCODE_PATCH +#ifdef CONFIG_SYS_SPI_UCODE_PATCH /* * Initialize required parameters if using microcode patch. */ @@ -247,7 +247,7 @@ void spi_init_f (void) cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cp_cpcr & CPM_CR_FLG) ; -#endif /* CFG_SPI_UCODE_PATCH */ +#endif /* CONFIG_SYS_SPI_UCODE_PATCH */ /* 5 */ /* Set SDMA configuration register */ @@ -299,10 +299,10 @@ void spi_init_r (void) volatile immap_t *immr; volatile cbd_t *tbdf, *rbdf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8xx_t *) &immr->im_cpm; -#ifdef CFG_SPI_UCODE_PATCH +#ifdef CONFIG_SYS_SPI_UCODE_PATCH spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; #else spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; @@ -392,10 +392,10 @@ ssize_t spi_xfer (size_t count) DPRINT (("*** spi_xfer entered ***\n")); - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8xx_t *) &immr->im_cpm; -#ifdef CFG_SPI_UCODE_PATCH +#ifdef CONFIG_SYS_SPI_UCODE_PATCH spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase]; #else spi = (spi_t *)&cp->cp_dparam[PROFF_SPI]; @@ -468,7 +468,7 @@ ssize_t spi_xfer (size_t count) return count; } -#endif /* CONFIG_SPI || (CONFIG_POST & CFG_POST_SPI) */ +#endif /* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */ /* * SPI test @@ -481,7 +481,7 @@ ssize_t spi_xfer (size_t count) * TEST_NUM - number of tests */ -#if CONFIG_POST & CFG_POST_SPI +#if CONFIG_POST & CONFIG_SYS_POST_SPI #define TEST_MIN_LENGTH 1 #define TEST_MAX_LENGTH MAX_BUFFER @@ -513,7 +513,7 @@ static int packet_check (char * packet, int length) int spi_post_test (int flags) { int res = -1; - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm; int i; int l; @@ -557,4 +557,4 @@ int spi_post_test (int flags) return res; } -#endif /* CONFIG_POST & CFG_POST_SPI */ +#endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */ diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index eca4b50..7b75660 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -93,7 +93,7 @@ version_string: . = EXC_OFF_SYS_RESET .globl _start _start: - lis r3, CFG_IMMR@h /* position IMMR */ + lis r3, CONFIG_SYS_IMMR@h /* position IMMR */ mtspr 638, r3 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ b boot_cold @@ -159,8 +159,8 @@ boot_warm: * Calculate absolute address in FLASH and jump there *----------------------------------------------------------------------*/ - lis r3, CFG_MONITOR_BASE@h - ori r3, r3, CFG_MONITOR_BASE@l + lis r3, CONFIG_SYS_MONITOR_BASE@h + ori r3, r3, CONFIG_SYS_MONITOR_BASE@l addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr @@ -170,8 +170,8 @@ in_flash: /* initialize some SPRs that are hard to access from C */ /*----------------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* pass IMMR as arg1 to C routine */ - ori r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ + lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */ + ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */ /* Note: R0 is still 0 here */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -187,8 +187,8 @@ in_flash: /* Set up debug mode entry */ - lis r2, CFG_DER@h - ori r2, r2, CFG_DER@l + lis r2, CONFIG_SYS_DER@h + ori r2, r2, CONFIG_SYS_DER@l mtspr DER, r2 /* let the C-code set up the rest */ @@ -495,16 +495,16 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c index 4d6c522..a8cb735 100644 --- a/cpu/mpc8xx/upatch.c +++ b/cpu/mpc8xx/upatch.c @@ -1,8 +1,8 @@ #include #include -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \ - defined(CFG_SMC_UCODE_PATCH) +#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ + defined(CONFIG_SYS_SMC_UCODE_PATCH) static void UcodeCopy (volatile cpm8xx_t *cpm); @@ -11,36 +11,36 @@ void cpm_load_patch (volatile immap_t *immr) immr->im_cpm.cp_rccr &= ~0x0003; /* Disable microcode program area */ UcodeCopy ((cpm8xx_t *)&immr->im_cpm); /* Copy ucode patch to DPRAM */ -#ifdef CFG_SPI_UCODE_PATCH +#ifdef CONFIG_SYS_SPI_UCODE_PATCH { volatile spi_t *spi = (spi_t *) & immr->im_cpm.cp_dparam[PROFF_SPI]; /* Activate the microcode per the instructions in the microcode manual */ /* NOTE: We're only relocating the SPI parameters (not I2C). */ immr->im_cpm.cp_cpmcr1 = 0x802a; /* Write Trap register 1 value */ immr->im_cpm.cp_cpmcr2 = 0x8028; /* Write Trap register 2 value */ - spi->spi_rpbase = CFG_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */ + spi->spi_rpbase = CONFIG_SYS_SPI_DPMEM_OFFSET; /* Where to relocte SPI params */ } #endif -#ifdef CFG_I2C_UCODE_PATCH +#ifdef CONFIG_SYS_I2C_UCODE_PATCH { volatile iic_t *iip = (iic_t *) & immr->im_cpm.cp_dparam[PROFF_IIC]; /* Activate the microcode per the instructions in the microcode manual */ /* NOTE: We're only relocating the I2C parameters (not SPI). */ immr->im_cpm.cp_cpmcr3 = 0x802e; /* Write Trap register 3 value */ immr->im_cpm.cp_cpmcr4 = 0x802c; /* Write Trap register 4 value */ - iip->iic_rpbase = CFG_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */ + iip->iic_rpbase = CONFIG_SYS_I2C_DPMEM_OFFSET; /* Where to relocte I2C params */ } #endif -#ifdef CFG_SMC_UCODE_PATCH +#ifdef CONFIG_SYS_SMC_UCODE_PATCH { volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1]; /* Activate the microcode per the instructions in the microcode manual */ /* NOTE: We're only relocating the SMC parameters. */ immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */ immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */ - up->smc_rpbase = CFG_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */ + up->smc_rpbase = CONFIG_SYS_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */ } #endif @@ -48,14 +48,14 @@ void cpm_load_patch (volatile immap_t *immr) * Enable DPRAM microcode to execute from the first 512 bytes * and a 256 byte extension of DPRAM. */ -#ifdef CFG_SMC_UCODE_PATCH +#ifdef CONFIG_SYS_SMC_UCODE_PATCH immr->im_cpm.cp_rccr |= 0x0002; #else immr->im_cpm.cp_rccr |= 0x0001; #endif } -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCh) +#if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCh) static ulong patch_2000[] = { 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7, @@ -191,4 +191,4 @@ static void UcodeCopy (volatile cpm8xx_t *cpm) } } -#endif /* CFG_I2C_UCODE_PATCH, CFG_SPI_UCODE_PATCH */ +#endif /* CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_SPI_UCODE_PATCH */ diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c index ef91165..2e6a22a 100644 --- a/cpu/mpc8xx/video.c +++ b/cpu/mpc8xx/video.c @@ -517,7 +517,7 @@ static void inline video_mode_addentry (VRAM * vr, static int video_mode_generate (void) { - immap_t *immap = (immap_t *) CFG_IMMR; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; VRAM *vr = (VRAM *) (((void *) immap) + 0xb00); /* Pointer to the VRAM table */ int DX, X1, X2, DY, Y1, Y2, entry = 0, fifo; @@ -808,7 +808,7 @@ static void video_encoder_init (void) /* Initialize the I2C */ debug ("[VIDEO ENCODER] Initializing I2C bus...\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #ifdef CONFIG_FADS /* Reset ADV7176 chip */ @@ -856,7 +856,7 @@ static void video_encoder_init (void) static void video_ctrl_init (void *memptr) { - immap_t *immap = (immap_t *) CFG_IMMR; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; video_fb_address = memptr; @@ -1235,13 +1235,13 @@ static int video_init (void *videobase) video_setpalette (CONSOLE_COLOR_GREY2, 0xF8, 0xF8, 0xF8); video_setpalette (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); -#ifndef CFG_WHITE_ON_BLACK +#ifndef CONFIG_SYS_WHITE_ON_BLACK video_setfgcolor (CONSOLE_COLOR_BLACK); video_setbgcolor (CONSOLE_COLOR_GREY2); #else video_setfgcolor (CONSOLE_COLOR_GREY2); video_setbgcolor (CONSOLE_COLOR_BLACK); -#endif /* CFG_WHITE_ON_BLACK */ +#endif /* CONFIG_SYS_WHITE_ON_BLACK */ #ifdef CONFIG_VIDEO_LOGO /* Paint the logo and retrieve tv base address */ diff --git a/cpu/mpc8xxx/ddr/ddr.h b/cpu/mpc8xxx/ddr/ddr.h index f5dc40a..0d79be3 100644 --- a/cpu/mpc8xxx/ddr/ddr.h +++ b/cpu/mpc8xxx/ddr/ddr.h @@ -31,17 +31,17 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd, * * All data structures have to be on the stack */ -#define CFG_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS -#define CFG_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR +#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR typedef struct { generic_spd_eeprom_t - spd_installed_dimms[CFG_NUM_DDR_CTLRS][CFG_DIMM_SLOTS_PER_CTLR]; + spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; struct dimm_params_s - dimm_params[CFG_NUM_DDR_CTLRS][CFG_DIMM_SLOTS_PER_CTLR]; - memctl_options_t memctl_opts[CFG_NUM_DDR_CTLRS]; - common_timing_params_t common_timing_params[CFG_NUM_DDR_CTLRS]; - fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CFG_NUM_DDR_CTLRS]; + dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; + common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; + fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; } fsl_ddr_info_t; /* Compute steps */ diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c index c2cd8fe..2c2e838 100644 --- a/cpu/nios/asmi.c +++ b/cpu/nios/asmi.c @@ -27,8 +27,8 @@ #include #include -#if !defined(CFG_NIOS_ASMIBASE) -#error "*** CFG_NIOS_ASMIBASE not defined ***" +#if !defined(CONFIG_SYS_NIOS_ASMIBASE) +#error "*** CONFIG_SYS_NIOS_ASMIBASE not defined ***" #endif /*-----------------------------------------------------------------------*/ @@ -69,7 +69,7 @@ #define ASMI_STATUS_WIP (1<<0) /* Write in progress */ #define ASMI_STATUS_WEL (1<<1) /* Write enable latch */ -static nios_asmi_t *asmi = (nios_asmi_t *)CFG_NIOS_ASMIBASE; +static nios_asmi_t *asmi = (nios_asmi_t *)CONFIG_SYS_NIOS_ASMIBASE; /*********************************************************************** * Device access diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c index 75e491d..55a5718 100644 --- a/cpu/nios/interrupts.c +++ b/cpu/nios/interrupts.c @@ -68,15 +68,15 @@ void set_timer (ulong t) /* The board must handle this interrupt if a timer is not * provided. */ -#if defined(CFG_NIOS_TMRBASE) +#if defined(CONFIG_SYS_NIOS_TMRBASE) void timer_interrupt (struct pt_regs *regs) { /* Interrupt is cleared by writing anything to the * status register. */ - nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE; + nios_timer_t *tmr = (nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; tmr->status = 0; - timestamp += CFG_NIOS_TMRMS; + timestamp += CONFIG_SYS_NIOS_TMRMS; #ifdef CONFIG_STATUS_LED status_led_tick(timestamp); #endif @@ -125,14 +125,14 @@ int interrupt_init (void) { int vec; -#if defined(CFG_NIOS_TMRBASE) - nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE; +#if defined(CONFIG_SYS_NIOS_TMRBASE) + nios_timer_t *tmr = (nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; tmr->control &= ~NIOS_TIMER_ITO; tmr->control |= NIOS_TIMER_STOP; -#if defined(CFG_NIOS_TMRCNT) - tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; - tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; +#if defined(CONFIG_SYS_NIOS_TMRCNT) + tmr->periodl = CONFIG_SYS_NIOS_TMRCNT & 0xffff; + tmr->periodh = (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff; #endif #endif @@ -143,11 +143,11 @@ int interrupt_init (void) } /* Need timus interruptus -- start the lopri timer */ -#if defined(CFG_NIOS_TMRBASE) +#if defined(CONFIG_SYS_NIOS_TMRBASE) tmr->control |= ( NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START ); - ipri (CFG_NIOS_TMRIRQ + 1); + ipri (CONFIG_SYS_NIOS_TMRIRQ + 1); #endif enable_interrupts (); return (0); diff --git a/cpu/nios/serial.c b/cpu/nios/serial.c index 5ecdc6d..44aa600 100644 --- a/cpu/nios/serial.c +++ b/cpu/nios/serial.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; *-----------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE; +static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; void serial_setbrg( void ){ return; } int serial_init( void ) { return(0);} @@ -71,9 +71,9 @@ int serial_getc (void) *-----------------------------------------------------------------*/ #else -static nios_uart_t *uart = (nios_uart_t *)CFG_NIOS_CONSOLE; +static nios_uart_t *uart = (nios_uart_t *)CONFIG_SYS_NIOS_CONSOLE; -#if defined(CFG_NIOS_FIXEDBAUD) +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) /* Everything's already setup for fixed-baud PTF * assignment @@ -98,7 +98,7 @@ int serial_init (void) return (0); } -#endif /* CFG_NIOS_FIXEDBAUD */ +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ /*----------------------------------------------------------------------- diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c index 6408180..89f9797 100644 --- a/cpu/nios/spi.c +++ b/cpu/nios/spi.c @@ -28,19 +28,19 @@ #include #include -#if !defined(CFG_NIOS_SPIBASE) -#error "*** CFG_NIOS_SPIBASE not defined ***" +#if !defined(CONFIG_SYS_NIOS_SPIBASE) +#error "*** CONFIG_SYS_NIOS_SPIBASE not defined ***" #endif -#if !defined(CFG_NIOS_SPIBITS) -#error "*** CFG_NIOS_SPIBITS not defined ***" +#if !defined(CONFIG_SYS_NIOS_SPIBITS) +#error "*** CONFIG_SYS_NIOS_SPIBITS not defined ***" #endif -#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16) -#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***" +#if (CONFIG_SYS_NIOS_SPIBITS != 8) && (CONFIG_SYS_NIOS_SPIBITS != 16) +#error "*** CONFIG_SYS_NIOS_SPIBITS should be either 8 or 16 ***" #endif -static nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; +static nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE; /* Warning: * You cannot enable DEBUG for early system initalization, i. e. when @@ -139,7 +139,7 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); - if (!(flags & SPI_XFER_END) || bitlen > CFG_NIOS_SPIBITS) { + if (!(flags & SPI_XFER_END) || bitlen > CONFIG_SYS_NIOS_SPIBITS) { /* leave chip select active */ spi->control |= NIOS_SPI_SSO; } @@ -147,7 +147,7 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, for ( j = 0; /* count each byte in */ j < ((bitlen + 7) / 8); /* dout[] and din[] */ -#if (CFG_NIOS_SPIBITS == 8) +#if (CONFIG_SYS_NIOS_SPIBITS == 8) j++) { while ((spi->status & NIOS_SPI_TRDY) == 0) @@ -158,7 +158,7 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, ; rxd[j] = (unsigned char)(spi->rxdata & 0xff); -#elif (CFG_NIOS_SPIBITS == 16) +#elif (CONFIG_SYS_NIOS_SPIBITS == 16) j++, j++) { while ((spi->status & NIOS_SPI_TRDY) == 0) @@ -175,12 +175,12 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, rxd[j+1] = (unsigned char)(spi->rxdata & 0xff); #else -#error "*** unsupported value of CFG_NIOS_SPIBITS ***" +#error "*** unsupported value of CONFIG_SYS_NIOS_SPIBITS ***" #endif } - if (bitlen > CFG_NIOS_SPIBITS && (flags & SPI_XFER_END)) { + if (bitlen > CONFIG_SYS_NIOS_SPIBITS && (flags & SPI_XFER_END)) { spi->control &= ~NIOS_SPI_SSO; } diff --git a/cpu/nios/start.S b/cpu/nios/start.S index 9e73941..5d15e8d 100644 --- a/cpu/nios/start.S +++ b/cpu/nios/start.S @@ -71,10 +71,10 @@ _start: /* * STACK */ - pfx %hi(CFG_INIT_SP) - movi %sp, %lo(CFG_INIT_SP) - pfx %xhi(CFG_INIT_SP) - movhi %sp, %xlo(CFG_INIT_SP) + pfx %hi(CONFIG_SYS_INIT_SP) + movi %sp, %lo(CONFIG_SYS_INIT_SP) + pfx %xhi(CONFIG_SYS_INIT_SP) + movhi %sp, %xlo(CONFIG_SYS_INIT_SP) mov %fp, %sp pfx %hi(4*16) @@ -152,10 +152,10 @@ reloc: /* * INIT VECTOR TABLE */ - pfx %hi(CFG_VECT_BASE) - movi %g0, %lo(CFG_VECT_BASE) - pfx %xhi(CFG_VECT_BASE) - movhi %g0, %xlo(CFG_VECT_BASE) /* dst */ + pfx %hi(CONFIG_SYS_VECT_BASE) + movi %g0, %lo(CONFIG_SYS_VECT_BASE) + pfx %xhi(CONFIG_SYS_VECT_BASE) + movhi %g0, %xlo(CONFIG_SYS_VECT_BASE) /* dst */ mov %l0, %g0 pfx %hi(_vectors) diff --git a/cpu/nios2/cpu.c b/cpu/nios2/cpu.c index f4217a8..6379534 100644 --- a/cpu/nios2/cpu.c +++ b/cpu/nios2/cpu.c @@ -25,14 +25,14 @@ #include #include -#if defined (CFG_NIOS_SYSID_BASE) +#if defined (CONFIG_SYS_NIOS_SYSID_BASE) extern void display_sysid (void); -#endif /* CFG_NIOS_SYSID_BASE */ +#endif /* CONFIG_SYS_NIOS_SYSID_BASE */ int checkcpu (void) { printf ("CPU : Nios-II\n"); -#if !defined(CFG_NIOS_SYSID_BASE) +#if !defined(CONFIG_SYS_NIOS_SYSID_BASE) printf ("SYSID : \n"); #else display_sysid (); @@ -43,7 +43,7 @@ int checkcpu (void) int do_reset (void) { - void (*rst)(void) = (void(*)(void))CFG_RESET_ADDR; + void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR; disable_interrupts (); rst(); return(0); diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c index 414c38c..968b50f 100644 --- a/cpu/nios2/epcs.c +++ b/cpu/nios2/epcs.c @@ -23,7 +23,7 @@ #include -#if defined(CFG_NIOS_EPCSBASE) +#if defined(CONFIG_SYS_NIOS_EPCSBASE) #include #include #include @@ -72,7 +72,7 @@ */ #define EPCS_TIMEOUT 100 /* 100 msec timeout */ -static nios_spi_t *epcs = (nios_spi_t *)CFG_NIOS_EPCSBASE; +static nios_spi_t *epcs = (nios_spi_t *)CONFIG_SYS_NIOS_EPCSBASE; /*********************************************************************** * Device access diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index ec5db31b..1c3566e 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -37,8 +37,8 @@ #include #endif -#if defined(CFG_NIOS_TMRBASE) && !defined(CFG_NIOS_TMRIRQ) -#error CFG_NIOS_TMRIRQ not defined (see documentation) +#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) +#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) #endif /****************************************************************************/ @@ -74,7 +74,7 @@ void set_timer (ulong t) /* The board must handle this interrupt if a timer is not * provided. */ -#if defined(CFG_NIOS_TMRBASE) +#if defined(CONFIG_SYS_NIOS_TMRBASE) void tmr_isr (void *arg) { nios_timer_t *tmr = (nios_timer_t *)arg; @@ -82,7 +82,7 @@ void tmr_isr (void *arg) * status register. */ writel (&tmr->status, 0); - timestamp += CFG_NIOS_TMRMS; + timestamp += CONFIG_SYS_NIOS_TMRMS; #ifdef CONFIG_STATUS_LED status_led_tick(timestamp); #endif @@ -90,22 +90,22 @@ void tmr_isr (void *arg) static void tmr_init (void) { - nios_timer_t *tmr =(nios_timer_t *)CFG_NIOS_TMRBASE; + nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; writel (&tmr->status, 0); writel (&tmr->control, 0); writel (&tmr->control, NIOS_TIMER_STOP); -#if defined(CFG_NIOS_TMRCNT) - writel (&tmr->periodl, CFG_NIOS_TMRCNT & 0xffff); - writel (&tmr->periodh, (CFG_NIOS_TMRCNT >> 16) & 0xffff); +#if defined(CONFIG_SYS_NIOS_TMRCNT) + writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff); + writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff); #endif writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START ); - irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr); + irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); } -#endif /* CFG_NIOS_TMRBASE */ +#endif /* CONFIG_SYS_NIOS_TMRBASE */ /*************************************************************************/ int disable_interrupts (void) @@ -195,7 +195,7 @@ int interrupt_init (void) vecs[i].count = 0; } -#if defined(CFG_NIOS_TMRBASE) +#if defined(CONFIG_SYS_NIOS_TMRBASE) tmr_init (); #endif diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c index 0bd3821..8bbb803 100644 --- a/cpu/nios2/serial.c +++ b/cpu/nios2/serial.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; *-----------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE; +static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE; void serial_setbrg( void ){ return; } int serial_init( void ) { return(0);} @@ -79,9 +79,9 @@ int serial_getc (void) *-----------------------------------------------------------------*/ #else -static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE; +static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; -#if defined(CFG_NIOS_FIXEDBAUD) +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) /* Everything's already setup for fixed-baud PTF * assignment @@ -106,7 +106,7 @@ int serial_init (void) return (0); } -#endif /* CFG_NIOS_FIXEDBAUD */ +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ /*----------------------------------------------------------------------- diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S index 6c6f294..ea41435 100644 --- a/cpu/nios2/start.S +++ b/cpu/nios2/start.S @@ -39,9 +39,9 @@ _start: * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - ori r4, r0, %lo(CFG_ICACHELINE_SIZE) - movhi r5, %hi(CFG_ICACHE_SIZE) - ori r5, r5, %lo(CFG_ICACHE_SIZE) + ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) + movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) + ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) mov r6, r0 0: initi r6 add r6, r6, r4 @@ -67,10 +67,10 @@ _except_end: /* DCACHE INIT -- if dcache not implemented, initd behaves as * nop. */ - movhi r4, %hi(CFG_DCACHELINE_SIZE) - ori r4, r4, %lo(CFG_DCACHELINE_SIZE) - movhi r5, %hi(CFG_DCACHE_SIZE) - ori r5, r5, %lo(CFG_DCACHE_SIZE) + movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE) + ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE) + movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE) + ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE) mov r6, r0 1: initd 0(r6) add r6, r6, r4 @@ -136,8 +136,8 @@ _reloc: ori r4, r4, %lo(_except_start) movhi r5, %hi(_except_end) ori r5, r5, %lo(_except_end) - movhi r6, %hi(CFG_EXCEPTION_ADDR) - ori r6, r6, %lo(CFG_EXCEPTION_ADDR) + movhi r6, %hi(CONFIG_SYS_EXCEPTION_ADDR) + ori r6, r6, %lo(CONFIG_SYS_EXCEPTION_ADDR) beq r4, r6, 7f /* Skip if at proper addr */ 6: ldwio r7, 0(r4) @@ -150,8 +150,8 @@ _reloc: /* STACK INIT -- zero top two words for call back chain. */ - movhi sp, %hi(CFG_INIT_SP) - ori sp, sp, %lo(CFG_INIT_SP) + movhi sp, %hi(CONFIG_SYS_INIT_SP) + ori sp, sp, %lo(CONFIG_SYS_INIT_SP) addi sp, sp, -8 stw r0, 0(sp) stw r0, 4(sp) @@ -195,7 +195,7 @@ _reloc: dly_clks: -#if (CFG_ICACHE_SIZE > 0) +#if (CONFIG_SYS_ICACHE_SIZE > 0) subi r4, r4, 3 /* 3 clocks/loop */ #else subi r4, r4, 12 /* 12 clocks/loop */ diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index 697ed03..afd5d83 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -23,7 +23,7 @@ #include -#if defined (CFG_NIOS_SYSID_BASE) +#if defined (CONFIG_SYS_NIOS_SYSID_BASE) #include #include @@ -32,7 +32,7 @@ void display_sysid (void) { - struct nios_sysid_t *sysid = (struct nios_sysid_t *)CFG_NIOS_SYSID_BASE; + struct nios_sysid_t *sysid = (struct nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE; struct tm t; char asc[32]; time_t stamp; @@ -55,4 +55,4 @@ U_BOOT_CMD( "sysid - display Nios-II system id\n\n", "\n - display Nios-II system id\n" ); -#endif /* CFG_NIOS_SYSID_BASE */ +#endif /* CONFIG_SYS_NIOS_SYSID_BASE */ diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index b21b13e..57861b3 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -52,12 +52,12 @@ /* * Set default values */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xFE #endif #define ONE_BILLION 1000000000 @@ -163,7 +163,7 @@ long int spd_sdram(int(read_spd)(uint addr)) * Make sure I2C controller is initialized * before continuing. */ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); } /* Make shure we are using SDRAM */ diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 9efcede..153391e 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -62,12 +62,12 @@ /* * Set default values */ -#ifndef CFG_I2C_SPEED -#define CFG_I2C_SPEED 50000 +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 #endif -#ifndef CFG_I2C_SLAVE -#define CFG_I2C_SLAVE 0xFE +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xFE #endif #define ONE_BILLION 1000000000 @@ -119,7 +119,7 @@ struct bank_param { typedef struct bank_param BANKPARMS; -#ifdef CFG_SIMULATE_SPD_EEPROM +#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM extern const unsigned char cfg_simulate_spd_eeprom[128]; #endif @@ -174,7 +174,7 @@ long int spd_sdram(void) { * Make sure I2C controller is initialized * before continuing. */ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* * Read the SPD information using I2C interface. Check to see if the @@ -265,7 +265,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - ecc_init(CFG_SDRAM_BASE, total_size); + ecc_init(CONFIG_SYS_SDRAM_BASE, total_size); #endif return total_size; @@ -275,14 +275,14 @@ static unsigned char spd_read(uchar chip, uint addr) { unsigned char data[2]; -#ifdef CFG_SIMULATE_SPD_EEPROM - if (chip == CFG_SIMULATE_SPD_EEPROM) { +#ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM + if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) { /* * Onboard spd eeprom requested -> simulate values */ return cfg_simulate_spd_eeprom[addr]; } -#endif /* CFG_SIMULATE_SPD_EEPROM */ +#endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */ if (i2c_probe(chip) == 0) { if (i2c_read(chip, addr, 1, data, 1) == 0) { @@ -1120,7 +1120,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, /* * reset the bank_base address */ - bank_base_addr = CFG_SDRAM_BASE; + bank_base_addr = CONFIG_SYS_SDRAM_BASE; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { if (dimm_populated[dimm_num] == TRUE) { diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f1d7684..30c2e44 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -402,8 +402,8 @@ phys_size_t initdram(int board_type) */ /* switch to correct I2C bus */ - I2C_SET_BUS(CFG_SPD_BUS_NUM); - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ * Clear out the serial presence detect buffers. @@ -2976,62 +2976,62 @@ phys_size_t initdram(int board_type) /* Set Memory Bank Configuration Registers */ - mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF); - mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF); - mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF); - mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF); + mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF); + mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF); + mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF); + mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF); /* Set Memory Clock Timing Register */ - mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR); + mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR); /* Set Refresh Time Register */ - mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR); + mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR); /* Set SDRAM Timing Registers */ - mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1); - mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2); - mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3); + mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1); + mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2); + mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3); /* Set Mode and Extended Mode Registers */ - mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE); - mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE); + mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE); + mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE); /* Set Memory Controller Options 1 Register */ - mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1); + mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1); /* Set Manual Initialization Control Registers */ - mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0); - mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1); - mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2); - mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3); - mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4); - mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5); - mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6); - mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7); - mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8); - mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9); - mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10); - mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11); - mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12); - mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13); - mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14); - mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15); + mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0); + mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1); + mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2); + mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3); + mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4); + mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5); + mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6); + mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7); + mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8); + mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9); + mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10); + mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11); + mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12); + mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13); + mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14); + mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15); /* Set On-Die Termination Registers */ - mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT); - mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0); - mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1); + mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT); + mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0); + mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1); /* Set Write Timing Register */ - mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR); + mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR); /* * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and @@ -3052,12 +3052,12 @@ phys_size_t initdram(int board_type) /* Set Delay Control Registers */ - mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR); + mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR); #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) - mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC); - mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC); - mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC); + mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC); + mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC); + mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC); #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ /* @@ -3077,7 +3077,7 @@ phys_size_t initdram(int board_type) #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ #if defined(CONFIG_DDR_ECC) - ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); + ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* defined(CONFIG_DDR_ECC) */ ppc4xx_ibm_ddr2_register_dump(); @@ -3093,7 +3093,7 @@ phys_size_t initdram(int board_type) #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ - return (CFG_MBYTES_SDRAM << 20); + return (CONFIG_SYS_MBYTES_SDRAM << 20); } #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 6d4d043..d7b16da 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -225,7 +225,7 @@ * Some boards do not have a PHY for each ethernet port. These ports * are known as Fixed PHY (or PHY-less) ports. For such ports, set * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and - * then define CFG_FIXED_PHY_PORTS to define what the speed and + * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and * duplex should be for these ports in the board configuration * file. * @@ -237,20 +237,20 @@ * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY * #define CONFIG_PHY3_ADDR 3 * - * #define CFG_FIXED_PHY_PORT(devnum,speed,duplex) \ + * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ * {devnum, speed, duplex}, * - * #define CFG_FIXED_PHY_PORTS \ - * CFG_FIXED_PHY_PORT(0,1000,FULL) \ - * CFG_FIXED_PHY_PORT(2,100,HALF) + * #define CONFIG_SYS_FIXED_PHY_PORTS \ + * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \ + * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF) */ #ifndef CONFIG_FIXED_PHY #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ #endif -#ifndef CFG_FIXED_PHY_PORTS -#define CFG_FIXED_PHY_PORTS /* default is an empty array */ +#ifndef CONFIG_SYS_FIXED_PHY_PORTS +#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ #endif struct fixed_phy_port { @@ -260,7 +260,7 @@ struct fixed_phy_port { }; static const struct fixed_phy_port fixed_phy_port[] = { - CFG_FIXED_PHY_PORTS /* defined in board configuration file */ + CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ }; /*-----------------------------------------------------------------------------+ @@ -1337,8 +1337,8 @@ get_speed: #ifdef CONFIG_4xx_DCACHE flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); if (!last_used_ea) -#if defined(CFG_MEM_TOP_HIDE) - bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE; +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE; #else bd_uncached = bis->bi_memsize; #endif diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 47ab39b..1e3e20d 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -53,11 +53,11 @@ #define MAXBXCF 4 #define SDRAM_RXBAS_SHIFT_1M 20 -#if defined(CFG_DECREMENT_PATTERNS) +#if defined(CONFIG_SYS_DECREMENT_PATTERNS) #define NUMMEMTESTS 24 #else #define NUMMEMTESTS 8 -#endif /* CFG_DECREMENT_PATTERNS */ +#endif /* CONFIG_SYS_DECREMENT_PATTERNS */ #define NUMLOOPS 1 /* configure as you deem approporiate */ #define NUMMEMWORDS 16 @@ -254,7 +254,7 @@ static int short_mem_test(u32 *base_address) 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}, -#if defined(CFG_DECREMENT_PATTERNS) +#if defined(CONFIG_SYS_DECREMENT_PATTERNS) /* 8 */ {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, @@ -319,7 +319,7 @@ static int short_mem_test(u32 *base_address) 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fffe, 0xfff0fff0, 0xfff0fff0}, -#endif /* CFG_DECREMENT_PATTERNS */ +#endif /* CONFIG_SYS_DECREMENT_PATTERNS */ }; mfsdram(SDRAM_MCOPT1, ecc_mode); diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index c28c7ac..eca92e8 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -108,12 +108,12 @@ void pci_405gp_init(struct pci_controller *hose) bd_t *bd = gd->bd; unsigned short temp_short; - unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; + unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI}; #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) char *ptmla_str, *ptmms_str; #endif - unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; - unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; + unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; + unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS}; #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; @@ -268,22 +268,22 @@ void pci_405gp_init(struct pci_controller *hose) /* * Insert Subsystem Vendor and Device ID */ - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID); #ifdef CONFIG_CPCI405 if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2); #else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); #endif /* * Insert Class-code */ -#ifdef CFG_PCI_CLASSCODE - pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); -#endif /* CFG_PCI_CLASSCODE */ +#ifdef CONFIG_SYS_PCI_CLASSCODE + pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE); +#endif /* CONFIG_SYS_PCI_CLASSCODE */ /*--------------------------------------------------------------------------+ * If PCI speed = 66Mhz, set 66Mhz capable bit. @@ -405,8 +405,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, */ static struct pci_config_table pci_405gp_config_table[] = { /*if VendID is 0 it terminates the table search (ie Walnut)*/ -#ifdef CFG_PCI_SUBSYS_VENDORID - {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, +#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID + {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, #endif {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, @@ -488,10 +488,10 @@ int pci_440_init (struct pci_controller *hose) /* PCI memory space */ pci_set_region(hose->regions + reg_num++, - CFG_PCI_TARGBASE, - CFG_PCI_MEMBASE, -#ifdef CFG_PCI_MEMSIZE - CFG_PCI_MEMSIZE, + CONFIG_SYS_PCI_TARGBASE, + CONFIG_SYS_PCI_MEMBASE, +#ifdef CONFIG_SYS_PCI_MEMSIZE + CONFIG_SYS_PCI_MEMSIZE, #else 0x10000000, #endif @@ -523,11 +523,11 @@ int pci_440_init (struct pci_controller *hose) /*--------------------------------------------------------------------------+ * PCI target init *--------------------------------------------------------------------------*/ -#if defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_SYS_PCI_TARGET_INIT) pci_target_init(hose); /* Let board setup pci target */ #else - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif @@ -542,9 +542,9 @@ int pci_440_init (struct pci_controller *hose) /*--------------------------------------------------------------------------+ * PCI master init: default is one 256MB region for PCI memory: - * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE + * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE *--------------------------------------------------------------------------*/ -#if defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_SYS_PCI_MASTER_INIT) pci_master_init(hose); /* Let board setup pci master */ #else out32r( PCIX0_POM0SA, 0 ); /* disable */ @@ -558,7 +558,7 @@ int pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); #endif - out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); + out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 0aadc06..fd40d8a 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -49,12 +49,12 @@ enum { static int validate_endpoint(struct pci_controller *hose) { - if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE) + if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE) return (is_end_point(0)); - else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE) + else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE) return (is_end_point(1)); -#if CFG_PCIE_NR_PORTS > 2 - else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE) +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE) return (is_end_point(2)); #endif @@ -67,13 +67,13 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) /* use local configuration space for the first bus */ if (PCI_BUS(devfn) == 0) { - if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) - base = (u8*)CFG_PCIE0_XCFGBASE; - if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) - base = (u8*)CFG_PCIE1_XCFGBASE; -#if CFG_PCIE_NR_PORTS > 2 - if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) - base = (u8*)CFG_PCIE2_XCFGBASE; + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE; #endif } @@ -86,7 +86,7 @@ static void pcie_dmer_disable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); #endif @@ -98,7 +98,7 @@ static void pcie_dmer_enable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); #endif @@ -286,7 +286,7 @@ static void ppc4xx_setup_utl(u32 port) { mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); break; } - utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); + utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); /* * Set buffer allocations and then assert VRB and TXE. @@ -412,21 +412,21 @@ static void ppc4xx_setup_utl(u32 port) */ switch (port) { case 0: - mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE)); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)); mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); break; case 1: - mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CFG_PCIE0_UTLBASE)); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CFG_PCIE0_UTLBASE) + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE) + 0x1000); mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); break; } - utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); + utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); /* * Set buffer allocations and then assert VRB and TXE. @@ -512,20 +512,20 @@ static void ppc4xx_setup_utl(u32 port) switch (port) { case 0: mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); - mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE); mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); break; case 1: mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); - mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE); mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); break; } - utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE; + utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE; /* * Set buffer allocations and then assert VRB and TXE. @@ -761,9 +761,9 @@ static inline u64 ppc4xx_get_cfgaddr(int port) { #if defined(CONFIG_405EX) if (port == 0) - return (u64)CFG_PCIE0_CFGBASE; + return (u64)CONFIG_SYS_PCIE0_CFGBASE; else - return (u64)CFG_PCIE1_CFGBASE; + return (u64)CONFIG_SYS_PCIE1_CFGBASE; #endif #if defined(CONFIG_440SPE) if (ppc440spe_revB()) { @@ -895,7 +895,7 @@ int ppc4xx_init_pcie_port(int port, int rootport) mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ break; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); @@ -947,20 +947,20 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) switch (port) { case 0: - mbase = (u32 *)CFG_PCIE0_XCFGBASE; - rmbase = (u32 *)CFG_PCIE0_CFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; break; case 1: - mbase = (u32 *)CFG_PCIE1_XCFGBASE; - rmbase = (u32 *)CFG_PCIE1_CFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; break; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: - mbase = (u32 *)CFG_PCIE2_XCFGBASE; - rmbase = (u32 *)CFG_PCIE2_CFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; break; #endif } @@ -979,19 +979,19 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00000000); - out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), in_le32(mbase + PECFG_POM0LAL)); switch (port) { case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), @@ -999,26 +999,26 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); break; case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); break; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), @@ -1072,17 +1072,17 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) switch (port) { case 0: - mbase = (u32 *)CFG_PCIE0_XCFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; break; case 1: - mbase = (u32 *)CFG_PCIE1_XCFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; break; -#if defined(CFG_PCIE2_CFGBASE) +#if defined(CONFIG_SYS_PCIE2_CFGBASE) case 2: - mbase = (u32 *)CFG_PCIE2_XCFGBASE; - hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; break; #endif } @@ -1098,29 +1098,29 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) switch (port) { case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); break; case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); break; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); break; #endif } @@ -1141,8 +1141,8 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) out_le32(mbase + PECFG_BAR2HMPA, 0); out_le32(mbase + PECFG_BAR2LMPA, 0); - out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE)); - out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE)); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index 766e586..c106ac2 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -66,20 +66,20 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART0_BASE (CFG_PERIPHERAL_BASE + 0x00000300) -#define UART1_BASE (CFG_PERIPHERAL_BASE + 0x00000400) +#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300) +#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400) #else -#define UART0_BASE (CFG_PERIPHERAL_BASE + 0x00000200) -#define UART1_BASE (CFG_PERIPHERAL_BASE + 0x00000300) +#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200) +#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300) #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE (CFG_PERIPHERAL_BASE + 0x00000600) +#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600) #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART2_BASE (CFG_PERIPHERAL_BASE + 0x00000500) -#define UART3_BASE (CFG_PERIPHERAL_BASE + 0x00000600) +#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500) +#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600) #endif #if defined(CONFIG_440GP) @@ -147,7 +147,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ACTING_UART1_BASE UART1_BASE #endif -#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) +#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK) #error "External serial clock not supported on AMCC PPC405EP!" #endif @@ -199,8 +199,8 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv) /* Correct UART frequency in bd-info struct now that * the UART divisor is available */ -#ifdef CFG_EXT_SERIAL_CLOCK - gd->uart_clk = CFG_EXT_SERIAL_CLOCK; +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; #else gd->uart_clk = sys_info.freqUART / udiv; #endif @@ -218,7 +218,7 @@ static void serial_init_common(u32 base, u32 udiv, u16 bdiv) } #if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ - !defined(CFG_EXT_SERIAL_CLOCK) + !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) { @@ -315,7 +315,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv, mtcpr(cprperd0, reg); *pbdiv = div / udiv; } -#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ +#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ /* * Minimal serial functions needed to use one of the SMC ports @@ -328,18 +328,18 @@ int serial_init_dev(unsigned long base) unsigned long reg; unsigned long udiv; unsigned short bdiv; -#ifdef CFG_EXT_SERIAL_CLOCK +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK unsigned long tmp; #endif MFREG(UART0_SDR, reg); reg &= ~CR0_MASK; -#ifdef CFG_EXT_SERIAL_CLOCK +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; tmp = gd->baudrate * 16; - bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; + bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; #else /* For 440, the cpu clock is on divider chain A, UART on divider * chain B ... so cpu clock is irrelevant. Get the "optimized" @@ -384,11 +384,11 @@ int serial_init_dev (unsigned long base) clk = tmp = 0; mfsdr(UART0_SDR, reg); reg &= ~CR0_MASK; -#ifdef CFG_EXT_SERIAL_CLOCK +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; tmp = gd->baudrate * 16; - bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; + bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; #else serial_divs(gd->baudrate, &udiv, &bdiv); #endif @@ -411,7 +411,7 @@ int serial_init_dev (unsigned long base) #ifdef CONFIG_405EP reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; - tmp = CFG_BASE_BAUD * 16; + tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; if (udiv > UDIV_MAX) /* max. n bits for udiv */ udiv = UDIV_MAX; @@ -420,16 +420,16 @@ int serial_init_dev (unsigned long base) mtdcr (cpc0_ucr, reg); #else /* CONFIG_405EP */ reg = mfdcr(cntrl0) & ~CR0_MASK; -#ifdef CFG_EXT_SERIAL_CLOCK - clk = CFG_EXT_SERIAL_CLOCK; +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; reg |= CR0_EXTCLK_ENA; #else clk = gd->cpu_clk; -#ifdef CFG_405_UART_ERRATA_59 +#ifdef CONFIG_SYS_405_UART_ERRATA_59 udiv = 31; /* Errata 59: stuck at 31 */ #else - tmp = CFG_BASE_BAUD * 16; + tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; if (udiv > UDIV_MAX) /* max. n bits for udiv */ udiv = UDIV_MAX; diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S index ceb3ec0..269716f 100644 --- a/cpu/ppc4xx/cache.S +++ b/cpu/ppc4xx/cache.S @@ -143,8 +143,8 @@ _GLOBAL(flush_dcache) _GLOBAL(invalidate_dcache) addi r6,0,0x0000 /* clear GPR 6 */ /* Do loop for # of dcache congruence classes. */ - lis r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */ - ori r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l + lis r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */ + ori r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l /* NOTE: dccci invalidates both */ mtctr r7 /* ways in the D cache */ ..dcloop: diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c index 8b2954c..a1696d3 100644 --- a/cpu/ppc4xx/commproc.c +++ b/cpu/ppc4xx/commproc.c @@ -30,10 +30,10 @@ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#if defined(CFG_POST_WORD_ADDR) -# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR)) -#elif defined(CFG_POST_ALT_WORD_ADDR) -# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR) +#if defined(CONFIG_SYS_POST_WORD_ADDR) +# define _POST_ADDR ((CONFIG_SYS_OCM_DATA_ADDR) + (CONFIG_SYS_POST_WORD_ADDR)) +#elif defined(CONFIG_SYS_POST_ALT_WORD_ADDR) +# define _POST_ADDR (CONFIG_SYS_POST_ALT_WORD_ADDR) #endif void post_word_store (ulong a) @@ -57,7 +57,7 @@ ulong post_word_load (void) void bootcount_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR); + (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR); save_addr[0] = a; save_addr[1] = BOOTCOUNT_MAGIC; @@ -66,7 +66,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_OCM_DATA_ADDR + CFG_BOOTCOUNT_ADDR); + (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR); if (save_addr[1] != BOOTCOUNT_MAGIC) return 0; diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index bc9335a..66a7737 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -629,14 +629,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_BOARD_RESET) board_reset(); #else -#if defined(CFG_4xx_RESET_TYPE) - mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); +#if defined(CONFIG_SYS_4xx_RESET_TYPE) + mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28); #else /* * Initiate system reset in debug control register DBCR */ mtspr(dbcr0, 0x30000000); -#endif /* defined(CFG_4xx_RESET_TYPE) */ +#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */ #endif /* defined(CONFIG_BOARD_RESET) */ return 1; diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index dee9807..b5d81f2 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -32,8 +32,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#ifndef CFG_PLL_RECONFIG -#define CFG_PLL_RECONFIG 0 +#ifndef CONFIG_SYS_PLL_RECONFIG +#define CONFIG_SYS_PLL_RECONFIG 0 #endif void reconfigure_pll(u32 new_cpu_freq) @@ -142,32 +142,32 @@ cpu_init_f (void) u32 val; #endif - reconfigure_pll(CFG_PLL_RECONFIG); + reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ -#if defined(CFG_GPIO0_OR) - out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */ +#if defined(CONFIG_SYS_GPIO0_OR) + out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */ #endif -#if defined(CFG_GPIO0_ODR) - out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */ +#if defined(CONFIG_SYS_GPIO0_ODR) + out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */ #endif - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ - out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ - out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TSRL, CFG_GPIO0_TSRL); -#if defined(CFG_GPIO0_ISR2H) - out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H); - out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L); + out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ + out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); + out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); + out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); +#if defined(CONFIG_SYS_GPIO0_ISR2H) + out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H); + out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L); #endif -#if defined (CFG_GPIO0_TCR) - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ +#if defined (CONFIG_SYS_GPIO0_TCR) + out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ #endif -#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */ +#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */ #if defined (CONFIG_405EP) /* @@ -181,14 +181,14 @@ cpu_init_f (void) mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ -#if defined(CFG_4xx_GPIO_TABLE) +#if defined(CONFIG_SYS_4xx_GPIO_TABLE) gpio_set_chip_configuration(); -#endif /* CFG_4xx_GPIO_TABLE */ +#endif /* CONFIG_SYS_4xx_GPIO_TABLE */ /* * External Bus Controller (EBC) Setup */ -#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405)) @@ -209,47 +209,47 @@ cpu_init_f (void) asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); #endif - mtebc(pb0ap, CFG_EBC_PB0AP); - mtebc(pb0cr, CFG_EBC_PB0CR); + mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); + mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); #endif -#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1)) - mtebc(pb1ap, CFG_EBC_PB1AP); - mtebc(pb1cr, CFG_EBC_PB1CR); +#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) + mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP); + mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR); #endif -#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2)) - mtebc(pb2ap, CFG_EBC_PB2AP); - mtebc(pb2cr, CFG_EBC_PB2CR); +#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) + mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP); + mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR); #endif -#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3)) - mtebc(pb3ap, CFG_EBC_PB3AP); - mtebc(pb3cr, CFG_EBC_PB3CR); +#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) + mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); + mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); #endif -#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, CFG_EBC_PB4AP); - mtebc(pb4cr, CFG_EBC_PB4CR); +#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) + mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP); + mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR); #endif -#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5)) - mtebc(pb5ap, CFG_EBC_PB5AP); - mtebc(pb5cr, CFG_EBC_PB5CR); +#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) + mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP); + mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR); #endif -#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6)) - mtebc(pb6ap, CFG_EBC_PB6AP); - mtebc(pb6cr, CFG_EBC_PB6CR); +#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) + mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP); + mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR); #endif -#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7)) - mtebc(pb7ap, CFG_EBC_PB7AP); - mtebc(pb7cr, CFG_EBC_PB7CR); +#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) + mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP); + mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR); #endif -#if defined (CFG_EBC_CFG) - mtebc(EBC0_CFG, CFG_EBC_CFG); +#if defined (CONFIG_SYS_EBC_CFG) + mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG); #endif #if defined(CONFIG_WATCHDOG) @@ -261,9 +261,9 @@ cpu_init_f (void) #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ #endif -#if defined(CFG_4xx_RESET_TYPE) +#if defined(CONFIG_SYS_4xx_RESET_TYPE) val &= ~0x30000000; /* clear WRC bits */ - val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ + val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ #endif mtspr(tcr, val); diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c index 967e61b..ffc3817 100644 --- a/cpu/ppc4xx/denali_data_eye.c +++ b/cpu/ppc4xx/denali_data_eye.c @@ -127,7 +127,7 @@ void denali_core_search_data_eye(void) 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); + ram_pointer = (volatile u32 *)(CONFIG_SYS_SDRAM_BASE); for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { /* for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) { */ diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 670fc5c..4705e21 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1048,8 +1048,8 @@ phys_size_t initdram(int board_type) * before continuing. */ /* switch to correct I2C bus */ - I2C_SET_BUS(CFG_SPD_BUS_NUM); - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ * Clear out the serial presence detect buffers. @@ -1185,27 +1185,27 @@ phys_size_t initdram(int board_type) * Map the first 1 MiB of memory in the TLB, and perform the data eye * search. */ - program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); + program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); denali_sdram_register_dump(); - remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE); + remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE); #endif #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) - program_tlb(0, CFG_SDRAM_BASE, dram_size, 0); + program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0); sync(); /* Zero the memory */ debug("Zeroing SDRAM..."); -#if defined(CFG_MEM_TOP_HIDE) - dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE); +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE); #else -#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file +#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file #endif /* Write modified dcache lines back to memory */ - clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE); + clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE); debug("Completed\n"); sync(); - remove_tlb(CFG_SDRAM_BASE, dram_size); + remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size); #if defined(CONFIG_DDR_ECC) /* @@ -1236,7 +1236,7 @@ phys_size_t initdram(int board_type) #endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ - program_tlb(0, CFG_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); + program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); return dram_size; } diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c index a2eb07b..3f989e7 100644 --- a/cpu/ppc4xx/ecc.c +++ b/cpu/ppc4xx/ecc.c @@ -68,7 +68,7 @@ * * Output(s): * start - A pointer to the start of memory covered by ECC with - * CFG_ECC_PATTERN written to all locations and ECC data + * CONFIG_SYS_ECC_PATTERN written to all locations and ECC data * primed. * * Returns: @@ -76,7 +76,7 @@ */ void ecc_init(unsigned long * const start, unsigned long size) { - const unsigned long pattern = CFG_ECC_PATTERN; + const unsigned long pattern = CONFIG_SYS_ECC_PATTERN; unsigned long * const end = (unsigned long * const)((long)start + size); unsigned long * current = start; unsigned long mcopt1; diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h index aecf291..67c3bff 100644 --- a/cpu/ppc4xx/ecc.h +++ b/cpu/ppc4xx/ecc.h @@ -33,9 +33,9 @@ #ifndef _ECC_H_ #define _ECC_H_ -#if !defined(CFG_ECC_PATTERN) -#define CFG_ECC_PATTERN 0x00000000 -#endif /* !defined(CFG_ECC_PATTERN) */ +#if !defined(CONFIG_SYS_ECC_PATTERN) +#define CONFIG_SYS_ECC_PATTERN 0x00000000 +#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */ /* * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index df99f53..c0d351a 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -26,8 +26,8 @@ #include #include -#if defined(CFG_4xx_GPIO_TABLE) -gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE; +#if defined(CONFIG_SYS_4xx_GPIO_TABLE) +gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE; #endif #if defined(GPIO0_OSRL) @@ -132,7 +132,7 @@ int gpio_read_in_bit(int pin) return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0); } -#if defined(CFG_4xx_GPIO_TABLE) +#if defined(CONFIG_SYS_4xx_GPIO_TABLE) void gpio_set_chip_configuration(void) { unsigned char i=0, j=0, offs=0, gpio_core; @@ -252,4 +252,4 @@ void gpio_set_chip_configuration(void) } } } -#endif /* CFG_4xx_GPIO_TABLE */ +#endif /* CONFIG_SYS_4xx_GPIO_TABLE */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index d8be2ce..0deb149 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -42,8 +42,8 @@ DECLARE_GLOBAL_DATA_PTR; * runs from ROM, and we can't switch buses because we can't modify * the global variables. */ -#ifdef CFG_SPD_BUS_NUM -static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; +#ifdef CONFIG_SYS_SPD_BUS_NUM +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CONFIG_SYS_SPD_BUS_NUM; #else static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; #endif @@ -95,14 +95,14 @@ void i2c_init(int speed, int slaveadd) int val, divisor; int bus; -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ i2c_init_board(); #endif - for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) { + for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) { I2C_SET_BUS(bus); /* Handle possible failed I2C state */ @@ -161,7 +161,7 @@ void i2c_init(int speed, int slaveadd) } /* set to SPD bus as default bus upon powerup */ - I2C_SET_BUS(CFG_SPD_BUS_NUM); + I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); } /* @@ -361,7 +361,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -374,7 +374,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if (alen > 0) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) { if (gd->have_console) @@ -401,7 +401,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) xaddr[3] = addr & 0xFF; } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -414,7 +414,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if (alen > 0) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); @@ -451,7 +451,7 @@ unsigned int i2c_get_bus_num(void) int i2c_set_bus_num(unsigned int bus) { - if (bus >= CFG_MAX_I2C_BUS) + if (bus >= CONFIG_SYS_MAX_I2C_BUS) return -1; i2c_bus_num = bus; @@ -463,12 +463,12 @@ int i2c_set_bus_num(unsigned int bus) /* TODO: add 100/400k switching */ unsigned int i2c_get_bus_speed(void) { - return CFG_I2C_SPEED; + return CONFIG_SYS_I2C_SPEED; } int i2c_set_bus_speed(unsigned int speed) { - if (speed != CFG_I2C_SPEED) + if (speed != CONFIG_SYS_I2C_SPEED) return -1; return 0; diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 7d96e79..3a5af12 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -149,8 +149,8 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len } #endif /* #ifndef CONFIG_NAND_SPL */ -#ifndef CFG_NAND_BCR -#define CFG_NAND_BCR 0x80002222 +#ifndef CONFIG_SYS_NAND_BCR +#define CONFIG_SYS_NAND_BCR 0x80002222 #endif void board_nand_select_device(struct nand_chip *nand, int chip) @@ -165,7 +165,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip) /* Set NandFlash Core Configuration Register */ /* 1 col x 2 rows */ out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); - out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CFG_NAND_BCR); + out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR); } static void ndfc_select_chip(struct mtd_info *mtd, int chip) @@ -214,8 +214,8 @@ int board_nand_init(struct nand_chip *nand) */ mtebc(EBC0_CFG, 0xb8400000); - mtebc(pb0cr, CFG_EBC_PB0CR); - mtebc(pb0ap, CFG_EBC_PB0AP); + mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); + mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); #endif chip++; diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index b5a6a4c..6d5f8d6 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -37,7 +37,7 @@ #ifndef CONFIG_440 -#ifndef CFG_SDRAM_TABLE +#ifndef CONFIG_SYS_SDRAM_TABLE sdram_conf_t mb0cf[] = { {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ @@ -46,72 +46,72 @@ sdram_conf_t mb0cf[] = { {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ }; #else -sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; +sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #endif #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) -#ifdef CFG_SDRAM_CASL +#ifdef CONFIG_SYS_SDRAM_CASL static ulong ns2clks(ulong ns) { ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10); return ((ns * 10) + bus_period_x_10) / bus_period_x_10; } -#endif /* CFG_SDRAM_CASL */ +#endif /* CONFIG_SYS_SDRAM_CASL */ static ulong compute_sdtr1(ulong speed) { -#ifdef CFG_SDRAM_CASL +#ifdef CONFIG_SYS_SDRAM_CASL ulong tmp; ulong sdtr1 = 0; /* CASL */ - if (CFG_SDRAM_CASL < 2) + if (CONFIG_SYS_SDRAM_CASL < 2) sdtr1 |= (1 << SDRAM0_TR_CASL); else - if (CFG_SDRAM_CASL > 4) + if (CONFIG_SYS_SDRAM_CASL > 4) sdtr1 |= (3 << SDRAM0_TR_CASL); else - sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL); + sdtr1 |= ((CONFIG_SYS_SDRAM_CASL-1) << SDRAM0_TR_CASL); /* PTA */ - tmp = ns2clks(CFG_SDRAM_PTA); + tmp = ns2clks(CONFIG_SYS_SDRAM_PTA); if ((tmp >= 2) && (tmp <= 4)) sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA); else sdtr1 |= ((4-1) << SDRAM0_TR_PTA); /* CTP */ - tmp = ns2clks(CFG_SDRAM_CTP); + tmp = ns2clks(CONFIG_SYS_SDRAM_CTP); if ((tmp >= 2) && (tmp <= 4)) sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP); else sdtr1 |= ((4-1) << SDRAM0_TR_CTP); /* LDF */ - tmp = ns2clks(CFG_SDRAM_LDF); + tmp = ns2clks(CONFIG_SYS_SDRAM_LDF); if ((tmp >= 2) && (tmp <= 4)) sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF); else sdtr1 |= ((2-1) << SDRAM0_TR_LDF); /* RFTA */ - tmp = ns2clks(CFG_SDRAM_RFTA); + tmp = ns2clks(CONFIG_SYS_SDRAM_RFTA); if ((tmp >= 4) && (tmp <= 10)) sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA); else sdtr1 |= ((10-4) << SDRAM0_TR_RFTA); /* RCD */ - tmp = ns2clks(CFG_SDRAM_RCD); + tmp = ns2clks(CONFIG_SYS_SDRAM_RCD); if ((tmp >= 2) && (tmp <= 4)) sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD); else sdtr1 |= ((4-1) << SDRAM0_TR_RCD); return sdtr1; -#else /* CFG_SDRAM_CASL */ +#else /* CONFIG_SYS_SDRAM_CASL */ /* * If no values are configured in the board config file * use the default values, which seem to be ok for most @@ -133,20 +133,20 @@ static ulong compute_sdtr1(ulong speed) */ return 0x0086400d; } -#endif /* CFG_SDRAM_CASL */ +#endif /* CONFIG_SYS_SDRAM_CASL */ } /* refresh is expressed in ms */ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) { -#ifdef CFG_SDRAM_CASL +#ifdef CONFIG_SYS_SDRAM_CASL ulong tmp; tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000); tmp /= 1000000; return ((tmp & 0x00003FF8) << 16); -#else /* CFG_SDRAM_CASL */ +#else /* CONFIG_SYS_SDRAM_CASL */ if (speed > 100000000) { /* * 133 MHz SDRAM @@ -158,7 +158,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) */ return 0x05f00000; } -#endif /* CFG_SDRAM_CASL */ +#endif /* CONFIG_SYS_SDRAM_CASL */ } /* @@ -256,17 +256,17 @@ phys_size_t initdram(int board_type) * board config file. */ -#ifndef CFG_SDRAM_TABLE +#ifndef CONFIG_SYS_SDRAM_TABLE sdram_conf_t mb0cf[] = { {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */ {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */ }; #else -sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; +sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #endif -#ifndef CFG_SDRAM0_TR0 -#define CFG_SDRAM0_TR0 0x41094012 +#ifndef CONFIG_SYS_SDRAM0_TR0 +#define CONFIG_SYS_SDRAM0_TR0 0x41094012 #endif #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) @@ -385,7 +385,7 @@ phys_size_t initdram(int board_type) * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(mem_b0cr, mb0cf[i].reg); - mtsdram(mem_tr0, CFG_SDRAM0_TR0); + mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h index 4fb9b1a..bea3376 100644 --- a/cpu/ppc4xx/sdram.h +++ b/cpu/ppc4xx/sdram.h @@ -47,19 +47,19 @@ typedef struct sdram_conf_s sdram_conf_t; #define SDRAM0_TR_RFTA (31 - 29) #define SDRAM0_TR_RCD (31 - 31) -#ifdef CFG_SDRAM_CL +#ifdef CONFIG_SYS_SDRAM_CL /* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */ -#define CFG_SDRAM_CASL CFG_SDRAM_CL -#define CFG_SDRAM_PTA CFG_SDRAM_tRP -#define CFG_SDRAM_CTP (CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP) -#define CFG_SDRAM_LDF 0 -#ifdef CFG_SDRAM_tRFC -#define CFG_SDRAM_RFTA CFG_SDRAM_tRFC +#define CONFIG_SYS_SDRAM_CASL CONFIG_SYS_SDRAM_CL +#define CONFIG_SYS_SDRAM_PTA CONFIG_SYS_SDRAM_tRP +#define CONFIG_SYS_SDRAM_CTP (CONFIG_SYS_SDRAM_tRC - CONFIG_SYS_SDRAM_tRCD - CONFIG_SYS_SDRAM_tRP) +#define CONFIG_SYS_SDRAM_LDF 0 +#ifdef CONFIG_SYS_SDRAM_tRFC +#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRFC #else -#define CFG_SDRAM_RFTA CFG_SDRAM_tRC +#define CONFIG_SYS_SDRAM_RFTA CONFIG_SYS_SDRAM_tRC #endif -#define CFG_SDRAM_RCD CFG_SDRAM_tRCD -#endif /* #ifdef CFG_SDRAM_CL */ +#define CONFIG_SYS_SDRAM_RCD CONFIG_SYS_SDRAM_tRCD +#endif /* #ifdef CONFIG_SYS_SDRAM_CL */ /* * Some defines for the 440 DDR controller diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 97411bd..31902a0 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -77,69 +77,69 @@ #define CONFIG_IDENT_STRING "" #endif -#ifdef CFG_INIT_DCACHE_CS -# if (CFG_INIT_DCACHE_CS == 0) +#ifdef CONFIG_SYS_INIT_DCACHE_CS +# if (CONFIG_SYS_INIT_DCACHE_CS == 0) # define PBxAP pb0ap # define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR +# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 1) +# if (CONFIG_SYS_INIT_DCACHE_CS == 1) # define PBxAP pb1ap # define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR +# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 2) +# if (CONFIG_SYS_INIT_DCACHE_CS == 2) # define PBxAP pb2ap # define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR +# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 3) +# if (CONFIG_SYS_INIT_DCACHE_CS == 3) # define PBxAP pb3ap # define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR +# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 4) +# if (CONFIG_SYS_INIT_DCACHE_CS == 4) # define PBxAP pb4ap # define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR +# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 5) +# if (CONFIG_SYS_INIT_DCACHE_CS == 5) # define PBxAP pb5ap # define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR +# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 6) +# if (CONFIG_SYS_INIT_DCACHE_CS == 6) # define PBxAP pb6ap # define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR +# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR # endif # endif -# if (CFG_INIT_DCACHE_CS == 7) +# if (CONFIG_SYS_INIT_DCACHE_CS == 7) # define PBxAP pb7ap # define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR +# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) +# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP +# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR # endif # endif # ifndef PBxAP_VAL @@ -149,11 +149,11 @@ # define PBxCR_VAL 0 # endif /* - * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB + * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB * used as temporary stack pointer for the primordial stack */ -# ifndef CFG_INIT_DCACHE_PBxAR -# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ +# ifndef CONFIG_SYS_INIT_DCACHE_PBxAR +# define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(7) | \ EBC_BXAP_BCE_DISABLE | \ EBC_BXAP_BCT_2TRANS | \ @@ -166,42 +166,42 @@ EBC_BXAP_SOR_NONDELAYED | \ EBC_BXAP_BEM_WRITEONLY | \ EBC_BXAP_PEN_DISABLED) -# endif /* CFG_INIT_DCACHE_PBxAR */ -# ifndef CFG_INIT_DCACHE_PBxCR -# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ +# endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ +# ifndef CONFIG_SYS_INIT_DCACHE_PBxCR +# define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ EBC_BXCR_BS_64MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_16BIT) -# endif /* CFG_INIT_DCACHE_PBxCR */ -# ifndef CFG_INIT_RAM_PATTERN -# define CFG_INIT_RAM_PATTERN 0xDEADDEAD +# endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ +# ifndef CONFIG_SYS_INIT_RAM_PATTERN +# define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD # endif -#endif /* CFG_INIT_DCACHE_CS */ +#endif /* CONFIG_SYS_INIT_DCACHE_CS */ -#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) -#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! +#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10))) +#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END! #endif /* * Unless otherwise overriden, enable two 128MB cachable instruction regions - * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering - * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. + * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering + * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. */ -#if !defined(CFG_FLASH_BASE) +#if !defined(CONFIG_SYS_FLASH_BASE) /* If not already defined, set it to the "last" 128MByte region */ -# define CFG_FLASH_BASE 0xf8000000 +# define CONFIG_SYS_FLASH_BASE 0xf8000000 #endif -#if !defined(CFG_ICACHE_SACR_VALUE) -# define CFG_ICACHE_SACR_VALUE \ - (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ - PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \ - PPC_128MB_SACR_VALUE(CFG_FLASH_BASE)) -#endif /* !defined(CFG_ICACHE_SACR_VALUE) */ - -#if !defined(CFG_DCACHE_SACR_VALUE) -# define CFG_DCACHE_SACR_VALUE \ +#if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) +# define CONFIG_SYS_ICACHE_SACR_VALUE \ + (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ + PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ + PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) +#endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ + +#if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) +# define CONFIG_SYS_DCACHE_SACR_VALUE \ (0x00000000) -#endif /* !defined(CFG_DCACHE_SACR_VALUE) */ +#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ #define function_prolog(func_name) .text; \ .align 2; \ @@ -609,15 +609,15 @@ _start: /*----------------------------------------------------------------*/ /* Debug setup -- some (not very good) ice's need an event*/ - /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */ + /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ /* value you need in this case 0x8cff 0000 should do the trick */ /*----------------------------------------------------------------*/ -#if defined(CFG_INIT_DBCR) +#if defined(CONFIG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr dbsr,r1 /* Clear all status bits */ - lis r0,CFG_INIT_DBCR@h - ori r0,r0,CFG_INIT_DBCR@l + lis r0,CONFIG_SYS_INIT_DBCR@h + ori r0,r0,CONFIG_SYS_INIT_DBCR@l mtspr dbcr0,r0 isync #endif @@ -627,12 +627,12 @@ _start: /*----------------------------------------------------------------*/ li r0,0 -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* Clear Dcache to use as RAM */ - addis r3,r0,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - addis r4,r0,CFG_INIT_RAM_END@h - ori r4,r4,CFG_INIT_RAM_END@l + addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + addis r4,r0,CONFIG_SYS_INIT_RAM_END@h + ori r4,r4,CONFIG_SYS_INIT_RAM_END@l rlwinm. r5,r4,0,27,31 rlwinm r5,r4,27,5,31 beq ..d_ran @@ -670,7 +670,7 @@ _start: mtspr dtv3,r1 msync isync -#endif /* CFG_INIT_RAM_DCACHE */ +#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* 440EP & 440GR are only 440er PPC's without internal SRAM */ #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) @@ -744,8 +744,8 @@ _start: /*----------------------------------------------------------------*/ /* Setup the stack in internal SRAM */ /*----------------------------------------------------------------*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + lis r1,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l li r0,0 stwu r0,-4(r1) stwu r0,-4(r1) /* Terminate call chain */ @@ -852,18 +852,18 @@ _start: sync /* Set-up icache cacheability. */ - lis r1, CFG_ICACHE_SACR_VALUE@h - ori r1, r1, CFG_ICACHE_SACR_VALUE@l + lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h + ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l mticcr r1 isync /* Set-up dcache cacheability. */ - lis r1, CFG_DCACHE_SACR_VALUE@h - ori r1, r1, CFG_DCACHE_SACR_VALUE@l + lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h + ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l mtdccr r1 - addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -908,31 +908,31 @@ _start: bl invalidate_dcache /* Set-up icache cacheability. */ - lis r4, CFG_ICACHE_SACR_VALUE@h - ori r4, r4, CFG_ICACHE_SACR_VALUE@l + lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h + ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l mticcr r4 isync /* Set-up dcache cacheability. */ - lis r4, CFG_DCACHE_SACR_VALUE@h - ori r4, r4, CFG_DCACHE_SACR_VALUE@l + lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h + ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l mtdccr r4 -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ bl ext_bus_cntlr_init #endif -#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) +#if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) /* * For boards that don't have OCM and can't use the data cache * for their primordial stack, setup stack here directly after the * SDRAM is initialized in ext_bus_cntlr_init. */ - lis r1, CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + lis r1, CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -946,7 +946,7 @@ _start: ori r0, r0, RESET_VECTOR@l stwu r1, -8(r1) /* Save back chain and move SP */ stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ +#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ #if defined(CONFIG_405EP) /*----------------------------------------------------------------------- */ @@ -959,25 +959,25 @@ _start: bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ -#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) +#if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) #if defined(CONFIG_405EZ) /******************************************************************** * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 *******************************************************************/ /* * We can map the OCM on the PLB3, so map it at - * CFG_OCM_DATA_ADDR + 0x8000 + * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 */ - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CFG_OCM_DATA_ADDR@l + lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ mtdcr ocmplb3cr1,r3 /* Set PLB Access */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ mtdcr ocmplb3cr2,r3 /* Set PLB Access */ isync - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CFG_OCM_DATA_ADDR@l + lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ mtdcr ocmdscr1, r3 /* Set Data Side */ mtdcr ocmiscr1, r3 /* Set Instruction Side */ @@ -1003,8 +1003,8 @@ _start: mtdcr ocmdscntl, r4 /* set data-side IRAM config */ isync - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CFG_OCM_DATA_ADDR@l + lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l mtdcr ocmdsarc, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 @@ -1015,26 +1015,26 @@ _start: /*----------------------------------------------------------------------- */ /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ -#ifdef CFG_INIT_DCACHE_CS +#ifdef CONFIG_SYS_INIT_DCACHE_CS li r4, PBxAP mtdcr ebccfga, r4 - lis r4, CFG_INIT_DCACHE_PBxAR@h - ori r4, r4, CFG_INIT_DCACHE_PBxAR@l + lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h + ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l mtdcr ebccfgd, r4 addi r4, 0, PBxCR mtdcr ebccfga, r4 - lis r4, CFG_INIT_DCACHE_PBxCR@h - ori r4, r4, CFG_INIT_DCACHE_PBxCR@l + lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h + ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l mtdcr ebccfgd, r4 /* * Enable the data cache for the 128MB storage access control region - * at CFG_INIT_RAM_ADDR. + * at CONFIG_SYS_INIT_RAM_ADDR. */ mfdccr r4 - oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h - ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l mtdccr r4 /* @@ -1044,11 +1044,11 @@ _start: */ li r0, 0 - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - lis r4, CFG_INIT_RAM_END@h - ori r4, r4, CFG_INIT_RAM_END@l + lis r4, CONFIG_SYS_INIT_RAM_END@h + ori r4, r4, CONFIG_SYS_INIT_RAM_END@l /* * Convert the size, in bytes, to the number of cache lines/blocks @@ -1072,18 +1072,18 @@ _start: * Load the initial stack pointer and data area and convert the size, * in bytes, to the number of words to initialize to a known value. */ - lis r1, CFG_INIT_RAM_ADDR@h - ori r1, r1, CFG_INIT_SP_OFFSET@l + lis r1, CONFIG_SYS_INIT_RAM_ADDR@h + ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l - lis r4, (CFG_INIT_RAM_END >> 2)@h - ori r4, r4, (CFG_INIT_RAM_END >> 2)@l + lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h + ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l mtctr r4 - lis r2, CFG_INIT_RAM_ADDR@h - ori r2, r2, CFG_INIT_RAM_END@l + lis r2, CONFIG_SYS_INIT_RAM_ADDR@h + ori r2, r2, CONFIG_SYS_INIT_RAM_END@l - lis r4, CFG_INIT_RAM_PATTERN@h - ori r4, r4, CFG_INIT_RAM_PATTERN@l + lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h + ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l ..stackloop: stwu r4, -4(r2) @@ -1106,15 +1106,15 @@ _start: stwu r1, -8(r1) /* Save back chain and move SP */ stw r0, +12(r1) /* Save return addr (underflow vect) */ -#elif defined(CFG_TEMP_STACK_OCM) && \ - (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)) +#elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ + (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) /* * Stack in OCM. */ /* Set up Stack at top of OCM */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l /* Set up a zeroized stack frame so that backtrace works right */ li r0, 0 @@ -1130,7 +1130,7 @@ _start: ori r0, r0, RESET_VECTOR@l stwu r1, -8(r1) /* Save back chain and move SP */ stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* CFG_INIT_DCACHE_CS */ +#endif /* CONFIG_SYS_INIT_DCACHE_CS */ #ifdef CONFIG_NAND_SPL bl nand_boot_common /* will not return */ @@ -1341,7 +1341,7 @@ in32r: */ .globl relocate_code relocate_code: -#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) +#if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) /* * We need to flush the initial global data (gd_t) before the dcache * will be invalidated. @@ -1354,10 +1354,10 @@ relocate_code: /* Flush initial global data range */ mr r3, r4 - addi r4, r4, CFG_GBL_DATA_SIZE@l + addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l bl flush_dcache_range -#if defined(CFG_INIT_DCACHE_CS) +#if defined(CONFIG_SYS_INIT_DCACHE_CS) /* * Undo the earlier data cache set-up for the primordial stack and * data area. First, invalidate the data cache and then disable data @@ -1366,19 +1366,19 @@ relocate_code: */ /* Invalidate the primordial stack and data area in cache */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l - lis r4, CFG_INIT_RAM_END@h - ori r4, r4, CFG_INIT_RAM_END@l + lis r4, CONFIG_SYS_INIT_RAM_END@h + ori r4, r4, CONFIG_SYS_INIT_RAM_END@l add r4, r4, r3 bl invalidate_dcache_range /* Disable cacheability for the region */ mfdccr r3 - lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h - ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l and r3, r3, r4 mtdccr r3 @@ -1394,15 +1394,15 @@ relocate_code: lis r3, PBxCR_VAL@h ori r3, r3, PBxCR_VAL@l mtdcr ebccfgd, r3 -#endif /* defined(CFG_INIT_DCACHE_CS) */ +#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ /* Restore registers */ mr r3, r9 mr r4, r10 mr r5, r11 -#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */ +#endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* * Unlock the previously locked d-cache */ @@ -1424,7 +1424,7 @@ relocate_code: mtspr dtv3,r6 msync isync -#endif /* CFG_INIT_RAM_DCACHE */ +#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -1439,11 +1439,11 @@ relocate_code: dccci 0,0 /* Invalidate data cache, now no longer our stack */ sync isync -#ifdef CFG_TLB_FOR_BOOT_FLASH - addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ +#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH + addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif /* CFG_TLB_FOR_BOOT_FLASH */ +#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */ tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ @@ -1455,8 +1455,8 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 li r6, L1_CACHE_BYTES /* Cache Line Size */ @@ -1464,7 +1464,7 @@ relocate_code: /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -1775,74 +1775,74 @@ ppc405ep_init: lis r3,GPIO0_OSRH@h /* config GPIO output select */ ori r3,r3,GPIO0_OSRH@l - lis r4,CFG_GPIO0_OSRH@h - ori r4,r4,CFG_GPIO0_OSRH@l + lis r4,CONFIG_SYS_GPIO0_OSRH@h + ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l stw r4,0(r3) lis r3,GPIO0_OSRL@h ori r3,r3,GPIO0_OSRL@l - lis r4,CFG_GPIO0_OSRL@h - ori r4,r4,CFG_GPIO0_OSRL@l + lis r4,CONFIG_SYS_GPIO0_OSRL@h + ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l stw r4,0(r3) lis r3,GPIO0_ISR1H@h /* config GPIO input select */ ori r3,r3,GPIO0_ISR1H@l - lis r4,CFG_GPIO0_ISR1H@h - ori r4,r4,CFG_GPIO0_ISR1H@l + lis r4,CONFIG_SYS_GPIO0_ISR1H@h + ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l stw r4,0(r3) lis r3,GPIO0_ISR1L@h ori r3,r3,GPIO0_ISR1L@l - lis r4,CFG_GPIO0_ISR1L@h - ori r4,r4,CFG_GPIO0_ISR1L@l + lis r4,CONFIG_SYS_GPIO0_ISR1L@h + ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l stw r4,0(r3) lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ ori r3,r3,GPIO0_TSRH@l - lis r4,CFG_GPIO0_TSRH@h - ori r4,r4,CFG_GPIO0_TSRH@l + lis r4,CONFIG_SYS_GPIO0_TSRH@h + ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l stw r4,0(r3) lis r3,GPIO0_TSRL@h ori r3,r3,GPIO0_TSRL@l - lis r4,CFG_GPIO0_TSRL@h - ori r4,r4,CFG_GPIO0_TSRL@l + lis r4,CONFIG_SYS_GPIO0_TSRL@h + ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l stw r4,0(r3) lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ ori r3,r3,GPIO0_TCR@l - lis r4,CFG_GPIO0_TCR@h - ori r4,r4,CFG_GPIO0_TCR@l + lis r4,CONFIG_SYS_GPIO0_TCR@h + ori r4,r4,CONFIG_SYS_GPIO0_TCR@l stw r4,0(r3) li r3,pb1ap /* program EBC bank 1 for RTC access */ mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1AP@h - ori r3,r3,CFG_EBC_PB1AP@l + lis r3,CONFIG_SYS_EBC_PB1AP@h + ori r3,r3,CONFIG_SYS_EBC_PB1AP@l mtdcr ebccfgd,r3 li r3,pb1cr mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1CR@h - ori r3,r3,CFG_EBC_PB1CR@l + lis r3,CONFIG_SYS_EBC_PB1CR@h + ori r3,r3,CONFIG_SYS_EBC_PB1CR@l mtdcr ebccfgd,r3 li r3,pb1ap /* program EBC bank 1 for RTC access */ mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1AP@h - ori r3,r3,CFG_EBC_PB1AP@l + lis r3,CONFIG_SYS_EBC_PB1AP@h + ori r3,r3,CONFIG_SYS_EBC_PB1AP@l mtdcr ebccfgd,r3 li r3,pb1cr mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB1CR@h - ori r3,r3,CFG_EBC_PB1CR@l + lis r3,CONFIG_SYS_EBC_PB1CR@h + ori r3,r3,CONFIG_SYS_EBC_PB1CR@l mtdcr ebccfgd,r3 li r3,pb4ap /* program EBC bank 4 for FPGA access */ mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB4AP@h - ori r3,r3,CFG_EBC_PB4AP@l + lis r3,CONFIG_SYS_EBC_PB4AP@h + ori r3,r3,CONFIG_SYS_EBC_PB4AP@l mtdcr ebccfgd,r3 li r3,pb4cr mtdcr ebccfga,r3 - lis r3,CFG_EBC_PB4CR@h - ori r3,r3,CFG_EBC_PB4CR@l + lis r3,CONFIG_SYS_EBC_PB4CR@h + ori r3,r3,CONFIG_SYS_EBC_PB4CR@l mtdcr ebccfgd,r3 #endif @@ -2111,20 +2111,20 @@ nand_boot_common: * First initialize SDRAM. It has to be available *before* calling * nand_boot(). */ - lis r3,CFG_SDRAM_BASE@h - ori r3,r3,CFG_SDRAM_BASE@l + lis r3,CONFIG_SYS_SDRAM_BASE@h + ori r3,r3,CONFIG_SYS_SDRAM_BASE@l bl initdram /* * Now copy the 4k SPL code into SDRAM and continue execution * from there. */ - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l - lis r4,CFG_NAND_BOOT_SPL_SRC@h - ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l - lis r5,CFG_NAND_BOOT_SPL_SIZE@h - ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l + lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h + ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l + lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h + ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l + lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h + ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l bl nand_boot_relocate /* diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c index cb8d5c7..592efe7 100644 --- a/cpu/ppc4xx/usb.c +++ b/cpu/ppc4xx/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) #ifdef CONFIG_4xx_DCACHE #include @@ -63,4 +63,4 @@ int usb_cpu_init_fail(void) return 0; } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index 5dbd842..2c80d5c 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -1600,9 +1600,9 @@ int usb_lowlevel_init(void) gohci.sleeping = 0; gohci.irq = -1; #if defined(CONFIG_440EP) - gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); -#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) - gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); + gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000); +#elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST) + gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST); #endif gohci.flags = 0; diff --git a/cpu/ppc4xx/usbdev.h b/cpu/ppc4xx/usbdev.h index 3446d98..ef6a2da 100644 --- a/cpu/ppc4xx/usbdev.h +++ b/cpu/ppc4xx/usbdev.h @@ -1,31 +1,31 @@ #include /*Common Registers*/ -#define USB2D0_INTRIN_16 (CFG_USB_DEVICE | 0x100) -#define USB2D0_POWER_8 (CFG_USB_DEVICE | 0x102) -#define USB2D0_FADDR_8 (CFG_USB_DEVICE | 0x103) -#define USB2D0_INTRINE_16 (CFG_USB_DEVICE | 0x104) -#define USB2D0_INTROUT_16 (CFG_USB_DEVICE | 0x106) -#define USB2D0_INTRUSBE_8 (CFG_USB_DEVICE | 0x108) -#define USB2D0_INTRUSB_8 (CFG_USB_DEVICE | 0x109) -#define USB2D0_INTROUTE_16 (CFG_USB_DEVICE | 0x10a) -#define USB2D0_TSTMODE_8 (CFG_USB_DEVICE | 0x10c) -#define USB2D0_INDEX_8 (CFG_USB_DEVICE | 0x10d) -#define USB2D0_FRAME_16 (CFG_USB_DEVICE | 0x10e) +#define USB2D0_INTRIN_16 (CONFIG_SYS_USB_DEVICE | 0x100) +#define USB2D0_POWER_8 (CONFIG_SYS_USB_DEVICE | 0x102) +#define USB2D0_FADDR_8 (CONFIG_SYS_USB_DEVICE | 0x103) +#define USB2D0_INTRINE_16 (CONFIG_SYS_USB_DEVICE | 0x104) +#define USB2D0_INTROUT_16 (CONFIG_SYS_USB_DEVICE | 0x106) +#define USB2D0_INTRUSBE_8 (CONFIG_SYS_USB_DEVICE | 0x108) +#define USB2D0_INTRUSB_8 (CONFIG_SYS_USB_DEVICE | 0x109) +#define USB2D0_INTROUTE_16 (CONFIG_SYS_USB_DEVICE | 0x10a) +#define USB2D0_TSTMODE_8 (CONFIG_SYS_USB_DEVICE | 0x10c) +#define USB2D0_INDEX_8 (CONFIG_SYS_USB_DEVICE | 0x10d) +#define USB2D0_FRAME_16 (CONFIG_SYS_USB_DEVICE | 0x10e) /*Indexed Registers*/ -#define USB2D0_INCSR0_8 (CFG_USB_DEVICE | 0x110) -#define USB2D0_INCSR_16 (CFG_USB_DEVICE | 0x110) -#define USB2D0_INMAXP_16 (CFG_USB_DEVICE | 0x112) -#define USB2D0_OUTCSR_16 (CFG_USB_DEVICE | 0x114) -#define USB2D0_OUTMAXP_16 (CFG_USB_DEVICE | 0x116) -#define USB2D0_OUTCOUNT0_8 (CFG_USB_DEVICE | 0x11a) -#define USB2D0_OUTCOUNT_16 (CFG_USB_DEVICE | 0x11a) +#define USB2D0_INCSR0_8 (CONFIG_SYS_USB_DEVICE | 0x110) +#define USB2D0_INCSR_16 (CONFIG_SYS_USB_DEVICE | 0x110) +#define USB2D0_INMAXP_16 (CONFIG_SYS_USB_DEVICE | 0x112) +#define USB2D0_OUTCSR_16 (CONFIG_SYS_USB_DEVICE | 0x114) +#define USB2D0_OUTMAXP_16 (CONFIG_SYS_USB_DEVICE | 0x116) +#define USB2D0_OUTCOUNT0_8 (CONFIG_SYS_USB_DEVICE | 0x11a) +#define USB2D0_OUTCOUNT_16 (CONFIG_SYS_USB_DEVICE | 0x11a) /*FIFOs*/ -#define USB2D0_FIFO_0 (CFG_USB_DEVICE | 0x120) -#define USB2D0_FIFO_1 (CFG_USB_DEVICE | 0x124) -#define USB2D0_FIFO_2 (CFG_USB_DEVICE | 0x128) -#define USB2D0_FIFO_3 (CFG_USB_DEVICE | 0x12c) +#define USB2D0_FIFO_0 (CONFIG_SYS_USB_DEVICE | 0x120) +#define USB2D0_FIFO_1 (CONFIG_SYS_USB_DEVICE | 0x124) +#define USB2D0_FIFO_2 (CONFIG_SYS_USB_DEVICE | 0x128) +#define USB2D0_FIFO_3 (CONFIG_SYS_USB_DEVICE | 0x12c) void usb_dev_init(void); diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index 0ee8180..e84cb5b 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -44,7 +44,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index df537c4..08042be 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -37,7 +37,7 @@ #ifdef CONFIG_HARD_I2C /* - * - CFG_I2C_SPEED + * - CONFIG_SYS_I2C_SPEED * - I2C_PXA_SLAVE_ADDR */ @@ -48,7 +48,7 @@ /*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ -#if (CFG_I2C_SPEED == 400000) +#if (CONFIG_SYS_I2C_SPEED == 400000) #define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) #else #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) @@ -254,7 +254,7 @@ i2c_transfer_finish: void i2c_init(int speed, int slaveaddr) { -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ @@ -329,7 +329,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * send memory address bytes; * alen defines how much bytes we have to send. */ - /*addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); */ + /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */ addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c index 8b577e1..ec8fb9e 100644 --- a/cpu/pxa/interrupts.c +++ b/cpu/pxa/interrupts.c @@ -78,10 +78,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 1000; } else { - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -109,6 +109,6 @@ unsigned long long get_ticks(void) ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 1cfede7..d735c8d 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -234,7 +234,7 @@ mmc_read(ulong src, uchar * dst, int size) mmc_block_size = MMC_BLOCK_SIZE; mmc_block_address = ~(mmc_block_size - 1); - src -= CFG_MMC_BASE; + src -= CONFIG_SYS_MMC_BASE; end = src + size; part_start = ~mmc_block_address & src; part_end = ~mmc_block_address & end; @@ -310,7 +310,7 @@ mmc_write(uchar * src, ulong dst, int size) mmc_block_size = MMC_BLOCK_SIZE; mmc_block_address = ~(mmc_block_size - 1); - dst -= CFG_MMC_BASE; + dst -= CONFIG_SYS_MMC_BASE; end = dst + size; part_start = ~mmc_block_address & dst; part_end = ~mmc_block_address & end; @@ -379,7 +379,7 @@ mmc_bread(int dev_num, ulong blknr, lbaint_t blkcnt, void *dst) /****************************************************/ { int mmc_block_size = MMC_BLOCK_SIZE; - ulong src = blknr * mmc_block_size + CFG_MMC_BASE; + ulong src = blknr * mmc_block_size + CONFIG_SYS_MMC_BASE; mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size); return blkcnt; @@ -652,8 +652,8 @@ int mmc_ident(block_dev_desc_t * dev) int mmc2info(ulong addr) { - if (addr >= CFG_MMC_BASE - && addr < CFG_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) { + if (addr >= CONFIG_SYS_MMC_BASE + && addr < CONFIG_SYS_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) { return 1; } return 0; diff --git a/cpu/pxa/pxafb.c b/cpu/pxa/pxafb.c index b2caa73..97efcb6 100644 --- a/cpu/pxa/pxafb.c +++ b/cpu/pxa/pxafb.c @@ -60,11 +60,11 @@ vidinfo_t panel_info = { vl_row: 480, vl_width: 640, vl_height: 480, - vl_clkp: CFG_HIGH, - vl_oep: CFG_HIGH, - vl_hsp: CFG_HIGH, - vl_vsp: CFG_HIGH, - vl_dp: CFG_HIGH, + vl_clkp: CONFIG_SYS_HIGH, + vl_oep: CONFIG_SYS_HIGH, + vl_hsp: CONFIG_SYS_HIGH, + vl_vsp: CONFIG_SYS_HIGH, + vl_dp: CONFIG_SYS_HIGH, vl_bpix: LCD_BPP, vl_lbw: 0, vl_splt: 0, @@ -94,11 +94,11 @@ vidinfo_t panel_info = { vl_row: 480, vl_width: 157, vl_height: 118, - vl_clkp: CFG_HIGH, - vl_oep: CFG_HIGH, - vl_hsp: CFG_HIGH, - vl_vsp: CFG_HIGH, - vl_dp: CFG_HIGH, + vl_clkp: CONFIG_SYS_HIGH, + vl_oep: CONFIG_SYS_HIGH, + vl_hsp: CONFIG_SYS_HIGH, + vl_vsp: CONFIG_SYS_HIGH, + vl_dp: CONFIG_SYS_HIGH, vl_bpix: LCD_BPP, vl_lbw: 0, vl_splt: 1, @@ -127,11 +127,11 @@ vidinfo_t panel_info = { vl_row: 240, vl_width: 167, vl_height: 109, - vl_clkp: CFG_HIGH, - vl_oep: CFG_HIGH, - vl_hsp: CFG_HIGH, - vl_vsp: CFG_HIGH, - vl_dp: CFG_HIGH, + vl_clkp: CONFIG_SYS_HIGH, + vl_oep: CONFIG_SYS_HIGH, + vl_hsp: CONFIG_SYS_HIGH, + vl_vsp: CONFIG_SYS_HIGH, + vl_dp: CONFIG_SYS_HIGH, vl_bpix: LCD_BPP, vl_lbw: 1, vl_splt: 0, diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 23005e2..63ab0c5 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -135,8 +135,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif /* CONFIG_USE_IRQ */ @@ -191,20 +191,20 @@ OSTIMER_BASE: .word 0x40a00000 /* Clock Manager Registers */ #ifdef CONFIG_CPU_MONAHANS -# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO -# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" -# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */ -# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO -# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 -# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */ +# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO +# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!" +# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */ +# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO +# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 +# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */ #else /* !CONFIG_CPU_MONAHANS */ -#ifdef CFG_CPUSPEED +#ifdef CONFIG_SYS_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 -cpuspeed: .word CFG_CPUSPEED -#else /* !CFG_CPUSPEED */ -#error "You have to define CFG_CPUSPEED!!" -#endif /* CFG_CPUSPEED */ +cpuspeed: .word CONFIG_SYS_CPUSPEED +#else /* !CONFIG_SYS_CPUSPEED */ +#error "You have to define CONFIG_SYS_CPUSPEED!!" +#endif /* CONFIG_SYS_CPUSPEED */ #endif /* CONFIG_CPU_MONAHANS */ /* takes care the CP15 update has taken place */ @@ -245,10 +245,10 @@ cpu_init_crit: /* set clock speed */ #ifdef CONFIG_CPU_MONAHANS ldr r0, =ACCR - ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) + ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) str r1, [r0] #else /* !CONFIG_CPU_MONAHANS */ -#ifdef CFG_CPUSPEED +#ifdef CONFIG_SYS_CPUSPEED ldr r0, CC_BASE ldr r1, cpuspeed str r1, [r0, #CCCR] @@ -257,7 +257,7 @@ cpu_init_crit: setspeed_done: -#endif /* CFG_CPUSPEED */ +#endif /* CONFIG_SYS_CPUSPEED */ #endif /* CONFIG_CPU_MONAHANS */ /* @@ -336,8 +336,8 @@ setspeed_done: add r8, sp, #S_PC ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ @@ -373,8 +373,8 @@ setspeed_done: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/cpu/pxa/usb.c b/cpu/pxa/usb.c index aa6f4b7..bd718a6 100644 --- a/cpu/pxa/usb.c +++ b/cpu/pxa/usb.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) #include @@ -109,4 +109,4 @@ int usb_cpu_init_fail(void) } # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/interrupts.c index ed79648..eb23e6a 100644 --- a/cpu/s3c44b0/interrupts.c +++ b/cpu/s3c44b0/interrupts.c @@ -80,7 +80,7 @@ void udelay (unsigned long usec) ulong tmo; tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 8; tmo += get_timer (0); @@ -120,10 +120,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 8; } else { - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*8); } diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S index 1d88c1c..f5a3d3a 100644 --- a/cpu/s3c44b0/start.S +++ b/cpu/s3c44b0/start.S @@ -157,8 +157,8 @@ vector_copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c index f1bd644..bb4e5a1 100644 --- a/cpu/sa1100/cpu.c +++ b/cpu/sa1100/cpu.c @@ -43,7 +43,7 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c index 53f2745..2eff045 100644 --- a/cpu/sa1100/interrupts.c +++ b/cpu/sa1100/interrupts.c @@ -74,10 +74,10 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { tmo = usec / 1000; - tmo *= CFG_HZ; + tmo *= CONFIG_SYS_HZ; tmo /= 1000; } else { - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } @@ -106,6 +106,6 @@ ulong get_tbclk (void) { ulong tbclk; - tbclk = CFG_HZ; + tbclk = CONFIG_SYS_HZ; return tbclk; } diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S index 910650d..278c500 100644 --- a/cpu/sa1100/start.S +++ b/cpu/sa1100/start.S @@ -147,8 +147,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -196,7 +196,7 @@ RST_BASE: .word 0x90030000 PWR_BASE: .word 0x90020000 #define PSPR 0x08 #define PPCR 0x14 -cpuspeed: .word CFG_CPUSPEED +cpuspeed: .word CONFIG_SYS_CPUSPEED cpu_init_crit: @@ -288,8 +288,8 @@ cpu_init_crit: add r8, sp, #S_PC ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -321,8 +321,8 @@ cpu_init_crit: .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/cpu/sh2/start.S b/cpu/sh2/start.S index c4fa688..0ab867d 100644 --- a/cpu/sh2/start.S +++ b/cpu/sh2/start.S @@ -73,6 +73,6 @@ loop: ._reloc_dst_end: .long reloc_dst_end ._bss_start: .long bss_start ._bss_end: .long bss_end -._gd_init: .long (_start - CFG_GBL_DATA_SIZE) -._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) +._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE) +._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) ._sh_generic_init: .long sh_generic_init diff --git a/cpu/sh2/time.c b/cpu/sh2/time.c index d6eb0cb..fcbb921 100644 --- a/cpu/sh2/time.c +++ b/cpu/sh2/time.c @@ -101,11 +101,11 @@ void udelay(unsigned long usec) { unsigned int start = get_timer(0); - while (get_timer((ulong) start) < (usec * (CFG_HZ / 1000000))) + while (get_timer((ulong) start) < (usec * (CONFIG_SYS_HZ / 1000000))) continue; } unsigned long get_tbclk(void) { - return CFG_HZ; + return CONFIG_SYS_HZ; } diff --git a/cpu/sh3/start.S b/cpu/sh3/start.S index ee0bcdf..c0f8326 100644 --- a/cpu/sh3/start.S +++ b/cpu/sh3/start.S @@ -72,6 +72,6 @@ loop: ._reloc_dst_end: .long reloc_dst_end ._bss_start: .long bss_start ._bss_end: .long bss_end -._gd_init: .long (_start - CFG_GBL_DATA_SIZE) -._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) +._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE) +._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) ._sh_generic_init: .long sh_generic_init diff --git a/cpu/sh3/time.c b/cpu/sh3/time.c index 0c273dd..aab3659 100644 --- a/cpu/sh3/time.c +++ b/cpu/sh3/time.c @@ -91,7 +91,7 @@ void reset_timer(void) void udelay(unsigned long usec) { unsigned int start = get_timer(0); - unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000)); + unsigned int end = start + (usec * ((CONFIG_SYS_HZ + 500000) / 1000000)); while (get_timer(0) < end) continue; @@ -99,5 +99,5 @@ void udelay(unsigned long usec) unsigned long get_tbclk(void) { - return CFG_HZ; + return CONFIG_SYS_HZ; } diff --git a/cpu/sh4/start.S b/cpu/sh4/start.S index a68ebb8..711ae66 100644 --- a/cpu/sh4/start.S +++ b/cpu/sh4/start.S @@ -69,6 +69,6 @@ loop: ._reloc_dst_end: .long reloc_dst_end ._bss_start: .long bss_start ._bss_end: .long bss_end -._gd_init: .long (_start - CFG_GBL_DATA_SIZE) -._stack_init: .long (_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16) +._gd_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE) +._stack_init: .long (_start - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16) ._sh_generic_init: .long sh_generic_init diff --git a/cpu/sh4/time.c b/cpu/sh4/time.c index 5f8a3a0..77e0ae2 100644 --- a/cpu/sh4/time.c +++ b/cpu/sh4/time.c @@ -86,7 +86,7 @@ void reset_timer (void) void udelay (unsigned long usec) { unsigned int start = get_timer (0); - unsigned int end = start + (usec * ((CFG_HZ + 500000) / 1000000)); + unsigned int end = start + (usec * ((CONFIG_SYS_HZ + 500000) / 1000000)); while (get_timer (0) < end) continue; @@ -94,5 +94,5 @@ void udelay (unsigned long usec) unsigned long get_tbclk (void) { - return CFG_HZ; + return CONFIG_SYS_HZ; } -- cgit v1.1 From 54e091d3b603a3332c619199ca83a07e95960da4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 22 Sep 2008 14:11:10 -0500 Subject: 85xx: Export invalidate_{i,d}cache and add flush_dcache Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 25d0390..fc3c336 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -565,6 +565,7 @@ mck_return: /* Cache functions. */ +.globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 ori r0,r0,L1CSR1_ICFI @@ -574,6 +575,7 @@ invalidate_icache: isync blr /* entire I cache */ +.globl invalidate_dcache invalidate_dcache: mfspr r0,L1CSR0 ori r0,r0,L1CSR0_DCFI @@ -1019,3 +1021,50 @@ unlock_ram_in_cache: tlbivax 0,r3 isync blr + +.globl flush_dcache +flush_dcache: + mfspr r3,SPRN_L1CFG0 + + rlwinm r5,r3,9,3 /* Extract cache block size */ + twlgti r5,1 /* Only 32 and 64 byte cache blocks + * are currently defined. + */ + li r4,32 + subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - + * log2(number of ways) + */ + slw r5,r4,r5 /* r5 = cache block size */ + + rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ + mulli r7,r7,13 /* An 8-way cache will require 13 + * loads per set. + */ + slw r7,r7,r6 + + /* save off HID0 and set DCFA */ + mfspr r8,SPRN_HID0 + ori r9,r8,HID0_DCFA@l + mtspr SPRN_HID0,r9 + isync + + lis r4,0 + mtctr r7 + +1: lwz r3,0(r4) /* Load... */ + add r4,r4,r5 + bdnz 1b + + msync + lis r4,0 + mtctr r7 + +1: dcbf 0,r4 /* ...and flush. */ + add r4,r4,r5 + bdnz 1b + + /* restore HID0 */ + mtspr SPRN_HID0,r8 + isync + + blr -- cgit v1.1 From dbbbb3abeff325855cae76e33d69d5665631443f Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 12:36:39 -0400 Subject: Make DDR interleaving mode work correctly Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang --- cpu/mpc8xxx/ddr/ctrl_regs.c | 61 ++++++++++++++++++++++++++++++++++++--------- cpu/mpc8xxx/ddr/main.c | 5 ++++ 2 files changed, 54 insertions(+), 12 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index e6c2a5c..6297141 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -95,16 +95,10 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, col_bits_cs_n = dimm_params[i/2].n_col_addr - 8; } - /* FIXME: intlv_en, intlv_ctl only on CS0_CONFIG */ - if (i != 0) { - intlv_en = 0; - intlv_ctl = 0; - } - ddr->cs[i].config = (0 | ((cs_n_en & 0x1) << 31) | ((intlv_en & 0x3) << 29) - | ((intlv_en & 0xf) << 24) + | ((intlv_ctl & 0xf) << 24) | ((ap_n_en & 0x1) << 23) /* XXX: some implementation only have 1 bit starting at left */ @@ -874,8 +868,13 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { phys_size_t sa = 0; phys_size_t ea = 0; - if (popts->ba_intlv_ctl && i > 0) { - /* Don't set up boundaries if bank interleaving */ + + if (popts->ba_intlv_ctl && (i > 0) && + ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { + /* Don't set up boundaries for other CS + * other than CS0, if bank interleaving + * is enabled and not CS2+CS3 interleaved. + */ break; } @@ -894,7 +893,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * on each controller is twice the amount present on * each controller. */ - ea = (2 * common_dimm->total_mem >> dbw_cap_adj) - 1; + unsigned long long rank_density + = dimm_params[0].capacity; + ea = (2 * (rank_density >> dbw_cap_adj)) - 1; } else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { /* @@ -906,8 +907,44 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * controller needs to be programmed into its * respective CS0_BNDS. */ - sa = common_dimm->base_address; - ea = sa + (common_dimm->total_mem >> dbw_cap_adj) - 1; + unsigned long long rank_density + = dimm_params[i/2].rank_density; + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS + * needs to be set. + */ + sa = common_dimm->base_address; + ea = sa + (4 * (rank_density >> dbw_cap_adj))-1; + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS + * and CS2_CNDS need to be set. + */ + if (!(i&1)) { + sa = dimm_params[i/2].base_address; + ea = sa + (i * (rank_density >> + dbw_cap_adj)) - 1; + } + break; + case FSL_DDR_CS0_CS1: + /* CS0+CS1 interleaving, CS0_CNDS needs + * to be set + */ + sa = common_dimm->base_address; + ea = sa + (2 * (rank_density >> dbw_cap_adj))-1; + break; + case FSL_DDR_CS2_CS3: + /* CS2+CS3 interleaving*/ + if (i == 2) { + sa = dimm_params[i/2].base_address; + ea = sa + (2 * (rank_density >> + dbw_cap_adj)) - 1; + } + break; + default: /* No bank(chip-select) interleaving */ + break; + } } else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) { /* diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index c340d56..d26c5c5 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -179,6 +179,7 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, if (*memctl_interleaving) { phys_addr_t addr; + phys_size_t total_mem_per_ctlr = 0; /* * If interleaving between memory controllers, @@ -197,14 +198,18 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { addr = 0; + pinfo->common_timing_params[i].base_address = + (phys_addr_t)addr; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { unsigned long long cap = pinfo->dimm_params[i][j].capacity; pinfo->dimm_params[i][j].base_address = addr; addr += (phys_addr_t)(cap >> dbw_cap_adj[i]); + total_mem_per_ctlr += cap >> dbw_cap_adj[i]; } } + pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr; } else { /* * Simple linear assignment if memory -- cgit v1.1 From dfb49108e4f86c2224e1f30124328b0de66ef72e Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 12:36:55 -0400 Subject: Pass dimm parameters to populate populate controller options Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang --- cpu/mpc8xxx/ddr/ddr.h | 3 +- cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h | 84 ------------------------------------ cpu/mpc8xxx/ddr/main.c | 3 +- cpu/mpc8xxx/ddr/options.c | 4 +- 4 files changed, 7 insertions(+), 87 deletions(-) delete mode 100644 cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ddr.h b/cpu/mpc8xxx/ddr/ddr.h index 0d79be3..9ffd548 100644 --- a/cpu/mpc8xxx/ddr/ddr.h +++ b/cpu/mpc8xxx/ddr/ddr.h @@ -10,8 +10,8 @@ #define FSL_DDR_MAIN_H #include +#include -#include "ddr1_2_dimm_params.h" #include "common_timing_params.h" /* @@ -71,6 +71,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, unsigned int number_of_dimms); extern unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, + dimm_params_t *pdimm, unsigned int ctrl_num); extern unsigned int mclk_to_picos(unsigned int mclk); diff --git a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h b/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h deleted file mode 100644 index c794eed..0000000 --- a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef DDR2_DIMM_PARAMS_H -#define DDR2_DIMM_PARAMS_H - -/* Parameters for a DDR2 dimm computed from the SPD */ -typedef struct dimm_params_s { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int n_banks_per_sdram_device; - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - unsigned int row_density; - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - - /* DIMM timing parameters */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - unsigned int tCKmin_X_ps; - unsigned int tCKmin_X_minus_1_ps; - unsigned int tCKmin_X_minus_2_ps; - unsigned int tCKmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_X; - unsigned int caslat_X_minus_1; - unsigned int caslat_X_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; - - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ -} dimm_params_t; - -extern unsigned int ddr_compute_dimm_parameters( - const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number); - -#endif diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index d26c5c5..700b897 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -319,7 +319,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) */ populate_memctl_options( timing_params[i].all_DIMMs_registered, - &pinfo->memctl_opts[i], i); + &pinfo->memctl_opts[i], + pinfo->dimm_params[i], i); } case STEP_ASSIGN_ADDRESSES: diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 6c2b43c..99b5685 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -13,10 +13,12 @@ /* Board-specific functions defined in each board's ddr.c */ extern void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, unsigned int ctrl_num); unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, + dimm_params_t *pdimm, unsigned int ctrl_num) { unsigned int i; @@ -191,7 +193,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * controllers. */ - fsl_ddr_board_options(popts, ctrl_num); + fsl_ddr_board_options(popts, pdimm, ctrl_num); return 0; } -- cgit v1.1 From c9ffd839b1ada502c86f88edaf1534426b6688ce Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 12:37:10 -0400 Subject: Check DDR interleaving mode * Check DDR interleaving mode from environment by reading memctl_intlv_ctl and ba_intlv_ctl. * Print DDR interleaving mode information * Add doc/README.fsl-ddr to describe the interleaving setting Signed-off-by: Haiying Wang --- cpu/mpc8xxx/ddr/main.c | 37 ++++++++++++++++++++++ cpu/mpc8xxx/ddr/options.c | 80 ++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 112 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index 700b897..21a16d9 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -164,6 +164,24 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, } if (j == 2) { *memctl_interleaving = 1; + + printf("\nMemory controller interleaving enabled: "); + + switch (pinfo->memctl_opts[0].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + printf("Cache-line interleaving!\n"); + break; + case FSL_DDR_PAGE_INTERLEAVING: + printf("Page interleaving!\n"); + break; + case FSL_DDR_BANK_INTERLEAVING: + printf("Bank interleaving!\n"); + break; + case FSL_DDR_SUPERBANK_INTERLEAVING: + printf("Super bank interleaving\n"); + default: + break; + } } /* Check that all controllers are rank interleaving. */ @@ -175,6 +193,25 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, } if (j == 2) { *rank_interleaving = 1; + + printf("Bank(chip-select) interleaving enabled: "); + + switch (pinfo->memctl_opts[0].ba_intlv_ctl & + FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + printf("CS0+CS1+CS2+CS3\n"); + break; + case FSL_DDR_CS0_CS1: + printf("CS0+CS1\n"); + break; + case FSL_DDR_CS2_CS3: + printf("CS2+CS3\n"); + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + printf("CS0+CS1 and CS2+CS3\n"); + default: + break; + } } if (*memctl_interleaving) { diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 99b5685..714e88d 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -22,6 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int ctrl_num) { unsigned int i; + const char *p; /* Chip select options. */ @@ -181,17 +182,86 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, #error "FIXME determine four activates for DDR3" #endif - /* ODT should only be used for DDR2 */ - - /* FIXME? */ - /* - * Interleaving checks. + * Check interleaving configuration from environment. + * Please refer to doc/README.fsl-ddr for the detail. * * If memory controller interleaving is enabled, then the data * bus widths must be programmed identically for the 2 memory * controllers. + * + * XXX: Attempt to set both controllers to the same chip select + * interleaving mode. It will do a best effort to get the + * requested ranks interleaved together such that the result + * should be a subset of the requested configuration. */ + if ((p = getenv("memctl_intlv_ctl")) != NULL) { + if (pdimm[0].n_ranks == 0) { + printf("There is no rank on CS0. Because only rank on \ + CS0 and ranks chip-select interleaved with CS0\ + are controller interleaved, force non memory \ + controller interleaving\n"); + popts->memctl_interleaving = 0; + } else { + popts->memctl_interleaving = 1; + if (strcmp(p, "cacheline") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_CACHE_LINE_INTERLEAVING; + else if (strcmp(p, "page") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_PAGE_INTERLEAVING; + else if (strcmp(p, "bank") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_BANK_INTERLEAVING; + else if (strcmp(p, "superbank") == 0) + popts->memctl_interleaving_mode = + FSL_DDR_SUPERBANK_INTERLEAVING; + else + popts->memctl_interleaving_mode = + simple_strtoul(p, NULL, 0); + } + } + + if( (p = getenv("ba_intlv_ctl")) != NULL) { + if (strcmp(p, "cs0_cs1") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; + else if (strcmp(p, "cs2_cs3") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; + else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; + else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; + else + popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0); + + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + case FSL_DDR_CS0_CS1: + if (pdimm[0].n_ranks != 2) { + popts->ba_intlv_ctl = 0; + printf("No enough bank(chip-select) for \ + CS0+CS1, force non-interleaving!\n"); + } + break; + case FSL_DDR_CS2_CS3: + if (pdimm[1].n_ranks !=2){ + popts->ba_intlv_ctl = 0; + printf("No enough bank(CS) for CS2+CS3, \ + force non-interleaving!\n"); + } + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) { + popts->ba_intlv_ctl = 0; + printf("No enough bank(CS) for CS0+CS1 or \ + CS2+CS3, force non-interleaving!\n"); + } + break; + default: + popts->ba_intlv_ctl = 0; + break; + } + } fsl_ddr_board_options(popts, pdimm, ctrl_num); -- cgit v1.1 From 1f293b417ac6ab8e317ca2b770377ca93edf2370 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 3 Oct 2008 12:37:26 -0400 Subject: Add debug information for DDR controller registers Signed-off-by: Haiying Wang --- cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 6297141..1783e92 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -111,6 +111,7 @@ static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr, | ((row_bits_cs_n & 0x7) << 8) | ((col_bits_cs_n & 0x7) << 0) ); + debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); } /* Chip Select Configuration 2 (CSn_CONFIG_2) */ @@ -120,6 +121,7 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) unsigned int pasr_cfg = 0; /* Partial array self refresh config */ ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); + debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); } /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ @@ -190,6 +192,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, | ((ext_caslat & 0x1) << 12) | ((cntl_adj & 0x7) << 0) ); + debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); } /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ @@ -257,6 +260,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, | ((acttoact_mclk & 0x07) << 4) | ((wrtord_mclk & 0x07) << 0) ); + debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); } /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ @@ -313,6 +317,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((cke_pls & 0x7) << 6) | ((four_act & 0x1f) << 0) ); + debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); } /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ @@ -379,6 +384,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((mem_halt & 0x1) << 1) | ((bi & 0x1) << 0) ); + debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); } /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ @@ -443,6 +449,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((rcw_en & 0x1) << 2) | ((md_en & 0x1) << 0) ); + debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); } /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ @@ -455,6 +462,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) | ((esdmode2 & 0xFFFF) << 16) | ((esdmode3 & 0xFFFF) << 0) ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); } /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ @@ -474,6 +482,7 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, | ((refint & 0xFFFF) << 16) | ((bstopre & 0x3FFF) << 0) ); + debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); } /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ @@ -607,6 +616,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, | ((esdmode & 0xFFFF) << 16) | ((sdmode & 0xFFFF) << 0) ); + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); } @@ -669,6 +679,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr) | ((wwt & 0xf) << 16) | (dll_lock & 0x3) ); + debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); } /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ @@ -685,6 +696,7 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) | ((wodt_on & 0xf) << 12) | ((wodt_off & 0xf) << 8) ); + debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); } /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ @@ -992,6 +1004,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, | ((ea & 0xFFF) << 0) /* ending address MSB */ ); + debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); set_csn_config(i, ddr, popts, dimm_params); set_csn_config_2(i, ddr); } -- cgit v1.1 From 0e17f02a8a78d85225a4d805f6a1ea95a0a460b5 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 7 Oct 2008 08:09:50 -0500 Subject: Have u-boot pass stashing parameters into device tree Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming --- cpu/mpc85xx/fdt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 3c8fbd8..59aafb1 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -201,6 +201,15 @@ static inline void ft_fixup_cache(void *blob) } +void fdt_add_enet_stashing(void *fdt) +{ + do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); +} + void ft_cpu_setup(void *blob, bd_t *bd) { /* delete crypto node if not on an E-processor */ @@ -210,6 +219,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob); + + fdt_add_enet_stashing(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, -- cgit v1.1 From 6856b3d0221a838580e6bb06f61425fd7529ba93 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 8 Oct 2008 23:37:59 -0500 Subject: 85xx if NUM_CPUS>1, print cpu number Signed-off-by: Ed Swarthout --- cpu/mpc85xx/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 61162a8..9c4f214 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -99,7 +99,12 @@ int checkcpu (void) #endif minor = SVR_MIN(svr); +#if (CONFIG_NUM_CPUS > 1) + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); +#else puts("CPU: "); +#endif cpu = identify_cpu(ver); if (cpu) { -- cgit v1.1