From 5001b99606655a6f91984afb54625e4af1ed1058 Mon Sep 17 00:00:00 2001 From: Terry Lv Date: Wed, 27 May 2009 21:43:40 +0800 Subject: ENGR00112845 spi nor boot and pmic support for BBG2. spi nor boot support for BBG2. Signed-off-by: Terry Lv --- cpu/arm_cortexa8/mx51/generic.c | 57 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c index 8982a80..ef8ef98 100644 --- a/cpu/arm_cortexa8/mx51/generic.c +++ b/cpu/arm_cortexa8/mx51/generic.c @@ -49,6 +49,7 @@ static u32 __decode_pll(enum pll_clocks pll, u32 infreq) pd = (mfi & 0xF) + 1; mfi = (mfi >> 4) & 0xF; mfi = (mfi >= 5) ? mfi : 5; + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; } @@ -136,9 +137,57 @@ static u32 __get_uart_clk(void) podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; freq /= (pred + 1) * (podf + 1); + return freq; } +/*! ++ * This function returns the low power audio clock. ++ */ +u32 get_lp_apm(void) +{ + u32 ret_val = 0; + u32 ccsr = __REG(MXC_CCM_CCSR); + + if (((ccsr >> 9) & 1) == 0) + ret_val = CONFIG_MX51_HCLK_FREQ; + else + ret_val = ((32768 * 1024)); + + return ret_val; +} + +static u32 __get_cspi_clk(void) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + u32 cscmr1 = __REG(MXC_CCM_CSCMR1); + u32 cscdr2 = __REG(MXC_CCM_CSCDR2); + + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + + switch (clk_sel) { + case 0: + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); + break; + case 1: + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); + break; + case 2: + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); + break; + default: + ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); + break; + } + + return ret_val; +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -152,6 +201,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return __get_ipg_per_clk(); case MXC_UART_CLK: return __get_uart_clk(); + case MXC_CSPI_CLK: + return __get_cspi_clk(); } return -1; } @@ -165,8 +216,10 @@ void mxc_dump_clocks(void) printf("mx51 pll2: %dMHz\n", freq / 1000000); freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ); printf("mx51 pll3: %dMHz\n", freq / 1000000); - printf("ipg clock : %dHz\n", __get_ipg_clk()); - printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK)); } #if defined(CONFIG_DISPLAY_CPUINFO) -- cgit v1.1