From 63247a5acd58032e6cf33f525bc3923b467bac88 Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Wed, 20 Dec 2006 11:01:00 +0800 Subject: u-boot: v2: Remove the fixed TLB and LAW entrynubmer Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward Signed-off-by: Roy Zang --- cpu/mpc85xx/start.S | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index f96a4c3..20c7ebc 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -251,13 +251,10 @@ _start_e500: */ bl tlb1_entry mr r5,r0 - li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ - mtctr r1 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ + mtctr r4 -0: cmpwi r4,0 - beq 1f - lwzu r0,4(r5) +0: lwzu r0,4(r5) lwzu r1,4(r5) lwzu r2,4(r5) lwzu r3,4(r5) @@ -269,7 +266,6 @@ _start_e500: msync tlbwe isync - addi r4,r4,-1 bdnz 0b 1: @@ -301,20 +297,16 @@ _start_e500: bl law_entry mr r6,r0 - li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ - mtctr r1 lwzu r5,0(r6) /* how many windows we actually use */ + mtctr r5 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ li r1,0x0c30 -0: cmpwi r5,0 - beq 1f - lwzu r4,4(r6) +0: lwzu r4,4(r6) lwzu r3,4(r6) stwx r4,r7,r2 stwx r3,r7,r1 - addi r5,r5,-1 addi r2,r2,0x0020 addi r1,r1,0x0020 bdnz 0b -- cgit v1.1 From 96629cbabdb727d4a5e62542deefc01d498db6dc Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Tue, 5 Dec 2006 16:42:30 +0800 Subject: u-boot: Fix e500 v2 core reset bug The following patch fixes the e500 v2 core reset bug. For e500 v2 core, a new reset control register is added to reset the processor. Signed-off-by: Roy Zang --- cpu/mpc85xx/cpu.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 0507c47..2fe4f2a 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -140,16 +140,25 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + uint pvr; + uint ver; + pvr = get_pvr(); + ver = PVR_VER(pvr); + if (ver & 1){ + /* e500 v2 core has reset control register */ + volatile unsigned int * rstcr; + rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + *rstcr = 0x2; /* HRESET_REQ */ + }else{ /* * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val; - - val = mfspr(DBCR0); - val |= 0x70000000; - mtspr(DBCR0,val); - + unsigned long val; + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); + } return 1; } -- cgit v1.1 From 151d5d992eab8c497b24c816c73dc1ad8bffb4eb Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 01:32:22 -0500 Subject: Add cpu support for the 8544 Recognize new SVR values, and add a few register definitions Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger Acked-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe4f2a..2fe6bdf 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004,2007 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -70,6 +70,12 @@ int checkcpu (void) case SVR_8548_E: puts("8548_E"); break; + case SVR_8544: + puts("8544"); + break; + case SVR_8544_E: + puts("8544_E"); + break; default: puts("Unknown"); break; @@ -112,7 +118,7 @@ int checkcpu (void) #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 +#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. -- cgit v1.1 From 03b81b48eec0ad249ec97a4ae16c36fa2e014ff4 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 01:44:44 -0500 Subject: Some 85xx cpu cleanups * Cleaned up the TSR[WIS] clearing * Cleaned up DMA initialization Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger Acked-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe6bdf..b701b47 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -198,9 +198,9 @@ reset_85xx_watchdog(void) * Clear TSR(WIS) bit by writing 1 */ unsigned long val; - val = mfspr(tsr); - val |= 0x40000000; - mtspr(tsr, val); + val = mfspr(SPRN_TSR); + val |= TSR_WIS; + mtspr(SPRN_TSR, val); } #endif /* CONFIG_WATCHDOG */ @@ -211,6 +211,7 @@ void dma_init(void) { dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; + dma->sr0 = 0xfffffff; /* clear any errors */ asm("sync; isync; msync"); return; } @@ -225,6 +226,10 @@ uint dma_check(void) { status = dma->sr0; } + /* clear MR0[CS] channel start bit */ + dma->mr0 &= 0x00000001; + asm("sync;isync;msync"); + if (status != 0) { printf ("DMA Error: status = %x\n", status); } -- cgit v1.1 From 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 12 Feb 2007 13:34:55 -0600 Subject: 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi --- cpu/mpc85xx/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index b701b47..d5102df 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -275,21 +275,41 @@ ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_MPC85XX_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enetaddr, 6); #endif #if defined(CONFIG_HAS_ETH1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet1addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enet1addr, 6); #endif #if defined(CONFIG_HAS_ETH2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet2addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enet2addr, 6); #endif #if defined(CONFIG_HAS_ETH3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); + if (p) + memcpy(p, bd->bi_enet3addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len); + if (p) memcpy(p, bd->bi_enet3addr, 6); #endif -- cgit v1.1 From 9343dbf85bc03033f2102d8e8543567c2c1ad2d2 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:16:45 -0600 Subject: Tweak DDR ECC error counter Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 6da5367..4b3c4eb 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -786,14 +786,17 @@ spd_sdram(void) * Is this an ECC DDR chip? * But don't mess with it if the DDR controller will init mem. */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +#ifdef CONFIG_DDR_ECC if (spd.config == 0x02) { +#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER ddr->err_disable = 0x0000000d; +#endif ddr->err_sbe = 0x00ff0000; } + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); -#endif +#endif /* CONFIG_DDR_ECC */ asm("sync;isync;msync"); udelay(500); -- cgit v1.1 From 1f9a318cea14272edd10d63739e2d326c90f430e Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 16:28:46 -0600 Subject: Only set ddrioovcr for 8548 rev1. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 4b3c4eb..16a697d 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -263,13 +263,14 @@ spd_sdram(void) } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. + * Only 8548 rev 1 needs the fix */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - gur->ddrioovcr = (0 - | 0x80000000 /* Enable */ - | 0x10000000 /* VSEL to 1.8V */ - ); + if ((SVR_VER(get_svr()) == SVR_8548_E) && + (SVR_MJREV(get_svr()) == 1) && + (spd.mem_type == SPD_MEMTYPE_DDR2)) { + gur->ddrioovcr = (0x80000000 /* Enable */ + | 0x10000000);/* VSEL to 1.8V */ } /* -- cgit v1.1 From 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Fri, 23 Feb 2007 17:12:25 -0600 Subject: Support 1G size on 8548 e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout Signed-off-by: Andy Fleming --- cpu/mpc85xx/spd_sdram.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 16a697d..3777f49 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -995,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize) break; case 256: case 512: + tlb_size = BOOKE_PAGESZ_256M; + break; case 1024: case 2048: - tlb_size = BOOKE_PAGESZ_256M; + if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) + tlb_size = BOOKE_PAGESZ_1G; + else + tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); /* * The memory was not able to be mapped. + * Default to a small size. */ - return 0; + tlb_size = BOOKE_PAGESZ_64M; + memsize=64; break; } -- cgit v1.1 From 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:37:47 -0500 Subject: Reworked 85xx speed detection code Changed the code to read the registers and calculate the clock rates, rather than using a "switch" statement. Idea from Andrew Klossner Signed-off-by: Andy Fleming --- cpu/mpc85xx/speed.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index ca81ee7..12359a2 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -37,49 +37,21 @@ void get_sys_info (sys_info_t * sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint plat_ratio,e500_ratio; + uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - switch(plat_ratio) { - case 0x02: - case 0x03: - case 0x04: - case 0x05: - case 0x06: - case 0x08: - case 0x09: - case 0x0a: - case 0x0c: - case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - break; - default: - sysInfo->freqSystemBus = 0; - break; - } - + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; e500_ratio = (gur->porpllsr) & 0x003f0000; e500_ratio >>= 16; - switch(e500_ratio) { - case 0x04: - sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; - break; - case 0x05: - sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; - break; - case 0x06: - sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; - break; - case 0x07: - sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; - break; - default: - sysInfo->freqProcessor = 0; - break; - } + + /* Divide before multiply to avoid integer + * overflow for processor speeds above 2GHz */ + half_freqSystemBus = sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; } + int get_clocks (void) { sys_info_t sys_info; -- cgit v1.1 From 6743105988fc44d5b0d30388c790607835aae7a6 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 23 Apr 2007 02:54:25 -0500 Subject: Add support for the 8568 MDS board This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 7 +++++++ cpu/mpc85xx/cpu_init.c | 2 -- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index d5102df..63176d2 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -76,6 +76,9 @@ int checkcpu (void) case SVR_8544_E: puts("8544_E"); break; + case SVR_8568_E: + puts("8568_E"); + break; default: puts("Unknown"); break; @@ -265,6 +268,10 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); + p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); if (p != NULL) *p = cpu_to_be32(clock); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9f4d36c..9517146 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -143,12 +143,10 @@ void cpu_init_f (void) memctl->br1 = CFG_BR1_PRELIM; #endif -#if !defined(CONFIG_MPC85xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif -#endif #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; -- cgit v1.1 From ffa621a0d12a1ccd81c936c567f8917a213787a8 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Sat, 24 Feb 2007 01:08:13 -0600 Subject: Cleaned up some 85xx PCI bugs * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming --- cpu/mpc85xx/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 84f839a..3c1a323 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -90,14 +90,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | POWAR_MEM_512M); + POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1)); pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; pcix->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | POWAR_IO_1M); + POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1)); pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; @@ -175,14 +175,14 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; pcix2->powbear1 = 0x00000000; pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | POWAR_MEM_512M); + POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1)); pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; pcix2->potear2 = 0x00000000; pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; pcix2->powbear2 = 0x00000000; pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | POWAR_IO_1M); + POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1)); pcix2->pitar1 = 0x00000000; pcix2->piwbar1 = 0x00000000; -- cgit v1.1