From 2d1a537d87727907bf4d888760cba4abc0b52ad3 Mon Sep 17 00:00:00 2001 From: wdenk Date: Mon, 23 Feb 2004 19:30:57 +0000 Subject: * Patch by Thomas Elste, 10 Feb 2004: Add support for NET+50 CPU and ModNET50 board * Patch by Sam Song, 10 Feb 2004: Fix typos in cfi_flash.c * Patch by Leon Kukovec, 10 Feb 2004 Fixed long dir entry slot id calculation in get_vfatname * Patch by Robin Gilks, 10 Feb 2004: add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, !=, <>, <, >, <=, >=) --- cpu/arm720t/Makefile | 2 +- cpu/arm720t/cpu.c | 4 +- cpu/arm720t/interrupts.c | 25 +++++- cpu/arm720t/serial.c | 4 + cpu/arm720t/serial_netarm.c | 185 ++++++++++++++++++++++++++++++++++++++++++++ cpu/arm720t/start.S | 72 ++++++++++++++++- 6 files changed, 288 insertions(+), 4 deletions(-) create mode 100644 cpu/arm720t/serial_netarm.c (limited to 'cpu') diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile index 8c950da..f273d92 100644 --- a/cpu/arm720t/Makefile +++ b/cpu/arm720t/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -OBJS = serial.o interrupts.o cpu.o +OBJS = serial.o serial_netarm.o interrupts.o cpu.o all: .depend $(START) $(LIB) diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 5637eb6..0ad5481 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -106,7 +106,9 @@ int cleanup_before_linux (void) unsigned long i; disable_interrupts (); - +#ifdef CONFIG_NETARM + return 0; +#endif /* turn off I-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~0x1000; diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index b1ee188..0291193 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -30,14 +30,24 @@ #include #include +#ifdef CONFIG_NETARM +#include +#endif extern void reset_cpu(ulong addr); +#ifndef CONFIG_NETARM /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff - /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) +#else +#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) +#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) +#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) +#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK +#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) +#endif #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ @@ -177,6 +187,18 @@ static ulong lastdec; int interrupt_init (void) { +#ifdef CONFIG_NETARM + /* disable all interrupts */ + IRQEN = 0; + + /* operate timer 2 in non-prescale mode */ + TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) | + NETARM_GEN_TCTL_ENABLE | + NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); + + /* set timer 2 counter */ + lastdec = TIMER_LOAD_VAL; +#else /* disable all interrupts */ IO_INTMR1 = 0; @@ -188,6 +210,7 @@ int interrupt_init (void) /* set timer 1 counter */ lastdec = IO_TC1D = TIMER_LOAD_VAL; +#endif timestamp = 0; return (0); diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index d38ac39..5c6a0cc 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -31,6 +31,8 @@ #include #include +#ifndef CONFIG_NETARM + void serial_setbrg (void) { DECLARE_GLOBAL_DATA_PTR; @@ -124,3 +126,5 @@ serial_puts (const char *s) serial_putc (*s++); } } + +#endif /* CONFIG_NETARM */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c new file mode 100644 index 0000000..8cfe049 --- /dev/null +++ b/cpu/arm720t/serial_netarm.c @@ -0,0 +1,185 @@ +/* + * Serial Port stuff - taken from Linux + * + * (C) Copyright 2002 + * MAZeT GmbH + * Stephan Linz , + * + * (c) 2004 + * IMMS gGmbH + * Thomas Elste + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +#ifdef CONFIG_NETARM + +#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) +#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) + +/* wait until transmitter is ready for another character */ +#define TXWAITRDY(registers) \ +{ \ + ulong tmo = get_timer(0) + 1 * CFG_HZ; \ + while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ + if (get_timer(0) > tmo) \ + break; \ + } \ +} + + +volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); +volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); + +extern void _netarm_led_FAIL1(void); + +/* + * Setup both serial i/f with given baudrate + */ +void serial_setbrg (void) +{ + /* get the gd pointer */ + DECLARE_GLOBAL_DATA_PTR; + + /* set 0 ... make sure pins are configured for serial */ + PORTA = PORTB = + NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); + + /* first turn em off */ + serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; + + /* clear match register, we don't need it */ + serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; + + /* setup bit rate generator and rx buffer gap timer (1 byte only) */ + if ((gd->baudrate >= MIN_BAUD_RATE) + && (gd->baudrate <= MAX_BAUD_RATE)) { + serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = + NETARM_SER_BR_X16 (gd->baudrate); + serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = + 0; + serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = + NETARM_SER_RXGAP (gd->baudrate); + } else { + hang (); + } + + /* setup port mode */ + serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = + ( NETARM_SER_CTLB_RCGT_EN | + NETARM_SER_CTLB_UART_MODE); + serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = + ( NETARM_SER_CTLA_ENABLE | + NETARM_SER_CTLA_P_NONE | + /* see errata */ + NETARM_SER_CTLA_2STOP | + NETARM_SER_CTLA_8BITS | + NETARM_SER_CTLA_DTR_EN | + NETARM_SER_CTLA_RTS_EN); +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +int serial_init (void) +{ + serial_setbrg (); + return 0; +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + volatile unsigned char *fifo; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); + + fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); + TXWAITRDY (serial_reg_ch1); + *fifo = c; +} + +/* + * Test of a single byte from the serial port. Returns 1 on success, 0 + * otherwise. + */ +int serial_tstc(void) +{ + return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. + */ +int serial_getc (void) +{ + unsigned int ch_uint; + volatile unsigned int *fifo; + volatile unsigned char *fifo_char = NULL; + int buf_count = 0; + + while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) + /* NOP */ ; + + fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); + fifo_char = (unsigned char *) &ch_uint; + ch_uint = *fifo; + + buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); + switch (buf_count) { + case NETARM_SER_STATA_RXFDB_4BYTES: + buf_count = 4; + break; + case NETARM_SER_STATA_RXFDB_3BYTES: + buf_count = 3; + break; + case NETARM_SER_STATA_RXFDB_2BYTES: + buf_count = 2; + break; + case NETARM_SER_STATA_RXFDB_1BYTES: + buf_count = 1; + break; + default: + /* panic, be never here */ + } + + serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; + + return ch_uint & 0xff; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* CONFIG_NETARM */ diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 7fe36c6..791049a 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -26,7 +26,9 @@ #include #include - +#ifdef CONFIG_NETARM +#include +#endif /* ************************************************************************* @@ -195,6 +197,7 @@ SYSCON3: .word 0x80002200 #define CLKCTL_73 0x6 /* 73.728 MHz */ cpu_init_crit: +#ifndef CONFIG_NETARM /* * mask all IRQs by clearing all bits in the INTMRs */ @@ -221,6 +224,54 @@ cpu_init_crit: bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) orr r0, r0, #0x00000002 @ set bit 2 (A) Align mcr p15,0,r0,c1,c0 +#else /* CONFIG_NETARM */ + /* + * prior to software reset : need to set pin PORTC4 to be *HRESET + */ + ldr r0, =NETARM_GEN_MODULE_BASE + ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ + NETARM_GEN_PORT_DIR(0x10)) + str r1, [r0, #+NETARM_GEN_PORTC] + /* + * software reset : see HW Ref. Guide 8.2.4 : Software Service register + * for an explanation of this process + */ + ldr r0, =NETARM_GEN_MODULE_BASE + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + /* + * setup PLL and System Config + */ + ldr r0, =NETARM_GEN_MODULE_BASE + + ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ + NETARM_GEN_SYS_CFG_BUSFULL | \ + NETARM_GEN_SYS_CFG_USER_EN | \ + NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ + NETARM_GEN_SYS_CFG_BUSARB_INT | \ + NETARM_GEN_SYS_CFG_BUSMON_EN ) + + str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] + + ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ + NETARM_GEN_PLL_CTL_POLTST_DEF | \ + NETARM_GEN_PLL_CTL_INDIV(1) | \ + NETARM_GEN_PLL_CTL_ICP_DEF | \ + NETARM_GEN_PLL_CTL_OUTDIV(2) ) + str r1, [r0, #+NETARM_GEN_PLL_CONTROL] + /* + * mask all IRQs by clearing all bits in the INTMRs + */ + mov r1, #0 + ldr r0, =NETARM_GEN_MODULE_BASE + str r1, [r0, #+NETARM_GEN_INTR_ENABLE] +#endif /* CONFIG_NETARM */ #ifdef CONFIG_ARM7_REVD /* set clock speed */ @@ -415,6 +466,7 @@ fiq: .align 5 .globl reset_cpu reset_cpu: +#ifndef CONFIG_NETARM mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) @@ -423,3 +475,21 @@ reset_cpu: bic ip, ip, #0x2100 @ ..v....s........ mcr p15, 0, ip, c1, c0, 0 @ ctrl register mov pc, r0 +#else + ldr r1, =NETARM_MEM_MODULE_BASE + ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] + ldr r1, =0xFFFFF000 + and r0, r1, r0 + ldr r1, =(relocate-TEXT_BASE) + add r0, r1, r0 + ldr r4, =NETARM_GEN_MODULE_BASE + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + mov pc, r0 +#endif -- cgit v1.1