From eacbd317757327e8e7f018f5701c950429c4c6ae Mon Sep 17 00:00:00 2001 From: "Zachary P. Landau" Date: Thu, 26 Jan 2006 17:35:56 -0500 Subject: Add support for Freescale M5271 processor --- cpu/mcf52x2/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ cpu/mcf52x2/cpu_init.c | 37 +++++++++++++++++++++++++++++++++++++ cpu/mcf52x2/fec.c | 22 +++++++++++++++++++++- cpu/mcf52x2/interrupts.c | 7 ++++++- cpu/mcf52x2/serial.c | 8 +++++++- cpu/mcf52x2/start.S | 34 +++++++++++++++++++++++++++++++++- 6 files changed, 144 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 32a524f..302832b 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -25,6 +25,11 @@ #include #include +#ifdef CONFIG_M5271 +#include +#include +#endif + #ifdef CONFIG_M5272 #include #include @@ -38,6 +43,41 @@ #include #endif +#ifdef CONFIG_M5271 +int checkcpu (void) +{ + puts ("CPU: MOTOROLA Coldfire MCF5271\n"); + return 0; +} + +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + mbar_writeByte(MCF_RCM_RCR, + MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); + return 0; +}; + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + mbar_writeShort(MCF_WTM_WSR, 0x5555); + mbar_writeShort(MCF_WTM_WSR, 0xAAAA); +} + +int watchdog_disable (void) +{ + mbar_writeShort(MCF_WTM_WCR, 0); + return (0); +} + +int watchdog_init (void) +{ + mbar_writeShort(MCF_WTM_WCNTR, CONFIG_WATCHDOG_TIMEOUT); + mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ + +#endif #ifdef CONFIG_M5272 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 350c431..d33adc2 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -24,6 +24,11 @@ #include #include +#ifdef CONFIG_M5271 +#include +#include +#endif + #ifdef CONFIG_M5272 #include #include @@ -38,6 +43,38 @@ #include #endif +#if defined(CONFIG_M5271) +void cpu_init_f (void) +{ +#ifndef CONFIG_WATCHDOG + /* Disable the watchdog if we aren't using it */ + mbar_writeShort(MCF_WTM_WCR, 0); +#endif + + /* Set clockspeed to 100MHz */ + mbar_writeShort(MCF_FMPLL_SYNCR, + MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); + while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK); + + /* Enable UART pins */ + mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | + MCF_GPIO_PAR_UART_U0RXD | + MCF_GPIO_PAR_UART_U1RXD_UART1 | + MCF_GPIO_PAR_UART_U1TXD_UART1); + + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r (void) +{ + return (0); +} +#endif + #if defined(CONFIG_M5272) /* * Breath some life into the CPU... diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index a5c50af..f207dd6 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -25,6 +25,11 @@ #include #include +#ifdef CONFIG_M5271 +#include +#include +#endif + #ifdef CONFIG_M5272 #include #include @@ -41,7 +46,7 @@ #ifdef CONFIG_M5272 #define FEC_ADDR (CFG_MBAR + 0x840) #endif -#ifdef CONFIG_M5282 +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) #define FEC_ADDR (CFG_MBAR + 0x1000) #endif @@ -240,10 +245,22 @@ int eth_init (bd_t * bd) #endif #undef ea +#ifdef CONFIG_M5271 + /* Clear multicast address hash table + */ + fecp->fec_ghash_table_high = 0; + fecp->fec_ghash_table_low = 0; + + /* Clear individual address hash table + */ + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else /* Clear multicast address hash table */ fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; +#endif /* Set maximum receive buffer size. */ @@ -295,6 +312,9 @@ int eth_init (bd_t * bd) fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; #else /* Half duplex mode */ fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; +#ifdef CONFIG_M5271 + fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */ +#endif fecp->fec_x_cntrl = 0; #endif /* Set MII speed */ diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 868df39..116747a 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -27,6 +27,11 @@ #include #include +#ifdef CONFIG_M5271 +#include +#include +#endif + #ifdef CONFIG_M5272 #include #include @@ -171,7 +176,7 @@ int interrupt_init (void) } #endif -#ifdef CONFIG_M5282 +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) int interrupt_init (void) { return 0; diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c index c730922..641f0d9 100644 --- a/cpu/mcf52x2/serial.c +++ b/cpu/mcf52x2/serial.c @@ -26,6 +26,10 @@ #include +#ifdef CONFIG_M5271 +#include +#endif + #ifdef CONFIG_M5272 #include #endif @@ -46,7 +50,7 @@ void rs_serial_setbaudrate(int port,int baudrate) { -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) volatile unsigned char *uartp; double clock, fraction; @@ -61,8 +65,10 @@ void rs_serial_setbaudrate(int port,int baudrate) uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ +#ifndef CONFIG_M5271 uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ #endif +#endif }; void rs_serial_init(int port,int baudrate) diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index b4926e2..8ae9591 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -55,7 +55,11 @@ */ _vectors: +#ifndef CONFIG_M5271 .long 0x00000000, _START +#else +.long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */ +#endif .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -124,26 +128,42 @@ _start: movec %d0, %RAMBAR0 #endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ -#ifdef CONFIG_M5282 +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 +#ifdef CONFIG_M5282 /* Initialize FLASHBAR: locate internal Flash and validate it */ move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 movec %d0, %RAMBAR0 +#endif /* Initialize RAMBAR1: locate SRAM and validate it */ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 +#ifdef CONFIG_M5271 + move.l #(_flash_setup-CFG_FLASH_BASE), %a0 + move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 + move.l #(CFG_INIT_RAM_ADDR), %a2 +_copy_flash: + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash +#endif + + jmp CFG_INIT_RAM_ADDR +_after_flash_copy: #endif +#if 0 /* invalidate and disable cache */ move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 movec %d0, %ACR1 +#endif /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp @@ -158,6 +178,18 @@ _start: /*------------------------------------------------------------------------------*/ +#ifdef CONFIG_M5271 +_flash_setup: + move.l #0x1000, %d0 + move.w %d0, 0x40000080 + move.l #0x2180, %d0 + move.w %d0, 0x4000008A + move.l #0x3f0001, %d0 + move.l %d0, 0x40000084 + jmp _after_flash_copy.L +_flash_setup_end: +#endif + /* * void relocate_code (addr_sp, gd, addr_moni) * -- cgit v1.1 From 0c056f0e274b83fb98b6a562b124709f8fe26c11 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Tue, 9 May 2006 11:37:13 +0200 Subject: Fix serial console support for MCF5271. --- cpu/mcf52x2/serial.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c index 8fbfad4..1cde1b6 100644 --- a/cpu/mcf52x2/serial.c +++ b/cpu/mcf52x2/serial.c @@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_M5249 +#if defined(CONFIG_M5249) || defined(CONFIG_M5271) #define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) #else #define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) @@ -54,7 +54,10 @@ void rs_serial_setbaudrate(int port,int baudrate) { #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) volatile unsigned char *uartp; - double clock, fraction; +#ifndef CONFIG_M5271 + double fraction; +#endif + double clock; if (port == 0) uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); @@ -63,11 +66,11 @@ void rs_serial_setbaudrate(int port,int baudrate) clock = DoubleClock(baudrate); /* Set baud above */ - fraction = ((clock - (int)clock) * 16.0) + 0.5; - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ + #ifndef CONFIG_M5271 + fraction = ((clock - (int)clock) * 16.0) + 0.5; uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ #endif #endif @@ -85,8 +88,9 @@ void rs_serial_init(int port,int baudrate) else uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ @@ -96,9 +100,15 @@ void rs_serial_init(int port,int baudrate) uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; - rs_serial_setbaudrate(port,baudrate); + /* Mask UART interrupts */ + uartp[MCFUART_UIMR] = 0; + /* Set clock Select Register: Tx/Rx clock is timer */ uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; + + rs_serial_setbaudrate(port,baudrate); + + /* Enable Tx/Rx */ uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; return; -- cgit v1.1 From b75ef85f42f75206a9a2c278c042e911c92ea28c Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Tue, 9 May 2006 11:45:31 +0200 Subject: Update CPU target identification strings for Coldfire family. --- cpu/mcf52x2/cpu.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 302832b..e6e5d9b 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -46,7 +46,9 @@ #ifdef CONFIG_M5271 int checkcpu (void) { - puts ("CPU: MOTOROLA Coldfire MCF5271\n"); + char buf[32]; + + printf ("CPU: Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK)); return 0; } @@ -71,7 +73,6 @@ int watchdog_disable (void) int watchdog_init (void) { - mbar_writeShort(MCF_WTM_WCNTR, CONFIG_WATCHDOG_TIMEOUT); mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); return (0); } @@ -106,12 +107,12 @@ int checkcpu(void) { case 0x4: suf = "3K75N"; break; default: suf = NULL; - printf ("MOTOROLA MCF5272 (Mask:%01x)\n", msk); + printf ("Freescale MCF5272 (Mask:%01x)\n", msk); break; } if (suf) - printf ("MOTOROLA MCF5272 %s\n", suf); + printf ("Freescale MCF5272 %s\n", suf); return 0; }; @@ -157,7 +158,7 @@ int watchdog_init (void) #ifdef CONFIG_M5282 int checkcpu (void) { - puts ("CPU: MOTOROLA Coldfire MCF5282\n"); + puts ("CPU: Freescale Coldfire MCF5282\n"); return 0; } @@ -171,7 +172,7 @@ int checkcpu (void) { char buf[32]; - printf ("CPU: MOTOROLA Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); + printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); return 0; } -- cgit v1.1 From 6f5155a95cc6d4b80cda10785c64a55fbb18e8ee Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Tue, 9 May 2006 11:51:51 +0200 Subject: Make R5200 specific low level initialization board conditional. --- cpu/mcf52x2/start.S | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) (limited to 'cpu') diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 8ae9591..3ab812b 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -55,7 +55,7 @@ */ _vectors: -#ifndef CONFIG_M5271 +#ifndef CONFIG_R5200 .long 0x00000000, _START #else .long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */ @@ -142,7 +142,9 @@ _start: /* Initialize RAMBAR1: locate SRAM and validate it */ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 -#ifdef CONFIG_M5271 +#endif + +#ifdef CONFIG_R5200 move.l #(_flash_setup-CFG_FLASH_BASE), %a0 move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 move.l #(CFG_INIT_RAM_ADDR), %a2 @@ -150,8 +152,6 @@ _copy_flash: move.l (%a0)+, (%a2)+ cmp.l %a0, %a1 bgt.s _copy_flash -#endif - jmp CFG_INIT_RAM_ADDR _after_flash_copy: #endif @@ -174,18 +174,24 @@ _after_flash_copy: bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ - /* board_init_f() does not return + /* board_init_f() does not return */ /*------------------------------------------------------------------------------*/ -#ifdef CONFIG_M5271 +#ifdef CONFIG_R5200 _flash_setup: - move.l #0x1000, %d0 + /* CSAR0 */ + move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0 move.w %d0, 0x40000080 - move.l #0x2180, %d0 + + /* CSCR0 */ + move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */ move.w %d0, 0x4000008A - move.l #0x3f0001, %d0 + + /* CSMR0 */ + move.l #0x001f0001, %d0 /* 2 MB, valid */ move.l %d0, 0x40000084 + jmp _after_flash_copy.L _flash_setup_end: #endif -- cgit v1.1