From f5a24259190c388c2527bdc49fee34577d862cc7 Mon Sep 17 00:00:00 2001 From: Wheatley Travis Date: Fri, 2 May 2008 13:35:15 -0700 Subject: 7450 and 86xx L2 cache invalidate bug corrections The 7610 and related parts have an L2IP bit in the L2CR that is monitored to signal when the L2 cache invalidate is complete whereas the 7450 and related parts utilize L2I for this purpose. However, the current code does not account for this difference. Additionally the 86xx L2 cache invalidate code used an "andi" instruction where an "andis" instruction should have been used. This patch addresses both of these bugs. Signed-off-by: Travis Wheatley Acked-By: Jon Loeliger --- cpu/mpc86xx/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index f316b3e..2e4ea02 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate) invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2I@h + andis. r3, r3, L2CR_L2I@h bne invl2 blr -- cgit v1.1