From 255a3577c848706441daee0174543efe205a77f8 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 16 May 2007 16:52:19 -0500 Subject: Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips --- cpu/mpc86xx/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index a33acfe..9456471 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_MPC86XX_TSEC1) +#if defined(CONFIG_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); @@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enetaddr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC2) +#if defined(CONFIG_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); @@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enet1addr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC3) +#if defined(CONFIG_TSEC3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet2addr, 6); @@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enet2addr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC4) +#if defined(CONFIG_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet3addr, 6); -- cgit v1.1 From 32922cdc470fdfd39bea0c1c4f582d3fb340421e Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 5 Jun 2007 12:30:52 -0500 Subject: mpc8641 image size cleanup e600 does not have a bootpg restriction. Move the version string to beginning of image at fff00000. Resetvec.S is not needed. Update flash copy instructions. Add tftpflash env variable Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- cpu/mpc86xx/resetvec.S | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 cpu/mpc86xx/resetvec.S (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/resetvec.S b/cpu/mpc86xx/resetvec.S deleted file mode 100644 index 9a552f6..0000000 --- a/cpu/mpc86xx/resetvec.S +++ /dev/null @@ -1,2 +0,0 @@ - .section .resetvec,"ax" - b _start -- cgit v1.1 From 02032e8f14751a1a751b09240a4f1cf9f8a2077f Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 22 Jun 2007 14:58:04 +0200 Subject: [ppc] Fix build breakage for all non-4xx PowerPC variants. - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup --- cpu/mpc86xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 67c56db..412745b 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -116,7 +116,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -134,7 +134,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ -- cgit v1.1 From f48070fe5fe440dfb5ee5268c920de70e48ea327 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:03:08 -0500 Subject: cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger --- cpu/mpc86xx/traps.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 8ea14e5..06334b7 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -122,7 +122,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -155,7 +155,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -170,7 +170,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -193,7 +193,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -205,7 +205,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif -- cgit v1.1 From b24629fa377214d63bb40d1360e354b6d3e4af56 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 13 Jun 2007 13:23:15 -0500 Subject: mpc86xx: Remove old CFG_CMD_* references. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/traps.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index 06334b7..fab1975 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -34,7 +34,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -122,7 +122,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -155,7 +155,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -170,7 +170,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -193,7 +193,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif @@ -205,7 +205,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) || defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif -- cgit v1.1 From cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 2 Aug 2007 00:48:45 +0200 Subject: Fix build errors and warnings / code cleanup. Signed-off-by: Wolfgang Denk --- cpu/mpc86xx/interrupts.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 49820bb..08e0675 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -71,7 +71,7 @@ static __inline__ void set_dec(unsigned long val) } /* interrupt is not supported yet */ -int interrupt_init_cpu(unsigned *decrementer_count) +int interrupt_init_cpu(unsigned long *decrementer_count) { return 0; } @@ -107,7 +107,7 @@ int interrupt_init(void) return ret; decrementer_count = get_tbclk() / CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n", (get_tbclk() / 1000000), decrementer_count); @@ -158,7 +158,7 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; - ppcDcbf(×tamp); + ppcDcbf((unsigned long)×tamp); /* Restore Decrementer Count */ set_dec(decrementer_count); -- cgit v1.1 From 63cec5814fab5d2b1c86982327433807a5ac0249 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 2 Aug 2007 14:09:49 -0500 Subject: Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout Signed-off-by: Zhang Wei Signed-off-by: Jon Loeliger --- cpu/mpc86xx/Makefile | 3 +- cpu/mpc86xx/pci.c | 146 -------------------------------- cpu/mpc86xx/pcie_indirect.c | 199 -------------------------------------------- 3 files changed, 2 insertions(+), 346 deletions(-) delete mode 100644 cpu/mpc86xx/pci.c delete mode 100644 cpu/mpc86xx/pcie_indirect.c (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index fffcfd2..6d9300e 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -1,4 +1,5 @@ # +# Copyright 2007 Freescale Semiconductor, Inc. # (C) Copyright 2002,2003 Motorola Inc. # Xianghua Xiao,X.Xiao@motorola.com # @@ -30,7 +31,7 @@ LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o pcie_indirect.o spd_sdram.o + spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c deleted file mode 100644 index b86548d..0000000 --- a/cpu/mpc86xx/pci.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor,Inc. - * 2005, 2006. All rights reserved. - * - * Ed Swarthout (ed.swarthout@freescale.com) - * Jason Jin (Jason.jin@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCIE Configuration space access support for PCIE Bridge - */ -#include -#include - -#if defined(CONFIG_PCI) -void -pci_mpc86xx_init(struct pci_controller *hose) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_pex_t *pcie1 = &immap->im_pex1; - u16 temp16; - u32 temp32; - - volatile ccsr_gur_t *gur = &immap->im_gur; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); - uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || - io_sel == 7 || io_sel == 0xf) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - printf("PCI-EXPRESS 1: Configured as %s \n", - pcie1_agent ? "Agent" : "Host"); - if (pcie1_agent) - return; /*Don't scan bus when configured as agent */ - printf(" Scanning PCIE bus"); - debug("0x%08x=0x%08x ", - &pcie1->pme_msg_det, - pcie1->pme_msg_det); - if (pcie1->pme_msg_det) { - pcie1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pcie1->pme_msg_det); - } - debug("\n"); - } else { - printf("PCI-EXPRESS 1 disabled!\n"); - return; - } - - /* - * Set first_bus=0 only skipped B0:D0:F0 which is - * a reserved device in M1575, but make it easy for - * most of the scan process. - */ - hose->first_busno = 0x00; - hose->last_busno = 0xfe; - - pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); - - pci_hose_read_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); - - pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, - PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); - - pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - &temp32); - temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); - pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - temp32); - - pcie1->powar1 = 0; - pcie1->powar2 = 0; - pcie1->piwar1 = 0; - pcie1->piwar1 = 0; - - pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->powar1 = 0x8004401c; /* 512M MEM space */ - pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->potear1 = 0x00000000; - - pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcie1->powar2 = 0x80088017; /* 16M IO space */ - pcie1->potar2 = 0x00000000; - pcie1->potear2 = 0x00000000; - - pcie1->pitar1 = 0x00000000; - pcie1->piwbar1 = 0x00000000; - /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ - pcie1->piwar1 = 0xa0f5501e; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); - debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); - - printf("....PCIE1 scan & enumeration done\n"); -} -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c deleted file mode 100644 index b00ad76..0000000 --- a/cpu/mpc86xx/pcie_indirect.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Support for indirect PCI bridges. - * - * Copyright (c) Freescale Semiconductor, Inc. - * 2006. All rights reserved. - * - * Jason Jin - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * partly derived from - * arch/powerpc/platforms/86xx/mpc86xx_pcie.c - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include - -#define PCI_CFG_OUT out_be32 -#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) - -static int -indirect_read_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 *val) -{ - int bus = PCI_BUS(dev); - - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - switch (len) { - case 1: - *val = (temp >> (((offset & 3)) * 8)) & 0xff; - break; - case 2: - *val = (temp >> (((offset & 3)) * 8)) & 0xffff; - break; - default: - *val = temp; - break; - } - - return 0; -} - -static int -indirect_write_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 val) -{ - int bus = PCI_BUS(dev); - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - switch (len) { - case 1: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xff << ((offset & 3) * 8))) | - (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - case 2: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xffff << ((offset & 3) * 8))); - temp |= (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - default: - PEX_FIX; - out_le32((u32 *) cfg_data, val); - break; - } - PEX_FIX; - return 0; -} - -static int -indirect_read_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 1, &val32); - *val = (u8) val32; - return 0; -} - -static int -indirect_read_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u16 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 2, &val32); - *val = (u16) val32; - return 0; -} - -static int -indirect_read_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 *val) -{ - return indirect_read_config_pcie(hose, dev, offset, 4, val); -} - -static int -indirect_write_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); -} - -static int -indirect_write_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - unsigned short val) -{ - return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); -} - -static int -indirect_write_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 4, val); -} - -void -pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) -{ - pci_set_ops(hose, - indirect_read_config_byte_pcie, - indirect_read_config_word_pcie, - indirect_read_config_dword_pcie, - indirect_write_config_byte_pcie, - indirect_write_config_word_pcie, - indirect_write_config_dword_pcie); - - hose->cfg_addr = (unsigned int *)cfg_addr; - hose->cfg_data = (unsigned char *)cfg_data; -} - -#endif /* CONFIG_PCI */ -- cgit v1.1 From cfc7a7f5bb3273c9951173c788001d45118f141f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 2 Aug 2007 14:42:20 -0500 Subject: cpu/86xx fixes. Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- cpu/mpc86xx/cpu_init.c | 4 +-- cpu/mpc86xx/interrupts.c | 51 ++++++++++++++++------------- cpu/mpc86xx/start.S | 85 ++++++++---------------------------------------- cpu/mpc86xx/traps.c | 8 +++-- 4 files changed, 51 insertions(+), 97 deletions(-) (limited to 'cpu/mpc86xx') diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 4673d05..c8e4666 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -104,8 +104,8 @@ void cpu_init_f(void) /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); - /* enable SYNCBE | ABE bits in HID1 */ - set_hid1(get_hid1() | 0x00000C00); + /* enable EMCP, SYNCBE | ABE bits in HID1 */ + set_hid1(get_hid1() | 0x80000C00); } /* diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 08e0675..d9f634f 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -8,7 +8,7 @@ * (C) Copyright 2003 Motorola Inc. (MPC85xx port) * Xianghua Xiao (X.Xiao@motorola.com) * - * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) + * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port) * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -80,25 +80,10 @@ int interrupt_init(void) { int ret; - /* - * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to - * implement PEX10 errata. As INT is active high, it - * will cause core to take 0x500 interrupt. - * - * Due to the PIC's default pass through mode, as soon - * as interrupts are enabled (MSR[EE] = 1), an interrupt - * will be taken and u-boot will hang. This is due to a - * hardware change (per an errata fix) on new revisions - * of the board with Rev 2.x parts. - * - * Setting the PIC to mixed mode prevents the hang. - */ - if ((get_svr() & 0xf0) == 0x20) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; - immr->im_pic.gcr = MPC86xx_PICGCR_RST; - while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); - immr->im_pic.gcr = MPC86xx_PICGCR_MODE; - } + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); @@ -119,6 +104,30 @@ int interrupt_init(void) get_msr(), get_dec()); +#ifdef CONFIG_INTERRUPTS + volatile ccsr_pic_t *pic = &immr->im_pic; + + pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ + debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3); + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1) + pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ + debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ + debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9); +#endif + + pic->ctpr = 0; /* 40080 clear current task priority register */ +#endif + return 0; } @@ -158,8 +167,6 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; - ppcDcbf((unsigned long)×tamp); - /* Restore Decrementer Count */ set_dec(decrementer_count); diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 412745b..c83310a 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Srikanth Srinivasan * * See file CREDITS for list of people who contributed to this @@ -44,11 +44,9 @@ #define CONFIG_IDENT_STRING "" #endif -/* We don't want the MMU yet. -*/ -#undef MSR_KERNEL -/* Machine Check and Recoverable Interr. */ -#define MSR_KERNEL ( MSR_ME | MSR_RI ) +/* + * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions + */ /* * Set up GOT: Global Offset Table @@ -195,17 +193,21 @@ boot_warm: bl secondary_cpu_setup #endif +1: +#ifdef CFG_RAMBOOT /* disable everything */ -1: li r0, 0 + li r0, 0 mtspr HID0, r0 sync mtmsr 0 +#endif + bl invalidate_bats sync #ifdef CFG_L2 /* init the L2 cache */ - addis r3, r0, L2_INIT@h + lis r3, L2_INIT@h ori r3, r3, L2_INIT@l mtspr l2cr, r3 /* invalidate the L2 cache */ @@ -241,69 +243,9 @@ in_flash: bl setup_ccsrbar #endif - - /* -- MPC8641 Rev 1.0 MCM Errata fixups -- */ - - /* skip fixups if not Rev 1.0 */ - mfspr r4, SVR - rlwinm r4,r4,0,24,31 - cmpwi r4,0x10 - bne 1f - - lis r3,MCM_ABCR@ha - lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */ - - /* set ABCR[A_STRM_CNT] = 0 */ - rlwinm r4,r4,0,0,29 - - /* set ABCR[ARB_POLICY] to 0x1 (round-robin) */ - addi r0,r0,1 - rlwimi r4,r0,12,18,19 - - stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */ - sync - - /* Set DBCR[ERD_DIS] */ - lis r3,MCM_DBCR@ha - lwz r4,MCM_DBCR@l(r3) - oris r4, r4, 0x4000 - stw r4,MCM_DBCR@l(r3) - sync -1: /* setup the law entries */ bl law_entry sync - - -#if (EMULATOR_RUN == 1) - /* On the emulator we want to adjust these ASAP */ - /* otherwise things are sloooow */ - /* Setup OR0 (LALE FIX)*/ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x5004 - li r4, 0x0FF3 - stw r4, 0(r3) - sync - - /* Setup LCRR */ - lis r3, CFG_CCSRBAR@h - ori r3, r3, 0x50D4 - lis r4, 0x8000 - ori r4, r4, 0x0002 - stw r4, 0(r3) - sync -#endif -#if 1 - /* make sure timer enabled in guts register too */ - lis r3, CFG_CCSRBAR@h - oris r3,r3, 0xE - ori r3,r3,0x0070 - lwz r4, 0(r3) - lis r5,0xFFFC - ori r5,r5,0x5FFF - and r4,r4,r5 - stw r4,0(r3) -#endif /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -346,8 +288,6 @@ in_flash: #ifdef RUN_DIAG - /* Sri: Code to run the diagnostic automatically */ - /* Load PX_AUX register address in r4 */ lis r4, 0xf810 ori r4, r4, 0x6 @@ -392,6 +332,7 @@ diag_done: .globl invalidate_bats invalidate_bats: + li r0, 0 /* invalidate BATs */ mtspr IBAT0U, r0 mtspr IBAT1U, r0 @@ -1040,6 +981,7 @@ trap_init: mfmsr r7 li r8,MSR_IP andc r7,r7,r8 + ori r7,r7,MSR_ME /* Enable Machine Check */ mtmsr r7 mtlr r4 /* restore link register */ @@ -1224,8 +1166,9 @@ secondary_cpu_setup: sync isync - /*SYNCBE|ABE in HID1*/ + /* MCP|SYNCBE|ABE in HID1 */ mfspr r4, HID1 + oris r4, r4, 0x8000 ori r4, r4, 0x0C00 mtspr HID1, r4 sync diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index fab1975..c84bfbf 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -130,8 +130,11 @@ MachineCheckException(struct pt_regs *regs) printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); printf("regs %p ", regs); - switch (regs->msr & 0x000F0000) { - case (0x80000000 >> 12): + switch ( regs->msr & 0x001F0000) { + case (0x80000000>>11): + printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); + break; + case (0x80000000>>12): printf("Machine check signal - probably due to mm fault\n" "with mmu off\n"); break; @@ -209,6 +212,7 @@ UnknownException(struct pt_regs *regs) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; #endif + printf("UnknownException regs@%x\n", regs); printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", regs->nip, regs->msr, regs->trap); _exception(0, regs); -- cgit v1.1