From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/mpc85xx/commproc.c | 16 ++++---- cpu/mpc85xx/cpu.c | 18 ++++----- cpu/mpc85xx/cpu_init.c | 88 ++++++++++++++++++++++---------------------- cpu/mpc85xx/ddr-gen1.c | 4 +- cpu/mpc85xx/ddr-gen2.c | 2 +- cpu/mpc85xx/ddr-gen3.c | 4 +- cpu/mpc85xx/ether_fcc.c | 26 ++++++------- cpu/mpc85xx/fdt.c | 6 +-- cpu/mpc85xx/interrupts.c | 4 +- cpu/mpc85xx/mp.c | 10 ++--- cpu/mpc85xx/mpc8536_serdes.c | 4 +- cpu/mpc85xx/pci.c | 62 +++++++++++++++---------------- cpu/mpc85xx/qe_io.c | 2 +- cpu/mpc85xx/serial_scc.c | 8 ++-- cpu/mpc85xx/speed.c | 6 +-- cpu/mpc85xx/start.S | 48 ++++++++++++------------ cpu/mpc85xx/tlb.c | 2 +- cpu/mpc85xx/traps.c | 2 +- 18 files changed, 156 insertions(+), 156 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index b0ecd25..fff8dff 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -37,10 +37,10 @@ DECLARE_GLOBAL_DATA_PTR; void m8560_cpm_reset(void) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile ulong count; - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Reclaim the DP memory for our use. */ @@ -64,7 +64,7 @@ m8560_cpm_reset(void) uint m8560_cpm_dpalloc(uint size, uint align) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; uint retloc; uint align_mask, off; uint savebase; @@ -120,7 +120,7 @@ m8560_cpm_hostalloc(uint size, uint align) void m8560_cpm_setbrg(uint brg, uint rate) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... @@ -142,7 +142,7 @@ m8560_cpm_setbrg(uint brg, uint rate) void m8560_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile uint *bp; /* This is good enough to get SMCs running..... @@ -167,7 +167,7 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16) void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile uint *bp; if (brg < 4) { @@ -190,7 +190,7 @@ m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) void post_word_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); *save_addr = a; } @@ -198,7 +198,7 @@ void post_word_store (ulong a) ulong post_word_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR); return *save_addr; } diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index f15b0a8..61162a8 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -84,7 +84,7 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else @@ -151,11 +151,11 @@ int checkcpu (void) break; } -#if defined(CFG_LBC_LCRR) - lcrr = CFG_LBC_LCRR; +#if defined(CONFIG_SYS_LBC_LCRR) + lcrr = CONFIG_SYS_LBC_LCRR; #else { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } @@ -200,7 +200,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ udelay(100); } @@ -256,7 +256,7 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; @@ -266,7 +266,7 @@ void dma_init(void) { } uint dma_check(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -285,7 +285,7 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->dar0 = (uint) dest; dma->sar0 = (uint) src; @@ -306,7 +306,7 @@ void upmconfig (uint upm, uint * table, uint size) { int i, mdr, mad, old_mad = 0; volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile u32 *brp,*orp; volatile u8* dummy = NULL; int upmmask; diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 783c5ba..3a8aef2 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -132,28 +132,28 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) { u32 temp; - set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, + set_tlb(0, CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 1, BOOKE_PAGESZ_4K, 0); - temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT); + out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CFG_CCSRBAR); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); } #endif /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); @@ -172,69 +172,69 @@ void cpu_init_early_f(void) void cpu_init_f (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); disable_tlb(14); disable_tlb(15); #ifdef CONFIG_CPM2 - config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); + config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); #endif /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary * addresses - these have to be modified later when FLASH size * has been determined */ -#if defined(CFG_OR0_REMAP) - memctl->or0 = CFG_OR0_REMAP; +#if defined(CONFIG_SYS_OR0_REMAP) + memctl->or0 = CONFIG_SYS_OR0_REMAP; #endif -#if defined(CFG_OR1_REMAP) - memctl->or1 = CFG_OR1_REMAP; +#if defined(CONFIG_SYS_OR1_REMAP) + memctl->or1 = CONFIG_SYS_OR1_REMAP; #endif /* now restrict to preliminary range */ /* if cs1 is already set via debugger, leave cs0/cs1 alone */ if (! memctl->br1 & 1) { -#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; +#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) + memctl->br0 = CONFIG_SYS_BR0_PRELIM; + memctl->or0 = CONFIG_SYS_OR0_PRELIM; #endif -#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) + memctl->or1 = CONFIG_SYS_OR1_PRELIM; + memctl->br1 = CONFIG_SYS_BR1_PRELIM; #endif } -#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) - memctl->or2 = CFG_OR2_PRELIM; - memctl->br2 = CFG_BR2_PRELIM; +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) + memctl->or2 = CONFIG_SYS_OR2_PRELIM; + memctl->br2 = CONFIG_SYS_BR2_PRELIM; #endif -#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) - memctl->or3 = CFG_OR3_PRELIM; - memctl->br3 = CFG_BR3_PRELIM; +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + memctl->or3 = CONFIG_SYS_OR3_PRELIM; + memctl->br3 = CONFIG_SYS_BR3_PRELIM; #endif -#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) - memctl->or4 = CFG_OR4_PRELIM; - memctl->br4 = CFG_BR4_PRELIM; +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) + memctl->or4 = CONFIG_SYS_OR4_PRELIM; + memctl->br4 = CONFIG_SYS_BR4_PRELIM; #endif -#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) - memctl->or5 = CFG_OR5_PRELIM; - memctl->br5 = CFG_BR5_PRELIM; +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) + memctl->or5 = CONFIG_SYS_OR5_PRELIM; + memctl->br5 = CONFIG_SYS_BR5_PRELIM; #endif -#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM) - memctl->or6 = CFG_OR6_PRELIM; - memctl->br6 = CFG_BR6_PRELIM; +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) + memctl->or6 = CONFIG_SYS_OR6_PRELIM; + memctl->br6 = CONFIG_SYS_BR6_PRELIM; #endif -#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM) - memctl->or7 = CFG_OR7_PRELIM; - memctl->br7 = CFG_BR7_PRELIM; +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) + memctl->or7 = CONFIG_SYS_OR7_PRELIM; + memctl->br7 = CONFIG_SYS_BR7_PRELIM; #endif #if defined(CONFIG_CPM2) @@ -264,7 +264,7 @@ int cpu_init_r(void) puts ("L2: "); #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; uint l2srbar; @@ -317,13 +317,13 @@ int cpu_init_r(void) if (l2cache->l2ctl & 0x80000000) { puts("already enabled"); l2srbar = l2cache->l2srbar0; -#ifdef CFG_INIT_L2_ADDR - if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { - l2srbar = CFG_INIT_L2_ADDR; +#ifdef CONFIG_SYS_INIT_L2_ADDR + if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE) { + l2srbar = CONFIG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf("moving to 0x%08x", CFG_INIT_L2_ADDR); + printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); } -#endif /* CFG_INIT_L2_ADDR */ +#endif /* CONFIG_SYS_INIT_L2_ADDR */ puts("\n"); } else { asm("msync;isync"); @@ -335,7 +335,7 @@ int cpu_init_r(void) puts("disabled\n"); #endif #ifdef CONFIG_QE - uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ qe_init(qe_base); qe_reset(); #endif diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c index 2c11ee4..e24c9af 100644 --- a/cpu/mpc85xx/ddr-gen1.c +++ b/cpu/mpc85xx/ddr-gen1.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; if (ctrl_num != 0) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); @@ -79,7 +79,7 @@ ddr_enable_ecc(unsigned int dram_size) { uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_init(); diff --git a/cpu/mpc85xx/ddr-gen2.c b/cpu/mpc85xx/ddr-gen2.c index 130090c..655f99c 100644 --- a/cpu/mpc85xx/ddr-gen2.c +++ b/cpu/mpc85xx/ddr-gen2.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; if (ctrl_num) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index d7cc9db..e0654bb 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, switch (ctrl_num) { case 0: - ddr = (void *)CFG_MPC85xx_DDR_ADDR; + ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; break; case 1: - ddr = (void *)CFG_MPC85xx_DDR2_ADDR; + ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; break; default: printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index bd62aab..32ad469 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -74,8 +74,8 @@ static struct ether_fcc_info_s PROFF_FCC1, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, - CFG_CMXFCR_MASK1, - CFG_CMXFCR_VALUE1 + CONFIG_SYS_CMXFCR_MASK1, + CONFIG_SYS_CMXFCR_VALUE1 }, #endif @@ -85,8 +85,8 @@ static struct ether_fcc_info_s PROFF_FCC2, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, - CFG_CMXFCR_MASK2, - CFG_CMXFCR_VALUE2 + CONFIG_SYS_CMXFCR_MASK2, + CONFIG_SYS_CMXFCR_VALUE2 }, #endif @@ -96,8 +96,8 @@ static struct ether_fcc_info_s PROFF_FCC3, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, - CFG_CMXFCR_MASK3, - CFG_CMXFCR_VALUE3 + CONFIG_SYS_CMXFCR_MASK3, + CONFIG_SYS_CMXFCR_VALUE3 }, #endif }; @@ -230,7 +230,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -257,11 +257,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 1){ - cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 2){ - cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; } /* 28.9 - (6): FDSR: Ethernet Syn */ @@ -321,14 +321,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis) pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ /* localbus SDRAM should be preferred */ pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); pram_ptr->fen_genfcc.fcc_rbdstat = 0; pram_ptr->fen_genfcc.fcc_rbdlen = 0; pram_ptr->fen_genfcc.fcc_rdptr = 0; /* localbus SDRAM should be preferred */ pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CFG_CPMFCR_RAMTYPE) << 24; + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); pram_ptr->fen_genfcc.fcc_tbdstat = 0; pram_ptr->fen_genfcc.fcc_tbdlen = 0; @@ -426,7 +426,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; /* write GFMR: disable tx/rx */ if(info->ether_index == 0) { diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 037a60f..3c8fbd8 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -83,7 +83,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) /* return size in kilobytes */ static inline u32 l2cache_size(void) { - volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; u32 ver = SVR_SOC_VER(get_svr()); @@ -224,9 +224,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_qe_setup(blob); #endif -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CFG_NS16550_CLK, 1); + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_CPM2 diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index d702ca6..4ef8395 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -34,14 +34,14 @@ int interrupt_init_cpu(unsigned long *decrementer_count) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); pic->gcr = MPC85xx_PICGCR_RST; while (pic->gcr & MPC85xx_PICGCR_RST) ; pic->gcr = MPC85xx_PICGCR_M; - *decrementer_count = get_tbclk() / CFG_HZ; + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; /* PIE is same as DIE, dec interrupt enable */ mtspr(SPRN_TCR, TCR_PIE); diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 4e09c9c..3338c1a 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -36,7 +36,7 @@ u32 get_my_id() int cpu_reset(int nr) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); (void)in_be32(&pic->pir); out_be32(&pic->pir, 0x0); @@ -87,7 +87,7 @@ int cpu_release(int nr, int argc, char *argv[]) return 1; } -#ifdef CFG_64BIT_STRTOUL +#ifdef CONFIG_SYS_64BIT_STRTOUL boot_addr = simple_strtoull(argv[0], NULL, 16); #else boot_addr = simple_strtoul(argv[0], NULL, 16); @@ -129,9 +129,9 @@ static void pq3_mp_up(unsigned long bootpg) u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_addr(); volatile u32 bpcr; - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/cpu/mpc85xx/mpc8536_serdes.c b/cpu/mpc85xx/mpc8536_serdes.c index ae091e6..d9ac466 100644 --- a/cpu/mpc85xx/mpc8536_serdes.c +++ b/cpu/mpc85xx/mpc8536_serdes.c @@ -54,8 +54,8 @@ void fsl_serdes_init(void) { - void *guts = (void *)(CFG_MPC85xx_GUTS_ADDR); - void *sd = (void *)CFG_MPC85xx_SERDES2_ADDR; + void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR; u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); u32 srds2_io_sel; u32 tmp; diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index fdc4c83..112f18c 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -39,11 +39,11 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u16 reg16; u32 dev; - volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); #ifdef CONFIG_MPC85XX_PCI2 - volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR); + volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR); #endif - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct pci_controller * hose; pci_hose = board_hose; @@ -54,8 +54,8 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = 0xff; pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); + (CONFIG_SYS_IMMR+0x8000), + (CONFIG_SYS_IMMR+0x8004)); /* * Hose scan. @@ -80,19 +80,19 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); } - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff; pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; + pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1)); + POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1)); - pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; + pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; pcix->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1)); + POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1)); pcix->pitar1 = 0x00000000; pcix->piwbar1 = 0x00000000; @@ -105,15 +105,15 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix->piwar3 = 0; pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = 2; @@ -152,8 +152,8 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = 0xff; pci_setup_indirect(hose, - (CFG_IMMR+0x9000), - (CFG_IMMR+0x9004)); + (CONFIG_SYS_IMMR+0x9000), + (CONFIG_SYS_IMMR+0x9004)); dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); @@ -165,19 +165,19 @@ pci_mpc85xx_init(struct pci_controller *board_hose) */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff; + pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff; pcix2->potear1 = 0x00000000; - pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; + pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff; pcix2->powbear1 = 0x00000000; pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1)); + POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1)); - pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; + pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff; pcix2->potear2 = 0x00000000; - pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; + pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff; pcix2->powbear2 = 0x00000000; pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1)); + POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1)); pcix2->pitar1 = 0x00000000; pcix2->piwbar1 = 0x00000000; @@ -190,15 +190,15 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix2->piwar3 = 0; pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); hose->region_count = 2; diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c index 21ea38b..72a29b7 100644 --- a/cpu/mpc85xx/qe_io.c +++ b/cpu/mpc85xx/qe_io.c @@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io); diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 7ee3cc8..05fb808 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -88,7 +88,7 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; volatile ccsr_cpm_scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -201,7 +201,7 @@ serial_putc(const char c) { volatile scc_uart_t *up; volatile cbd_t *tbdf; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; if (c == '\n') serial_putc ('\r'); @@ -234,7 +234,7 @@ serial_getc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; unsigned char c; up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); @@ -258,7 +258,7 @@ serial_tstc() { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 70dfad0..d9f9a8c 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; plat_ratio = (gur->porpllsr) & 0x0000003e; @@ -67,10 +67,10 @@ int get_clocks (void) { sys_info_t sys_info; #ifdef CONFIG_MPC8544 - volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR; + volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; #endif #if defined(CONFIG_CPM2) - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; uint sccr, dfbrg; /* set VCO = 4 * BRG */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 10fe936..25d0390 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -172,12 +172,12 @@ _start_e500: mtspr BUCSR,r0 #endif -#if defined(CFG_INIT_DBCR) +#if defined(CONFIG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CFG_INIT_DBCR@l + lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CONFIG_SYS_INIT_DBCR@l mtspr DBCR0,r0 #endif @@ -210,11 +210,11 @@ _start_e500: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l - lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h - ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l - lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l mtspr MAS0,r6 mtspr MAS1,r7 @@ -238,8 +238,8 @@ switch_as: /* Allocate Initial RAM in data cache. */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l mfspr r2, L1CFG0 andi. r2, r2, 0x1ff /* cache size * 1024 / (2 * L1 line size) */ @@ -249,17 +249,17 @@ switch_as: 1: dcbz r0,r3 dcbtls 0,r0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b /* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CFG_RAMBOOT +#ifdef CONFIG_SYS_RAMBOOT b _start_cont #else /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3,CFG_MONITOR_BASE@h - ori r3,r3,CFG_MONITOR_BASE@l + lis r3,CONFIG_SYS_MONITOR_BASE@h + ori r3,r3,CONFIG_SYS_MONITOR_BASE@l addi r3,r3,_start_cont - _start + _START_OFFSET mtlr r3 blr @@ -279,8 +279,8 @@ version_string: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + lis r1,CONFIG_SYS_INIT_RAM_ADDR@h + ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l li r0,0 stwu r0,-4(r1) @@ -778,16 +778,16 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ mr r3,r5 /* Destination Address */ - lis r4,CFG_MONITOR_BASE@h /* Source Address */ - ori r4,r4,CFG_MONITOR_BASE@l + lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4,r4,CONFIG_SYS_MONITOR_BASE@l lwz r5,GOT(__init_end) sub r5,r5,r4 - li r6,CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -996,20 +996,20 @@ trap_reloc: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CFG_INIT_RAM_ADDR & ~31)@h - ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l + lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync /* Invalidate the TLB entries for the cache */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l tlbivax 0,r3 addi r3,r3,0x1000 tlbivax 0,r3 diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 7ce7a14..a2d16ae 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -138,7 +138,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) * Starting at TLB1 8, use no more than 8 TLB1 entries. */ ram_tlb_index = 8; - ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; + ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 0eab694..1045cc1 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -290,7 +290,7 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); uint vect; -- cgit v1.1 From 54e091d3b603a3332c619199ca83a07e95960da4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 22 Sep 2008 14:11:10 -0500 Subject: 85xx: Export invalidate_{i,d}cache and add flush_dcache Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 25d0390..fc3c336 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -565,6 +565,7 @@ mck_return: /* Cache functions. */ +.globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 ori r0,r0,L1CSR1_ICFI @@ -574,6 +575,7 @@ invalidate_icache: isync blr /* entire I cache */ +.globl invalidate_dcache invalidate_dcache: mfspr r0,L1CSR0 ori r0,r0,L1CSR0_DCFI @@ -1019,3 +1021,50 @@ unlock_ram_in_cache: tlbivax 0,r3 isync blr + +.globl flush_dcache +flush_dcache: + mfspr r3,SPRN_L1CFG0 + + rlwinm r5,r3,9,3 /* Extract cache block size */ + twlgti r5,1 /* Only 32 and 64 byte cache blocks + * are currently defined. + */ + li r4,32 + subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - + * log2(number of ways) + */ + slw r5,r4,r5 /* r5 = cache block size */ + + rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ + mulli r7,r7,13 /* An 8-way cache will require 13 + * loads per set. + */ + slw r7,r7,r6 + + /* save off HID0 and set DCFA */ + mfspr r8,SPRN_HID0 + ori r9,r8,HID0_DCFA@l + mtspr SPRN_HID0,r9 + isync + + lis r4,0 + mtctr r7 + +1: lwz r3,0(r4) /* Load... */ + add r4,r4,r5 + bdnz 1b + + msync + lis r4,0 + mtctr r7 + +1: dcbf 0,r4 /* ...and flush. */ + add r4,r4,r5 + bdnz 1b + + /* restore HID0 */ + mtspr SPRN_HID0,r8 + isync + + blr -- cgit v1.1 From 0e17f02a8a78d85225a4d805f6a1ea95a0a460b5 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 7 Oct 2008 08:09:50 -0500 Subject: Have u-boot pass stashing parameters into device tree Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming --- cpu/mpc85xx/fdt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 3c8fbd8..59aafb1 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -201,6 +201,15 @@ static inline void ft_fixup_cache(void *blob) } +void fdt_add_enet_stashing(void *fdt) +{ + do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); +} + void ft_cpu_setup(void *blob, bd_t *bd) { /* delete crypto node if not on an E-processor */ @@ -210,6 +219,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) fdt_fixup_ethernet(blob); + + fdt_add_enet_stashing(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, -- cgit v1.1 From 6856b3d0221a838580e6bb06f61425fd7529ba93 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 8 Oct 2008 23:37:59 -0500 Subject: 85xx if NUM_CPUS>1, print cpu number Signed-off-by: Ed Swarthout --- cpu/mpc85xx/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 61162a8..9c4f214 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -99,7 +99,12 @@ int checkcpu (void) #endif minor = SVR_MIN(svr); +#if (CONFIG_NUM_CPUS > 1) + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); +#else puts("CPU: "); +#endif cpu = identify_cpu(ver); if (cpu) { -- cgit v1.1