From 87c7661b42aa7672539b54b51d3d5c4013ec6f6c Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Fri, 31 Jul 2009 12:08:27 +0530 Subject: 85xx: Added P1020 Processor Support. P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 8809302..1477eac 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -48,8 +48,9 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o -COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o +COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ -- cgit v1.1