From 3dd7f0f0ca1720aee5d8b1b40fd2ae093deb81a0 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Mon, 4 Apr 2005 23:43:44 +0000
Subject: * Add FEC support for TQM8540 board.   Interfaces are named as
 follows: "ENET1" - TSEC2, "ENET2" - FEC

* Patch by Martin Krause, 04 Apr 2005:
  Update default configuration for CMC_PU2 board.
---
 cpu/mpc85xx/tsec.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++----
 cpu/mpc85xx/tsec.h |  8 ++++++++
 2 files changed, 57 insertions(+), 4 deletions(-)

(limited to 'cpu/mpc85xx')

diff --git a/cpu/mpc85xx/tsec.c b/cpu/mpc85xx/tsec.c
index 992475c..eee5f25 100644
--- a/cpu/mpc85xx/tsec.c
+++ b/cpu/mpc85xx/tsec.c
@@ -277,7 +277,21 @@ static int init_phy(struct eth_device *dev)
 	struct phy_info *curphy;
 
 	/* Assign a Physical address to the TBI */
-	priv->regs->tbipa=TBIPA_VALUE;
+	
+	{
+		volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
+		regs->tbipa = TBIPA_VALUE;
+		regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
+		regs->tbipa = TBIPA_VALUE;
+		asm("msync");
+	}
+
+	/* Reset MII (due to new addresses) */
+	priv->phyregs->miimcfg = MIIMCFG_RESET;
+	asm("msync");
+	priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
+	asm("msync");
+	while(priv->phyregs->miimind & MIIMIND_BUSY);
 
 	if(0 == relocated)
 		relocate_cmds();
@@ -793,19 +807,50 @@ struct phy_info phy_info_dm9161 = {
 	},
 };
 
+uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
+{
+        unsigned int speed;
+        if (priv->link) {
+                speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
+
+                switch (speed) {
+                case MIIM_LXT971_SR2_10HDX:
+                        priv->speed = 10;
+                        priv->duplexity = 0;
+                        break;
+                case MIIM_LXT971_SR2_10FDX:
+                        priv->speed = 10;
+                        priv->duplexity = 1;
+                        break;
+                case MIIM_LXT971_SR2_100HDX:
+                        priv->speed = 100;
+                        priv->duplexity = 0;
+                default:
+                        priv->speed = 100;
+                        priv->duplexity = 1;
+                        break;
+                }
+        } else {
+                priv->speed = 0;
+                priv->duplexity = 0;
+        }
+
+        return 0;
+}
+
 static struct phy_info phy_info_lxt971 = {
 	0x0001378e,
 	"LXT971",
 	4,
 	(struct phy_cmd []) {  /* config */
-		{ MIIM_CONTROL, MIIM_CONTROL_INIT, mii_cr_init }, /* autonegotiate */
+		{ MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
 		{ miim_end, }
 	},
 	(struct phy_cmd []) {  /* startup - enable interrupts */
 		/* { 0x12, 0x00f2, NULL }, */
-		{ 0x14, 0xd422, NULL }, /* LED config */
 		{ MIIM_STATUS, miim_read, NULL },
-		{ MIIM_STATUS, miim_read, mii_parse_sr },
+		{ MIIM_STATUS, miim_read, &mii_parse_sr },
+		{ MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
 		{ miim_end, }
 	},
 	(struct phy_cmd []) {  /* shutdown - disable interrupts */
diff --git a/cpu/mpc85xx/tsec.h b/cpu/mpc85xx/tsec.h
index 275bbd2..e24351a 100644
--- a/cpu/mpc85xx/tsec.h
+++ b/cpu/mpc85xx/tsec.h
@@ -142,6 +142,14 @@
 #define MIIM_DM9161_10BTCSR	0x12
 #define MIIM_DM9161_10BTCSR_INIT	0x7800
 
+/* LXT971 Status 2 registers */
+#define MIIM_LXT971_SR2       	17  /* Status Register 2  */
+#define MIIM_LXT971_SR2_SPEED_MASK	0xf000
+#define MIIM_LXT971_SR2_10HDX	0x1000  /* 10 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_10FDX	0x2000  /* 10 Mbit full duplex selected */
+#define MIIM_LXT971_SR2_100HDX	0x4000  /* 100 Mbit half duplex selected */
+#define MIIM_LXT971_SR2_100FDX	0x8000  /* 100 Mbit full duplex selected */
+
 #define MIIM_READ_COMMAND       0x00000001
 
 #define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
-- 
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