From a38a5b6edd30f29fd5fdb1d7f674521906c0e677 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 23 Oct 2008 01:47:37 -0500 Subject: 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx/start.S') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index fc3c336..f16d4c0 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -998,8 +998,8 @@ trap_reloc: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l + lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) -- cgit v1.1 From 0f060c3bf82832331a509f2e5d2442539e7aad09 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 23 Oct 2008 01:47:38 -0500 Subject: 85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu/mpc85xx/start.S') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index f16d4c0..651ff1c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -163,8 +163,10 @@ _start_e500: ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0 +#ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mtspr HID1,r0 +#endif /* Enable Branch Prediction */ #if defined(CONFIG_BTB) -- cgit v1.1