From b3d7f20f43a0f8d11c65e2f92153b5512b11580c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 20 May 2009 12:30:29 -0400 Subject: 85xx: Add QE clk support Signed-off-by: Haiying Wang Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'cpu/mpc85xx/speed.c') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index b0f47e0..286b6b2 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor Inc. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo) uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; +#ifdef CONFIG_QE + u32 qe_ratio; +#endif plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; @@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif +#ifdef CONFIG_QE + qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) + >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; + sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; +#endif + #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; @@ -112,6 +121,10 @@ int get_clocks (void) gd->mem_clk = sys_info.freqDDRBus; gd->lbc_clk = sys_info.freqLocalBus; +#ifdef CONFIG_QE + gd->qe_clk = sys_info.freqQE; + gd->brg_clk = gd->qe_clk / 2; +#endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, * there is no pattern that can be used to determine the frequency, so -- cgit v1.1