From 29372ff38c5baab7d0e3a8c14fe11fa194a38704 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:47 -0500 Subject: mpc85xx L2 cache reporting and SRAM relocation option. Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 65 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 18 deletions(-) (limited to 'cpu/mpc85xx/cpu_init.c') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9517146..888417f 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,4 +1,6 @@ /* + * Copyright 2007 Freescale Semiconductor. + * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com * @@ -133,15 +135,18 @@ void cpu_init_f (void) #endif /* now restrict to preliminary range */ + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (! memctl->br1 & 1) { #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; #endif + } #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; @@ -185,16 +190,23 @@ void cpu_init_f (void) * The newer 8548, etc, parts have twice as much cache, but * use the same bit-encoding as the older 8555, etc, parts. * - * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? */ int cpu_init_r(void) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; + +#ifdef CONFIG_CLEAR_LAW0 + /* clear alternate boot location LAW (used for sdram, or ddr bank) */ + ecm->lawar0 = 0; +#endif + #if defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; volatile uint cache_ctl; uint svr, ver; + uint l2srbar; svr = get_svr(); ver = SVR_VER(svr); @@ -204,30 +216,47 @@ int cpu_init_r(void) switch (cache_ctl & 0x30000000) { case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E) { + if (ver == SVR_8548 || ver == SVR_8548_E || + ver == SVR_8544) { printf ("L2 cache 512KB:"); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; } else { printf ("L2 cache 256KB:"); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + cache_ctl = 0xc8000000; } break; - case 0x00000000: case 0x10000000: + printf ("L2 cache 256KB:"); + if (ver == SVR_8544 || ver == SVR_8544_E) { + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; case 0x30000000: + case 0x00000000: default: printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); return -1; } - asm("msync;isync"); - l2cache->l2ctl = 0x68000000; /* invalidate */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - printf(" enabled\n"); + if (l2cache->l2ctl & 0x80000000) { + printf(" already enabled."); + l2srbar = l2cache->l2srbar0; +#ifdef CFG_INIT_L2_ADDR + if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { + l2srbar = CFG_INIT_L2_ADDR; + l2cache->l2srbar0 = l2srbar; + printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + } +#endif /* CFG_INIT_L2_ADDR */ + puts("\n"); + } else { + asm("msync;isync"); + l2cache->l2ctl = cache_ctl; /* invalidate & enable */ + asm("msync;isync"); + printf(" enabled\n"); + } #else printf("L2 cache: disabled\n"); #endif -- cgit v1.1 From 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:38:06 -0500 Subject: Fix minor 85xx warnings Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'cpu/mpc85xx/cpu_init.c') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 888417f..c7fe130 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -194,10 +194,12 @@ void cpu_init_f (void) int cpu_init_r(void) { +#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE) volatile immap_t *immap = (immap_t *)CFG_IMMR; +#endif +#ifdef CONFIG_CLEAR_LAW0 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; -#ifdef CONFIG_CLEAR_LAW0 /* clear alternate boot location LAW (used for sdram, or ddr bank) */ ecm->lawar0 = 0; #endif -- cgit v1.1 From da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 00:14:25 -0500 Subject: Add support for UEC to 8568 Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'cpu/mpc85xx/cpu_init.c') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c7fe130..7b99610 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -34,6 +34,29 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_QE +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif #ifdef CONFIG_CPM2 static void config_8560_ioports (volatile immap_t * immr) @@ -181,6 +204,11 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif +#ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +#endif + } @@ -262,6 +290,11 @@ int cpu_init_r(void) #else printf("L2 cache: disabled\n"); #endif +#ifdef CONFIG_QE + uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); +#endif return 0; } -- cgit v1.1 From 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 23 Aug 2007 15:20:54 -0400 Subject: Enable L2 cache for MPC8568MDS board The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang --- cpu/mpc85xx/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/mpc85xx/cpu_init.c') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 7b99610..79ad20c 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -247,7 +247,7 @@ int cpu_init_r(void) switch (cache_ctl & 0x30000000) { case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || - ver == SVR_8544) { + ver == SVR_8544 || ver == SVR_8568_E) { printf ("L2 cache 512KB:"); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; -- cgit v1.1