From 79d696fc558b2bcdb8aa8dc6cd7e4ccd22008e21 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Thu, 11 Mar 2004 22:46:36 +0000
Subject: Fix LOWBOOT configuration for MPC5200 with DDR memory

---
 cpu/mpc5xxx/start.S | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

(limited to 'cpu/mpc5xxx/start.S')

diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index a1631f4..559c7f4 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -108,18 +108,19 @@ boot_warm:
 #error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
 #endif /* CFG_RAMBOOT */
 	lis	r4, CFG_DEFAULT_MBAR@h
-	lis	r3,     0x0000FF00@h
-	ori	r3, r3, 0x0000FF00@l
-	stw	r3, 0x4(r4)
-	lis	r3,     0x0000FFFF@h
-	ori	r3, r3, 0x0000FFFF@l
-	stw	r3, 0x8(r4)
+	lis	r3,	START_REG(CFG_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+	stw	r3, 0x4(r4)		/* CS0 start */
+	lis	r3,	STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+
+	stw	r3, 0x8(r4)		/* CS0 stop */
 	lis	r3,     0x00047800@h
 	ori	r3, r3, 0x00047800@l
-	stw	r3, 0x300(r4)
+	stw	r3, 0x300(r4)		/* set timing, CS0/boot conf reg */
 	lis	r3,     0x02010000@h
 	ori	r3, r3, 0x02010000@l
-	stw	r3, 0x54(r4)
+	stw	r3, 0x54(r4)		/* CS0 and Boot enable, IPBI ctrl reg */
 
 	lis     r3,	lowboot_reentry@h
 	ori     r3, r3, lowboot_reentry@l
@@ -127,18 +128,18 @@ boot_warm:
 	blr				/* jump to flash based address */
 
 lowboot_reentry:
-	lis	r3,     0x0000FF00@h
-	ori	r3, r3, 0x0000FF00@l
-	stw	r3, 0x4c(r4)
-	lis	r3,     0x0000FFFF@h
-	ori	r3, r3, 0x0000FFFF@l
-	stw	r3, 0x50(r4)
+	lis	r3,	START_REG(CFG_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+	stw	r3, 0x4c(r4)		/* Boot start */
+	lis	r3,	STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+	stw	r3, 0x50(r4)		/* Boot stop */
 	lis	r3,     0x00047800@h
 	ori	r3, r3, 0x00047800@l
-	stw	r3, 0x300(r4)
+	stw	r3, 0x300(r4)		/* set timing, CS0/boot conf reg */
 	lis	r3,     0x02000001@h
 	ori	r3, r3, 0x02000001@l
-	stw	r3, 0x54(r4)
+	stw	r3, 0x54(r4)		/* Boot enable, CS0 disable, wait state enable */
 #endif	/* CFG_LOWBOOT */
 
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
-- 
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