From e2ad8426624bac457acc6925b6ff408e9bf20466 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Fri, 30 May 2008 00:53:38 +0900 Subject: [MIPS] : Update coprocessor register access macros Signed-off-by: Shinya Kuribayashi --- cpu/mips/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'cpu/mips') diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index e267bba..0f58d25 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size) void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { - write_32bit_cp0_register(CP0_ENTRYLO0, low0); - write_32bit_cp0_register(CP0_PAGEMASK, pagemask); - write_32bit_cp0_register(CP0_ENTRYLO1, low1); - write_32bit_cp0_register(CP0_ENTRYHI, hi); - write_32bit_cp0_register(CP0_INDEX, index); + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); tlb_write_indexed(); } -- cgit v1.1