From e1390801a3c1a2b6d12fa90be368efc19f5b9bfd Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Tue, 25 Mar 2008 11:39:29 +0900 Subject: [MIPS] Request for the 'mips_cache_lock()' removal The initial intension of having mips_cache_lock() was to use the cache as memory for temporary stack use so that a C environment can be set up as early as possible. But now mips_cache_lock() follow lowlevel_init(). We've already have the real memory initilaized at this point, therefore we could/should use it. No reason to lock at all. Other problems: Cache locking is not consistent across MIPS implementaions. Some imple- mentations don't support locking at all. The style of locking varies - some support per line locking, others per way, etc. Some parts use bits in status registers instead of cache ops. Current mips_cache_lock() is not necessarily general-purpose. And this is worthy of special mention; once U-Boot/MIPS locks the lines, they are never get unlocked, so the code relies on whatever gets loaded after U-Boot to re-initialize the cache and clear the locks. We're sup- posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, but leave the situation as it is for a long time. For these reasons, I proposed the removal of mips_cache_lock() from the global start-up code. This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that *things have changed*. If he wants the same behavior as before, he needs to have CFG_INIT_RAM_LOCK_MIPS in his config file. If we don't have any regression report through several releases, then we'll remove codes entirely. Signed-off-by: Shinya Kuribayashi Acked-by: Andrew Dyer --- cpu/mips/start.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu/mips/start.S') diff --git a/cpu/mips/start.S b/cpu/mips/start.S index c92b162..930f9b3 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -267,10 +267,12 @@ reset: /* Set up temporary stack. */ +#ifdef CFG_INIT_RAM_LOCK_MIPS li a0, CFG_INIT_SP_OFFSET la t9, mips_cache_lock jalr t9 nop +#endif li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET la sp, 0(t0) -- cgit v1.1 From 26138623230ca2bad3c78e05a65527ea70c8b688 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Tue, 25 Mar 2008 21:30:07 +0900 Subject: [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init() Move things to appropriate place. Signed-off-by: Shinya Kuribayashi --- cpu/mips/start.S | 8 -------- 1 file changed, 8 deletions(-) (limited to 'cpu/mips/start.S') diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 930f9b3..fde2944 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -240,14 +240,6 @@ reset: 1: lw gp, 0(ra) -#ifdef CONFIG_INCA_IP - /* Disable INCA-IP Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop -#endif - /* Initialize any external memory. */ la t9, lowlevel_init -- cgit v1.1 From d43d43ef2845af309c25a64bb9c2c5fb3261bc23 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Tue, 25 Mar 2008 21:30:07 +0900 Subject: [MIPS] Initialize CP0 Cause before setting up CP0 Status register Without this change, we'll be suffering from deffered WATCH exception once Status.EXL is cleared. Make sure Cause.WP is cleared. Signed-off-by: Shinya Kuribayashi --- cpu/mips/start.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu/mips/start.S') diff --git a/cpu/mips/start.S b/cpu/mips/start.S index fde2944..0ecdd83 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -211,6 +211,9 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI + /* WP(Watch Pending), SW0/1 should be cleared. */ + mtc0 zero, CP0_CAUSE + /* STATUS register */ #ifdef CONFIG_TB0229 li k0, ST0_CU0 @@ -221,9 +224,6 @@ reset: and k0, k1 mtc0 k0, CP0_STATUS - /* CAUSE register */ - mtc0 zero, CP0_CAUSE - /* Init Timer */ mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE -- cgit v1.1 From decaba6f5cf386d569ac3997bebb871b966c6b18 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Tue, 25 Mar 2008 21:30:07 +0900 Subject: [MIPS] Cleanup CP0 Status initialization Add setup_c0_status from Linux. For the moment we disable interrupts, set CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for reset-time configuration and will work well across most processors. Signed-off-by: Shinya Kuribayashi --- cpu/mips/start.S | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) (limited to 'cpu/mips/start.S') diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 0ecdd83..baac2ce 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -27,6 +27,30 @@ #include #include + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -214,15 +238,7 @@ reset: /* WP(Watch Pending), SW0/1 should be cleared. */ mtc0 zero, CP0_CAUSE - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0 k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS + setup_c0_status_reset /* Init Timer */ mtc0 zero, CP0_COUNT -- cgit v1.1