From 83ec20bc4380eebddfde45da6e3a69a92d4db21d Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:21:21 -0500 Subject: ColdFire: MCF52x2 update Signed-off-by: TsiChungLiew --- cpu/mcf52x2/cpu.c | 154 +++++++++++++++++++++++++----------------------------- 1 file changed, 72 insertions(+), 82 deletions(-) (limited to 'cpu/mcf52x2/cpu.c') diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index ce59d39..96fe371 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -28,33 +28,15 @@ #include #include #include +#include #ifdef CONFIG_M5271 -#include -#include -#endif - -#ifdef CONFIG_M5272 -#include -#include -#endif - -#ifdef CONFIG_M5282 -#include -#include -#endif - -#ifdef CONFIG_M5249 -#include -#endif - -#ifdef CONFIG_M5271 /* * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to * determine which one we are running on, based on the Chip Identification * Register (CIR). */ -int checkcpu (void) +int checkcpu(void) { char buf[32]; unsigned short cir; /* Chip Identification Register */ @@ -80,156 +62,164 @@ int checkcpu (void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CFG_CLK)); + cpu_model, prn, strmhz(buf, CFG_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" - " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CFG_CLK)); + " (PIN: 0x%x) rev. %hu, at %s MHz\n", + pin, prn, strmhz(buf, CFG_CLK)); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ mbar_writeByte(MCF_RCM_RCR, - MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); + MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); return 0; }; #if defined(CONFIG_WATCHDOG) -void watchdog_reset (void) +void watchdog_reset(void) { mbar_writeShort(MCF_WTM_WSR, 0x5555); mbar_writeShort(MCF_WTM_WSR, 0xAAAA); } -int watchdog_disable (void) +int watchdog_disable(void) { mbar_writeShort(MCF_WTM_WCR, 0); return (0); } -int watchdog_init (void) +int watchdog_init(void) { mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_WATCHDOG */ #endif #ifdef CONFIG_M5272 -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR); +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); wdp->wdog_wrrr = 0; - udelay (1000); + udelay(1000); /* enable watchdog, set timeout to 0 and wait */ wdp->wdog_wrrr = 1; - while (1); + while (1) ; /* we don't return! */ return 0; }; -int checkcpu(void) { - ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR); +int checkcpu(void) +{ + volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); uchar msk; - char *suf; + char *suf; - puts ("CPU: "); - msk = (*dirp > 28) & 0xf; + puts("CPU: "); + msk = (sysctrl->sc_dir > 28) & 0xf; switch (msk) { - case 0x2: suf = "1K75N"; break; - case 0x4: suf = "3K75N"; break; - default: - suf = NULL; - printf ("Freescale MCF5272 (Mask:%01x)\n", msk); - break; - } + case 0x2: + suf = "1K75N"; + break; + case 0x4: + suf = "3K75N"; + break; + default: + suf = NULL; + printf("Freescale MCF5272 (Mask:%01x)\n", msk); + break; + } if (suf) - printf ("Freescale MCF5272 %s\n", suf); + printf("Freescale MCF5272 %s\n", suf); return 0; }; #if defined(CONFIG_WATCHDOG) /* Called by macro WATCHDOG_RESET */ -void watchdog_reset (void) +void watchdog_reset(void) { - volatile immap_t * regp = (volatile immap_t *)CFG_MBAR; - regp->wdog_reg.wdog_wcr = 0; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdt->wdog_wcr = 0; } -int watchdog_disable (void) +int watchdog_disable(void) { - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ - regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */ + wdt->wdog_wcr = 0; /* reset watchdog counter */ + wdt->wdog_wirr = 0; /* disable watchdog interrupt */ + wdt->wdog_wrrr = 0; /* disable watchdog timer */ - puts ("WATCHDOG:disabled\n"); + puts("WATCHDOG:disabled\n"); return (0); } -int watchdog_init (void) +int watchdog_init(void) { - volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ + wdt->wdog_wirr = 0; /* disable watchdog interrupt */ /* set timeout and enable watchdog */ - regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; - regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ + wdt->wdog_wrrr = + ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + wdt->wdog_wcr = 0; /* reset watchdog counter */ - puts ("WATCHDOG:enabled\n"); + puts("WATCHDOG:enabled\n"); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ - -#endif /* #ifdef CONFIG_M5272 */ +#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_M5272 */ #ifdef CONFIG_M5282 -int checkcpu (void) +int checkcpu(void) { unsigned char resetsource = MCFRESET_RSR; - printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", - MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); - printf ("Reset:%s%s%s%s%s%s%s\n", - (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", - (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", - (resetsource & MCFRESET_RSR_EXT) ? " External" : "", - (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", - (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", - (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", - (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" - ); + printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); + printf("Reset:%s%s%s%s%s%s%s\n", + (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", + (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", + (resetsource & MCFRESET_RSR_EXT) ? " External" : "", + (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", + (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", + (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", + (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { MCFRESET_RCR = MCFRESET_RCR_SOFTRST; return 0; }; #endif -#ifdef CONFIG_M5249 /* test-only: todo... */ -int checkcpu (void) +#ifdef CONFIG_M5249 /* test-only: todo... */ +int checkcpu(void) { char buf[32]; - printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); + printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", + strmhz(buf, CFG_CLK)); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ /* enable watchdog, set timeout to 0 and wait */ mbar_writeByte(MCFSIM_SYPCR, 0xc0); - while (1); + while (1) ; /* we don't return! */ return 0; -- cgit v1.1 From a1436a842654a8d3927d082a8ae9ee0a10da62d7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 13:20:50 -0500 Subject: ColdFire: Add M5253EVBE platform for MCF52x2 Signed-off-by: TsiChungLiew --- cpu/mcf52x2/cpu.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'cpu/mcf52x2/cpu.c') diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 96fe371..71ea408 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -205,7 +205,7 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) }; #endif -#ifdef CONFIG_M5249 /* test-only: todo... */ +#ifdef CONFIG_M5249 int checkcpu(void) { char buf[32]; @@ -225,3 +225,33 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) return 0; }; #endif + +#ifdef CONFIG_M5253 +int checkcpu(void) +{ + char buf[32]; + + unsigned char resetsource = mbar_readLong(SIM_RSR); + printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", + strmhz(buf, CFG_CLK)); + + if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { + printf("Reset:%s%s\n", + (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" + : "", + (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : + ""); + } + return 0; +} + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + /* enable watchdog, set timeout to 0 and wait */ + mbar_writeByte(SIM_SYPCR, 0xc0); + while (1) ; + + /* we don't return! */ + return 0; +}; +#endif -- cgit v1.1