From 53677ef18e25c97ac613349087c5cb33ae5a2741 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 20 May 2008 16:00:29 +0200 Subject: Big white-space cleanup. This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk --- cpu/ixp/npe/include/IxDmaAcc.h | 12 ++++++------ cpu/ixp/npe/include/IxEthAcc.h | 6 +++--- cpu/ixp/npe/include/IxEthAccMii_p.h | 6 +++--- cpu/ixp/npe/include/IxEthAcc_p.h | 2 +- cpu/ixp/npe/include/IxEthMii.h | 14 +++++++------- cpu/ixp/npe/include/IxI2cDrv.h | 4 ++-- cpu/ixp/npe/include/IxOsalAssert.h | 2 +- cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h | 2 +- cpu/ixp/npe/include/IxOsalBackwardMemMap.h | 2 +- cpu/ixp/npe/include/IxOsalIoMem.h | 2 +- cpu/ixp/npe/include/IxOsalMemAccess.h | 6 +++--- cpu/ixp/npe/include/IxOsalTypes.h | 2 +- cpu/ixp/npe/include/IxQMgr.h | 4 ++-- cpu/ixp/npe/include/IxQMgrAqmIf_p.h | 10 +++++----- cpu/ixp/npe/include/IxQueueAssignments.h | 2 +- 15 files changed, 38 insertions(+), 38 deletions(-) (limited to 'cpu/ixp/npe/include') diff --git a/cpu/ixp/npe/include/IxDmaAcc.h b/cpu/ixp/npe/include/IxDmaAcc.h index 53d2625..45c7527 100644 --- a/cpu/ixp/npe/include/IxDmaAcc.h +++ b/cpu/ixp/npe/include/IxDmaAcc.h @@ -172,7 +172,7 @@ typedef UINT32 IxDmaAccRequestId; #define IX_DMA_REQUEST_FULL 16 /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * @brief DMA completion notification * This function is called to notify a client that the DMA has been completed * @param status @ref IxDmaReturnStatus [out] - reporting to client @@ -181,11 +181,11 @@ typedef UINT32 IxDmaAccRequestId; typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status); /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * * @fn ixDmaAccInit(IxNpeDlNpeId npeId) * - * @brief Initialise the DMA Access component + * @brief Initialise the DMA Access component * This function will initialise the DMA Access component internals * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer * @return @li IX_SUCCESS succesfully initialised the component @@ -196,7 +196,7 @@ PUBLIC IX_STATUS ixDmaAccInit(IxNpeDlNpeId npeId); /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * * @fn ixDmaAccDmaTransfer( IxDmaAccDmaCompleteCallback callback, @@ -225,8 +225,8 @@ ixDmaAccInit(IxNpeDlNpeId npeId); * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width * - * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful - * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured + * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful + * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid diff --git a/cpu/ixp/npe/include/IxEthAcc.h b/cpu/ixp/npe/include/IxEthAcc.h index b424648..ff706c4 100644 --- a/cpu/ixp/npe/include/IxEthAcc.h +++ b/cpu/ixp/npe/include/IxEthAcc.h @@ -626,8 +626,8 @@ PUBLIC void ixEthAccUnload(void); * required features. * * Dependant on Services: (Must be initialized before using this service may be initialized) - * ixNPEmh - NPE Message handling service. - * ixQmgr - Queue Manager component. + * ixNPEmh - NPE Message handling service. + * ixQmgr - Queue Manager component. * * @param portId @ref IxEthAccPortId [in] * @@ -745,7 +745,7 @@ typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *b * * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag) + UINT32 callbackTag) * * @brief Register a callback function to allow * the transmitted buffers to return to the user. diff --git a/cpu/ixp/npe/include/IxEthAccMii_p.h b/cpu/ixp/npe/include/IxEthAccMii_p.h index aa42f9c..568d4a0 100644 --- a/cpu/ixp/npe/include/IxEthAccMii_p.h +++ b/cpu/ixp/npe/include/IxEthAccMii_p.h @@ -81,13 +81,13 @@ #define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */ #define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ #define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ /* Advertisement Register */ -#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ /* partner ability Register */ #define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ /* Expansion Register */ -#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ /* next-page transmit Register */ IxEthAccStatus ixEthAccMdioShow (void); diff --git a/cpu/ixp/npe/include/IxEthAcc_p.h b/cpu/ixp/npe/include/IxEthAcc_p.h index 37c5560..0ee4123 100644 --- a/cpu/ixp/npe/include/IxEthAcc_p.h +++ b/cpu/ixp/npe/include/IxEthAcc_p.h @@ -262,7 +262,7 @@ typedef struct { IxEthAccPortTxDoneCallback txBufferDoneCallbackFn; UINT32 txCallbackTag; - IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ + IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */ IxQMgrQId txQueue; /**< txQueue for this port */ IxEthAccTxDataStats stats; /**< Transmit s/w stats */ diff --git a/cpu/ixp/npe/include/IxEthMii.h b/cpu/ixp/npe/include/IxEthMii.h index a1bfe06..397253a 100644 --- a/cpu/ixp/npe/include/IxEthMii.h +++ b/cpu/ixp/npe/include/IxEthMii.h @@ -106,9 +106,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); * @ingroup IxEthMii * * @fn ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate) + BOOL speed100, + BOOL fullDuplex, + BOOL autonegotiate) * * * @brief Configure a PHY @@ -209,10 +209,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); * @ingroup IxEthMii * * @fn ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) + BOOL *linkUp, + BOOL *speed100, + BOOL *fullDuplex, + BOOL *autoneg) * * @brief Retrieve the current status of a PHY * Retrieve the link, speed, duplex and autonegotiation status of a PHY diff --git a/cpu/ixp/npe/include/IxI2cDrv.h b/cpu/ixp/npe/include/IxI2cDrv.h index 2472f31..92c6b24 100644 --- a/cpu/ixp/npe/include/IxI2cDrv.h +++ b/cpu/ixp/npe/include/IxI2cDrv.h @@ -64,8 +64,8 @@ /** * @ingroup IxI2cDrv * @brief The interval of micro/mili seconds the IXP will wait before it polls for - * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ - * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected + * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ + * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected * through the API ixI2cDrvDelayTypeSelect. */ #define IX_I2C_US_POLL_FOR_XFER_STATUS 20 diff --git a/cpu/ixp/npe/include/IxOsalAssert.h b/cpu/ixp/npe/include/IxOsalAssert.h index 45cebcd..04a4f51 100644 --- a/cpu/ixp/npe/include/IxOsalAssert.h +++ b/cpu/ixp/npe/include/IxOsalAssert.h @@ -1,6 +1,6 @@ /* * @file IxOsalAssert.h - * @author Intel Corporation + * @author Intel Corporation * @date 25-08-2004 * * @brief description goes here diff --git a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h index 5ac3f0c..4cf80d3 100644 --- a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h +++ b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h @@ -76,7 +76,7 @@ typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL; #define IX_MBUF_MTYPE(m_blk_ptr) \ IX_OSAL_MBUF_MTYPE(m_blk_ptr) -#define IX_MBUF_FLAGS(m_blk_ptr) \ +#define IX_MBUF_FLAGS(m_blk_ptr) \ IX_OSAL_MBUF_FLAGS(m_blk_ptr) diff --git a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h index 18f8f24..3881a3b 100644 --- a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h +++ b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h @@ -136,6 +136,6 @@ #define IX_OSSERV_MEM_MAP(physAddr, size) IX_OSAL_MEM_MAP(physAddr, size) -#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr) +#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr) #endif /* IX_OSAL_BACKWARD_MEM_MAP_H */ diff --git a/cpu/ixp/npe/include/IxOsalIoMem.h b/cpu/ixp/npe/include/IxOsalIoMem.h index ac0ce65..ea6d64d 100644 --- a/cpu/ixp/npe/include/IxOsalIoMem.h +++ b/cpu/ixp/npe/include/IxOsalIoMem.h @@ -1,6 +1,6 @@ /* * @file IxOsalIoMem.h - * @author Intel Corporation + * @author Intel Corporation * @date 25-08-2004 * * @brief description goes here diff --git a/cpu/ixp/npe/include/IxOsalMemAccess.h b/cpu/ixp/npe/include/IxOsalMemAccess.h index 2ad0ccf..9e7fb87 100644 --- a/cpu/ixp/npe/include/IxOsalMemAccess.h +++ b/cpu/ixp/npe/include/IxOsalMemAccess.h @@ -410,7 +410,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData) @@ -419,7 +419,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) @@ -428,7 +428,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) diff --git a/cpu/ixp/npe/include/IxOsalTypes.h b/cpu/ixp/npe/include/IxOsalTypes.h index c617ec5..a190a70 100644 --- a/cpu/ixp/npe/include/IxOsalTypes.h +++ b/cpu/ixp/npe/include/IxOsalTypes.h @@ -175,7 +175,7 @@ typedef volatile INT32 VINT32; #ifndef __inline__ -#define __inline__ IX_OSAL_INLINE +#define __inline__ IX_OSAL_INLINE #endif diff --git a/cpu/ixp/npe/include/IxQMgr.h b/cpu/ixp/npe/include/IxQMgr.h index c083a2b..165ed96 100644 --- a/cpu/ixp/npe/include/IxQMgr.h +++ b/cpu/ixp/npe/include/IxQMgr.h @@ -1134,7 +1134,7 @@ ixQMgrQRead (IxQMgrQId qId, * day scenario there are many entries in the queue * and the counter does not reach zero. */ - if (infoPtr->qReadCount-- == 0) + if (infoPtr->qReadCount-- == 0) { /* There is maybe no entry in the queue * qReadCount is now negative, but will be corrected before @@ -1475,7 +1475,7 @@ ixQMgrQWrite (IxQMgrQId qId, ++entry; IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry); } - entrySize = infoPtr->qEntrySizeInWords; + entrySize = infoPtr->qEntrySizeInWords; } /* overflow is available for lower queues only */ diff --git a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h index 7f5733c..4f0f64d 100644 --- a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h +++ b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h @@ -498,7 +498,7 @@ ixQMgrAqmIfQPop (IxQMgrQId qId, volatile UINT32 *accRegAddr; accRegAddr = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_ACCESS_ADDR_GET(qId)); + IX_QMGR_Q_ACCESS_ADDR_GET(qId)); switch (numWords) { @@ -533,7 +533,7 @@ ixQMgrAqmIfQPush (IxQMgrQId qId, volatile UINT32 *accRegAddr; accRegAddr = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_ACCESS_ADDR_GET(qId)); + IX_QMGR_Q_ACCESS_ADDR_GET(qId)); switch (numWords) { @@ -683,9 +683,9 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, * multiple queues split accross registers */ registerAddress = (UINT32*)(aqmBaseAddress + - registerBaseAddrOffset + - ((qId / queuesPerRegWord) * - IX_QMGR_NUM_BYTES_PER_WORD)); + registerBaseAddrOffset + + ((qId / queuesPerRegWord) * + IX_QMGR_NUM_BYTES_PER_WORD)); /* * Get the status word diff --git a/cpu/ixp/npe/include/IxQueueAssignments.h b/cpu/ixp/npe/include/IxQueueAssignments.h index 0c1543f..f7194e7 100644 --- a/cpu/ixp/npe/include/IxQueueAssignments.h +++ b/cpu/ixp/npe/include/IxQueueAssignments.h @@ -409,7 +409,7 @@ * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration * */ -#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4) +#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4) /** * -- cgit v1.1