From ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 4 Apr 2009 08:09:24 -0400 Subject: Blackfin: add workaround for anomaly 05000171 DESCRIPTION: The Boot ROM is executed at power up/reset and changes the value of the SICA_IWR registers from their default reset value of 0xFFFF, but does not restore them. WORKAROUND: User code should not rely on the default value of these registers. Set the desired values explicitly. Signed-off-by: Mike Frysinger --- cpu/blackfin/initcode.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'cpu/blackfin') diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 3120447..d44c6a6 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -356,6 +356,10 @@ void initcode(ADI_BOOT_DATA *bootstruct) #if ANOMALY_05000432 bfin_write_SIC_IWR1(-1); #endif +#if ANOMALY_05000171 + bfin_write_SICA_IWR0(-1); + bfin_write_SICA_IWR1(-1); +#endif } else { serial_putc('G'); -- cgit v1.1 From 48ab1509254a4c175e4f65c478a978928ffe09ec Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 4 Apr 2009 08:10:22 -0400 Subject: Blackfin: add workaround for anomaly 05000242 DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger --- cpu/blackfin/initcode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/blackfin') diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index d44c6a6..7f54860 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -401,7 +401,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) /* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ - if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { + if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { serial_putc('!'); bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); asm("idle;"); -- cgit v1.1 From c2e07449f546fb375289cdac1a608fdc20357873 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 4 Apr 2009 08:29:55 -0400 Subject: Blackfin: add comment about anomaly 05000430 avoidance Signed-off-by: Mike Frysinger --- cpu/blackfin/initcode.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'cpu/blackfin') diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 7f54860..062cbb8 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -335,6 +335,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) if (!ANOMALY_05000386) { serial_putc('F'); + /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ ADI_SYSCTRL_VALUES memory_settings; uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT; if (CONFIG_HAS_VR) { @@ -379,6 +380,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) serial_putc('H'); + /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */ bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); serial_putc('I'); -- cgit v1.1 From 8ef929afa43c77c9573caa57c6e17a97a33775c0 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 4 Apr 2009 08:40:13 -0400 Subject: Blackfin: add check for anomaly 05000362 DESCRIPTION: The column address width settings for banks 2 and 3 are misconnected in the SDRAM controller. Accesses to bank 2 will result in an error if the Column Address Width for bank 3 (EB3CAW ) is not set to be the same as that of bank 2. WORKAROUND: If using bank 2, make sure that banks 2 and 3 have the same column address width settings in the EBIU_SDBCTL register. This must be the case regardless of whether or not bank 3 is enabled. Signed-off-by: Mike Frysinger --- cpu/blackfin/initcode.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'cpu/blackfin') diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 062cbb8..aba00e0 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -246,6 +246,15 @@ static inline void serial_putc(char c) #endif #endif +/* Conflicting Column Address Widths Causes SDRAM Errors: + * EB2CAW and EB3CAW must be the same + */ +#if ANOMALY_05000362 +# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000) +# error "Anomaly 05000362: EB2CAW and EB3CAW must be the same" +# endif +#endif + BOOTROM_CALLED_FUNC_ATTR void initcode(ADI_BOOT_DATA *bootstruct) { -- cgit v1.1 From aad4eca4ba8d597747199d8af723426681557dda Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 4 Apr 2009 09:10:27 -0400 Subject: Blackfin: audit UART for all known anomalies There is no code change here, just new comments, but this keeps me from having to do another audit from scratch in the future. Signed-off-by: Mike Frysinger --- cpu/blackfin/serial.c | 21 ++++++++++++++++++++- cpu/blackfin/serial.h | 2 +- 2 files changed, 21 insertions(+), 2 deletions(-) (limited to 'cpu/blackfin') diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 3861955..2abda18 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -24,6 +24,19 @@ * Licensed under the GPL-2 or later. */ +/* Anomaly notes: + * 05000086 - we don't support autobaud + * 05000099 - we only use DR bit, so losing others is not a problem + * 05000100 - we don't use the UART_IIR register + * 05000215 - we poll the uart (no dma/interrupts) + * 05000225 - no workaround possible, but this shouldnt cause errors ... + * 05000230 - we tweak the baud rate calculation slightly + * 05000231 - we always use 1 stop bit + * 05000309 - we always enable the uart before we modify it in anyway + * 05000350 - we always enable the uart regardless of boot mode + * 05000363 - we don't support break signals, so don't generate one + */ + #include #include #include @@ -43,7 +56,9 @@ uint16_t cached_rbr[256]; size_t cache_count; /* The LSR is read-to-clear on some parts, so we have to make sure status - * bits aren't inadvertently lost when doing various tests. + * bits aren't inadvertently lost when doing various tests. This also + * works around anomaly 05000099 at the same time by keeping a cumulative + * tally of all the status bits. */ static uint16_t uart_lsr_save; static uint16_t uart_lsr_read(void) @@ -59,6 +74,10 @@ static void uart_lsr_clear(void) *pUART_LSR |= -1; } #else +/* When debugging is disabled, we only care about the DR bit, so if other + * bits get set/cleared, we don't really care since we don't read them + * anyways (and thus anomaly 05000099 is irrelevant). + */ static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; } static inline void uart_lsr_clear(void) { *pUART_LSR = -1; } #endif diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index ce39148..7b47878 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -146,7 +146,7 @@ static inline void serial_early_init(void) /* handle portmux crap on different Blackfins */ serial_do_portmux(); - /* Enable UART */ + /* always enable UART -- avoids anomalies 05000309 and 05000350 */ *pUART_GCTL = UCEN; /* Set LCR to Word Lengh 8-bit word select */ -- cgit v1.1