From 8db13d63157811c839d15a313d9f2d2f5fd10af3 Mon Sep 17 00:00:00 2001 From: Aubrey Li Date: Sat, 10 Mar 2007 23:49:29 +0800 Subject: [Blackfin][PATCH] code cleanup --- cpu/bf533/bf533_serial.h | 2 +- cpu/bf533/cache.S | 6 +- cpu/bf533/flush.S | 10 +- cpu/bf533/init_sdram.S | 161 +++++++++++++++--------------- cpu/bf533/init_sdram_bootrom_initblock.S | 162 +++++++++++++++---------------- cpu/bf533/interrupt.S | 4 +- cpu/bf533/start.S | 10 +- cpu/bf533/video.c | 2 +- 8 files changed, 177 insertions(+), 180 deletions(-) (limited to 'cpu/bf533') diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h index 82fcd57..0a04f3e 100644 --- a/cpu/bf533/bf533_serial.h +++ b/cpu/bf533/bf533_serial.h @@ -3,7 +3,7 @@ * * Copyright (c) 2005 blackfin.uclinux.org * - * This file is based on + * This file is based on * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. * Copyright (C) 2003 Bas Vermeulen * BuyWays B.V. (www.buyways.nl) diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index d2b34a9..5dcc24f 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -68,7 +68,7 @@ ENTRY(_invalidate_entire_icache) (R7:5) =[SP++]; RTS; -/* +/* * Invalidate the Entire Data cache by * clearing DMC[1:0] bits */ @@ -80,7 +80,7 @@ ENTRY(_dcache_invalidate) P0.H = (DMEM_CONTROL >> 16); R7 =[P0]; -/* +/* * Clear the DMC[1:0] bits, All valid bits in the data * cache are set to the invalid state */ @@ -118,7 +118,7 @@ ENTRY(_blackfin_dcache_invalidate_range) CC = P0 < P1(iu); IF CC JUMP 1b(bp); -/* +/* * If the data crosses a cache line, then we'll be pointing to * the last cache line, but won't have flushed/invalidated it yet, so do * one more. diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S index 8010f72..58fe4c8 100644 --- a/cpu/bf533/flush.S +++ b/cpu/bf533/flush.S @@ -95,7 +95,7 @@ ENTRY(_icplb_flush) * R0 = Page start * R1 = Page length (actually, offset into size/prefix tables) * R3 = sub-bank deposit values - * + * * The cache has 2 Ways, and 64 sets, so we iterate through * the sets, accessing the tag for each Way, for our Bank and * sub-bank, looking for dirty, valid tags that match our @@ -142,7 +142,7 @@ ifs0: R6 = R5 << 5; /* Combine set*/ IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ /* Tag address matches against page, so this is an entry - * we must flush. + * we must flush. */ R7 >>= 10; /* Mask off the non-address bits*/ @@ -185,7 +185,7 @@ ieall: NOP; SSYNC; JUMP ifinished; -/* This is an external function being called by the user +/* This is an external function being called by the user * application through __flush_cache_all. Currently this function * serves the purpose of flushing all the pending writes in * in the data cache. @@ -222,7 +222,7 @@ skip: R6 += -1; /* This is an internal function to flush all pending * writes in the cache associated with a particular DCPLB. - * + * * R0 - page's start address * R1 - CPLB's data field. */ @@ -260,7 +260,7 @@ ENTRY(_dcplb_flush) /* The page could be mapped into Bank A or Bank B, depending * on (a) whether both banks are configured as cache, and * (b) on whether address bit A[x] is set. x is determined - * by DCBS in DMEM_CONTROL + * by DCBS in DMEM_CONTROL */ R2 = 0; /* Default to Bank A (Bank B would be 1)*/ diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S index d92c877..1aae9e3 100644 --- a/cpu/bf533/init_sdram.S +++ b/cpu/bf533/init_sdram.S @@ -28,17 +28,17 @@ init_sdram: [--SP] = (R7:0); [--SP] = (P5:0); -#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) p0.h = hi(SPI_BAUD); p0.l = lo(SPI_BAUD); r0.l = CONFIG_SPI_BAUD; w[p0] = r0.l; - SSYNC; + SSYNC; #endif /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ + * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable + */ p0.h = hi(PLL_LOCKCNT); p0.l = lo(PLL_LOCKCNT); r0 = 0x300(Z); @@ -46,43 +46,43 @@ init_sdram: ssync; /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ + * Put SDRAM in self-refresh, incase anything is running + */ + P2.H = hi(EBIU_SDGCTL); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITSET (R0, 24); + [P2] = R0; + SSYNC; + + /* + * Set PLL_CTL with the value that we calculate in R0 + * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors + * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK + * - [7] = output delay (add 200ps of delay to mem signals) + * - [6] = input delay (add 200ps of input delay to mem signals) + * - [5] = PDWN : 1=All Clocks off + * - [3] = STOPCK : 1=Core Clock off + * - [1] = PLL_OFF : 1=Disable Power to PLL + * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL + * all other bits set to zero + */ + + r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ + r0 = r0 << 9; /* Shift it over, */ + r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ + r0 = r1 | r0; + r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ + r1 = r1 << 8; /* Shift it over */ + r0 = r1 | r0; /* add them all together */ + + p0.h = hi(PLL_CTL); + p0.l = lo(PLL_CTL); /* Load the address */ + cli r2; /* Disable interrupts */ ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ + w[p0] = r0.l; /* Set the value */ + idle; /* Wait for the PLL to stablize */ + sti r2; /* Enable interrupts */ check_again: p0.h = hi(PLL_STAT); @@ -92,46 +92,46 @@ check_again: if ! CC jump check_again; /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; + r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); + p0.h = hi(PLL_DIV); + p0.l = lo(PLL_DIV); + w[p0] = r0.l; + ssync; /* - * We now are running at speed, time to set the Async mem bank wait states + * We now are running at speed, time to set the Async mem bank wait states * This will speed up execution, since we are normally running from FLASH. */ - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; + p2.h = (EBIU_AMBCTL1 >> 16); + p2.l = (EBIU_AMBCTL1 & 0xFFFF); + r0.h = (AMBCTL1VAL >> 16); + r0.l = (AMBCTL1VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMBCTL0 >> 16); + p2.l = (EBIU_AMBCTL0 & 0xFFFF); + r0.h = (AMBCTL0VAL >> 16); + r0.l = (AMBCTL0VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMGCTL >> 16); + p2.l = (EBIU_AMGCTL & 0xffff); + r0 = AMGCTLVAL; + w[p2] = r0; + ssync; /* * Now, Initialize the SDRAM, * start with the SDRAM Refresh Rate Control Register - */ + */ p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; + p0.h = hi(EBIU_SDRRC); + r0 = mem_SDRRC; + w[p0] = r0.l; + ssync; /* * SDRAM Memory Bank Control Register - bank specific parameters @@ -147,29 +147,29 @@ check_again: * Disable self-refresh */ P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITCLR (R0, 24); /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ + * Check if SDRAM is already powered up, if it is, enable self-refresh + */ p0.h = hi(EBIU_SDSTAT); p0.l = lo(EBIU_SDSTAT); r2.l = w[p0]; cc = bittst(r2,3); if !cc jump skip; - NOP; + NOP; BITSET (R0, 23); skip: [P2] = R0; - SSYNC; + SSYNC; /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); + R0.L = lo(mem_SDGCTL); + R0.H = hi(mem_SDGCTL); [P2] = R0; - SSYNC; + SSYNC; nop; (P5:0) = [SP++]; @@ -177,4 +177,3 @@ skip: RETS = [SP++]; ASTAT = [SP++]; RTS; - diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S index 67074f9..21cfeec 100644 --- a/cpu/bf533/init_sdram_bootrom_initblock.S +++ b/cpu/bf533/init_sdram_bootrom_initblock.S @@ -28,17 +28,17 @@ init_sdram: [--SP] = (R7:0); [--SP] = (P5:0); -#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) p0.h = hi(SPI_BAUD); p0.l = lo(SPI_BAUD); r0.l = CONFIG_SPI_BAUD_INITBLOCK; w[p0] = r0.l; - SSYNC; + SSYNC; #endif /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ + * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable + */ p0.h = hi(PLL_LOCKCNT); p0.l = lo(PLL_LOCKCNT); r0 = 0x300(Z); @@ -46,43 +46,43 @@ init_sdram: ssync; /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ + * Put SDRAM in self-refresh, incase anything is running + */ + P2.H = hi(EBIU_SDGCTL); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITSET (R0, 24); + [P2] = R0; + SSYNC; + + /* + * Set PLL_CTL with the value that we calculate in R0 + * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors + * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK + * - [7] = output delay (add 200ps of delay to mem signals) + * - [6] = input delay (add 200ps of input delay to mem signals) + * - [5] = PDWN : 1=All Clocks off + * - [3] = STOPCK : 1=Core Clock off + * - [1] = PLL_OFF : 1=Disable Power to PLL + * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL + * all other bits set to zero + */ + + r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ + r0 = r0 << 9; /* Shift it over, */ + r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ + r0 = r1 | r0; + r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ + r1 = r1 << 8; /* Shift it over */ + r0 = r1 | r0; /* add them all together */ + + p0.h = hi(PLL_CTL); + p0.l = lo(PLL_CTL); /* Load the address */ + cli r2; /* Disable interrupts */ ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ + w[p0] = r0.l; /* Set the value */ + idle; /* Wait for the PLL to stablize */ + sti r2; /* Enable interrupts */ check_again: p0.h = hi(PLL_STAT); @@ -92,46 +92,46 @@ check_again: if ! CC jump check_again; /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; + r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); + p0.h = hi(PLL_DIV); + p0.l = lo(PLL_DIV); + w[p0] = r0.l; + ssync; /* - * We now are running at speed, time to set the Async mem bank wait states + * We now are running at speed, time to set the Async mem bank wait states * This will speed up execution, since we are normally running from FLASH. */ - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; + p2.h = (EBIU_AMBCTL1 >> 16); + p2.l = (EBIU_AMBCTL1 & 0xFFFF); + r0.h = (AMBCTL1VAL >> 16); + r0.l = (AMBCTL1VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMBCTL0 >> 16); + p2.l = (EBIU_AMBCTL0 & 0xFFFF); + r0.h = (AMBCTL0VAL >> 16); + r0.l = (AMBCTL0VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMGCTL >> 16); + p2.l = (EBIU_AMGCTL & 0xffff); + r0 = AMGCTLVAL; + w[p2] = r0; + ssync; /* * Now, Initialize the SDRAM, * start with the SDRAM Refresh Rate Control Register - */ + */ p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; + p0.h = hi(EBIU_SDRRC); + r0 = mem_SDRRC; + w[p0] = r0.l; + ssync; /* * SDRAM Memory Bank Control Register - bank specific parameters @@ -147,35 +147,33 @@ check_again: * Disable self-refresh */ P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); + P2.L = lo(EBIU_SDGCTL); + R0 = [P2]; + BITCLR (R0, 24); /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ + * Check if SDRAM is already powered up, if it is, enable self-refresh + */ p0.h = hi(EBIU_SDSTAT); p0.l = lo(EBIU_SDSTAT); r2.l = w[p0]; cc = bittst(r2,3); if !cc jump skip; - NOP; + NOP; BITSET (R0, 23); skip: [P2] = R0; - SSYNC; + SSYNC; /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); + R0.L = lo(mem_SDGCTL); + R0.H = hi(mem_SDGCTL); [P2] = R0; - SSYNC; + SSYNC; nop; - (P5:0) = [SP++]; (R7:0) = [SP++]; RETS = [SP++]; ASTAT = [SP++]; RTS; - diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S index a5de96b..524da8f 100644 --- a/cpu/bf533/interrupt.S +++ b/cpu/bf533/interrupt.S @@ -95,7 +95,7 @@ _evt_rst: sp += 12; _evt_rst_exit: - rtn; + rtn; irq_panic: r0 = IRQ_EVX; @@ -134,7 +134,7 @@ _evt_evt7: evt_evt7_exit: RESTORE_CONTEXT - rti; + rti; .global _evt_evt8 _evt_evt8: diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 8e2d725..3a31e2f 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -32,7 +32,7 @@ /* * Note: A change in this file subsequently requires a change in - * board/$(board_name)/config.mk for a valid u-boot.bin + * board/$(board_name)/config.mk for a valid u-boot.bin */ #define ASSEMBLY @@ -152,10 +152,10 @@ no_soft_reset: [ p0 ++ ] = r1; p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; + p0.l = lo(SIC_IWR); + r0.l = 0x1; + w[p0] = r0.l; + SSYNC; sp.l = (0xffb01000 & 0xFFFF); sp.h = (0xffb01000 >> 16); diff --git a/cpu/bf533/video.c b/cpu/bf533/video.c index 056564a..3ff0151 100644 --- a/cpu/bf533/video.c +++ b/cpu/bf533/video.c @@ -45,7 +45,7 @@ int is_vblank_line(const int line) { /* * This array contains a single bit for each line in - * an NTSC frame. + * an NTSC frame. */ if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528)) return true; -- cgit v1.1