From 48b42616e928ce6eacfe20276a1614e2b27ac4b5 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Thu, 19 Jun 2003 23:01:32 +0000
Subject: =?UTF-8?q?*=20Patches=20by=20David=20M=FCller,=2012=20Jun=202003:?=
 =?UTF-8?q?=20=20=20-=20rewrite=20of=20the=20S3C24X0=20register=20definiti?=
 =?UTF-8?q?ons=20stuff=20=20=20-=20"driver"=20for=20the=20built-in=20S3C24?=
 =?UTF-8?q?X0=20RTC?=
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* Patches by Yuli Barcohen, 12 Jun 2003:
  - Add MII support and Ethernet PHY initialization for MPC8260ADS board
  - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
    configuration word supplied by FPGA on some MPC8260ADS boards

* Patch by Pantelis Antoniou, 10 Jun 2003:
  Unify status LED interface
---
 cpu/arm920t/speed.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'cpu/arm920t/speed.c')

diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/speed.c
index 4942727..1f43543 100644
--- a/cpu/arm920t/speed.c
+++ b/cpu/arm920t/speed.c
@@ -51,12 +51,13 @@
 
 static ulong get_PLLCLK(int pllreg)
 {
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
     ulong r, m, p, s;
 
     if (pllreg == MPLL)
-	r = rMPLLCON;
+	r = clk_power->MPLLCON;
     else if (pllreg == UPLL)
-	r = rUPLLCON;
+	r = clk_power->UPLLCON;
     else
 	hang();
 
@@ -76,17 +77,17 @@ ulong get_FCLK(void)
 /* return HCLK frequency */
 ulong get_HCLK(void)
 {
-    ulong clkdiv = rCLKDIVN;
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
-    return((clkdiv & 0x2) ? get_FCLK()/2 : get_FCLK());
+    return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
 }
 
 /* return PCLK frequency */
 ulong get_PCLK(void)
 {
-    ulong clkdiv = rCLKDIVN;
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
-    return((clkdiv & 0x1) ? get_HCLK()/2 : get_HCLK());
+    return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
 }
 
 /* return UCLK frequency */
-- 
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