From 11dadd547c08a3480ea153482e99c6ae70b73415 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Fri, 27 Feb 2004 00:07:27 +0000
Subject: * Patch by Steven Scholz, 25 Feb 2004:   - Timeouts in FPGA code
 should be based on CFG_HZ   - Minor cleanup in code for Altera FPGA ACEX1K

* Patch by Steven Scholz, 25 Feb 2004:
  Changed "Directory Hierarchy" section in README

* Patch by Masami Komiya, 25 Feb 2004:
  Reduce copy count in nfs_read_reply() of NFS code
---
 common/ACEX1K.c   | 11 +++--------
 common/spartan2.c |  2 +-
 common/virtex2.c  |  6 +++---
 3 files changed, 7 insertions(+), 12 deletions(-)

(limited to 'common')

diff --git a/common/ACEX1K.c b/common/ACEX1K.c
index 53b2f50..2a421e2 100644
--- a/common/ACEX1K.c
+++ b/common/ACEX1K.c
@@ -31,17 +31,12 @@
 #if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
 
 /* Define FPGA_DEBUG to get debug printf's */
-/* #define FPGA_DEBUG */
-
 #ifdef	FPGA_DEBUG
 #define PRINTF(fmt,args...)	printf (fmt ,##args)
 #else
 #define PRINTF(fmt,args...)
 #endif
 
-#undef CFG_FPGA_CHECK_BUSY
-#define CFG_FPGA_PROG_FEEDBACK
-
 /* Note: The assumption is that we cannot possibly run fast enough to
  * overrun the device (the Slave Parallel mode can free run at 50MHz).
  * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
@@ -52,7 +47,7 @@
 #endif
 
 #ifndef CFG_FPGA_WAIT
-#define CFG_FPGA_WAIT 100
+#define CFG_FPGA_WAIT CFG_HZ/10		/* 100 ms */
 #endif
 
 static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
@@ -162,7 +157,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
 				__FUNCTION__, &fn, fn, fn->config, fn->status,
 				fn->clk, fn->data, fn->done);
 #ifdef CFG_FPGA_PROG_FEEDBACK
-		printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);
+		printf ("Loading FPGA Device %d...", cookie);
 #endif
 
 		/*
@@ -246,7 +241,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
 		CONFIG_FPGA_DELAY ();
 
 #ifdef CFG_FPGA_PROG_FEEDBACK
-		putc ('\n');			/* terminate the dotted line */
+		putc (' ');			/* terminate the dotted line */
 #endif
 
 	/*
diff --git a/common/spartan2.c b/common/spartan2.c
index 279a426..0fb23b6 100644
--- a/common/spartan2.c
+++ b/common/spartan2.c
@@ -47,7 +47,7 @@
 #endif
 
 #ifndef CFG_FPGA_WAIT
-#define CFG_FPGA_WAIT 10
+#define CFG_FPGA_WAIT CFG_HZ/100	/* 10 ms */
 #endif
 
 static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
diff --git a/common/virtex2.c b/common/virtex2.c
index b519be9..bb44eaa 100644
--- a/common/virtex2.c
+++ b/common/virtex2.c
@@ -80,7 +80,7 @@
  * an XC2V1000, if anyone can ever get ahold of one.
  */
 #ifndef CFG_FPGA_WAIT_INIT
-#define CFG_FPGA_WAIT_INIT 	500	/* time in milliseconds */
+#define CFG_FPGA_WAIT_INIT 	CFG_HZ/2	/* 500 ms */
 #endif
 
 /*
@@ -89,14 +89,14 @@
  * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
  */
 #ifndef CFG_FPGA_WAIT_BUSY
-#define CFG_FPGA_WAIT_BUSY	5	/* time in milliseconds */
+#define CFG_FPGA_WAIT_BUSY	CFG_HZ/200	/* 5 ms*/
 #endif
 
 /* Default timeout for waiting for FPGA to enter operational mode after
  * configuration data has been written.
  */
 #ifndef	CFG_FPGA_WAIT_CONFIG
-#define CFG_FPGA_WAIT_CONFIG	200	/* time in milliseconds */
+#define CFG_FPGA_WAIT_CONFIG	CFG_HZ/5	/* 200 ms */
 #endif
 
 static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize);
-- 
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