From fdc18aceb57291e48149d210721b3e6d755d5ba2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 25 Mar 2016 14:50:37 +0800 Subject: MLK-12436-10: mx6sabresd: update board code and header file Align board code and header file with imx_v2016.03. Update pmic settings for i.MX6QP. wrap spi code together using CONFIG_MXC_SPI macro. To i.MX6SOLO, need to define nosmp in bootargs. Signed-off-by: Peng Fan (cherry picked from commit bb35d09d140efc7ff9b74bbcd77d7827c1dd503e) Signed-off-by: Ye Li --- board/freescale/mx6sabresd/mx6sabresd.c | 160 +++++++++++++++++++++++++++----- 1 file changed, 138 insertions(+), 22 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 9097426..d0db0c6 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -34,6 +34,9 @@ #include #include #endif +#ifdef CONFIG_CMD_SATA +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -150,6 +153,7 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -157,6 +161,18 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS"); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -226,12 +242,7 @@ static struct i2c_pads_info i2c_pad_info1 = { }; #endif -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - gpio_request(IMX_GPIO_NR(4, 9), "ECSPI1 CS"); -} - +#ifdef CONFIG_PCIE_IMX iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ @@ -243,6 +254,7 @@ static void setup_pcie(void) gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable"); gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset"); } +#endif iomux_v3_cfg_t const di0_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ @@ -889,35 +901,93 @@ int board_init(void) setup_epdc(); #endif +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } #ifdef CONFIG_POWER int power_init_board(void) { - struct pmic *p; + struct pmic *pfuze; unsigned int reg; int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; - ret = pfuze_mode_init(p, APS_PFM); + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) return ret; /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); + pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW2STBY, ®); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + } return 0; } @@ -933,7 +1003,10 @@ int power_init_board(void) if (!dev) return -ENODEV; - ret = pfuze_mode_init(dev, APS_PFM); + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; @@ -949,14 +1022,57 @@ int power_init_board(void) reg |= LDOB_3_00V; pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); - return 0; -} -#endif + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + } -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; + return 0; } #endif -- cgit v1.1