From 8e585f02f82c17cc66cd229dbf0fd3066bbbf658 Mon Sep 17 00:00:00 2001 From: TsiChung Liew Date: Mon, 18 Jun 2007 13:50:13 -0500 Subject: Added M5329AFEE and M5329BFEE Platforms Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, include/configs/M5329EVB.h, lib_m68k/interrupts.c, and rtc/mcfrtc.c Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, lib_m68k/time.c, net/eth.c and rtc/Makefile Signed-off-by: TsiChung Liew --- board/freescale/m5329evb/Makefile | 44 +++ board/freescale/m5329evb/config.mk | 25 ++ board/freescale/m5329evb/flash.c | 643 ++++++++++++++++++++++++++++++++++++ board/freescale/m5329evb/m5329evb.c | 376 +++++++++++++++++++++ board/freescale/m5329evb/u-boot.lds | 144 ++++++++ 5 files changed, 1232 insertions(+) create mode 100644 board/freescale/m5329evb/Makefile create mode 100644 board/freescale/m5329evb/config.mk create mode 100644 board/freescale/m5329evb/flash.c create mode 100644 board/freescale/m5329evb/m5329evb.c create mode 100644 board/freescale/m5329evb/u-boot.lds (limited to 'board') diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile new file mode 100644 index 0000000..f94ee9d --- /dev/null +++ b/board/freescale/m5329evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m5329evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m5329evb/flash.c b/board/freescale/m5329evb/flash.c new file mode 100644 index 0000000..7d3b0e8 --- /dev/null +++ b/board/freescale/m5329evb/flash.c @@ -0,0 +1,643 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef CFG_FLASH_CFI + +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 +#define INTEL_CFI_BLK1 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK2 0x31 + +#define WR_BLOCK 0x20 + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(FPWV * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + FPWV *flash_addr[CFG_MAX_FLASH_BANKS]; + ulong size; + int i; + + flash_addr[0] = (FPW *) CFG_FLASH0_BASE; +#ifdef CFG_FLASH1_BASE + flash_addr[1] = (FPW *) CFG_FLASH1_BASE; +#endif + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + size = flash_get_size(flash_addr[i], &flash_info[i]); + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + size - 1, + &flash_info[0]); + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + printf("28F160C3B\n"); + break; + case FLASH_28F160C3T: + printf("28F160C3T\n"); + break; + case FLASH_28F320C3B: + printf("28F320C3B\n"); + break; + case FLASH_28F320C3T: + printf("28F320C3T\n"); + break; + case FLASH_28F640C3B: + printf("28F640C3B\n"); + break; + case FLASH_28F640C3T: + printf("28F640C3T\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + int intel = 0; + u16 value; + static int bank = 0; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + *addr = (FPW) INTEL_READID; + + switch (addr[INTEL_CFI_MFG] & 0xff) { + case (ushort) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + value = addr[INTEL_CFI_PART]; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u16) INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + break; + case (u16) INTEL_ID_28F160C3T: + info->flash_id += FLASH_28F160C3T; + break; + case (u16) INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + break; + case (u16) INTEL_ID_28F320C3T: + info->flash_id += FLASH_28F320C3T; + break; + case (u16) INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + break; + case (u16) INTEL_ID_28F640C3T: + info->flash_id += FLASH_28F640C3T; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz, size, offset; + int sec, sectors, bs; + int part, i, j, cnt; + + part = flash_cmd_rd(addr, INTEL_CFI_BANK); + + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + offset = (u32) addr; + sectors = sec = 0; + size = sz = cnt = 0; + for (i = 0; i < part; i++) { + bs = (((addr[INTEL_CFI_SZ1B + i * 4] << 8) | + addr[INTEL_CFI_SZ1A + i * 4]) * 0x100); + sec = addr[INTEL_CFI_BLK1 + i * 4] + 1; + sz = bs * sec; + + for (j = 0; j < sec; j++) { + info->start[cnt++] = offset; + offset += bs; + } + + sectors += sec; + size += sz; + } + info->sector_count = sectors; + info->size = size; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (info->size); +} + +int flash_cmd_rd(FPWV * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + type = (info->flash_id & FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB]; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + + printf(" done\n"); + } + } + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + { + ulong cp, wp; + FPW data; + int i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + /* handle word aligned part */ + while (cnt >= 2) { + data = *((FPW *) src); + + if ((rc = + write_data(info, (ulong) ((FPWV *) wp), + (FPW) data)) != 0) { + return (rc); + } + + src += sizeof(FPW); + wp += sizeof(FPW); + cnt -= sizeof(FPW); + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data |= (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif /* CFG_FLASH_PROTECTION */ +#endif /* CFG_FLASH_CFI */ diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c new file mode 100644 index 0000000..4ccea30 --- /dev/null +++ b/board/freescale/m5329evb/m5329evb.c @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale FireEngine 5329 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CFG_SDRAM_BASE | i); + sdram->cfg1 = CFG_SDRAM_CFG1; + sdram->cfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->ctrl = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->mode = CFG_SDRAM_EMOD; + sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CFG_SDRAM_CTRL | 2); + + /* Perform two refresh cycles */ + sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CFG_SDRAM_CTRL | 4; + + sdram->mode = CFG_SDRAM_MODE; + + sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CFG_FLASH_CFI +void sync(void) +{ + /* This sync function is PowerPC intruction, + coldfire does not have this instruction. Dummy function */ +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds new file mode 100644 index 0000000..9b994a0 --- /dev/null +++ b/board/freescale/m5329evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From e09f7ab5749c345f924da272bea0521a73af5b11 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 9 Jul 2007 10:10:04 +0200 Subject: Migrate esd 405EP boards to new NAND subsystem This patch prepares the migration from the legacy NAND driver to U-Boot's new NAND subsystem for esd boards. Signed-off-by: Matthias Fuchs --- board/esd/common/auto_update.c | 4 ++ board/esd/common/esd405ep_nand.c | 87 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 board/esd/common/esd405ep_nand.c (limited to 'board') diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 001fd68..b5f7722 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -31,7 +31,9 @@ #include #include #include +#if defined(CFG_NAND_LEGACY) #include +#endif #include #include @@ -294,6 +296,8 @@ int au_do_update(int i, long sz) rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); +#else + rc = -1; #endif } if (rc != 0) { diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c new file mode 100644 index 0000000..7ac4b83 --- /dev/null +++ b/board/esd/common/esd405ep_nand.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +#include + +/* + * hardware specific access to control-lines + */ +static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + switch(cmd) { + case NAND_CTL_SETCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + break; + case NAND_CTL_CLRCLE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + break; + case NAND_CTL_SETALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + break; + case NAND_CTL_CLRALE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + break; + case NAND_CTL_SETNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + break; + case NAND_CTL_CLRNCE: + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + break; + } +} + + +/* + * read device ready pin + */ +static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) +{ + if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) + return 1; + return 0; +} + + +int board_nand_init(struct nand_chip *nand) +{ + /* + * Set NAND-FLASH GPIO signals to defaults + */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + + /* + * Initialize nand_chip structure + */ + nand->hwcontrol = esd405ep_nand_hwcontrol; + nand->dev_ready = esd405ep_nand_device_ready; + nand->eccmode = NAND_ECC_SOFT; + nand->chip_delay = NAND_BIG_DELAY_US; + nand->options = NAND_SAMSUNG_LP_OPTIONS; + return 0; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ -- cgit v1.1 From bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 9 Jul 2007 10:10:06 +0200 Subject: Migrate esd 405EP boards to new NAND subsystem Migrate esd 405EP boards to new NAND subsystem -cleanup -use correct io accessors (in/out_be32()) Signed-off-by: Matthias Fuchs --- board/esd/ash405/Makefile | 4 +++- board/esd/ash405/ash405.c | 43 ++++++++++-------------------------- board/esd/cms700/Makefile | 5 ++++- board/esd/cms700/cms700.c | 39 +++++++-------------------------- board/esd/hh405/Makefile | 5 ++++- board/esd/hh405/hh405.c | 22 +------------------ board/esd/hub405/Makefile | 4 +++- board/esd/hub405/hub405.c | 34 ---------------------------- board/esd/plu405/Makefile | 5 ++++- board/esd/plu405/plu405.c | 56 ++++++++--------------------------------------- board/esd/voh405/Makefile | 4 +++- board/esd/voh405/voh405.c | 20 ----------------- board/esd/wuh405/Makefile | 4 +++- board/esd/wuh405/wuh405.c | 33 ---------------------------- 14 files changed, 53 insertions(+), 225 deletions(-) (limited to 'board') diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 4d75868..308f752 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 84fc3a0..0151d74 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -33,6 +34,7 @@ #endif extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void lxt971_no_sleep(void); /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -164,18 +166,12 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -218,35 +214,18 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} +#ifdef CONFIG_LXT971_NO_SLEEP -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); #endif +} diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index df48766..0d4ab2d 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + $(CPLD) \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index cb04710..2cdd7be 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2007 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -68,9 +69,9 @@ int board_early_init_f (void) /* * Reset CPLD via GPIO12 (CS3) pin */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET); udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; @@ -94,13 +95,7 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); return (0); } @@ -153,11 +148,6 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } @@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state) switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); break; } } @@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index ce7876c..0e5e57a 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index ea344c0..67b5d54 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,7 +5,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -477,12 +477,6 @@ int misc_init_r (void) out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Reset touch-screen controller */ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); @@ -690,20 +684,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - #if defined(CFG_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 4d75868..308f752 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 1e0accb..25c8068 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -153,12 +153,6 @@ int misc_init_r (void) out32(GPIO0_OR, val); /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * check board type and setup AP power */ str = getenv("bd_type"); /* this is only set on non prototype hardware */ @@ -242,33 +236,5 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index ce7876c..0e5e57a 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -28,7 +28,10 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 59171f8..f026a7a 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -31,6 +32,8 @@ #define FPGA_DEBUG #endif +DECLARE_GLOBAL_DATA_PTR; + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); @@ -114,6 +117,10 @@ int misc_init_r (void) int index; int i; + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + dst = malloc(CFG_FPGA_MAX_SIZE); if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); @@ -177,18 +184,12 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -226,24 +227,10 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { @@ -262,31 +249,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - -#ifdef CONFIG_AUTO_UPDATE_SHOW -void board_auto_update_show(int au_active) -{ - if (au_active) { - printf("\n Dies ist die board-funktion: Updating!!!\n"); - } else { - printf("\n Dies ist die board-funktion: Updating done!!!\n"); - } -} -#endif - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 4d75868..308f752 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 22995b5..2857a0be 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -195,12 +195,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -340,17 +334,3 @@ void ide_set_reset(int on) } } #endif /* CONFIG_IDE_RESET */ - - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 4d75868..308f752 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS = $(BOARD).o flash.o \ + ../common/misc.o \ + ../common/esd405ep_nand.o \ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 5a1a3f3..0b53062 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -170,12 +170,6 @@ int misc_init_r (void) udelay(1000); /* wait 1ms */ /* - * Set NAND-FLASH GPIO signals to default - */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); - - /* * Enable interrupts in exar duart mcr[3] */ *duart0_mcr = 0x08; @@ -218,35 +212,8 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CFG_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif -- cgit v1.1 From c8603cfbd4573379a6076c9c208545ba2bbf019a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 9 Jul 2007 11:00:24 +0200 Subject: Small coding style cleanup Signed-off-by: Stefan Roese --- board/esd/cpci405/cpci405.c | 1 - board/esd/wuh405/wuh405.c | 1 - 2 files changed, 2 deletions(-) (limited to 'board') diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 2ed0fc2..2358577 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -585,7 +585,6 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ - #ifdef CONFIG_CPCI405AB #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 0b53062..5fde8d6 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -216,4 +216,3 @@ long int initdram (int board_type) } /* ------------------------------------------------------------------------- */ - -- cgit v1.1 From 01a793fda09c63df5a496f09dc1c7cb26e6751a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:51:05 -0500 Subject: Duplicate code There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file. Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/flash.c | 643 --------------------------------------- 1 file changed, 643 deletions(-) delete mode 100644 board/freescale/m5329evb/flash.c (limited to 'board') diff --git a/board/freescale/m5329evb/flash.c b/board/freescale/m5329evb/flash.c deleted file mode 100644 index 7d3b0e8..0000000 --- a/board/freescale/m5329evb/flash.c +++ /dev/null @@ -1,643 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifndef CFG_FLASH_CFI - -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_WRSETUP 0x00400040 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CFIQRY 0x00980098 -#define INTEL_SUSERASE 0x00B000B0 -#define INTEL_PROTPROG 0x00C000C0 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0x00FF00FF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 -#define INTEL_ERASESUS 0x00600060 -#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) - -/* 28F160C3B CFI Data offset - This could vary */ -#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ -#define INTEL_CFI_PART 0x01 /* Product ID */ -#define INTEL_CFI_LOCK 0x02 /* */ -#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ -#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ -#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ -#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ -#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ -#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ -#define INTEL_CFI_BANK 0x2C /* Number of Bank */ -#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ -#define INTEL_CFI_SZ1B 0x30 -#define INTEL_CFI_SZ2A 0x33 -#define INTEL_CFI_SZ2B 0x34 -#define INTEL_CFI_BLK1 0x2D /* Number of Blocks */ -#define INTEL_CFI_BLK2 0x31 - -#define WR_BLOCK 0x20 - -#define SYNC __asm__("nop") - -/*----------------------------------------------------------------------- - * Functions - */ - -ulong flash_get_size(FPWV * addr, flash_info_t * info); -int flash_get_offsets(ulong base, flash_info_t * info); -int flash_cmd_rd(FPWV * addr, int index); -int write_data(flash_info_t * info, ulong dest, FPW data); -void flash_sync_real_protect(flash_info_t * info); -uchar intel_sector_protected(flash_info_t * info, ushort sector); - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -ulong flash_init(void) -{ - FPWV *flash_addr[CFG_MAX_FLASH_BANKS]; - ulong size; - int i; - - flash_addr[0] = (FPW *) CFG_FLASH0_BASE; -#ifdef CFG_FLASH1_BASE - flash_addr[1] = (FPW *) CFG_FLASH1_BASE; -#endif - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - memset(&flash_info[i], 0, sizeof(flash_info_t)); - - size = flash_get_size(flash_addr[i], &flash_info[i]); - flash_protect(FLAG_PROTECT_CLEAR, - flash_info[i].start[0], - flash_info[i].start[0] + size - 1, - &flash_info[0]); - /* get the h/w and s/w protection status in sync */ - flash_sync_real_protect(&flash_info[i]); - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -void flash_print_info(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - printf("28F160C3B\n"); - break; - case FLASH_28F160C3T: - printf("28F160C3T\n"); - break; - case FLASH_28F320C3B: - printf("28F320C3B\n"); - break; - case FLASH_28F320C3T: - printf("28F320C3T\n"); - break; - case FLASH_28F640C3B: - printf("28F640C3B\n"); - break; - case FLASH_28F640C3T: - printf("28F640C3T\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - if (info->size > 0x100000) { - int remainder; - - printf(" Size: %ld", info->size >> 20); - - remainder = (info->size % 0x100000); - if (remainder) { - remainder >>= 10; - remainder = (int)((float) - (((float)remainder / (float)1024) * - 10000)); - printf(".%d ", remainder); - } - - printf("MB in %d Sectors\n", info->sector_count); - } else - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size(FPWV * addr, flash_info_t * info) -{ - int intel = 0; - u16 value; - static int bank = 0; - - /* Write auto select command: read Manufacturer ID */ - /* Write auto select command sequence and test FLASH answer */ - *addr = (FPW) INTEL_RESET; /* restore read mode */ - *addr = (FPW) INTEL_READID; - - switch (addr[INTEL_CFI_MFG] & 0xff) { - case (ushort) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - value = addr[INTEL_CFI_PART]; - intel = 1; - break; - default: - printf("Unknown Flash\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - *addr = (FPW) INTEL_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - switch (value) { - case (u16) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - break; - case (u16) INTEL_ID_28F160C3T: - info->flash_id += FLASH_28F160C3T; - break; - case (u16) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - break; - case (u16) INTEL_ID_28F320C3T: - info->flash_id += FLASH_28F320C3T; - break; - case (u16) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - break; - case (u16) INTEL_ID_28F640C3T: - info->flash_id += FLASH_28F640C3T; - break; - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (intel) { - /* Intel spec. under CFI section */ - u32 sz, size, offset; - int sec, sectors, bs; - int part, i, j, cnt; - - part = flash_cmd_rd(addr, INTEL_CFI_BANK); - - /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. - * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count - * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count - */ - offset = (u32) addr; - sectors = sec = 0; - size = sz = cnt = 0; - for (i = 0; i < part; i++) { - bs = (((addr[INTEL_CFI_SZ1B + i * 4] << 8) | - addr[INTEL_CFI_SZ1A + i * 4]) * 0x100); - sec = addr[INTEL_CFI_BLK1 + i * 4] + 1; - sz = bs * sec; - - for (j = 0; j < sec; j++) { - info->start[cnt++] = offset; - offset += bs; - } - - sectors += sec; - size += sz; - } - info->sector_count = sectors; - info->size = size; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - *addr = (FPW) INTEL_RESET; /* restore read mode */ - - return (info->size); -} - -int flash_cmd_rd(FPWV * addr, int index) -{ - return (int)addr[index]; -} - -/* - * This function gets the u-boot flash sector protection status - * (flash_info_t.protect[]) in sync with the sector protection - * status stored in hardware. - */ -void flash_sync_real_protect(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - for (i = 0; i < info->sector_count; ++i) { - info->protect[i] = intel_sector_protected(info, i); - } - break; - default: - /* no h/w protect support */ - break; - } -} - -/* - * checks if "sector" in bank "info" is protected. Should work on intel - * strata flash chips 28FxxxJ3x in 8-bit mode. - * Returns 1 if sector is protected (or timed-out while trying to read - * protection status), 0 if it is not. - */ -uchar intel_sector_protected(flash_info_t * info, ushort sector) -{ - FPWV *addr; - FPWV *lock_conf_addr; - ulong start; - unsigned char ret; - - /* - * first, wait for the WSM to be finished. The rationale for - * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy - * because of: (1) erase, (2) program or (3) lock bit - * configuration. So we just wait for the longest timeout of - * the (1)-(3), i.e. the erase timeout. - */ - - /* wait at least 35ns (W12) before issuing Read Status Register */ - /*udelay(1); */ - addr = (FPWV *) info->start[sector]; - *addr = (FPW) INTEL_STATUS; - - start = get_timer(0); - while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { - *addr = (FPW) INTEL_RESET; /* restore read mode */ - printf("WSM busy too long, can't get prot status\n"); - return 1; - } - } - - /* issue the Read Identifier Codes command */ - *addr = (FPW) INTEL_READID; - - /* Intel example code uses offset of 4 for 8-bit flash */ - lock_conf_addr = (FPWV *) info->start[sector]; - ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; - - /* put flash back in read mode */ - *addr = (FPW) INTEL_RESET; - - return ret; -} - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - type = (info->flash_id & FLASH_VENDMASK); - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf("\n"); - - start = get_timer(0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - FPWV *addr = (FPWV *) (info->start[sect]); - int min = 0; - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) INTEL_READID; - min = addr[INTEL_CFI_TERB]; - min = 1 << min; /* ms */ - min = (min / info->sector_count) * 1000; - - /* start erase block */ - *addr = (FPW) INTEL_CLEAR; /* clear status register */ - *addr = (FPW) INTEL_ERASE; /* erase setup */ - *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ - - while ((*addr & (FPW) INTEL_FINISHED) != - (FPW) INTEL_FINISHED) { - - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ - *addr = (FPW) INTEL_RESET; /* reset to read mode */ - - rcode = 1; - break; - } - } - - *addr = (FPW) INTEL_RESET; /* resest to read mode */ - - printf(" done\n"); - } - } - - return rcode; -} - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - { - ulong cp, wp; - FPW data; - int i, l, rc, port_width; - - /* get lower word aligned address */ - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < port_width; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_data(info, wp, data)) != 0) - return (rc); - - wp += port_width; - } - - /* handle word aligned part */ - while (cnt >= 2) { - data = *((FPW *) src); - - if ((rc = - write_data(info, (ulong) ((FPWV *) wp), - (FPW) data)) != 0) { - return (rc); - } - - src += sizeof(FPW); - wp += sizeof(FPW); - cnt -= sizeof(FPW); - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data |= (*(uchar *) cp); - } - - return write_data(info, (ulong) ((FPWV *) wp), - (FPW) data); - - } /* case FLASH_MAN_INTEL */ - - } /* switch */ - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_data(flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = (int)disable_interrupts(); - - *addr = (FPW) INTEL_CLEAR; - *addr = (FPW) INTEL_RESET; - - *addr = (FPW) INTEL_WRSETUP; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ - *addr = (FPW) INTEL_CLEAR; /* clear status */ - *addr = (FPW) INTEL_RESET; /* reset */ - return (1); - } - } - - *addr = (FPW) INTEL_CLEAR; /* clear status */ - *addr = (FPW) INTEL_RESET; /* restore read mode */ - - return (0); -} - -#ifdef CFG_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - *addr = (FPW) INTEL_RESET; /* make sure in read mode */ - *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ - - if (prot) - *addr = (FPW) INTEL_PROTECT; /* lock sector */ - else - *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) INTEL_READID; - - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) INTEL_PROTECT; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) INTEL_PROTECT) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect(info); - break; - - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif /* CFG_FLASH_PROTECTION */ -#endif /* CFG_FLASH_CFI */ -- cgit v1.1 From 427c814104560e29bda14955c67703245aaaa5b4 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:54:42 -0500 Subject: Removed MII functions and replaced immap_5329.h and m5329.h with immap.h. The removed MII routines will be placed in mii.c. Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/m5329evb.c | 285 +----------------------------------- 1 file changed, 3 insertions(+), 282 deletions(-) (limited to 'board') diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 4ccea30..07a02c2 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -24,13 +24,9 @@ * MA 02111-1307 USA */ -#include -#include -#include -#include - #include -#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -97,280 +93,5 @@ void sync(void) /* This sync function is PowerPC intruction, coldfire does not have this instruction. Dummy function */ } -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; - } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) -#include - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ - (REG & 0x1f) << 18) | \ - (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - strcpy(info->phy_name, - STR_ID_DP83848VV); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - printf(STR_ID_DP83848VV); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} +#endif /* CFG_FLASH_CFI */ -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From c5ded275d839e4ff79f41718d50a835d989f57bc Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:56:19 -0500 Subject: MII functions calls. Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/mii.c | 304 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 304 insertions(+) create mode 100644 board/freescale/m5329evb/mii.c (limited to 'board') diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c new file mode 100644 index 0000000..691b144 --- /dev/null +++ b/board/freescale/m5329evb/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; + gpio->par_feci2c |= + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + } else { + gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +void mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From 3b635492c95bd0d6e08f93f699821cba1f602a64 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 5 Jul 2007 22:57:46 -0500 Subject: Update for flash.o and mii.o Removed flash.o and added mii.o Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile index f94ee9d..74c2528 100644 --- a/board/freescale/m5329evb/Makefile +++ b/board/freescale/m5329evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -- cgit v1.1 From df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:00:43 +0200 Subject: ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese --- board/amcc/yucca/yucca.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'board') diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 7316c34..d08fcf3 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -562,6 +562,40 @@ int checkboard (void) return 0; } +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +static int ppc440spe_rev_a(void) +{ + if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) + return 1; + else + return 0; +} + +u32 ddr_wrdtr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_WRDTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); + + return default_val; +} + +u32 ddr_clktr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_CLKTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_CLKTR_CLKP_180_DEG_ADV); + + return default_val; +} + #if defined(CFG_DRAM_TEST) int testdram (void) { -- cgit v1.1 From 2a49fc17d09020e7ebd9536694d99d20e419fcb8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:01:38 +0200 Subject: ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup Signed-off-by: Stefan Roese --- board/amcc/luan/luan.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 2eff3b3..7b16f8a 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -104,6 +104,13 @@ int checkboard(void) return 0; } +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +u32 ddr_clktr(u32 default_val) { + return (SDRAM_CLKTR_CLKP_180_DEG_ADV); +} /************************************************************************* * int testdram() -- cgit v1.1 From 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 10:02:12 +0200 Subject: ppc4xx: Code cleanup Signed-off-by: Stefan Roese --- board/lwmon5/sdram.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 9a4a8ee..b6863b6 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -54,7 +54,6 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); -- cgit v1.1 From c883f6ea32dce91f07670b3aafecf6c99b1e5341 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 16 Jul 2007 13:11:12 +0200 Subject: Coding style cleanup Signed-off-by: Stefan Roese --- board/freescale/m5329evb/m5329evb.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 07a02c2..d180b6f 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -94,4 +94,3 @@ void sync(void) coldfire does not have this instruction. Dummy function */ } #endif /* CFG_FLASH_CFI */ - -- cgit v1.1 From 531e3e8b831f357056448fa573137d5fb37000fd Mon Sep 17 00:00:00 2001 From: Pavel Kolesnikov Date: Fri, 20 Jul 2007 15:03:03 +0200 Subject: POST: Add ECC POST for the lwmon5 board This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov Acked-by: Yuri Tikhonov Acked-by: Stefan Roese --- board/lwmon5/lwmon5.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'board') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index d916284..b7dbba3 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -463,3 +463,14 @@ void hw_watchdog_reset(void) val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; gpio_write_bit(CFG_GPIO_WATCHDOG, val); } + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return (ctrlc()); +} +#endif -- cgit v1.1 From aedf5bde179ecfbd0a96130d18996a96518b785f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 24 Jul 2007 07:20:09 +0200 Subject: ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...) As suggested by Hakan Eryigit, here an updated setup for the lwmon5 interrupt controller. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b7dbba3..5c4cf9d 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -45,16 +45,16 @@ int board_early_init_f(void) mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */ - mtdcr(uic0tr, 0x00000810); /* per ref-board manual */ + mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ + mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */ - mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */ + mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ + mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(uic1sr, 0xffffffff); /* clear all */ @@ -62,9 +62,9 @@ int board_early_init_f(void) mtdcr(uic2er, 0x00000000); /* disable all */ mtdcr(uic2cr, 0x00000000); /* all non-critical */ mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */ + mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); -- cgit v1.1 From 9f24a808f17fc0f37b7fb4805f734741335caecc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 24 Jul 2007 09:52:52 +0200 Subject: ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added The used Intel NOR FLASH chips have internally two dies, and are now treated as two seperate chips. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 5c4cf9d..66cef2f 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -158,13 +158,13 @@ int misc_init_r(void) (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, - &flash_info[0]); + &flash_info[1]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); + &flash_info[1]); /* * USB suff... -- cgit v1.1 From b66091de6c7390620312c2501db23d8391e7cabb Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 26 Jul 2007 15:08:01 +0200 Subject: ppc4xx: lwmon5: Update Lime initialization Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 66cef2f..830ec19 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -221,8 +221,8 @@ int misc_init_r(void) udelay(500); gpio_write_bit(CFG_GPIO_LIME_RST, 1); - /* Lime memory clock adjusted to 133MHz */ - out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ); + /* Lime memory clock adjusted to 100MHz */ + out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ); /* Wait untill time expired. Because of requirements in lime manual */ udelay(300); /* Write lime controller memory parameters */ @@ -237,6 +237,64 @@ int misc_init_r(void) gpio_write_bit(CFG_GPIO_PHY0_RST, 1); gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + /* + * Init display controller + */ + /* Setup dot clock (internal PLL, division rate 1/16) */ + out_be32((void *)0xc1fd0100, 0x00000f00); + + /* Lime L0 init (16 bpp, 640x480) */ + out_be32((void *)0xc1fd0020, 0x801401df); + out_be32((void *)0xc1fd0024, 0x0); + out_be32((void *)0xc1fd0028, 0x0); + out_be32((void *)0xc1fd002c, 0x0); + out_be32((void *)0xc1fd0110, 0x0); + out_be32((void *)0xc1fd0114, 0x0); + out_be32((void *)0xc1fd0118, 0x01df0280); + + /* Display timing init */ + out_be32((void *)0xc1fd0004, 0x031f0000); + out_be32((void *)0xc1fd0008, 0x027f027f); + out_be32((void *)0xc1fd000c, 0x015f028f); + out_be32((void *)0xc1fd0010, 0x020c0000); + out_be32((void *)0xc1fd0014, 0x01df01ea); + out_be32((void *)0xc1fd0018, 0x0); + out_be32((void *)0xc1fd001c, 0x01e00280); + +#if 1 + /* + * Clear framebuffer using Lime's drawing engine + * (draw blue rect. with white border around it) + */ + /* Setup mode and fbbase, xres, fg, bg */ + out_be32((void *)0xc1ff0420, 0x8300); + out_be32((void *)0xc1ff0440, 0x0000); + out_be32((void *)0xc1ff0444, 0x0280); + out_be32((void *)0xc1ff0480, 0x7fff); + out_be32((void *)0xc1ff0484, 0x0000); + /* Reset clipping rectangle */ + out_be32((void *)0xc1ff0454, 0x0000); + out_be32((void *)0xc1ff0458, 0x0280); + out_be32((void *)0xc1ff045c, 0x0000); + out_be32((void *)0xc1ff0460, 0x01e0); + /* Draw white rect. */ + out_be32((void *)0xc1ff04a0, 0x09410000); + out_be32((void *)0xc1ff04a0, 0x00000000); + out_be32((void *)0xc1ff04a0, 0x01e00280); + udelay(2000); + /* Draw blue rect. */ + out_be32((void *)0xc1ff0480, 0x001f); + out_be32((void *)0xc1ff04a0, 0x09410000); + out_be32((void *)0xc1ff04a0, 0x00010001); + out_be32((void *)0xc1ff04a0, 0x01de027e); +#endif + /* Display enable, L0 layer */ + out_be32((void *)0xc1fd0100, 0x80010f00); + + /* TFT-LCD enable - PWM duty, lamp on */ + out_be32((void *)0xc4000024, 0x64); + out_be32((void *)0xc4000020, 0x701); + return 0; } -- cgit v1.1 From d4024bb72dd81695ec099b2199eda0d27c623e62 Mon Sep 17 00:00:00 2001 From: John Otken Date: Thu, 26 Jul 2007 17:49:11 +0200 Subject: ppc4xx: Add support for AMCC 405EP Taihu board Signed-off-by: John Otken --- board/amcc/taihu/Makefile | 49 ++ board/amcc/taihu/config.mk | 24 + board/amcc/taihu/flash.c | 1083 +++++++++++++++++++++++++++++++++++++++++++ board/amcc/taihu/lcd.c | 257 ++++++++++ board/amcc/taihu/taihu.c | 234 ++++++++++ board/amcc/taihu/u-boot.lds | 150 ++++++ board/amcc/taihu/update.c | 132 ++++++ 7 files changed, 1929 insertions(+) create mode 100644 board/amcc/taihu/Makefile create mode 100644 board/amcc/taihu/config.mk create mode 100644 board/amcc/taihu/flash.c create mode 100644 board/amcc/taihu/lcd.c create mode 100644 board/amcc/taihu/taihu.c create mode 100644 board/amcc/taihu/u-boot.lds create mode 100644 board/amcc/taihu/update.c (limited to 'board') diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile new file mode 100644 index 0000000..9731c6e --- /dev/null +++ b/board/amcc/taihu/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o lcd.o update.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/taihu/config.mk b/board/amcc/taihu/config.mk new file mode 100644 index 0000000..1bdf5e4 --- /dev/null +++ b/board/amcc/taihu/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c new file mode 100644 index 0000000..290259e --- /dev/null +++ b/board/amcc/taihu/flash.c @@ -0,0 +1,1083 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include +#include +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define CFG_FLASH_CHAR_SIZE unsigned char +#define CFG_FLASH_CHAR_ADDR0 (0x0aaa) +#define CFG_FLASH_CHAR_ADDR1 (0x0555) +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef FLASH_BASE1_PRELIM +static int write_word_1(flash_info_t * info, ulong dest, ulong data); +static int write_word_2(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_1(flash_info_t * info, int s_first, int s_last); +static int flash_erase_2(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); +#endif + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1=0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + if (size_b0) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + /* Also protect sector containing initial power-up instruction */ + /* (flash_protect() checks address range - other call ignored) */ + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); + + flash_info[0].size = size_b0; + } +#ifdef FLASH_BASE1_PRELIM + size_b1 = + flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2; + + if (flash_info[1].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", + size_b1, size_b1 << 20); + } + + if (size_b1) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]); + flash_info[1].size = size_b1; + } +#endif + return (size_b0 + size_b1); +} + +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000*2); + } + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000*2); + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} + + +void flash_print_info(flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: + printf("AM29LV033C (32 Mbit, top boot sector)\n"); + break; + case FLASH_AMLV128U: + printf("AM29LV128U (128 Mbit * 2, top boot sector)\n"); + break; + case FLASH_SST800A: + printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: + printf ("M29W320DT (32 M, top sector)\n"); + break; + case FLASH_S29GL128N: + printf ("S29GL128N (256 Mbit, uniform sector size)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef FLASH_BASE1_PRELIM +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + if ((ulong)addr == FLASH_BASE1_PRELIM) { + return flash_get_size_2(addr, info); + } else { + return flash_get_size_1(addr, info); + } +} + +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return 0; /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } + else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000 * 2); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return info->size; +} + +static int wait_for_DQ7_1(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef FLASH_BASE1_PRELIM +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return flash_erase_2(info, s_first, s_last); + } else { + return flash_erase_1(info, s_first, s_last); + } +} + +static int flash_erase_1(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_1(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return 0; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef FLASH_BASE1_PRELIM +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return write_word_2(info, dest, data); + } else { + return write_word_1(info, dest, data); + } +} + +static int write_word_1(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return 2; + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return 1; + } + } + } + + return 0; +} + +#ifdef FLASH_BASE1_PRELIM + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) +{ + short i; + CFG_FLASH_CHAR_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + udelay(1000); + + value = (CFG_FLASH_CHAR_SIZE)addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return 0; /* no or unknown flash */ + } + + value = (CFG_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR: + if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 + && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { + info->flash_id += FLASH_AMLV128U; + info->sector_count = 256; + info->size = 0x01000000; + } else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 + && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { + info->flash_id += FLASH_S29GL128N; + info->sector_count = 128; + info->size = 0x01000000; + } + else + info->flash_id = FLASH_UNKNOWN; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00020000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; + return info->size; +} + +static int wait_for_DQ7_2(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) != + (CFG_FLASH_WORD_SIZE) 0x80808080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_2(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080; + addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_2(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_2(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return 2; + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return 1; + } + } + } + + return 0; +} + +#endif /* FLASH_BASE1_PRELIM */ diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c new file mode 100644 index 0000000..3d042df --- /dev/null +++ b/board/amcc/taihu/lcd.c @@ -0,0 +1,257 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define LCD_CMD_ADDR 0x50100002 +#define LCD_DATA_ADDR 0x50100003 +#define LCD_BLK_CTRL CPLD_REG1_ADDR + +static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT"; +static int addr_flag = 0x80; + +static void lcd_bl_ctrl(char val) +{ + out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val); +} + +static void lcd_putc(int val) +{ + int i = 100; + char addr; + + while (i--) { + if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ + udelay(50); + break; + } + udelay(50); + } + + if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { + printf("LCD is busy\n"); + return; + } + + addr = in_8((u8 *) LCD_CMD_ADDR); + udelay(50); + if ((addr != 0) && (addr % 0x10 == 0)) { + addr_flag ^= 0x40; + out_8((u8 *) LCD_CMD_ADDR, addr_flag); + } + + udelay(50); + out_8((u8 *) LCD_DATA_ADDR, val); + udelay(50); +} + +static void lcd_puts(char *s) +{ + char *p = s; + int i = 100; + + while (i--) { + if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ + udelay(50); + break; + } + udelay(50); + } + + if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { + printf("LCD is busy\n"); + return; + } + + while (*p) + lcd_putc(*p++); +} + +static void lcd_put_logo(void) +{ + int i = 100; + char *p = amcc_logo; + + while (i--) { + if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ + udelay(50); + break; + } + udelay(50); + } + + if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { + printf("LCD is busy\n"); + return; + } + + out_8((u8 *) LCD_CMD_ADDR, 0x80); + while (*p) + lcd_putc(*p++); +} + +int lcd_init(void) +{ + puts("LCD: "); + out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */ + udelay(50); + out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */ + udelay(50); + out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */ + udelay(2000); + out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */ + udelay(50); + lcd_bl_ctrl(0x02); /* set backlight on */ + lcd_put_logo(); + puts("ready\n"); + + return 0; +} + +static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + out_8((u8 *) LCD_CMD_ADDR, 0x01); + udelay(2000); + + return 0; +} + +static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf("%s", cmdtp->usage); + return 1; + } + lcd_puts(argv[1]); + + return 0; +} + +static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf("%s", cmdtp->usage); + return 1; + } + lcd_putc((char)argv[1][0]); + + return 0; +} + +static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong count; + ulong dir; + char cur_addr; + + if (argc < 3) { + printf("%s", cmdtp->usage); + return 1; + } + + count = simple_strtoul(argv[1], NULL, 16); + if (count > 31) { + printf("unable to shift > 0x20\n"); + count = 0; + } + + dir = simple_strtoul(argv[2], NULL, 16); + cur_addr = in_8((u8 *) LCD_CMD_ADDR); + udelay(50); + + if (dir == 0x0) { + if (addr_flag == 0x80) { + if (count >= (cur_addr & 0xf)) { + out_8((u8 *) LCD_CMD_ADDR, 0x80); + udelay(50); + count = 0; + } + } else { + if (count >= ((cur_addr & 0x0f) + 0x0f)) { + out_8((u8 *) LCD_CMD_ADDR, 0x80); + addr_flag = 0x80; + udelay(50); + count = 0x0; + } else if (count >= ( cur_addr & 0xf)) { + count -= cur_addr & 0xf ; + out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf); + addr_flag = 0x80; + udelay(50); + } + } + } else { + if (addr_flag == 0x80) { + if (count >= (0x1f - (cur_addr & 0xf))) { + count = 0x0; + addr_flag = 0xc0; + out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf); + udelay(50); + } else if ((count + (cur_addr & 0xf ))>= 0x0f) { + count = count + (cur_addr & 0xf) - 0x0f; + addr_flag = 0xc0; + out_8((u8 *) LCD_CMD_ADDR, 0xc0); + udelay(50); + } + } else if ((count + (cur_addr & 0xf )) >= 0x0f) { + count = 0x0; + out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F); + udelay(50); + } + } + while (count--) { + if (dir == 0) + out_8((u8 *) LCD_CMD_ADDR, 0x10); + else + out_8((u8 *) LCD_CMD_ADDR, 0x14); + udelay(50); + } + + return 0; +} + +U_BOOT_CMD( + lcd_cls, 1, 1, do_lcd_clear, + "lcd_cls - lcd clear display\n", + NULL + ); + +U_BOOT_CMD( + lcd_puts, 2, 1, do_lcd_puts, + "lcd_puts - display string on lcd\n", + " - to be displayed\n" + ); + +U_BOOT_CMD( + lcd_putc, 2, 1, do_lcd_putc, + "lcd_putc - display char on lcd\n", + " - to be displayed\n" + ); + +U_BOOT_CMD( + lcd_cur, 3, 1, do_lcd_cur, + "lcd_cur - shift cursor on lcd\n", + " - shift cursor on lcd times, direction is \n" + " - 0..31\n" + " - 0=backward 1=forward\n" + ); diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c new file mode 100644 index 0000000..ee9d3b5 --- /dev/null +++ b/board/amcc/taihu/taihu.c @@ -0,0 +1,234 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2005-2007 + * Beijing UD Technology Co., Ltd., taihusupport@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +extern int lcd_init(void); + +/* + * board_early_init_f + */ +int board_early_init_f(void) +{ + lcd_init(); + + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); + mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + + mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ + mtebc(pb3cr, CFG_EBC_PB3CR); + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Taihu - AMCC PPC405EP Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram(int board) +{ + return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */ +} + +static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) +{ + char stat; + int i; + + stat = in_8((u8 *) CPLD_REG0_ADDR); + printf("SW2 status: "); + for (i=0; i<4; i++) /* 4-position */ + printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); + printf("\n"); + return 0; +} + +U_BOOT_CMD ( + sw2_stat, 1, 1, do_sw_stat, + "sw2_stat - show status of switch 2\n", + NULL + ); + +static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) +{ + int led_no; + + if (argc != 3) { + printf("%s", cmd_tp->usage); + return -1; + } + + led_no = simple_strtoul(argv[1], NULL, 16); + if (led_no != 1 && led_no != 2) { + printf("%s", cmd_tp->usage); + return -1; + } + + if (strcmp(argv[2],"off") == 0x0) { + if (led_no == 1) + gpio_write_bit(30, 1); + else + gpio_write_bit(31, 1); + } else if (strcmp(argv[2],"on") == 0x0) { + if (led_no == 1) + gpio_write_bit(30, 0); + else + gpio_write_bit(31, 0); + } else { + printf("%s", cmd_tp->usage); + return -1; + } + + return 0; +} + +U_BOOT_CMD ( + led_ctl, 3, 1, do_led_ctl, + "led_ctl - make led 1 or 2 on or off\n", + " - make led on/off,\n" + "\tled_no is 1 or 2\t" + ); + +#define SPI_CS_GPIO0 0 +#define SPI_SCLK_GPIO14 14 +#define SPI_DIN_GPIO15 15 +#define SPI_DOUT_GPIO16 16 + +void spi_scl(int bit) +{ + gpio_write_bit(SPI_SCLK_GPIO14, bit); +} + +void spi_sda(int bit) +{ + gpio_write_bit(SPI_DOUT_GPIO16, bit); +} + +unsigned char spi_read(void) +{ + return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15); +} + +void taihu_spi_chipsel(int cs) +{ + gpio_write_bit(SPI_CS_GPIO0, cs); +} + +spi_chipsel_type spi_chipsel[]= { + taihu_spi_chipsel +}; + +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#ifdef CONFIG_PCI +static unsigned char int_lines[32] = { + 29, 30, 27, 28, 29, 30, 25, 27, + 29, 30, 27, 28, 29, 30, 27, 28, + 29, 30, 27, 28, 29, 30, 27, 28, + 29, 30, 27, 28, 29, 30, 27, 28}; + +static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = int_lines[PCI_DEV(dev) & 31]; + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +int pci_pre_init(struct pci_controller *hose) +{ + hose->fixup_irq = taihu_pci_fixup_irq; + return 1; +} +#endif /* CONFIG_PCI */ + +#ifdef CFG_DRAM_TEST +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + unsigned long msr; + unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024; + + msr = mfmsr(); + mtmsr(msr & ~(MSR_EE)); + + for (k = 0; k < total_kbytes ; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) + printf("%3d MB\r", k / 1024); + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + mtmsr(msr); + + return 0; +} +#endif /* CFG_DRAM_TEST */ diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds new file mode 100644 index 0000000..be03092 --- /dev/null +++ b/board/amcc/taihu/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c new file mode 100644 index 0000000..55ad535 --- /dev/null +++ b/board/amcc/taihu/update.c @@ -0,0 +1,132 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define PCI_M66EN 0x10 + +static uchar buf_33[] = +{ + 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ + 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ + 0x00, + 0x00, + 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ + 0x00, + 0x00, + 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ + 0x14, + 0x00, /* 0x0f~0x10:device id 0x0000*/ + 0x00, + 0x00, /* 0x11:revision 0x00 */ + 0x00, /* 0x12~0x14:class 0x000000 */ + 0x00, + 0x00, + 0x10, /* 0x15~0x16:subsystem vendor id */ + 0xe8, + 0x00, /* 0x17~0x18:subsystem device id */ + 0x00, + 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ + 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ + 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ + 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ + 0xbe, /* 0x1d: tun[24-31]=0xbe */ + 0x00, + 0x00 +}; + +static uchar buf_66[] = +{ + 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ + 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ + 0x00, + 0x00, + 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ + 0x00, + 0x00, + 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ + 0x00, + 0x00, + 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ + 0x14, + 0x00, /* 0x0f~0x10:device id 0x0000*/ + 0x00, + 0x00, /* 0x11:revision 0x00 */ + 0x00, /* 0x12~0x14:class 0x000000 */ + 0x00, + 0x00, + 0x10, /* 0x15~0x16:subsystem vendor id */ + 0xe8, + 0x00, /* 0x17~0x18:subsystem device id */ + 0x00, + 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ + 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ + 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ + 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ + 0xbe, /* 0x1d: tun[24-31]=0xbe */ + 0x00, + 0x00 +}; + +static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[]) +{ + ulong len = 0x20; + uchar chip = CFG_I2C_EEPROM_ADDR; + uchar *pbuf; + uchar base; + int i; + + if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) { + pbuf = buf_33; + base = 0x00; + } else { + pbuf = buf_66; + base = 0x40; + } + + for (i = 0; i< len; i++, base++) { + if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) { + printf("i2c_write fail\n"); + return 1; + } + udelay(11000); + } + + return 0; +} + +U_BOOT_CMD ( + update_boot_eeprom, 1, 1, update_boot_eeprom, + "update_boot_eeprom - update boot eeprom content\n", + NULL + ); -- cgit v1.1 From e36220a4baf1f188ba60f17e9d0f043069b1362a Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 27 Jul 2007 16:44:31 +0200 Subject: new FPGA image for PLU405 board new FPGA image for PLU405 board with improved CompactFlash timing Signed-off-by: Matthias Fuchs --- board/esd/plu405/fpgadata.c | 2339 ++++++++++++++++++++++--------------------- 1 file changed, 1179 insertions(+), 1160 deletions(-) (limited to 'board') diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c index f6656c1..dc8c88b 100644 --- a/board/esd/plu405/fpgadata.c +++ b/board/esd/plu405/fpgadata.c @@ -1,1160 +1,1179 @@ - 0x1f,0x8b,0x08,0x08,0x9d,0x76,0x5c,0x3f,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x6c,0x1d,0x55, - 0x76,0xc7,0xcf,0xfc,0xb0,0x3d,0xf6,0x7b,0xf1,0x9b,0x24,0x76,0xeb,0x6e,0x82,0x33, - 0xfe,0x41,0xf4,0x48,0x9f,0x5f,0x5e,0x9c,0x1f,0x18,0x63,0xec,0x89,0x13,0xed,0x5a, - 0x4b,0xda,0x58,0x2a,0xad,0x56,0x15,0x62,0x0d,0x9b,0xad,0xa2,0xca,0x44,0xa6,0xdb, - 0x56,0x51,0xba,0x0d,0xd7,0x71,0x20,0x06,0x7b,0x89,0xa1,0x48,0x04,0x9a,0xd2,0x17, - 0x88,0x84,0x05,0xd6,0xea,0xe5,0x47,0x89,0x21,0x29,0x4c,0x8c,0x81,0x07,0x4d,0x83, - 0x9b,0xa0,0x2a,0x1b,0x68,0x78,0x50,0x2f,0x98,0x10,0xb2,0xce,0x8f,0x06,0x93,0x38, - 0x71,0xef,0x9d,0x99,0x7b,0xe7,0xce,0xaf,0x67,0xaf,0xf7,0x8f,0x3d,0x99,0x77,0x35, - 0xdc,0x73,0xde,0x9d,0x73,0x3e,0xf3,0x3d,0xe7,0x41,0x71,0x6c,0xd2,0xfa,0x1f,0x80, - 0xf0,0x20,0xa8,0x5d,0x9d,0x7f,0xb7,0x2a,0xb5,0xfa,0xa7,0x2b,0x7e,0x9a,0x4a,0x25, - 0xb7,0xfc,0x6c,0x13,0x3c,0x04,0x91,0xfa,0x5f,0xac,0x4e,0xfd,0xfc,0x6f,0x1f,0x59, - 0xb1,0x6a,0x15,0xfc,0x0c,0xff,0x2b,0x95,0x5a,0xb9,0x3c,0x75,0xd7,0xf2,0x54,0x03, - 0x6c,0x82,0xe2,0x15,0xab,0x1a,0x57,0xae,0x68,0xac,0x5f,0x05,0x3f,0x07,0x61,0xe5, - 0xfe,0x19,0xfc,0xf7,0xea,0xf3,0x7f,0xfe,0x57,0x29,0x40,0x02,0x00,0x14,0xa5,0x84, - 0x0e,0xf2,0xff,0x91,0x94,0xa0,0x09,0x80,0x5a,0xea,0x52,0x60,0x90,0x7f,0x83,0xfd, - 0x79,0x71,0x0a,0x34,0xfe,0xdf,0x42,0x0a,0x74,0x68,0x07,0xbd,0x1f,0x16,0xa8,0x30, - 0xeb,0x9f,0xa0,0xcb,0x88,0xda,0xbf,0xe7,0xfa,0x99,0x0f,0x51,0xe8,0x32,0xe7,0xaf, - 0xe5,0x72,0x9a,0x9a,0x62,0x6a,0x2e,0xf7,0x07,0x76,0xff,0xb3,0x73,0xba,0xff,0x35, - 0x7a,0xff,0xdf,0x77,0x3d,0x2c,0x98,0xc3,0x72,0x00,0x99,0xed,0xc7,0x0a,0x8f,0x0c, - 0x78,0x87,0x1d,0xa0,0x42,0x21,0x08,0xc4,0xa8,0x00,0xd1,0x75,0xff,0x51,0xba,0xfe, - 0x78,0xc1,0x2d,0x98,0x41,0x2d,0xe3,0xa5,0x5b,0xa5,0x2d,0xea,0x0d,0xf4,0x07,0xb9, - 0xd8,0x94,0x84,0xaf,0xec,0x6c,0xb1,0x8c,0xcf,0x90,0x69,0x4c,0xca,0x5d,0xf6,0xfa, - 0x91,0x8a,0x8b,0x70,0x14,0x25,0x0d,0x65,0x8f,0x98,0x94,0xb1,0xf1,0x79,0xdf,0xb0, - 0x68,0x5e,0xc9,0x45,0x1c,0x43,0xca,0xc8,0x34,0x8a,0x59,0xe8,0x87,0x43,0x10,0xcf, - 0xfe,0x20,0x25,0x9e,0xc0,0x46,0xad,0xb1,0xc8,0x32,0x12,0x46,0x84,0x18,0xff,0x64, - 0x19,0x97,0x05,0x7a,0x7f,0x03,0x86,0xe0,0x28,0xbe,0xa8,0x0c,0x8b,0xc4,0x48,0x1a, - 0x91,0x8c,0x78,0xc1,0x6d,0xf4,0x65,0x60,0x12,0xbb,0x64,0xfd,0xad,0x2d,0xbf,0x00, - 0x37,0xa0,0xd1,0x28,0xcd,0x48,0xc4,0x58,0x63,0xc4,0x2c,0xa3,0xd9,0x32,0x3e,0xb1, - 0x8c,0x31,0xa0,0xf7,0x4f,0x0b,0xc7,0x60,0x06,0x5a,0x8c,0xd8,0xa4,0xf4,0x4b,0x6a, - 0x4c,0xfb,0x8c,0x41,0x76,0x7f,0x43,0x1d,0x32,0xef,0x16,0x7d,0x53,0x4a,0x10,0xe3, - 0x38,0x7f,0x5b,0xfa,0x1f,0x5a,0x78,0x15,0x34,0xba,0xbe,0x20,0x61,0x6e,0x52,0x59, - 0x05,0x09,0xf8,0x46,0xb4,0xb7,0x7d,0xb7,0xc7,0x91,0xcb,0xf8,0xf4,0xdb,0xeb,0xe5, - 0x0d,0x66,0x34,0x8a,0xcb,0xc4,0xa8,0x2f,0x2c,0x2c,0x50,0x53,0x72,0xbb,0xbd,0x7e, - 0x4a,0x7d,0x00,0x8e,0xa0,0xba,0x5c,0xf1,0x4f,0xc4,0x4a,0x78,0x05,0xd5,0x4d,0x44, - 0xb6,0x8a,0xe7,0x10,0xb9,0x42,0x0c,0xb0,0x8d,0x5b,0xec,0xfe,0x6d,0xca,0x06,0xb8, - 0x82,0x37,0x39,0x4f,0x95,0x4a,0x8d,0x2b,0xdd,0x4d,0x13,0xb1,0x54,0xcd,0x49,0x38, - 0x0d,0x4d,0x46,0x2c,0x25,0x9d,0xc0,0x1f,0x35,0x8d,0x62,0xe3,0x14,0x3b,0x1d,0x7a, - 0xf9,0x31,0x99,0x04,0x21,0x99,0x21,0xd1,0x50,0x5b,0x46,0x63,0x97,0x2c,0xc3,0x15, - 0x9f,0xb1,0x42,0x1a,0x1f,0x45,0xb6,0xe2,0x13,0x1b,0xa8,0x21,0xd1,0x48,0x7a,0xe2, - 0x6f,0x1b,0xe7,0x59,0xfc,0x4f,0x54,0xec,0x85,0x23,0x50,0x67,0x44,0xba,0xc4,0x4f, - 0x4d,0xa3,0x94,0x1a,0x11,0xce,0xb8,0x2c,0xd3,0xfb,0x6b,0xf0,0x22,0x76,0xea,0xe1, - 0x5c,0xe4,0x27,0xe2,0x39,0x81,0x78,0xd7,0xc7,0xb9,0xc9,0x8c,0x1c,0x8b,0x7f,0xa7, - 0xdc,0x6f,0x05,0x6d,0x58,0x3c,0x21,0x10,0xe3,0x07,0xae,0xf3,0x66,0x1b,0xa7,0xd8, - 0xf9,0x9c,0x28,0x9f,0x80,0xeb,0xd0,0x8c,0x62,0x83,0x3d,0xb6,0x91,0x96,0x88,0xb1, - 0x9d,0x1a,0xe6,0x95,0xeb,0x6c,0x3f,0x6d,0x42,0x1a,0xa6,0xa0,0x19,0x62,0x48,0xca, - 0x99,0x46,0x29,0x31,0x86,0xf9,0x2b,0xd8,0x38,0x05,0xf4,0xfe,0x8a,0xba,0x1f,0xbe, - 0x87,0x66,0x3d,0x36,0x20,0x6d,0xb2,0x8d,0x75,0xe3,0xf4,0x0a,0x33,0x46,0xd8,0x7e, - 0x10,0x4e,0xb5,0x6f,0x40,0x52,0x8f,0xec,0x91,0x6c,0x63,0x40,0x1c,0x17,0xa8,0x61, - 0x5e,0x29,0x1d,0xc0,0xfe,0xd2,0x2c,0xd8,0x50,0x50,0x6b,0x2d,0x7b,0x46,0xac,0x65, - 0xeb,0x65,0xd7,0x7a,0x6c,0xbc,0xc7,0xce,0x83,0x56,0x26,0xc3,0x01,0x48,0xb4,0xf7, - 0x0d,0x2c,0x58,0x4f,0x0c,0x3d,0xa2,0x8a,0xa3,0x6e,0xa3,0x44,0x15,0x47,0x04,0x7a, - 0x1e,0xb6,0xce,0xeb,0xa0,0x4e,0x69,0x8e,0xe3,0x5e,0x7f,0x4f,0x4a,0xf4,0x7c,0xee, - 0x29,0xb7,0x9d,0x1a,0xb3,0xbd,0xdb,0x8d,0xdd,0x94,0x5d,0xfe,0x96,0x0e,0x48,0x5f, - 0x16,0xd2,0xf3,0x50,0x51,0x60,0x5d,0x5c,0x32,0x56,0x53,0xeb,0x0b,0x0b,0x33,0xde, - 0x63,0xe7,0xa7,0x41,0xc9,0xc9,0xc3,0x90,0x54,0x22,0x48,0xd4,0xcc,0x6d,0x60,0x83, - 0xec,0x27,0xe9,0x32,0x4e,0xb2,0x78,0xb6,0x95,0xef,0x24,0x4e,0xb5,0x46,0xd4,0xc2, - 0x9d,0xca,0x01,0xa1,0xd3,0x76,0x53,0x20,0xfe,0x16,0x32,0xc7,0x4f,0xb1,0xfc,0xb3, - 0x47,0xde,0x6f,0x06,0x6d,0xd1,0x40,0x09,0x31,0x96,0xb9,0xc2,0xe8,0xc4,0x93,0x9d, - 0x87,0xb4,0xed,0x6f,0x44,0x95,0xc8,0x17,0x9d,0x0c,0xde,0xff,0x04,0xcb,0x9f,0x59, - 0xc1,0x3a,0x0f,0xbb,0x9f,0xe9,0xc1,0xe7,0x41,0x60,0xcb,0xb6,0xbb,0xd6,0x5f,0x67, - 0xf9,0x47,0x51,0xed,0xf3,0xd6,0x2d,0x79,0x0e,0x1e,0x6f,0x7c,0x28,0xd3,0xf3,0x1f, - 0x2f,0x88,0xc3,0x9b,0x90,0x44,0xf7,0x8e,0x8b,0x13,0xc4,0xe8,0x8e,0xa4,0xc5,0x09, - 0xf9,0x4d,0xd8,0x82,0xee,0x4d,0x5b,0x57,0x50,0x24,0x2d,0x3d,0xc9,0xce,0x43,0xdc, - 0xce,0x3f,0x8b,0x34,0xb5,0x5f,0xf5,0x3e,0x26,0xcc,0xf8,0x10,0xe8,0xf7,0x8b,0xe0, - 0x7e,0xf2,0x90,0x9e,0x88,0x74,0x04,0x3c,0xb6,0xcc,0x18,0x64,0xf7,0xef,0x45,0x0f, - 0xa8,0xdf,0xa1,0x7b,0x72,0xb1,0xcd,0xd2,0x8b,0x60,0x1a,0x5b,0xa5,0x73,0xd8,0xa8, - 0xa3,0x86,0x79,0xe5,0x3c,0xcb,0x3f,0x4a,0xb9,0x9d,0x4f,0xd2,0x5c,0x1a,0x91,0xbd, - 0xf9,0x64,0x84,0xe5,0x1f,0x90,0xdf,0x22,0xf5,0xeb,0x6a,0xec,0x6b,0x69,0x3b,0x31, - 0x72,0xa5,0x66,0xfd,0x1a,0xb0,0xeb,0xd7,0x8c,0x55,0xbf,0x0c,0x76,0x7e,0x06,0x2b, - 0xf6,0xea,0x78,0x93,0x13,0x91,0x6d,0xe2,0x62,0xba,0xdb,0x93,0xbd,0xde,0xfd,0x9f, - 0x67,0xdf,0x2f,0x20,0x3b,0x5f,0xe9,0xa2,0xe9,0xb8,0x51,0x82,0x97,0xa1,0x23,0xf0, - 0xb0,0x6b,0xbd,0xc1,0xf2,0x8f,0x46,0xf3,0x8f,0xca,0xe7,0x73,0xaf,0x91,0x65,0xe7, - 0x73,0xd0,0xf4,0x17,0x27,0xd5,0x5e,0xa9,0xd3,0xf4,0xae,0x34,0x30,0x7f,0xb2,0xfd, - 0x20,0xc1,0xbe,0x38,0x58,0x94,0xf0,0x2d,0x63,0x46,0x8e,0xe5,0x9f,0x2a,0xf5,0x98, - 0x62,0x26,0x6d,0x63,0xdd,0x2f,0xe1,0x77,0xb4,0xcc,0x7d,0xe6,0xa9,0x77,0x68,0x3d, - 0x5d,0xbf,0x4f,0xee,0xb4,0x8a,0x54,0x5c,0x4c,0xd8,0xf9,0xdc,0x5b,0x7f,0xb1,0xe1, - 0xe4,0x1f,0x24,0x58,0xf5,0x2e,0xd2,0xdb,0x9a,0x08,0xa9,0xd7,0xd8,0x48,0xb3,0xf3, - 0xa0,0x94,0x99,0x61,0xc9,0x46,0x32,0x49,0x6c,0xa8,0x89,0xb1,0x7b,0x53,0xe2,0x7f, - 0x22,0x6f,0x7c,0x9c,0xfc,0x03,0xbf,0x22,0xfb,0x69,0xc9,0xe2,0x43,0xfe,0x30,0x7c, - 0xa3,0x37,0x8f,0x11,0x37,0x91,0xa7,0xfe,0x4a,0x88,0xe5,0x9f,0x74,0xf9,0x34,0x3c, - 0x0a,0x78,0xd9,0x7c,0xe9,0x98,0x46,0xfc,0x2d,0x9d,0x94,0xbe,0x45,0xde,0xfa,0x3e, - 0x21,0x32,0xde,0x30,0xf9,0xa7,0x39,0x17,0xfb,0xa2,0xa7,0x99,0x9e,0x96,0x21,0xf4, - 0x11,0x72,0x9f,0x9f,0x49,0x76,0x7e,0x90,0x6a,0x43,0xce,0x90,0x98,0x2c,0x30,0x8d, - 0xcc,0x43,0x33,0x7a,0x9f,0x9b,0x7f,0xc4,0x1c,0xfb,0x7e,0x95,0x82,0x13,0x8a,0xe9, - 0x14,0xf0,0xe7,0xa1,0x47,0xf4,0xfa,0xcb,0xf6,0x53,0x6e,0x61,0x8f,0x94,0x16,0x69, - 0x3c,0x5b,0x2f,0x88,0x7d,0x9e,0x78,0x4e,0x3a,0xe7,0xf3,0xd9,0x21,0x1a,0x04,0xb2, - 0xde,0x34,0x86,0xe0,0x3f,0xdc,0xf1,0x11,0x0d,0x96,0x7f,0x3e,0x07,0x9b,0x7f,0xb4, - 0x08,0x8b,0xc6,0xa7,0x3e,0xfe,0x99,0xe2,0xf8,0xc7,0x3e,0x66,0x03,0x52,0x82,0x7b, - 0x1e,0x45,0x77,0xfc,0x27,0x59,0xfe,0xc9,0xca,0xf6,0xb6,0x9d,0xfd,0x8b,0xd3,0xbe, - 0xf3,0xe0,0xf0,0x4f,0xae,0x80,0xe4,0x9f,0xb8,0x11,0xb9,0x23,0x2f,0xff,0xb0,0xfc, - 0xd3,0x21,0x54,0x5a,0x45,0x7f,0x33,0xe6,0x9f,0x23,0x3b,0xb1,0xb1,0xad,0xda,0xcf, - 0x03,0x67,0x38,0xfe,0x89,0xea,0x57,0xa0,0x21,0x17,0x83,0x48,0x14,0xd3,0xce,0x62, - 0x23,0xd6,0x28,0x9d,0x84,0x2b,0x99,0xa6,0x1c,0xe5,0x1f,0xc3,0xcd,0x3f,0xb7,0x99, - 0xf1,0x19,0x8d,0xe5,0x38,0xfe,0xd1,0xcd,0x2b,0x81,0xfc,0x33,0x58,0xe0,0x7f,0xfa, - 0x2e,0xa0,0x6f,0x42,0xf9,0x27,0x3b,0xdf,0xce,0x27,0x7c,0xfe,0x4c,0x87,0xf3,0x8f, - 0x61,0xf2,0x4f,0x9d,0xc9,0x3f,0xcc,0x4d,0xfd,0x15,0x8f,0xbf,0x93,0x2c,0xff,0xb4, - 0x95,0xd9,0x41,0xab,0x0d,0x48,0x3b,0x81,0xfc,0x33,0x68,0x41,0x4e,0x87,0xc4,0xf1, - 0xcf,0x79,0x07,0x84,0xbc,0xfc,0x03,0xb4,0xe8,0xf4,0xe4,0x60,0x2b,0x6c,0x0f,0xae, - 0x47,0x3c,0xff,0xd8,0x45,0x6d,0x8f,0x84,0xeb,0xbb,0xe4,0xaf,0xef,0x8d,0x21,0xfc, - 0xf3,0x34,0xc7,0x3f,0x3e,0xc3,0xc9,0x3f,0x15,0x72,0x2d,0xa5,0xa3,0xda,0xc0,0x7a, - 0xbd,0xcc,0xcd,0x3f,0x8a,0x2c,0x5b,0x45,0x9f,0xf1,0x4f,0x99,0x97,0x7f,0x22,0x3c, - 0xff,0x0c,0x17,0x7b,0xf8,0xe7,0x23,0x8f,0xbf,0x8d,0xc4,0xb8,0xe8,0xf0,0xcf,0x6d, - 0xb6,0x77,0x1f,0x3b,0x6e,0xfe,0xd6,0xc7,0x03,0x0e,0xff,0xec,0x31,0xf9,0xa7,0x45, - 0x4f,0x8c,0xf5,0x8c,0xc3,0x4d,0xf2,0xe9,0xb3,0xd2,0xd5,0x1d,0x1f,0x58,0x98,0xe4, - 0xac,0x67,0xf9,0xa1,0x41,0x35,0xf9,0x07,0x94,0x9d,0x8c,0x76,0x5a,0x73,0xd0,0x1b, - 0xca,0x3f,0x00,0x96,0x53,0x0a,0xe7,0xdd,0xbb,0x4a,0xb7,0x85,0x79,0x8e,0xbf,0xec, - 0xfb,0xaa,0x28,0xb7,0xf8,0x47,0x71,0x85,0xf1,0x89,0x70,0xfe,0x29,0xb3,0x78,0x26, - 0xba,0xc7,0xc6,0x98,0x08,0xd9,0x36,0xde,0xff,0xda,0xa7,0x02,0xf9,0x67,0x10,0x6c, - 0x1e,0x7e,0x86,0x7c,0x2a,0x58,0xd8,0x23,0x92,0x2b,0x1b,0xb9,0xf5,0xe7,0x59,0xfe, - 0x89,0x53,0xfe,0x41,0xeb,0x3c,0xc7,0x6c,0x49,0x30,0xff,0xc8,0x84,0x7f,0x12,0x28, - 0x32,0x48,0x68,0x47,0x48,0xe2,0xd3,0x2b,0x66,0x6d,0xec,0x61,0xfc,0x83,0x79,0x86, - 0x9e,0x87,0xf8,0x63,0x16,0xff,0x44,0x1a,0x0a,0xf3,0x3c,0x2f,0x0e,0xff,0x54,0x09, - 0x36,0x36,0xdc,0x47,0x9f,0xd6,0x5f,0x04,0xf0,0xcf,0x84,0x73,0x7f,0xa5,0x52,0x3d, - 0xe2,0x60,0x0f,0x36,0xb6,0xf5,0x58,0x46,0x24,0x98,0x7f,0xe6,0xd1,0xf7,0x29,0x3b, - 0x7b,0x94,0xbe,0x9e,0x97,0x7f,0xf4,0x02,0xf6,0x92,0x9e,0xd4,0xbf,0x43,0x2b,0x89, - 0x81,0x0f,0xe9,0x40,0xcb,0x38,0x5f,0xbf,0x9c,0xf7,0xdf,0xc1,0xf9,0x26,0xff,0xe0, - 0x4d,0x4a,0x0f,0x60,0x8c,0xa9,0xc2,0xd9,0x58,0x7a,0xc0,0x38,0x4d,0xdc,0xe4,0xf9, - 0x87,0xc5,0x7f,0x00,0xf6,0x52,0x7f,0x89,0xe3,0x55,0xe4,0xd3,0x0d,0xb0,0x4b,0xa8, - 0x33,0x24,0x6e,0xfd,0x7b,0x2c,0xff,0xfc,0x35,0xcd,0x3f,0x16,0xff,0x68,0x86,0x94, - 0xc2,0xeb,0x49,0x3e,0x2f,0xe6,0xe2,0x79,0x86,0x9d,0xcf,0x84,0xcd,0x7b,0xf8,0x22, - 0xa9,0x2f,0x07,0x71,0x76,0x2d,0xea,0xf4,0xd6,0x2f,0xfc,0xfd,0xea,0x6c,0x3f,0xf6, - 0xc5,0x3d,0x01,0xd8,0xc3,0x8c,0x71,0x76,0x9e,0x1f,0x53,0xa7,0x55,0x33,0x69,0x67, - 0x84,0xa6,0xf0,0x17,0x7f,0xa7,0x5e,0x1f,0xdf,0x69,0xf3,0xcf,0x00,0xd3,0x1f,0x24, - 0xcb,0xe0,0x41,0x28,0xa7,0x33,0xfe,0x91,0x59,0x99,0xb3,0xd7,0xa7,0x0a,0xad,0x2b, - 0x8b,0x5c,0xbc,0x44,0xf7,0xaf,0x80,0x59,0xe6,0x46,0xb1,0xbf,0xfd,0x04,0x7b,0x8e, - 0x13,0xc3,0x20,0x57,0x4a,0x9c,0xf8,0x54,0x8f,0x14,0xd0,0xf3,0x80,0x94,0x4e,0x0b, - 0xc3,0x06,0xa4,0xa1,0xb4,0x59,0xdf,0xaf,0x92,0x42,0xac,0x36,0x93,0x8d,0x39,0xbc, - 0xc7,0xf2,0x55,0xfa,0x36,0xd3,0xa9,0x2c,0x7e,0xff,0xb2,0x1d,0xbf,0xdc,0x8d,0xf9, - 0x47,0xc3,0x57,0x78,0xfe,0x29,0x70,0xf3,0x0f,0xa3,0x9d,0xbb,0x89,0xf1,0x16,0x7f, - 0x85,0x18,0x0b,0x1d,0xfe,0x31,0x30,0xff,0x7c,0x43,0x69,0xe7,0x1b,0xa4,0x11,0xef, - 0x12,0x5e,0xfd,0x07,0xd7,0x23,0xa6,0xff,0x14,0xb8,0x9e,0xa6,0x38,0x31,0xfa,0xe9, - 0x95,0x0d,0xd4,0xb8,0x5c,0xc0,0xf3,0xcf,0x6b,0x94,0x16,0x5e,0x83,0x6a,0x62,0x24, - 0x7d,0xfc,0xe0,0xf0,0x8f,0x5e,0xce,0x7d,0xfb,0x57,0xa0,0x91,0x18,0xaf,0xb8,0xcf, - 0x43,0x51,0x46,0x1a,0x63,0xf9,0x27,0xe3,0xe8,0x3f,0x2c,0x1a,0x57,0xdd,0x57,0x76, - 0xe3,0xf8,0xf8,0xf4,0x1f,0xfb,0x6e,0x8d,0x46,0x34,0xd3,0x73,0xbb,0xe8,0x3d,0x9f, - 0x0e,0xff,0x9c,0x29,0x70,0x61,0x70,0xf5,0x74,0x49,0x23,0x2e,0x4c,0x5e,0x7e,0xbb, - 0xe6,0xe1,0x1f,0x27,0x3e,0x39,0x25,0x85,0x1f,0x9c,0x97,0x43,0xf9,0x67,0x92,0xf2, - 0xcf,0x36,0xf1,0x1c,0x4e,0x2c,0x55,0xb9,0x92,0xad,0x96,0x10,0x14,0xaa,0xff,0x44, - 0x2d,0xc8,0x69,0x34,0x69,0xa7,0x01,0xef,0x5f,0xaa,0x83,0xff,0x75,0xf4,0x9f,0xc5, - 0x26,0xff,0xd0,0xe3,0x43,0xf9,0xc7,0x8c,0x86,0x4c,0x84,0xa3,0xd8,0xa5,0xc8,0xb4, - 0xfe,0x99,0x97,0x7f,0x58,0xfc,0x31,0xff,0xe0,0xec,0x54,0x69,0xc7,0xbf,0xbb,0xde, - 0xd8,0x9d,0x91,0xa2,0xae,0xe7,0xf7,0x78,0x30,0xff,0x58,0xd9,0x63,0xb5,0x11,0x99, - 0x14,0x2b,0xe0,0x95,0x50,0xfe,0x41,0x94,0x7f,0x4c,0xef,0xba,0xab,0x88,0xfe,0xd3, - 0x0c,0xbb,0x42,0xf5,0x1f,0xc6,0x3f,0x56,0xf4,0x96,0x62,0xa3,0xa4,0x14,0x79,0xe3, - 0x19,0xc0,0x3f,0x16,0xed,0xd4,0x13,0xe3,0x6e,0x9c,0xef,0x67,0xe7,0x1f,0xab,0xfa, - 0xa8,0xc4,0xd0,0xa7,0x3c,0x20,0x14,0xc0,0x3f,0x76,0x75,0xeb,0x58,0x4c,0x40,0xe8, - 0x83,0x70,0xfd,0x47,0xe6,0xb1,0xc7,0x48,0xea,0xf1,0xbd,0xd5,0xb2,0x53,0x7f,0xbf, - 0xf6,0xf1,0x4f,0x01,0x93,0x7d,0x70,0xe1,0x56,0x93,0xeb,0x4b,0xe6,0xef,0xa8,0xf5, - 0xd7,0x6b,0x3f,0xff,0xd8,0xd5,0xbf,0x5d,0x29,0x2b,0xb9,0x1d,0xba,0xe9,0x95,0x7d, - 0x5e,0xfe,0x69,0x70,0xf4,0x9f,0xb4,0x19,0x8d,0x2c,0x06,0x21,0x5c,0x51,0x43,0xf5, - 0x9f,0xdb,0x5c,0xfe,0x56,0x92,0xb2,0x7e,0x15,0xbe,0x17,0xed,0x2b,0x5f,0x7b,0xf9, - 0xa7,0x42,0x18,0x87,0xdf,0xd8,0xeb,0x95,0x9b,0xd0,0xd2,0x5e,0xfa,0xb1,0x24,0xfb, - 0xe2,0xf3,0x5e,0x39,0x8d,0x7f,0x03,0x78,0xd4,0x9e,0x38,0x12,0x35,0x31,0x9c,0x7f, - 0xda,0x0a,0x3c,0x74,0x87,0x41,0xa8,0x30,0xed,0xf5,0xf7,0x94,0xe0,0xe5,0x1f,0x3b, - 0x7a,0x78,0x7d,0x4a,0x24,0xf1,0x2f,0x0d,0xd7,0x7f,0xa2,0xcf,0x0b,0xcd,0x6b,0x8b, - 0x06,0x04,0xa6,0x6e,0x91,0xef,0xb7,0xd2,0xad,0xff,0xb0,0xf3,0x3f,0x21,0xec,0x87, - 0xbb,0xdc,0xde,0x45,0x7c,0x7a,0x51,0xcd,0x75,0x8e,0x7f,0x34,0x4a,0x3b,0xe4,0x8b, - 0xa8,0x87,0x28,0x8e,0xbf,0x9c,0x95,0x3d,0xfa,0x0f,0x3b,0xff,0x54,0xff,0xc1,0x90, - 0xb3,0x19,0xde,0xd2,0xef,0xec,0x56,0xbe,0x58,0x16,0x87,0xb3,0x60,0x82,0x50,0x10, - 0xff,0x38,0xf9,0x67,0x03,0x64,0x52,0x9a,0x11,0x6f,0x68,0x8d,0x42,0x4f,0x28,0xff, - 0xa4,0x05,0x26,0x9b,0xdc,0x0f,0xc7,0xd0,0xed,0x08,0xba,0x0a,0x9b,0xf4,0xe7,0x6c, - 0x61,0xc4,0xcf,0x3f,0x83,0x50,0x49,0x69,0xe7,0x01,0xf8,0x77,0xcc,0x27,0xd1,0xf3, - 0x52,0xa5,0xf1,0x7e,0x38,0xff,0xdc,0xe6,0xe4,0x5b,0x99,0x80,0x71,0x6c,0x1f,0x7e, - 0x7f,0xf7,0xd4,0xf7,0x1f,0x71,0xfa,0x0f,0x5f,0xbf,0x6e,0x0d,0xb4,0xe4,0xa2,0x67, - 0x22,0x04,0xd2,0x43,0xf5,0x1f,0xc1,0xe6,0x9f,0x15,0x78,0xb7,0xaf,0xa3,0xba,0xc1, - 0xde,0x47,0xc4,0x26,0xd8,0x15,0xae,0xff,0x00,0x97,0xaf,0x0e,0x6b,0x75,0x59,0xa5, - 0x43,0xbc,0x5f,0xf4,0xae,0xe7,0xf4,0x1f,0x3e,0xff,0x64,0xc8,0xf9,0xd1,0xc4,0x3f, - 0xf1,0xc5,0xd3,0xab,0xff,0xd8,0xde,0x65,0x48,0xa3,0xc1,0x10,0xff,0xd1,0xc7,0x3f, - 0x9c,0xfe,0x03,0x5c,0xbd,0x9b,0x22,0xd9,0xe9,0x59,0x69,0xc8,0xc7,0x3f,0x8e,0xfe, - 0x23,0xa8,0x5c,0x77,0xe3,0x5b,0x7d,0x65,0x7b,0x2c,0x1b,0x69,0xd2,0x3e,0xf2,0x54, - 0x40,0x63,0xbd,0x93,0x7f,0x3a,0x9d,0xfa,0xf5,0x86,0xb8,0x46,0x8f,0xfc,0x0a,0xd7, - 0x77,0x6f,0xfd,0xe2,0xf4,0x1f,0xbe,0xde,0x0d,0x93,0x7a,0x4d,0x84,0x0e,0xb2,0xbe, - 0x24,0x98,0x7f,0x64,0xee,0x35,0x3f,0xa3,0xd5,0xf6,0x9a,0xa0,0xe8,0x8d,0x0f,0xa7, - 0xff,0x14,0x74,0x3a,0xde,0x4d,0x68,0x29,0x7d,0x23,0x14,0x35,0xf9,0xea,0xaf,0xe1, - 0xe8,0x3f,0x7f,0x44,0x9d,0xea,0x99,0x86,0x29,0xb5,0x79,0x7d,0xcc,0x08,0xe8,0xef, - 0x70,0xfa,0x4f,0x39,0x3b,0x24,0xd7,0xe0,0x77,0x96,0x71,0xd1,0xcb,0x3f,0x41,0xfa, - 0xcf,0xb0,0xf8,0x25,0x1c,0xed,0x76,0x63,0x4f,0xb0,0xfe,0x43,0x9d,0x1a,0xf5,0x95, - 0xf5,0x20,0xfd,0xa7,0x80,0xb5,0xbd,0xc6,0xc3,0xf5,0x34,0x8e,0x7f,0x1c,0xfd,0x61, - 0x5c,0xf7,0xca,0x0e,0xcc,0x70,0xf8,0x27,0xe7,0xf0,0xcf,0xad,0xf0,0xfe,0x17,0xa7, - 0xff,0xc0,0x90,0x03,0xd5,0xfc,0xfd,0x73,0xd1,0x60,0xfd,0xa7,0x20,0x4c,0x06,0x54, - 0x82,0xf5,0x9f,0xf2,0x0d,0xbe,0x68,0x58,0x46,0x3c,0xbf,0xfe,0xe3,0xb4,0xbd,0x0a, - 0x2d,0x0c,0x50,0xc2,0xf4,0x1f,0x2a,0xf2,0x9c,0x44,0xd4,0x30,0xaf,0x44,0xf3,0xe9, - 0x3f,0x66,0x34,0x74,0x16,0x96,0x1b,0x70,0x4f,0x48,0xff,0x8b,0xd3,0x7f,0xbe,0x14, - 0xbc,0xc7,0x32,0x9f,0xfe,0xd3,0x25,0xed,0xf5,0x61,0xcf,0xa7,0xf0,0x15,0xe5,0x1f, - 0xba,0x7f,0xc3,0xe1,0x9f,0x6b,0x3e,0xec,0xc9,0xa7,0xff,0x10,0xcc,0x76,0x9d,0x37, - 0xf3,0xfd,0xeb,0xe5,0xbc,0xfc,0xe3,0xc5,0x9e,0x60,0xfe,0x91,0x19,0x0f,0x10,0xa3, - 0x08,0x2d,0xe4,0x88,0x68,0x62,0x36,0xfe,0x09,0x36,0xbc,0xfc,0xb3,0x34,0x58,0xf6, - 0x09,0xd2,0x7f,0x1c,0xfe,0x71,0x2f,0xeb,0xc8,0xc7,0x3f,0xb5,0x36,0x0f,0xc8,0x41, - 0xfd,0xaf,0x30,0xfe,0xf1,0xcb,0x5c,0xa1,0xfc,0xb3,0x86,0x38,0xf5,0xb1,0xed,0xdd, - 0x02,0xbf,0xbf,0xfe,0xfe,0x17,0xbe,0xd8,0xc9,0x2f,0x6b,0xd1,0x13,0xc1,0xfd,0x2f, - 0xd5,0xdf,0xed,0xb2,0x0c,0x25,0x90,0x7f,0x14,0x87,0x7f,0x68,0xbf,0xaf,0xd5,0xaf, - 0x08,0x39,0xf9,0xc7,0xc3,0x3f,0xd4,0x10,0xdc,0x8a,0x90,0xbf,0xff,0xc5,0xf5,0x37, - 0xed,0x6d,0x47,0x83,0xf5,0x1f,0x61,0x3f,0xb7,0x4c,0x68,0xd6,0x97,0x04,0x9d,0x07, - 0xb7,0xfe,0x33,0x11,0x18,0xf6,0x44,0xde,0xfe,0x97,0xa5,0xf6,0xc8,0xc4,0x68,0x25, - 0x42,0x50,0x22,0xad,0x84,0xf1,0x8f,0x12,0x9c,0x96,0x95,0x60,0xfe,0x59,0xbb,0x98, - 0x7b,0x7f,0x91,0xd9,0xf3,0x3b,0x6f,0x4c,0x09,0xe6,0x1f,0xa5,0x12,0xbe,0x72,0xe9, - 0x3f,0xd4,0x88,0xce,0xca,0x3f,0xcc,0x50,0x6f,0x40,0x93,0x1e,0xd2,0xff,0xb2,0xfa, - 0x17,0x8e,0xda,0xb3,0xfb,0x7b,0xe9,0xa2,0xee,0xad,0x5f,0x8e,0xfe,0x3f,0x68,0xe5, - 0x9f,0x09,0xbc,0xc9,0x13,0x70,0x44,0xad,0x1b,0x2d,0x36,0x13,0x29,0xd4,0x8d,0xe7, - 0xe5,0x9f,0xac,0xf3,0xe9,0xdf,0x98,0xfd,0xaf,0x3a,0xa3,0x6f,0x76,0xfe,0x61,0x69, - 0xe7,0x10,0x39,0x66,0x3c,0xff,0x80,0x9f,0x7f,0x5a,0x2f,0x68,0xc4,0xd8,0x68,0xb9, - 0xb9,0xdd,0x93,0x3f,0xe9,0x7e,0x5c,0xfc,0x43,0x8c,0x79,0xf9,0xfb,0x5f,0x1c,0xff, - 0xb8,0x5f,0xfc,0x73,0x4b,0x78,0xfe,0xd1,0xe9,0xfa,0x6e,0x9e,0x7f,0x78,0x43,0x8f, - 0x04,0xeb,0x3f,0xee,0x7a,0xb7,0x94,0xad,0xcf,0xba,0xd6,0xb3,0x7c,0x6e,0xf3,0x4f, - 0xb6,0xcf,0x8c,0x86,0x4c,0xa2,0x31,0x72,0x42,0xf3,0xf1,0x00,0x8b,0x3e,0xcc,0x33, - 0xf9,0x27,0x4b,0xbc,0xd3,0x4d,0xef,0x0e,0x5a,0x3c,0x9c,0x8d,0xb8,0xf8,0x87,0xee, - 0xc7,0xd6,0x7f,0xde,0x8d,0x4d,0x0a,0xd3,0x56,0xdb,0x2b,0x23,0x4d,0xa7,0x67,0x48, - 0x47,0x8c,0xe7,0x9f,0xa2,0x60,0xfd,0xe7,0xf1,0x96,0xdc,0xbc,0x29,0xbc,0x6c,0x0e, - 0xfd,0x2f,0x93,0x76,0x20,0x99,0xc3,0x65,0xfd,0x16,0xe1,0xbd,0xd9,0xf9,0xc7,0x5f, - 0x86,0xf2,0xf4,0xbf,0xdc,0xd8,0xf0,0x5a,0x28,0xff,0x40,0xd9,0x50,0xc0,0x79,0xf0, - 0x82,0x50,0x40,0xff,0xcb,0x85,0x3d,0xde,0x7e,0xe8,0x54,0x98,0xfe,0x63,0x19,0xba, - 0xf7,0x4a,0x40,0xff,0xcb,0xda,0x6d,0x22,0x87,0x8d,0x73,0xb3,0xf6,0xbf,0x9c,0x68, - 0xe4,0xfa,0x82,0xf8,0x30,0x98,0x7f,0x88,0x71,0xdd,0xcf,0x03,0x7d,0x21,0xfc,0x73, - 0x42,0xb9,0x82,0xc8,0xfc,0x0f,0xc1,0x1e,0xd5,0x99,0xff,0x99,0x0b,0xff,0x78,0x8d, - 0x59,0xfa,0x5f,0x86,0x07,0x84,0x16,0x86,0xea,0x3f,0xa6,0x71,0xa2,0xda,0xfb,0x3e, - 0xc5,0xf7,0xbf,0x2a,0x7d,0xb4,0x73,0x0e,0x79,0x41,0x68,0x52,0xa7,0xf1,0x6f,0xf3, - 0xe6,0x1f,0xab,0xdf,0xea,0xd5,0x7f,0x6a,0x43,0xf4,0x9f,0x10,0x10,0x0a,0xd7,0x7f, - 0x88,0x61,0xcc,0xa5,0xff,0x85,0xab,0x5b,0xd4,0x36,0x96,0x8a,0x73,0xd5,0x7f,0x20, - 0xd9,0x8a,0x8d,0xa5,0x3e,0x3d,0x87,0xef,0x7f,0x71,0xf5,0xfa,0x79,0x62,0xa8,0x25, - 0xb5,0x7a,0x1e,0xfd,0x47,0xe5,0xf4,0x9f,0x15,0x7a,0x94,0xf4,0xbf,0x64,0xe8,0xd6, - 0x43,0xf9,0x47,0xf1,0xf3,0x8f,0x06,0x5e,0xfd,0xe7,0xa2,0x7f,0xfe,0x87,0xf3,0x2e, - 0x5f,0xff,0xab,0xa2,0x80,0xe7,0x01,0xbc,0x23,0x6c,0x5c,0xd5,0xbc,0xf1,0xf9,0x32, - 0x80,0x7f,0x30,0x7f,0x0e,0xc3,0x4b,0x10,0x11,0xc5,0xcf,0xf3,0xf5,0xbf,0x64,0x9e, - 0xee,0x14,0x0d,0x1b,0x3b,0x46,0xa1,0x5b,0x71,0xfb,0x6b,0x04,0xf1,0x0f,0x31,0xaa, - 0xb1,0x51,0x9d,0xaf,0xff,0xf5,0x52,0x19,0xb7,0xff,0x4b,0x50,0x6f,0xce,0x77,0xf9, - 0xbe,0xdf,0x89,0x9d,0xbe,0xfe,0x17,0xd1,0xbb,0xec,0xb1,0x9f,0xd1,0x59,0xf8,0x87, - 0x8b,0x7f,0xbd,0x18,0x45,0x35,0x56,0xfc,0x77,0xe7,0xe9,0x7f,0xd9,0xfc,0xd3,0x2c, - 0xfc,0xf1,0x00,0xc6,0x9e,0xb8,0xf8,0x64,0x78,0xff,0xcb,0x9d,0x7f,0xb4,0x47,0x4c, - 0xbd,0x2b,0x5c,0xff,0x61,0xfd,0x2f,0xfc,0xb4,0xaa,0x47,0xb4,0x3b,0x1e,0x51,0xb6, - 0x95,0x44,0x61,0x97,0xe6,0xe9,0x7f,0xe9,0xec,0xfe,0x4a,0x25,0xc3,0x1e,0x79,0x26, - 0xbd,0xa2,0x23,0xb1,0x5d,0xaa,0x84,0xf7,0x7b,0xef,0x09,0x9b,0xff,0x71,0xf1,0xcf, - 0x66,0x1c,0x8d,0xc3,0xc4,0xe8,0x70,0xe7,0x93,0x11,0x91,0xc6,0x47,0x2f,0xb8,0x65, - 0xd1,0xce,0x30,0xa9,0x56,0x4f,0xb6,0x74,0x44,0xa7,0xa5,0xbf,0x87,0x99,0xde,0x95, - 0x21,0xf5,0x6b,0x90,0xe6,0x9f,0x6d,0xe2,0xa7,0x3a,0xc1,0x12,0x65,0x52,0x5c,0xac, - 0x1f,0xd9,0xbf,0x9a,0xdf,0x7f,0x2b,0xaf,0xb7,0xec,0x55,0x29,0xf6,0x90,0x4f,0x65, - 0xa5,0xab,0x04,0x47,0x40,0xab,0x72,0xf9,0x3b,0xca,0xf8,0xa7,0x83,0xe5,0x1f,0xab, - 0x9f,0x08,0xa6,0x9e,0x7f,0x14,0x6a,0x5d,0xf1,0x74,0xfa,0x5f,0x71,0x5e,0xff,0x99, - 0x11,0x9b,0x51,0x74,0x32,0x92,0xc0,0x69,0xb6,0xde,0x95,0x51,0xcf,0x05,0xeb,0x3f, - 0x37,0xc8,0x69,0x99,0x33,0xff,0x10,0x63,0xe5,0x20,0x35,0x5c,0xf9,0x7c,0xd2,0xe9, - 0x7f,0xb9,0xf8,0x47,0x5c,0xb6,0xd5,0x2e,0x5b,0xcb,0x5c,0xf5,0x6b,0x3c,0xa8,0xff, - 0x75,0x01,0x7b,0x57,0x6d,0x62,0x12,0x3a,0x6a,0x35,0x6e,0xf2,0xe9,0x3f,0xf5,0x56, - 0xbf,0xc3,0xc6,0x42,0x2d,0x1e,0xa6,0xff,0x28,0x74,0xec,0xa4,0x07,0xc7,0x47,0xaf, - 0x2f,0x8b,0x4d,0xae,0xbb,0x00,0xdf,0xc5,0xdd,0xf1,0xc9,0x39,0xfa,0xcf,0x6d,0xbc, - 0xbf,0xf1,0x7b,0x14,0xfb,0xfd,0xdd,0xa3,0xff,0x14,0xfa,0xf8,0x67,0x42,0xda,0xae, - 0x5f,0x45,0xcb,0xf1,0x69,0x29,0x9a,0x81,0x1b,0x5a,0xcb,0x48,0x34,0xf0,0xfc,0x18, - 0xea,0x16,0x0b,0x72,0x06,0xc5,0x04,0xbc,0x81,0x8d,0xd2,0x61,0xe2,0xa6,0x91,0x18, - 0x53,0xf8,0xfe,0x57,0xa1,0xaf,0xff,0x95,0x16,0x37,0xf4,0x66,0xec,0x17,0x73,0x74, - 0x48,0x4f,0xfe,0x98,0xef,0x87,0x5e,0xf6,0xf3,0xcf,0x4b,0x62,0x27,0xc9,0x66,0x4c, - 0x46,0x6b,0xe5,0xf5,0x13,0x67,0xfe,0x79,0x74,0xbe,0x1d,0x84,0x57,0xf1,0xfb,0xe3, - 0x14,0x9d,0xff,0xc1,0x57,0xda,0x13,0x5c,0x7c,0x3e,0x66,0xfc,0xc3,0xe6,0x9f,0x73, - 0xc2,0x31,0xe5,0xa6,0xba,0x84,0x85,0xa5,0x8d,0xe7,0xe1,0x80,0xfe,0x17,0x99,0xc7, - 0x9b,0xb0,0xfa,0x6b,0xf8,0x7d,0x04,0xd5,0xb7,0x07,0xeb,0x3f,0xac,0xff,0xa5,0x49, - 0x43,0xea,0x30,0x3d,0x36,0x6f,0x83,0xf6,0x17,0x9b,0xf3,0xf7,0xbf,0x34,0xa2,0x07, - 0x66,0x34,0xeb,0x18,0xac,0x84,0x34,0xf0,0xfa,0xcf,0x25,0x56,0xef,0x58,0xff,0x6b, - 0xb3,0xf8,0x22,0xdc,0x83,0xee,0xa0,0xfa,0x4f,0xd5,0xa6,0x5e,0x8e,0x07,0xa6,0x65, - 0xba,0xde,0xe6,0x9f,0x5c,0xac,0x7a,0xdd,0xc9,0xf6,0x9c,0xd6,0x60,0x0b,0x41,0x28, - 0x35,0x9a,0xe0,0xf8,0xe7,0xb4,0x48,0xd7,0xeb,0xff,0xc2,0xf8,0xe7,0xc2,0xfc,0x69, - 0x78,0xd4,0x02,0xa1,0xef,0xa0,0x65,0x74,0xb9,0x13,0x9f,0x85,0x4e,0xff,0xeb,0x55, - 0xca,0x3f,0x38,0x3e,0x05,0x93,0xa2,0x79,0x2c,0x2f,0x62,0x7e,0xae,0x37,0xf8,0xf8, - 0x8c,0x38,0xfc,0xf3,0x34,0x9d,0xff,0x91,0xf6,0xc2,0xbf,0xc1,0x6a,0x32,0xff,0x3c, - 0x0d,0xbb,0x50,0x95,0xc1,0xde,0x1f,0xf1,0x95,0xcb,0x8c,0xaf,0x58,0xff,0xab,0x0d, - 0x7b,0x77,0x78,0x67,0x95,0x85,0x3d,0xcf,0x21,0x6d,0x92,0xd7,0xbb,0xb2,0x8e,0xfe, - 0xa3,0xda,0x41,0xbb,0x4b,0xec,0x87,0x83,0xa8,0xd6,0x28,0xb1,0xe6,0xa9,0xaa,0x27, - 0xd9,0xfb,0x2c,0xbe,0x72,0x16,0x38,0xfe,0x51,0x4c,0xc8,0x99,0xc0,0x5f,0xfa,0xad, - 0xf4,0x41,0x32,0x1d,0x3a,0x01,0x67,0xe1,0x50,0x3a,0xe1,0xe2,0x1f,0xba,0x7f,0x8b, - 0x7f,0xb6,0x3b,0xfa,0x4f,0xa9,0x2d,0xfb,0x88,0xfc,0x44,0xf4,0x29,0x6e,0x7e,0xd5, - 0x2a,0x6a,0x1b,0x07,0x16,0x62,0x63,0xa0,0x3e,0x58,0x1f,0x18,0x61,0xe7,0xc7,0xe2, - 0x9f,0x46,0xab,0xda,0x1e,0x50,0x96,0xe9,0x7d,0xd8,0x50,0x70,0xd9,0x6d,0x8f,0xcf, - 0x45,0xff,0x59,0x6a,0xcf,0x4b,0xa3,0x64,0x3b,0xaf,0x57,0x9c,0x64,0xe7,0x0d,0x4c, - 0xfd,0x27,0x6e,0x8e,0xc1,0xf0,0x46,0xa2,0x3d,0xce,0xf1,0xc0,0x87,0xac,0xff,0xee, - 0xd6,0x7f,0xc4,0x7a,0x6c,0xd4,0x10,0xa3,0x99,0x34,0x62,0x02,0xf4,0x9f,0x33,0xb4, - 0xff,0x35,0x66,0xf6,0xb3,0x6c,0x7d,0xe3,0x92,0xde,0xd2,0xee,0xe2,0x19,0xd9,0xe1, - 0x1f,0x0e,0x93,0xfe,0x4f,0x58,0xa3,0xff,0x2b,0x59,0x76,0x73,0xf0,0xc0,0xb6,0x68, - 0xa0,0xfe,0xb3,0x95,0xf2,0x4f,0x5a,0xcc,0xa1,0x37,0x31,0xff,0x2c,0x42,0xa2,0x81, - 0x86,0xf5,0xea,0x54,0xdc,0x1a,0xcc,0x36,0xd1,0xe8,0x29,0x96,0x7f,0x38,0xfd,0x67, - 0x14,0xbd,0x61,0x0b,0x5f,0xa9,0x7d,0xa0,0xb5,0xf1,0xfa,0xcf,0x29,0x76,0x7e,0x28, - 0xff,0xfc,0xf3,0x33,0x44,0x7f,0x16,0xaa,0x69,0x60,0xab,0x7f,0xcc,0xc7,0xf3,0x71, - 0xb6,0xde,0xd1,0x7f,0xfe,0x6c,0x5c,0xbe,0xa4,0xaf,0xb1,0xe6,0x7f,0xbe,0x86,0xfa, - 0xf6,0x44,0xa0,0xfe,0x33,0x41,0xf5,0x1f,0x73,0x5e,0x48,0x6b,0xd6,0x8b,0xac,0x65, - 0x4d,0x64,0x19,0x43,0xa3,0xcb,0x7e,0xfe,0xd9,0xb9,0x30,0x27,0x66,0xd7,0x36,0xc3, - 0x46,0xe2,0x66,0x76,0x41,0xe3,0x02,0x3e,0xfe,0x23,0xc1,0xfa,0xcf,0x53,0xb9,0x65, - 0xa8,0x94,0x18,0x8f,0xa3,0x1a,0x14,0xaa,0xff,0x38,0xfc,0xd3,0xdd,0xcb,0xde,0x17, - 0xe2,0x61,0xfa,0x0f,0xe3,0x9f,0xc2,0x73,0xa8,0x1f,0xaa,0x8e,0xe3,0xea,0x7f,0x0e, - 0xf5,0x40,0x95,0xce,0xeb,0x3f,0xce,0xfb,0xfe,0x60,0x2f,0xc9,0x57,0x04,0x72,0x16, - 0xce,0x08,0xa3,0x16,0xed,0x7c,0xa6,0xbd,0x8f,0xee,0x1a,0xe7,0xf5,0x9f,0x2f,0x18, - 0xff,0x94,0xd0,0xf9,0x9f,0x4c,0xd1,0x05,0x61,0xca,0xfa,0x61,0xcb,0xb7,0x44,0x28, - 0x6b,0x5b,0xce,0xe7,0x13,0x96,0x7f,0xc4,0xc7,0x6e,0xd1,0xb1,0xe7,0x66,0xfd,0x1a, - 0x7a,0x1b,0x57,0xab,0x1a,0x53,0xff,0x49,0x47,0xb9,0x41,0x0e,0x47,0x9f,0xb1,0xf8, - 0x87,0x4c,0xfb,0x48,0x7f,0x8a,0x0e,0xc3,0xea,0xd1,0x45,0x5d,0xf8,0xe9,0x38,0x02, - 0x0f,0x2b,0x4a,0x97,0xe4,0xe8,0x3f,0x85,0x74,0x3d,0xed,0x7f,0x95,0x60,0x4c,0x82, - 0xc3,0xba,0x83,0x79,0x69,0x25,0xaf,0xfe,0xd3,0xd7,0x80,0xeb,0x57,0x86,0x62,0xcf, - 0x01,0xfc,0xfc,0xf2,0xf1,0x74,0xf2,0x15,0xd5,0x7f,0x4a,0x53,0x52,0x13,0x4c,0x1a, - 0xa6,0x77,0xd3,0x26,0xd8,0x44,0x33,0x4e,0x63,0x2b,0xa0,0xff,0x75,0x80,0xf4,0xbf, - 0x90,0x8d,0x3d,0xff,0x00,0xcd,0x23,0xbb,0xb9,0xf5,0x41,0xfc,0xd3,0xd3,0x04,0x27, - 0xe0,0x4e,0xbb,0xde,0x0d,0x34,0xeb,0xa5,0x5c,0xbd,0xcb,0x3a,0xfd,0x2f,0xa0,0xfc, - 0x83,0xef,0xd6,0x8b,0xd6,0xd8,0x8d,0x30,0x94,0x1c,0xe7,0xeb,0xef,0x84,0x4f,0xff, - 0x59,0x44,0xc6,0x60,0x7a,0x91,0xa3,0xff,0x80,0x92,0x59,0x90,0xf0,0xf3,0x4f,0x89, - 0x6c,0xcf,0xff,0x64,0xc4,0x7e,0xbd,0xd7,0x8c,0x4f,0xab,0x39,0xff,0x8c,0xf8,0x7a, - 0xe7,0xcc,0xff,0xd8,0xfa,0xcf,0x98,0x39,0xdf,0x9b,0xb5,0x7e,0xdf,0x74,0x13,0x6e, - 0xdc,0xd7,0x02,0xc9,0x8c,0xc0,0xce,0x83,0xd1,0xc3,0xce,0xe7,0xf3,0x96,0x53,0x1b, - 0xbb,0x16,0x0e,0x65,0xa7,0xe1,0x6e,0xec,0x5d,0xcd,0x4d,0x98,0xd1,0x3c,0xfc,0xb3, - 0x9e,0xf1,0x86,0x60,0x43,0xce,0xb0,0xf4,0xba,0x3a,0x53,0xd5,0x02,0x7b,0x39,0xec, - 0xc9,0xab,0xff,0x48,0x5b,0xa0,0x6f,0xb4,0x26,0xfd,0x97,0x73,0xeb,0x7f,0x95,0x90, - 0xb1,0xa8,0x43,0x6a,0x12,0x71,0x63,0x4e,0xf9,0xf5,0x9f,0xc2,0x2d,0xf1,0x3e,0xb9, - 0x1a,0x95,0xf8,0x1a,0x49,0x81,0xf3,0x3f,0xf8,0x31,0x29,0x25,0x3f,0x74,0xaa,0x5d, - 0x36,0xe7,0xfe,0x17,0x19,0x03,0x7b,0x0b,0xcd,0xd6,0xff,0x72,0xf4,0x9f,0x6f,0xc5, - 0x4f,0x94,0xca,0x2f,0x4c,0x7d,0x89,0xcd,0x9f,0x7f,0x12,0xda,0xff,0x5a,0x0d,0xdf, - 0xc2,0x6e,0x71,0x95,0x11,0x0f,0xda,0x7f,0x80,0xfe,0xb3,0x4a,0xdc,0xa0,0xf7,0xa8, - 0x09,0xa4,0x59,0xf5,0xda,0xee,0xe0,0x98,0x3f,0xcd,0x08,0xd1,0x7f,0x3e,0x33,0x76, - 0xa1,0xdb,0xf7,0x2b,0x3e,0xfd,0xe7,0xde,0x40,0xfd,0xa7,0x41,0xda,0x80,0xde,0x81, - 0xa6,0x9d,0xd1,0x7a,0x8c,0x3d,0xa7,0x33,0xb6,0xfe,0x73,0x3a,0x8f,0xfe,0x73,0xa6, - 0xf7,0xab,0x05,0x2d,0x3b,0xad,0xc7,0xa4,0x20,0xbf,0xfe,0x83,0xb1,0x70,0x18,0x9f, - 0xcf,0xd3,0xa8,0xe1,0x85,0xe0,0xdf,0x2f,0x78,0xf4,0x9f,0xbb,0x48,0xd2,0x58,0x0c, - 0xbb,0x1e,0xaa,0x42,0x7c,0x1a,0x09,0x9d,0x7f,0xc6,0x98,0x37,0x25,0xbe,0xa8,0x3d, - 0xd7,0x7d,0x47,0xee,0x05,0xea,0xe6,0xa2,0x3c,0xfd,0x2f,0xf3,0x6d,0xe2,0x29,0xad, - 0x07,0xb4,0x31,0x25,0xe8,0xbc,0x79,0xfb,0x5f,0x8d,0x18,0x72,0x4a,0x8e,0xca,0x67, - 0x71,0xed,0x2c,0xf1,0xf5,0xbf,0x22,0x81,0xfa,0xcf,0x4e,0xf1,0x41,0x65,0x4a,0x2f, - 0x14,0x03,0xfb,0x41,0x81,0xfa,0xcf,0x97,0xd1,0x0f,0x50,0xf3,0xda,0xfe,0x81,0x1a, - 0x67,0xe2,0x25,0xaf,0xfe,0xf3,0xae,0xfc,0x1b,0x31,0xb1,0x49,0x99,0xa5,0xff,0x25, - 0x30,0xfe,0xf9,0xad,0xfe,0xc4,0x83,0x76,0x9b,0xe6,0xf9,0xd9,0xe7,0x7f,0x52,0xe2, - 0xb8,0xfc,0xb4,0x90,0xd0,0x79,0xec,0x99,0xad,0xff,0x95,0xc5,0xe0,0xd7,0x4f,0x8c, - 0x33,0xb3,0xcf,0xff,0xb4,0x93,0xfe,0x17,0xc6,0x9e,0xdd,0x41,0xfd,0x1d,0x7f,0xff, - 0xab,0x74,0x4c,0xba,0x4f,0xfd,0x9f,0x65,0x77,0xba,0xb0,0xd0,0xe1,0x1f,0x81,0xc6, - 0x9f,0xd3,0x7f,0x34,0xe8,0xd5,0xab,0xc9,0xfc,0x4f,0xbe,0xdf,0x7f,0x51,0xfe,0x29, - 0x51,0x4b,0x46,0xe1,0x69,0x61,0x7f,0x7b,0x71,0xb0,0xbf,0x01,0xf3,0x3f,0xfb,0x1f, - 0x7f,0x02,0xbf,0xcf,0x16,0x0f,0xb4,0xce,0xe5,0xf7,0x5f,0xa5,0x78,0x93,0xe8,0xbf, - 0x60,0xcd,0x0f,0xe7,0x39,0xdb,0x16,0x99,0x11,0xd8,0xff,0xda,0xa4,0x92,0x79,0xb0, - 0xd2,0x20,0x7f,0x03,0xf4,0x9f,0x1d,0x98,0xb7,0xb3,0x4a,0x99,0x3a,0xc7,0xdf,0x7f, - 0x45,0x36,0xa1,0x86,0xaa,0x5f,0xa3,0x97,0x07,0x19,0xf6,0x2c,0xc9,0xcf,0x3f,0xb5, - 0x62,0x0f,0xda,0x81,0x34,0x34,0xcb,0xfc,0x33,0xe3,0x9f,0x0e,0xfc,0xca,0xf4,0x92, - 0x52,0x43,0xb1,0xe7,0xe1,0xb0,0xf9,0x1f,0xaa,0xff,0x6c,0x96,0x5e,0xc0,0x18,0xb6, - 0x42,0x63,0xb2,0xcf,0x2c,0xf3,0x3f,0x9a,0x94,0x53,0xae,0x8b,0x0d,0x7a,0x2c,0xb3, - 0xce,0x9f,0x4f,0x02,0xe6,0x7f,0xb2,0x18,0x1a,0xcf,0xa6,0x53,0xb5,0x51,0x6e,0x90, - 0x35,0x68,0xfe,0x87,0xea,0x3f,0x7a,0xfd,0x18,0xfa,0xef,0xf4,0xbe,0xae,0x62,0xb2, - 0xed,0x43,0x92,0xd9,0x91,0xcf,0x37,0xff,0xa3,0x8b,0x93,0xea,0xe3,0x6a,0x8d,0x52, - 0x11,0x94,0xaf,0x02,0xfa,0x5f,0x20,0xbe,0x03,0xcf,0x40,0x5a,0xbf,0xc3,0x0e,0xe3, - 0x71,0x7e,0xf0,0x35,0x60,0xfe,0x47,0x15,0xdf,0xd1,0x46,0x40,0xc3,0xaf,0x8d,0x3f, - 0xc2,0x6e,0x0a,0xe4,0x45,0x5b,0xcc,0x37,0xff,0x83,0x8a,0x72,0x08,0x67,0xa7,0xae, - 0x52,0x0c,0x8a,0x74,0xcc,0x35,0x9f,0xfe,0x63,0x48,0x5d,0xf2,0xc9,0xf4,0x21,0xbd, - 0x7f,0x72,0xa1,0x75,0x65,0x1e,0x37,0x08,0xed,0xcc,0xff,0x74,0x53,0xfe,0xe9,0xef, - 0xd9,0x57,0xfd,0x64,0x5b,0x75,0x7b,0x60,0xfd,0xf2,0xf6,0xbf,0xf0,0x6b,0x7e,0xaf, - 0xd8,0xb1,0xae,0x0f,0x3f,0x2f,0x4a,0xe0,0x7a,0xbf,0xfe,0x23,0x88,0x9b,0x60,0x07, - 0x54,0xb7,0x55,0x04,0xf3,0x00,0x0b,0xbf,0xc9,0x3f,0x38,0x1a,0xe8,0x0f,0x3b,0xe4, - 0x2c,0xd4,0xeb,0xd6,0x6b,0xb5,0x6e,0x36,0x7a,0xd8,0x68,0x90,0xe1,0xd7,0x7f,0x46, - 0xa4,0x01,0xb8,0xd6,0xfa,0x68,0xbb,0x2d,0x04,0xcd,0xaa,0xff,0x4c,0x49,0xbf,0x26, - 0xc6,0xe7,0xb8,0x90,0x35,0xc3,0x8c,0x12,0xa6,0x1f,0xf2,0xfd,0x2f,0xc5,0x9e,0xff, - 0x49,0xc2,0xdb,0x7a,0xf5,0xec,0xfd,0xaf,0xfe,0xb2,0x43,0x22,0x01,0xa1,0x1f,0x6e, - 0x80,0x4c,0x3c,0xcd,0xfb,0xbb,0x34,0xac,0xff,0x55,0x68,0x1a,0x9d,0xd6,0x60,0xd5, - 0x6c,0xf3,0xcf,0xf8,0x20,0xc9,0xa6,0x81,0xc3,0x62,0xb8,0xf5,0xb1,0x40,0xfe,0xc1, - 0xd1,0x10,0x89,0x11,0x39,0x06,0x57,0x06,0xde,0x9e,0x9d,0x7f,0x86,0xe8,0x34,0xef, - 0x05,0xf8,0xbe,0xeb,0x60,0x58,0xff,0xcb,0x37,0xff,0x93,0x22,0xfc,0x6c,0x54,0x1f, - 0x9f,0x5b,0xff,0xcb,0xb0,0x07,0xe7,0xb4,0x39,0xf6,0xbf,0x2c,0x0c,0x38,0x8c,0xaa, - 0xc2,0x7f,0xff,0xc5,0xe6,0x7f,0xf4,0x2b,0x6a,0x53,0x0e,0x83,0xd0,0x49,0xb8,0xdc, - 0x91,0xe2,0xfa,0x5f,0x2b,0x7c,0xfc,0xd3,0xec,0xea,0x7f,0x5d,0xd0,0x6f,0xa1,0x59, - 0x7e,0xff,0x95,0xb3,0xdb,0xd0,0x4d,0xb9,0x68,0x03,0x06,0xa1,0xef,0x3b,0xdc,0xf1, - 0xf1,0xf2,0xcf,0x72,0x47,0xed,0x51,0x08,0x08,0x1d,0x50,0xf7,0xe5,0xe5,0x9f,0xe5, - 0xb9,0x62,0xea,0x9d,0x42,0xe6,0xbd,0x8f,0x78,0xfc,0xf5,0xcf,0xff,0x30,0xec,0xb1, - 0xf5,0x67,0x77,0x3c,0xfd,0xf3,0x3f,0xf3,0x48,0x75,0x20,0x46,0x22,0x1d,0x89,0xc3, - 0x2d,0xfd,0xe0,0xef,0xd1,0xff,0xc2,0x86,0xfe,0xd6,0x1c,0xe7,0x9f,0x6d,0x63,0xb0, - 0x7e,0x76,0xfe,0xe1,0xcb,0xae,0x51,0x1d,0xc6,0x3f,0x21,0xf3,0x3f,0xd5,0xb3,0xf1, - 0xcf,0xff,0xb3,0x77,0xfd,0xc1,0x51,0x94,0x69,0xfa,0x9d,0x9e,0x06,0x3a,0xc9,0x24, - 0x69,0x02,0xdc,0x61,0x89,0xda,0x4c,0x58,0x1d,0xdc,0xc9,0x0f,0x03,0x22,0xc5,0x85, - 0xa4,0x09,0xfc,0xc1,0x09,0x77,0xe4,0xb6,0xf6,0x8f,0xfb,0x63,0xcb,0xcd,0x79,0x96, - 0xe5,0xd5,0xe1,0x16,0xe7,0x5d,0xd5,0xb1,0xee,0x95,0xdb,0x09,0xc1,0x4d,0x0c,0x4a, - 0x5c,0xbd,0x5d,0xbc,0xb2,0x76,0x27,0x91,0xb3,0xb0,0x8a,0xad,0x0a,0xc1,0x55,0x64, - 0xf7,0x70,0xc2,0x06,0x6f,0x80,0x08,0x51,0xd9,0x2d,0xd6,0x73,0xdd,0x81,0x4b,0x69, - 0xd0,0xc8,0x05,0x44,0x0d,0x10,0xe0,0xfa,0xfb,0xba,0xfb,0xfb,0xd1,0xfd,0x76,0xcf, - 0xa0,0xe5,0x95,0x55,0xe7,0xfc,0xf5,0x55,0xd2,0x35,0xd5,0xdf,0x3b,0x5f,0x7f,0xdf, - 0xd3,0xcf,0xfb,0xbc,0xcf,0x2b,0xc3,0x00,0x33,0x73,0x5d,0xfa,0x9f,0x4b,0x30,0x58, - 0x9c,0xfe,0xd9,0x1d,0x5c,0x59,0x5d,0x84,0xfe,0x87,0xd4,0x7f,0x35,0x3b,0x85,0xf3, - 0x57,0xac,0x2a,0x5e,0x41,0x4f,0xf0,0x0f,0x7b,0x7e,0x43,0xf4,0x3f,0xf9,0x64,0x18, - 0xfe,0x01,0x1b,0xf6,0xd0,0x49,0x35,0x38,0xb3,0xbb,0x91,0x4e,0x73,0x6d,0xc6,0x1d, - 0x14,0xa5,0xff,0x51,0x5f,0x59,0xe3,0x8f,0xa7,0xb7,0x1e,0x08,0xfe,0x11,0xd0,0xac, - 0x5b,0xc6,0x7e,0xce,0x92,0x7f,0xdf,0x71,0x40,0xf0,0x8f,0x18,0x28,0xa3,0xc8,0xfc, - 0x97,0x37,0x58,0x98,0x2c,0xac,0x7f,0xb6,0xd1,0x8e,0x52,0xeb,0xf0,0x3f,0x07,0x5a, - 0x92,0x05,0xf3,0x5f,0xac,0xfe,0xab,0x85,0x26,0xc2,0xb2,0xeb,0x9c,0x81,0x83,0x7f, - 0xd4,0x00,0xfe,0x71,0x9f,0xd6,0x21,0x0a,0x7b,0x5e,0x05,0x39,0x1f,0x24,0xe3,0x1f, - 0xa9,0xfe,0x6b,0x16,0x19,0x7c,0x62,0xdd,0x51,0x44,0xfe,0x4b,0x67,0xb0,0xe7,0x1c, - 0x1c,0x28,0x84,0x7f,0xec,0xd3,0xca,0xa9,0xff,0x22,0x89,0xb0,0xcb,0x56,0xc3,0x98, - 0xfd,0xb5,0x4d,0xa1,0xf8,0x27,0x4f,0x69,0xab,0x97,0xc1,0x18,0x3e,0xfa,0x83,0xaa, - 0x63,0xf0,0xea,0xde,0x85,0xe3,0x65,0x34,0xb1,0x15,0x86,0x7f,0x6e,0x74,0x66,0x47, - 0xa6,0xf9,0xad,0x77,0xe0,0x97,0xce,0x7c,0x17,0x44,0xe0,0x9f,0xfa,0x5b,0x9d,0x30, - 0xba,0xfc,0x0f,0x3d,0xef,0x12,0xe1,0xf8,0x67,0xbb,0x33,0x3b,0xb6,0x6d,0x92,0xf3, - 0xab,0x2c,0x1d,0x81,0x7f,0xa4,0xd7,0xcc,0x8b,0x11,0xf9,0x2f,0x07,0xe4,0x94,0x49, - 0xaf,0xf9,0x9f,0xf8,0xf2,0x5f,0x02,0xfe,0x41,0xf5,0x3f,0xfb,0x47,0x93,0x91,0xf8, - 0x27,0xa0,0x17,0x32,0x0b,0xe4,0xbf,0x0e,0x96,0xb9,0x65,0xef,0x04,0x16,0x8e,0x68, - 0x7b,0x12,0xc6,0xc1,0x28,0xfc,0x43,0xf5,0x3f,0x1f,0x91,0xc1,0x6f,0x2b,0x5f,0x5a, - 0xf2,0x51,0xf6,0xa2,0x31,0x98,0x0b,0xd1,0x3f,0x53,0xfc,0x43,0xcf,0x2f,0x5a,0xf6, - 0x9e,0xab,0xfc,0x78,0xcb,0x44,0x36,0xa0,0x7f,0xc6,0xf0,0xcf,0x24,0x1c,0x6d,0x6f, - 0xca,0x6e,0x2b,0x96,0xff,0xb1,0x27,0xd5,0x63,0x1f,0x4c,0x5a,0xd1,0xfa,0xe7,0x2c, - 0xb4,0xc7,0x68,0x3e,0x34,0x9a,0xff,0xe1,0xa4,0x99,0xd2,0x63,0xd5,0x66,0x50,0x3c, - 0x89,0xe2,0x9f,0xff,0x86,0xa3,0x56,0xd3,0x43,0x69,0x69,0x61,0x44,0xe1,0x9f,0x4f, - 0xed,0xf8,0xac,0x34,0x8b,0xe7,0x7f,0x26,0x95,0x1c,0xa9,0xbf,0xc0,0xbe,0x3f,0x04, - 0xff,0xf4,0x58,0xfd,0x06,0x7a,0xff,0x28,0xfe,0x19,0x87,0xa7,0x3a,0x8c,0x61,0x34, - 0x3e,0x28,0xfe,0x79,0x5b,0xfb,0xf9,0x3e,0x18,0x0f,0xf2,0x3f,0x61,0xf8,0xe7,0x0c, - 0xbc,0xd5,0x57,0x3f,0x2e,0xa6,0xbd,0x30,0xfd,0x4f,0x39,0x8b,0xcf,0x94,0xfa,0x3e, - 0x34,0x8f,0xa2,0xf1,0xc1,0xf5,0x3f,0xd6,0xc7,0xb1,0x86,0x51,0x34,0x3e,0xb8,0xfe, - 0xc7,0x24,0xf5,0x5f,0xa9,0x62,0xf8,0x1f,0x67,0x76,0x8b,0x9e,0xb7,0x61,0x0f,0x3a, - 0x5f,0x54,0xff,0x7c,0x5c,0xdb,0xbb,0x66,0x51,0xbe,0x28,0xfe,0x87,0x80,0x1c,0xe5, - 0x03,0xb8,0x0a,0x4b,0xac,0x84,0xc4,0xff,0xec,0x0f,0xe2,0x1f,0x86,0x07,0xb2,0xd6, - 0x54,0x5b,0xa3,0x5a,0x3c,0xff,0x73,0xd6,0x3a,0x6c,0x1f,0x8b,0x28,0xbf,0x81,0xe3, - 0x1f,0xad,0xbd,0x35,0xb9,0xaa,0xf4,0x3a,0xf4,0xcf,0xdd,0xb1,0xe4,0x9a,0x2e,0xd4, - 0xaf,0x06,0xc3,0x3f,0x87,0x94,0x12,0x30,0xcc,0x52,0x9c,0x0f,0xf1,0xd6,0x83,0x84, - 0x7f,0xee,0xb6,0x61,0xcf,0xb6,0x62,0xf4,0xcf,0x6e,0x3e,0xeb,0x0a,0xac,0x6c,0xad, - 0xc4,0xe6,0x2b,0xe3,0x1f,0x07,0x3f,0xc4,0x2e,0x18,0x87,0x62,0x4b,0xfc,0xc0,0x20, - 0x5c,0xff,0x1c,0xef,0xd3,0xba,0x62,0xc9,0x42,0xfe,0x3f,0x84,0xff,0x79,0xd2,0x9d, - 0x5d,0xe6,0x19,0x30,0x5a,0x43,0xf4,0xde,0x98,0xfe,0xa7,0xe3,0x99,0x64,0xb2,0xb5, - 0x08,0xff,0x1f,0x86,0x7f,0xde,0x30,0x06,0xf1,0xfb,0x97,0xf8,0x1f,0xcd,0xfb,0xaf, - 0x7e,0x26,0xd6,0xb4,0x16,0xbd,0x3e,0x04,0xff,0xe4,0x9c,0xfa,0xaf,0x42,0xfc,0xcf, - 0x0a,0x96,0xff,0xea,0xab,0xee,0xbb,0x5d,0x80,0x3d,0xd1,0xf9,0xaf,0xb3,0xd0,0x61, - 0x64,0x4c,0xf4,0x79,0x41,0xeb,0xbf,0xfe,0x00,0x9d,0xb0,0xf0,0x74,0x07,0xf6,0xfc, - 0x22,0xfc,0xcf,0xe6,0xf8,0x31,0xe5,0x50,0xfb,0x1d,0xa7,0xd4,0x80,0x10,0x3a,0x5c, - 0xff,0x73,0x91,0xec,0x4e,0xd8,0x7e,0x22,0xe0,0x1f,0xb1,0x7e,0x67,0xaa,0xb7,0x29, - 0x9f,0x98,0x5a,0x1d,0x3c,0xbf,0x10,0xfe,0xe7,0x61,0xe5,0x04,0x8c,0x0d,0xd4,0x4c, - 0x94,0x63,0xf7,0x8f,0xf0,0x3f,0x44,0xff,0xb3,0x33,0x55,0x93,0x43,0xf9,0x6a,0xd1, - 0xff,0x87,0x05,0xed,0x23,0x2d,0x93,0x4d,0xe7,0x4b,0xb0,0x78,0x0a,0xf8,0x67,0x06, - 0x9f,0xaf,0x79,0xaa,0xb7,0xe9,0x20,0xdb,0x3f,0x6f,0x11,0xf7,0x4f,0x0c,0xff,0x9c, - 0x85,0x33,0x2d,0x8d,0x9e,0x5e,0x3a,0x14,0xff,0x80,0xb0,0x7b,0xbf,0x0e,0x0d,0x93, - 0x09,0x6c,0x3f,0x0f,0xc1,0x3f,0xdd,0x56,0x32,0x5f,0x88,0xff,0xe1,0xe7,0xf5,0x18, - 0xec,0x78,0xec,0xf6,0xa1,0x62,0xf9,0x1f,0x52,0x0f,0xd5,0xa5,0x1b,0xb9,0x10,0x3c, - 0xc0,0xc2,0x5f,0x2e,0xd4,0x7f,0x9d,0x34,0x1a,0x4e,0xa0,0xe7,0x0b,0xc2,0xff,0xec, - 0x89,0x4f,0x2b,0xd3,0x6d,0x21,0xe7,0x97,0xdf,0xff,0xa7,0xd9,0x2d,0xfb,0xda,0xd2, - 0x3c,0xb6,0xe1,0xa2,0xbd,0x6c,0x8e,0xf7,0x16,0x81,0x7f,0x1c,0x23,0xc4,0xb2,0x41, - 0x65,0xc4,0xe8,0x31,0x8a,0xd5,0x3f,0x1f,0x26,0xc2,0x27,0x6b,0x4b,0x2c,0x9d,0xed, - 0x09,0xc1,0x3f,0x41,0xdb,0xc3,0x91,0x99,0xe1,0xfe,0x3f,0x52,0xfd,0x3b,0x1b,0xf8, - 0x0b,0x91,0xc2,0xf8,0x1f,0x96,0x0f,0xbd,0x3e,0xfd,0x33,0x1c,0x55,0x8b,0xc2,0x3f, - 0x1c,0x08,0x15,0xc4,0x3f,0xf2,0x63,0xe2,0xd7,0x1f,0xca,0xf8,0xe7,0x2e,0xe9,0xf4, - 0x7f,0xd8,0x1e,0xf8,0xf5,0xc0,0x41,0xfc,0x53,0xde,0xe0,0x96,0x7d,0xd1,0x42,0xf8, - 0xdf,0x40,0xe3,0x44,0x61,0xfd,0xb3,0x33,0x38,0x67,0x4f,0xf3,0x7a,0xf4,0xcf,0xfb, - 0x04,0xa3,0xa4,0x68,0xfc,0xe3,0x0d,0x82,0x7f,0xc1,0xf1,0x8f,0x37,0x08,0x2a,0xa2, - 0x51,0xfc,0x23,0x14,0x82,0x15,0x83,0x7f,0x38,0xec,0x49,0x45,0xd7,0x7f,0x15,0x51, - 0x0f,0x85,0xe1,0x9f,0x39,0xd7,0x51,0xff,0x25,0x94,0x1d,0x7d,0xde,0xfa,0xaf,0x62, - 0xeb,0xdf,0xcb,0xe6,0x12,0xfd,0x4f,0xb8,0xfe,0x39,0xc0,0xff,0x40,0x51,0xf8,0x87, - 0xba,0xd9,0x7c,0x3f,0x6c,0xbe,0x21,0xfc,0x8f,0x3d,0x68,0x9d,0xe5,0xfa,0xe7,0x44, - 0xe0,0x9f,0x71,0xa8,0x8d,0x79,0x68,0xc7,0x58,0x67,0xef,0xd1,0xd0,0xd5,0x57,0x28, - 0xff,0x45,0x66,0xa7,0xd1,0x41,0x55,0xc7,0x70,0x86,0xe9,0x9f,0xfb,0x30,0xfc,0xf3, - 0x42,0x20,0x8c,0x11,0xfe,0x3f,0x4c,0xff,0xb3,0x9a,0x4f,0x24,0xa8,0x7f,0x46,0xf2, - 0x5f,0x10,0xb1,0x30,0x42,0xf0,0x8f,0x53,0x08,0x36,0xa7,0xa8,0xfc,0x17,0x06,0x7b, - 0x0a,0xd5,0xbf,0xbb,0x44,0xd0,0x44,0x71,0xf8,0xc7,0x7b,0x5a,0x93,0x4e,0x3d,0x54, - 0x41,0xfc,0xf3,0xae,0x53,0x08,0xf6,0xfd,0xf8,0x1f,0xad,0x22,0xf1,0xcf,0x65,0xb0, - 0x4f,0x9f,0x3d,0xf6,0x8b,0xff,0x35,0x2b,0x14,0xff,0xcc,0xf0,0xa3,0x9d,0x7d,0xf1, - 0x66,0xe0,0x8a,0x68,0x17,0xff,0xb0,0xf8,0x77,0x79,0xfb,0xcf,0x3f,0x38,0xd5,0xa6, - 0xe3,0x65,0xfb,0xe3,0xdf,0x81,0x97,0xf5,0x34,0x55,0x44,0x17,0xa8,0x7f,0xb7,0x07, - 0xc3,0x36,0x10,0x5a,0xc0,0x11,0x51,0x74,0xfd,0xd7,0x73,0x0e,0xff,0xbf,0x9e,0x3a, - 0xfa,0x16,0xaa,0xff,0xa2,0xb3,0xab,0x23,0xbb,0x6b,0xa3,0xc3,0x60,0x48,0xfb,0xa7, - 0x77,0x3f,0x12,0xff,0x13,0x5a,0xef,0x1c,0xaa,0x7f,0x6e,0xce,0x26,0x9c,0xfc,0x97, - 0x8f,0xff,0x09,0xaf,0xff,0x22,0xfa,0x13,0x35,0xa0,0x67,0x0e,0xe7,0x7f,0x5c,0xfc, - 0xe3,0xbb,0xde,0x5f,0xff,0x45,0x82,0xf0,0x3a,0x19,0xe4,0x1e,0xbb,0xa3,0xc3,0x25, - 0xca,0x1a,0x0a,0xe0,0x1f,0xca,0xff,0xe4,0x12,0xe7,0xa9,0x3e,0x6a,0xf0,0xc4,0xf6, - 0xc1,0x2d,0x51,0xf8,0xc7,0x99,0xdd,0x23,0xc3,0xdb,0xcf,0xc7,0x5d,0x47,0xa0,0x82, - 0xfc,0x8f,0x3e,0x64,0xad,0x30,0x12,0x45,0xf3,0x3f,0x39,0x82,0x0f,0x21,0x85,0xf1, - 0x3f,0xdc,0xff,0x27,0x25,0xf2,0x3f,0xdd,0xb1,0x14,0xce,0xff,0x20,0xfa,0xe7,0x01, - 0x65,0x3c,0xd9,0x6d,0x19,0x38,0x7f,0x22,0xd4,0x7f,0xa9,0x6c,0xfd,0x9c,0x86,0x6c, - 0x6e,0x45,0x03,0xca,0xff,0x70,0xfc,0xdf,0xa7,0xb3,0xf3,0xfd,0xb2,0x0d,0x8d,0x9b, - 0xcd,0x3a,0x0c,0xff,0x4c,0xf0,0xf3,0x97,0xe3,0x9f,0x21,0xc8,0xe9,0x0d,0x90,0x96, - 0xf4,0x3f,0xee,0xbf,0x2e,0x60,0xf5,0x5f,0x1f,0x18,0x5d,0xa3,0xc9,0xb6,0x02,0xfc, - 0x4f,0x96,0xaf,0x87,0xac,0xd1,0xde,0x61,0xf4,0x6b,0x82,0xfe,0x87,0xc5,0x67,0x92, - 0x2d,0x87,0x36,0x9d,0x9d,0xfe,0xbf,0x53,0x3a,0xad,0xbe,0x7e,0x94,0x0f,0x99,0x66, - 0xd7,0x0b,0xfc,0xcf,0x30,0x0c,0x59,0x0d,0xe9,0xb4,0x20,0xfb,0xe1,0xf8,0x67,0xa6, - 0x77,0xbd,0x39,0x97,0xc5,0xe7,0x02,0x5c,0x89,0x85,0xd6,0x7f,0x79,0xf3,0xd5,0x66, - 0x08,0x0f,0x5d,0x8e,0xf8,0xe7,0xa0,0xef,0x6b,0xdc,0xff,0x84,0xe3,0x9f,0x69,0xf2, - 0xfe,0x28,0x6d,0x9b,0x08,0xfe,0x01,0x8e,0x7f,0x7e,0x07,0xcf,0x5b,0x7d,0x06,0x5a, - 0xff,0x9e,0xc3,0xf0,0xcf,0x31,0xb3,0x5f,0x31,0x72,0xa8,0x9e,0xe1,0x6d,0x8e,0x7f, - 0x54,0x86,0x7f,0x2e,0xc1,0x7b,0xd6,0x92,0x90,0xfa,0x77,0x41,0x5f,0xcd,0xce,0xa3, - 0x6c,0xe9,0xc9,0x13,0x38,0xfe,0xa9,0x7e,0x93,0xad,0x07,0xc1,0xff,0xf9,0x3d,0xe5, - 0x70,0x7f,0x28,0xff,0xe3,0x5d,0x6f,0x09,0xf5,0x5c,0x4a,0x77,0x26,0xd5,0x12,0xc2, - 0xff,0x78,0x9f,0xf9,0x2a,0xc7,0x3f,0x66,0x37,0x24,0xff,0x06,0xd5,0x0b,0xe1,0xfc, - 0x8f,0xfd,0x3c,0x96,0xb6,0xe2,0xfc,0x0f,0xd7,0x3f,0x8b,0xf5,0x5f,0x39,0xa8,0xc2, - 0xf9,0x07,0x5e,0xff,0xb5,0xef,0x26,0x36,0xdf,0x4f,0xf4,0x4f,0xc8,0x6a,0xc1,0xe6, - 0x7b,0x96,0xe7,0xb3,0x38,0xfe,0xb9,0x60,0xbc,0x0e,0x4b,0x5a,0xd1,0xf8,0x9c,0x65, - 0xeb,0x67,0x3e,0x64,0x3c,0x90,0x73,0x4a,0xe9,0x82,0x7e,0x4d,0xc3,0xf8,0x9f,0xd7, - 0xd8,0xef,0x6b,0xaa,0x9d,0x6c,0x76,0x99,0xf6,0x76,0x63,0xd5,0x62,0x6c,0xbe,0x82, - 0xfe,0x79,0x2e,0x8f,0x7f,0xb2,0xa7,0x9a,0xe8,0x7f,0x50,0xfe,0xc7,0xbb,0xbe,0x5f, - 0x15,0xf2,0x59,0x43,0xd0,0xd0,0x56,0x8e,0xdd,0xff,0x38,0xfb,0xfe,0x71,0xbe,0x1e, - 0x86,0x89,0xac,0xf7,0x6e,0x4c,0xff,0x33,0xeb,0x12,0xc7,0x33,0x7c,0xbd,0xf5,0x75, - 0xe5,0xa0,0x49,0x4f,0x47,0xf3,0x3f,0x1a,0xaf,0xff,0xba,0x04,0x4f,0x24,0xea,0x06, - 0x34,0x0c,0xff,0xf0,0xfa,0x62,0x8d,0xe3,0x9f,0xed,0xf4,0xbc,0x76,0xf7,0x67,0x5f, - 0x3d,0x0e,0x56,0xff,0x75,0x22,0xb9,0x15,0x6a,0x46,0x51,0x3e,0x24,0xc7,0xf1,0xd5, - 0x7c,0x86,0x7f,0x0e,0x28,0x87,0xac,0x66,0x23,0x81,0xf1,0x3f,0x47,0x30,0xfc,0x33, - 0x66,0xbf,0xf6,0xb9,0x7a,0x83,0x70,0xfe,0xa7,0x4d,0x3d,0x60,0xba,0x87,0xd4,0x25, - 0xe5,0xf5,0xce,0x25,0x99,0x1a,0xec,0xfc,0x3a,0xc9,0xf5,0xc6,0x1c,0xcf,0x8c,0xc2, - 0x56,0x20,0xfa,0xc3,0x38,0xc2,0xff,0xb0,0xeb,0x2d,0xdd,0xad,0xff,0xb2,0xaf,0x37, - 0xb7,0xea,0x21,0x7a,0x45,0x5e,0xff,0x65,0xce,0xdd,0xc6,0xcf,0x3b,0xcb,0x4c,0xf6, - 0x6a,0xd8,0xfb,0xd7,0xa8,0x80,0x57,0xbd,0xf9,0x2a,0x67,0xb4,0xdf,0xc0,0xa0,0x99, - 0x76,0x8e,0x09,0x79,0xbe,0x47,0x78,0xbe,0x55,0x67,0x78,0xe0,0x3d,0xeb,0xb2,0xd9, - 0xf4,0xb7,0xc1,0xf8,0x90,0x54,0x9a,0x2a,0xe0,0x9f,0x98,0xbb,0x69,0x7f,0x00,0xc7, - 0xb5,0x25,0x06,0xca,0xff,0x8c,0x31,0xfe,0x47,0xa8,0xff,0x7a,0x4f,0xe9,0xc9,0x26, - 0x57,0x95,0xa3,0x7c,0x4e,0x1b,0xc3,0x3f,0xfc,0xbc,0xcb,0xb5,0xf5,0x58,0x49,0x0d, - 0x3b,0xef,0xaa,0xf2,0x6c,0xfd,0xb8,0xfe,0x87,0x76,0x10,0x5a,0x4c,0x65,0xcb,0xaa, - 0xa4,0x5e,0x22,0xd8,0x00,0x62,0xf5,0xef,0x54,0x8f,0x44,0x67,0x37,0x0e,0x47,0x5b, - 0xea,0x67,0xaf,0x1f,0x98,0x33,0x11,0x0b,0xe0,0xbd,0x99,0xde,0xfd,0x10,0xff,0x67, - 0x67,0x52,0xd5,0x93,0xf0,0xd9,0xc2,0x57,0x35,0x9c,0xff,0xb9,0x15,0xc1,0x3f,0x57, - 0xe1,0xaa,0x35,0x98,0x4b,0x9c,0x8c,0x1f,0xf0,0x8c,0x80,0x38,0xfe,0x61,0xfa,0x43, - 0x6b,0xbe,0x80,0x76,0xf6,0x5b,0xd5,0x27,0x53,0x3b,0x94,0x5a,0xf0,0xfb,0x3f,0x73, - 0xfc,0xe3,0xf0,0x3f,0xee,0xd3,0x34,0x08,0xc6,0xa3,0xa9,0x01,0xbf,0x31,0x0b,0xc5, - 0x3f,0xf5,0xec,0x7e,0x04,0xfe,0x67,0x3f,0x24,0xad,0xb5,0xbd,0x4a,0x1a,0xca,0x8a, - 0xe3,0x7f,0xce,0x43,0x43,0x7d,0x5a,0x8f,0xef,0x0e,0xd6,0xbf,0x63,0xfd,0x2f,0xa6, - 0xe1,0x2a,0x34,0xd5,0xa3,0xf8,0x67,0x1c,0xc3,0x3f,0x13,0xf6,0x69,0x58,0x6f,0xe3, - 0x9f,0xd5,0x13,0x26,0x17,0x1a,0x39,0xff,0x3a,0x27,0xf2,0x3f,0x3a,0xbf,0x7f,0xe3, - 0x76,0xb0,0xd7,0xc3,0x48,0xc0,0x3f,0xf3,0x53,0x01,0xff,0x08,0xbf,0xbe,0x1d,0x9f, - 0x16,0x4d,0x9f,0x79,0xcc,0xff,0x46,0x26,0xe1,0x9f,0x7b,0xf8,0xe9,0x7f,0xc0,0x5a, - 0xdc,0xa6,0xfd,0x75,0x95,0x03,0x03,0x4a,0x1f,0xc6,0xf1,0xcf,0x7a,0x9e,0xed,0x1a, - 0x84,0xfa,0x4d,0xe9,0xe5,0xd5,0x0e,0xec,0x29,0x5b,0x11,0x5f,0x8f,0xe0,0x9f,0x19, - 0x4e,0x7c,0x66,0xd9,0xd1,0x50,0x3f,0x85,0xbb,0x36,0xd9,0xdb,0xf2,0xb4,0x33,0x4d, - 0x81,0x11,0x42,0xf1,0x0f,0x8d,0xff,0x68,0xba,0x37,0x12,0xff,0xe4,0x4a,0x84,0xf7, - 0xa9,0x97,0x40,0x28,0xfb,0x12,0xf7,0x93,0x8f,0xd9,0xf3,0x6e,0xe8,0x9c,0xff,0x51, - 0x97,0x59,0x46,0x3e,0xf5,0x2f,0x91,0xf8,0xe7,0x01,0x75,0x44,0x8c,0x67,0x72,0x8c, - 0xe9,0xeb,0x44,0x86,0xed,0xbf,0x82,0xfd,0x2f,0x08,0xda,0xf9,0x14,0x96,0xf4,0x26, - 0x0a,0xe0,0x1f,0xb7,0xff,0xc5,0x06,0xe7,0xf4,0x39,0xa0,0xe1,0xfc,0x8f,0x80,0x7f, - 0x16,0xd1,0x43,0x8d,0x96,0x05,0x5d,0xb4,0x1a,0xcc,0x34,0xd2,0xff,0x62,0x8e,0xbf, - 0xfe,0xcb,0x3b,0x6d,0x7b,0xfb,0xef,0x0d,0xd1,0x3f,0x7b,0x1f,0xd6,0xff,0xc2,0x95, - 0xfd,0xac,0x29,0x80,0x7f,0x52,0x32,0xff,0x63,0x48,0x65,0x5f,0x02,0xff,0x63,0xb0, - 0xef,0x97,0xf8,0x9f,0x90,0xfc,0xcb,0xd9,0x59,0x8c,0xff,0x91,0xea,0xdf,0x95,0xe6, - 0x56,0x51,0xc6,0xc3,0xa8,0xa1,0xb3,0xa1,0xfa,0x9f,0x4d,0x09,0xea,0x97,0x18,0x8a, - 0x7f,0x96,0xcf,0x77,0x40,0x4e,0x05,0xa1,0x7d,0xf6,0xc1,0x0a,0xc3,0xc1,0x3f,0x31, - 0x1f,0xfe,0x61,0xfb,0xcf,0xda,0x19,0x9d,0xe2,0xec,0x36,0x52,0xfd,0x73,0x2c,0x02, - 0xff,0xb8,0xf8,0xb3,0xd4,0x91,0x3d,0xdf,0x5e,0x08,0xff,0x08,0xfe,0x3f,0x63,0x73, - 0x2f,0xaa,0x4d,0x6b,0x6b,0x76,0x44,0xe2,0x1f,0xaf,0xff,0x85,0x0b,0x7b,0x56,0xb4, - 0xd4,0x3e,0x83,0xf0,0x3f,0x97,0x84,0xf5,0x23,0xeb,0x7f,0xf4,0x22,0xf2,0x5f,0x1e, - 0xda,0x51,0x0f,0x24,0xea,0x2c,0x2d,0x53,0x35,0x6e,0x7c,0x10,0x8a,0x7f,0xe4,0xfa, - 0xf7,0x58,0xc5,0x1b,0xe4,0x31,0x51,0xf7,0x42,0x22,0x04,0xff,0x58,0xb3,0x25,0xfe, - 0x67,0xe3,0x68,0x89,0x0d,0x84,0x02,0x46,0x5e,0x1c,0xff,0x74,0x69,0x37,0xcb,0x6a, - 0xe7,0x1a,0x14,0xff,0xb0,0xfd,0x47,0x9b,0xb1,0x5b,0xde,0x3d,0x2a,0x6c,0x20,0x14, - 0xd8,0xcf,0x03,0xfd,0x2f,0xf8,0x69,0xb5,0xe0,0x22,0x86,0x7f,0x58,0x7c,0x76,0xf9, - 0xfa,0xef,0x1c,0xb2,0xf1,0xc9,0x3b,0xc4,0x08,0x88,0x4c,0x13,0xc1,0x3f,0x7e,0xfe, - 0xc7,0xd4,0x36,0x75,0x04,0xf7,0xab,0xd7,0x98,0xff,0x06,0xeb,0x7f,0xe1,0x46,0xcf, - 0x4c,0x2d,0x47,0xde,0xbf,0x46,0xad,0x10,0xfe,0xa7,0xd1,0xd4,0x10,0xbc,0xa7,0x1c, - 0x0b,0xf5,0xff,0x31,0x09,0x50,0x04,0x47,0xff,0xcc,0xb7,0xe2,0x71,0xa1,0xff,0x85, - 0x78,0xba,0x19,0xcd,0x9b,0xd2,0xbe,0xf3,0x8e,0x66,0x40,0xf2,0x8c,0xff,0xe9,0x93, - 0xf8,0x1f,0xab,0xb6,0x3e,0xe5,0x19,0xf1,0x55,0x16,0xe6,0x7f,0xec,0xe7,0xa5,0xd5, - 0x3e,0xef,0xde,0xf3,0xfe,0xb2,0xdb,0x2b,0x0d,0xcb,0x33,0xfd,0x98,0xdb,0xff,0x22, - 0xeb,0x95,0xc5,0xad,0xd1,0x96,0xde,0x3f,0x0c,0x8e,0x30,0xb8,0x60,0xfe,0xeb,0x15, - 0x20,0xfe,0xc3,0xee,0x7c,0xcb,0x5e,0xa4,0x8a,0x5c,0x52,0x11,0xf6,0xa7,0xf9,0x47, - 0x83,0xf8,0x87,0xce,0x6e,0xa5,0xf3,0x22,0xef,0x18,0x41,0x3f,0xc5,0xcf,0xf7,0xd5, - 0x6c,0xfd,0x80,0xd2,0x09,0x7d,0x90,0x32,0xed,0xf7,0xc0,0xf0,0x01,0x88,0x1f,0x15, - 0xec,0xbb,0x33,0x41,0x8f,0x1a,0x88,0x1f,0xfb,0x2d,0x1f,0x34,0x53,0xd1,0xa3,0x06, - 0x5f,0xe4,0xfb,0x2d,0x7b,0xb1,0x6a,0xa4,0xbf,0x59,0xc4,0x40,0xf8,0x44,0x5f,0xe8, - 0x0c,0xbe,0xc8,0xf7,0x5f,0xef,0xe7,0x2b,0x16,0x7f,0x9d,0xf4,0xf2,0x1b,0x81,0x7f, - 0x84,0x05,0xd9,0x88,0x81,0xfa,0xb9,0xbf,0xff,0x4b,0x8e,0xbf,0xaa,0x5b,0x45,0xc4, - 0x3c,0xc6,0xf6,0xc3,0xeb,0xfd,0x34,0x36,0x16,0x73,0x55,0x65,0xe5,0xe7,0xfc,0xfa, - 0xff,0x83,0x4f,0xf3,0xb5,0x6b,0xd7,0xb2,0x05,0x06,0xff,0x9f,0xaf,0xff,0x8a,0x3d, - 0x8f,0x5f,0xef,0x87,0x5f,0xef,0x87,0x5f,0x20,0xfe,0x5f,0xef,0x87,0x85,0x3e,0x5f, - 0xb5,0xfd,0xe7,0xab,0x75,0xbd,0xc4,0x8f,0x5d,0xb1,0xee,0x20,0xfe,0x90,0x81,0xf7, - 0x8b,0x59,0x58,0x7e,0xb0,0x65,0x84,0xea,0xc7,0xb4,0x7d,0x0e,0x90,0x0e,0xe5,0xc7, - 0xd8,0xfb,0xc2,0x36,0xd8,0x13,0x33,0x86,0x6e,0x88,0xce,0x0f,0xe6,0xe7,0x09,0xec, - 0x62,0xb7,0x91,0xcc,0x17,0xc8,0x0f,0xc6,0xb8,0x3f,0xe4,0x36,0xed,0x1c,0x3c,0x94, - 0xc5,0xfc,0x42,0x15,0xce,0x8f,0xb5,0x8b,0xfe,0x90,0xd3,0x6a,0x48,0xfe,0x2b,0x84, - 0x1f,0x3b,0xec,0x1a,0x75,0x06,0xf8,0x1f,0x34,0x3f,0x38,0xd1,0xd9,0x15,0x4b,0x4f, - 0x26,0x8a,0xd6,0x87,0xff,0x25,0x69,0xd3,0x70,0x01,0xcd,0x9f,0x9e,0x63,0xbf,0x17, - 0xd7,0x87,0xcf,0x7c,0x17,0xb6,0x5a,0x35,0x63,0x68,0x7e,0xf0,0x2a,0xbb,0x9e,0xe4, - 0x07,0xf7,0x7a,0xfc,0xd8,0x10,0x34,0x0e,0x57,0x60,0xfa,0xf0,0xb7,0xd8,0xfb,0x69, - 0x9b,0xa0,0x8f,0x52,0xec,0xd9,0x0d,0x6f,0x38,0x87,0xe5,0x07,0x15,0x6f,0xbe,0x5e, - 0x7f,0x58,0x1a,0xf6,0xa1,0x58,0x03,0xb1,0x0d,0x3f,0x4b,0xfd,0xdb,0x2b,0x70,0x7e, - 0x4c,0x17,0xde,0x37,0x3b,0xe1,0xce,0x2c,0xd5,0x67,0x06,0xfc,0x21,0xd9,0xfb,0x20, - 0x88,0xfa,0xa8,0xad,0xd9,0xea,0x36,0x6d,0x73,0xd5,0xbb,0xea,0x8f,0xda,0x6b,0xf2, - 0x4a,0x48,0x7e,0x90,0xad,0xb7,0x09,0xb0,0x72,0x8b,0x1c,0x5a,0xcc,0xaf,0x37,0x7b, - 0x3b,0xa0,0x8f,0x2a,0x27,0x6c,0xd8,0x6b,0xd0,0xd0,0xa1,0x79,0xfe,0x90,0x15,0x38, - 0x3f,0xc6,0xf5,0x51,0xa7,0x94,0x29,0x15,0xef,0x8f,0x36,0xe7,0x4d,0x76,0x5e,0x88, - 0xfe,0x00,0x70,0x38,0xd3,0xd0,0xba,0x81,0xf8,0x03,0x44,0xe5,0x07,0x39,0x3f,0x66, - 0x95,0x9c,0x52,0x02,0x7a,0xa7,0xa6,0xd0,0xfc,0xe0,0x7d,0x66,0x37,0xf4,0x17,0xd2, - 0x47,0x81,0x9c,0x1f,0x4c,0x99,0x9e,0x3f,0x52,0x88,0x3e,0x6a,0x33,0xef,0x8f,0x96, - 0xa5,0xf9,0xdf,0x5b,0x2c,0x25,0xe8,0x87,0x29,0xf0,0x63,0x42,0x7d,0x9c,0x72,0x05, - 0xee,0x0c,0xe8,0xa3,0x56,0x50,0xbe,0x4b,0xe4,0xc7,0x3c,0xbd,0xf4,0x6f,0xe1,0x2f, - 0xe0,0x87,0x8e,0xb0,0x3c,0x82,0x1f,0x73,0xfb,0xa3,0x51,0x36,0xcc,0xb3,0x85,0xb4, - 0x02,0xf9,0x41,0xb6,0xff,0x98,0xa2,0x3f,0x52,0x7b,0xcc,0xfe,0xf5,0xa3,0xf3,0x83, - 0x3b,0xe6,0x89,0xf9,0xd9,0x58,0xed,0xda,0x10,0x7d,0xb8,0x77,0xbd,0xc8,0x8f,0xc1, - 0x61,0xdd,0xeb,0x0f,0xab,0x3c,0x12,0x96,0x1f,0xc4,0xeb,0xe3,0x8a,0xc9,0x0f,0x66, - 0x20,0x57,0xda,0x50,0x6c,0x7f,0xd8,0xb2,0x8c,0x72,0xb9,0xed,0x09,0xf3,0x9b,0x4f, - 0xa3,0xfa,0xa8,0x83,0x9c,0x2f,0xed,0x64,0xfb,0x4f,0x1d,0x74,0x0c,0x1b,0x43,0x65, - 0x05,0xf2,0x83,0xc0,0xf9,0xb1,0xaa,0x47,0xbb,0x16,0xe3,0xf9,0x7d,0x21,0x3f,0xd8, - 0x75,0xb3,0xee,0x92,0x60,0xff,0x06,0xff,0xd9,0x49,0xcb,0xe2,0xfe,0x18,0xc5,0x8f, - 0x2d,0x60,0xfb,0xed,0x29,0xda,0xd8,0x9a,0x6c,0xb3,0x46,0x78,0x7e,0xd0,0xe4,0xe7, - 0xd7,0x0f,0xe0,0xb8,0x25,0x97,0x75,0x63,0xf9,0x41,0xd6,0x1f,0x4d,0xd9,0x6c,0xfe, - 0x68,0xfe,0x9d,0x16,0x7a,0xff,0x1f,0xf0,0xe7,0xd1,0x22,0xfb,0x15,0x9d,0xe6,0x49, - 0xf8,0x39,0x2c,0x94,0x6c,0x10,0x78,0x7e,0x90,0xf1,0x63,0xdc,0x1f,0x52,0x59,0x0b, - 0x4f,0x65,0x17,0x39,0x1b,0x51,0x80,0x1f,0xeb,0x64,0xbf,0x17,0x3f,0xbf,0x36,0x56, - 0xfd,0xde,0x6a,0x68,0xab,0x18,0xf0,0xf2,0x11,0x68,0x7e,0xd0,0xe2,0xfd,0x1a,0x36, - 0xc2,0x99,0xb6,0xa6,0x49,0xf4,0x3c,0x12,0xf3,0x83,0xbc,0xde,0x07,0x58,0x5b,0x90, - 0xe3,0x8e,0x3f,0x00,0x9a,0x1f,0xf4,0xce,0x2f,0xc8,0xaa,0x1f,0x66,0x49,0xff,0xd3, - 0xf8,0xee,0x80,0x3f,0xb3,0xc0,0x8f,0xc5,0xd8,0xf5,0xe3,0xb1,0x9e,0x6c,0xed,0xa4, - 0xa3,0x07,0x56,0x7c,0xfc,0x18,0xcf,0x0f,0x52,0x3d,0xcc,0x46,0x12,0x84,0x9c,0xfe, - 0x9c,0x07,0x0c,0x9e,0x13,0xf9,0xd8,0x1b,0xed,0xf5,0xc6,0xf1,0x36,0xe5,0xc7,0x68, - 0xdb,0xf1,0x29,0x38,0xaa,0xd0,0x7c,0xf1,0x34,0xd5,0x3f,0x97,0x8b,0x7e,0x50,0x1d, - 0x8c,0x1f,0xbb,0x69,0x5a,0xff,0xa1,0x37,0xdf,0xf7,0xc3,0xfc,0x8d,0x05,0x7f,0x24, - 0xc7,0x5f,0x2b,0x9b,0x58,0x1b,0x6f,0x80,0xd7,0xed,0xd5,0x72,0x0b,0xd6,0x5f,0x58, - 0xf0,0x87,0xd4,0x1c,0x90,0xa3,0x59,0x4a,0x0a,0x4e,0x31,0x5b,0x6c,0x59,0x1f,0x1e, - 0x1f,0xe0,0xfd,0xd1,0x60,0x9b,0xba,0x37,0x96,0x36,0xbb,0x08,0x6a,0x6f,0x67,0xcb, - 0xc0,0x08,0xd5,0x47,0x01,0x0d,0x5a,0x4b,0xaa,0xb3,0x34,0x45,0x84,0x9a,0xfe,0xc2, - 0xc3,0x00,0xfe,0x71,0x48,0xd1,0xc9,0x44,0xb7,0xb2,0xd0,0xe8,0xae,0xf7,0xda,0xc6, - 0xc5,0x1f,0x91,0x12,0xeb,0x42,0x7e,0x70,0x36,0xad,0x7f,0x1f,0xaf,0xcb,0xda,0xf1, - 0xf9,0xc8,0x72,0xc2,0xa2,0xfb,0xe3,0xb3,0xcb,0x87,0x7f,0x1a,0x5b,0x13,0x9d,0x65, - 0x86,0xbd,0xbf,0x35,0x0c,0xb9,0xf5,0x08,0xb2,0xff,0x00,0xcf,0x0f,0x66,0x9d,0xfc, - 0xa0,0xa9,0x3d,0xa6,0xfc,0x3d,0xfc,0x9e,0xcb,0xe4,0x64,0xbd,0x1c,0xcf,0x0f,0xe6, - 0xe8,0x7a,0x30,0x2c,0x1b,0x46,0xde,0xaf,0xfc,0x18,0x5c,0xdb,0x84,0xa7,0x7c,0xf5, - 0xec,0x1c,0xff,0x4c,0x52,0x7d,0xd4,0x83,0x3b,0x53,0x53,0xca,0x77,0xcd,0x9f,0xd0, - 0x32,0x79,0xc7,0x1f,0x32,0x4c,0x1f,0x35,0x9f,0xe8,0xa3,0xea,0x87,0x13,0xf5,0xf1, - 0xfb,0xf3,0x6f,0x82,0x6b,0x0b,0x70,0x19,0xea,0x43,0xf0,0x8f,0xab,0x8f,0x22,0x6d, - 0x61,0x77,0xc3,0x55,0xcb,0xf1,0x57,0xb7,0xff,0xf2,0xaa,0x37,0xf0,0xe9,0xc3,0x5d, - 0xfc,0x63,0xd9,0xb0,0x67,0x11,0x81,0x0d,0x3c,0x2c,0x1b,0x06,0xaa,0x11,0xfc,0x33, - 0xa2,0x51,0x7f,0x36,0x22,0x33,0x68,0x84,0xe7,0x03,0xfd,0x41,0x02,0xf8,0xc7,0x70, - 0xf1,0x8f,0x36,0xa5,0xfc,0x09,0x3c,0x6a,0x7d,0xc3,0x99,0xa6,0xdb,0x0f,0xee,0x9e, - 0x20,0xfe,0xd9,0xe8,0xea,0xcd,0xa8,0x2d,0x40,0xbf,0x6f,0xdb,0xc1,0xf0,0x0f,0x10, - 0xfc,0xd3,0x6c,0xa5,0x8c,0x39,0x1a,0x6b,0x8b,0x16,0x2b,0xa4,0x8f,0x6a,0x84,0x0d, - 0x56,0x59,0x1e,0xa6,0x43,0xf5,0xe1,0x01,0x7d,0x54,0xa2,0x77,0xce,0xfd,0x96,0x5f, - 0x36,0x3c,0xe6,0xa5,0x0e,0x83,0xf8,0x27,0xd1,0xab,0xdc,0x06,0xdd,0x66,0xa8,0x3e, - 0xdc,0xfb,0x78,0xf9,0xc1,0x6f,0x3e,0xad,0x2c,0x85,0xc7,0x0b,0xeb,0xc3,0x8d,0xb9, - 0x0e,0xfe,0x29,0x3d,0x51,0xfa,0xcf,0xca,0xd6,0xac,0x57,0x2f,0x1f,0xaa,0x0f,0xdf, - 0x7c,0x93,0xd0,0x1f,0x76,0x24,0x6c,0xbe,0x1c,0xff,0xec,0xa3,0x78,0xa0,0xae,0x75, - 0xbd,0x1e,0x0f,0x3f,0xe8,0xe7,0x70,0xfc,0xb3,0x9c,0x5e,0xbf,0xcc,0xac,0x18,0x8d, - 0x2f,0x85,0x3f,0x80,0x57,0x56,0x6f,0xca,0x78,0x40,0xd4,0x47,0x51,0x90,0x33,0x57, - 0xeb,0x50,0x0c,0xab,0xcb,0x20,0x65,0xf2,0x04,0xf6,0x2c,0x0c,0xcd,0x0f,0x42,0xa7, - 0xeb,0x8f,0xd4,0xd1,0x69,0x38,0xfe,0xd8,0xca,0x9a,0x28,0xfc,0x03,0x6e,0x7f,0x58, - 0xbd,0x94,0xb4,0x99,0x53,0x4c,0x85,0x08,0xb9,0x23,0xf0,0x8f,0x4a,0x6f,0xf2,0xde, - 0x0a,0xc7,0xdd,0xf1,0xc7,0x6e,0x22,0x58,0x9e,0xaf,0x22,0xe4,0x07,0x1d,0x7f,0x6c, - 0xbc,0x2c,0x0e,0xcb,0x0f,0x02,0x5d,0x6f,0x34,0x2d,0x68,0x90,0xfa,0x38,0x16,0xf6, - 0x72,0x1e,0xff,0x59,0x41,0x7d,0x94,0x96,0x57,0x2e,0xc2,0xbb,0x66,0x12,0xd7,0x87, - 0x73,0xfc,0xa3,0xcd,0x5d,0xef,0x3d,0x2f,0xbf,0x30,0x5f,0xc8,0x0b,0xb0,0xa7,0x04, - 0xc5,0x3f,0xa0,0x7f,0x07,0x7e,0x0a,0x0f,0x66,0xb5,0x56,0xe5,0x02,0xbc,0x6c,0x7a, - 0xf8,0x47,0xf5,0xe3,0x1f,0xef,0x93,0xd8,0x71,0x8f,0x0d,0x72,0x1a,0xf3,0x89,0x07, - 0xe2,0x07,0x60,0xc2,0x7a,0xc5,0x85,0x3d,0x03,0x37,0xe5,0xcb,0x39,0xfe,0x51,0x38, - 0xfe,0x29,0x75,0xf3,0x65,0x75,0x96,0xfd,0x9a,0xf0,0xb6,0xe3,0x07,0x68,0x6f,0x23, - 0x9b,0x96,0x49,0xfb,0xed,0xc1,0x59,0xde,0x7c,0xef,0xe5,0xf9,0xc1,0x47,0xec,0x41, - 0x83,0xd7,0x28,0xc4,0x06,0x42,0x42,0xa2,0xf0,0x24,0xf3,0xd3,0xde,0xa5,0x39,0xef, - 0x5f,0x95,0xad,0xf1,0xad,0xd6,0xab,0xb0,0x30,0xef,0xc8,0xc2,0xf5,0xc5,0xb2,0x3e, - 0x9c,0xe7,0x07,0x2d,0xcf,0xcf,0x56,0x79,0xc7,0x78,0xd9,0x5c,0x98,0x73,0x65,0xe1, - 0x0b,0x25,0x7d,0xb8,0xa0,0x8f,0xf2,0xf4,0x09,0x60,0x2f,0xc2,0xbd,0x16,0xdb,0xc6, - 0x65,0x3c,0x29,0xea,0xa3,0xdc,0x49,0xd5,0xc7,0x4f,0xc3,0x45,0xc3,0xf5,0x07,0xb8, - 0x66,0xbf,0xc8,0x8b,0xfd,0x2f,0x8e,0x09,0xfa,0x28,0x7a,0x1e,0x65,0x2b,0x5e,0x8c, - 0xff,0x3b,0xf0,0x36,0x22,0x62,0xbd,0xd2,0xf6,0x01,0xfb,0xfd,0xdd,0x9f,0x1f,0x4c, - 0x5c,0x8a,0x13,0x7f,0xc8,0x25,0x38,0x1e,0xc8,0x30,0xfc,0xe3,0xe5,0x07,0xb5,0x17, - 0x4b,0x67,0x11,0xff,0xa2,0x6c,0x89,0x73,0x6c,0xad,0x90,0xf2,0x83,0xa7,0xb8,0x3e, - 0x6a,0x86,0x73,0x7d,0xea,0x45,0xe5,0x7b,0xd0,0xe3,0x3b,0xe6,0x98,0x3e,0x2a,0xc3, - 0xf1,0x8f,0x9b,0x1f,0xd4,0x06,0x94,0xfb,0x5a,0x7a,0xc0,0xc8,0x95,0x34,0xcc,0x24, - 0xf9,0x68,0x2d,0x5b,0x8a,0xeb,0xc3,0x6f,0xd8,0xa8,0x91,0x49,0x25,0x88,0x4d,0x50, - 0x0f,0x0c,0x1e,0xa9,0x24,0xb2,0xf0,0xcf,0xec,0xbf,0xdc,0x38,0xc8,0xe3,0xc3,0xbf, - 0xbf,0x9f,0xe7,0x07,0x5f,0xb4,0x88,0xff,0x4f,0x39,0x3b,0xb6,0xf6,0x08,0xf8,0xe7, - 0x1b,0xde,0x7e,0x32,0x34,0xe3,0xaa,0x2e,0xa0,0xe5,0x95,0x79,0x4c,0x1f,0xbe,0x5a, - 0xc0,0x3f,0xf3,0x7d,0x6a,0x70,0x5c,0x1f,0x3e,0x53,0xc0,0x3f,0xf2,0xe9,0xa3,0xd5, - 0x57,0x8d,0xe8,0x11,0xfc,0x8f,0xba,0x5b,0x97,0xa2,0x87,0xf3,0x3f,0x6c,0x3d,0xac, - 0x9a,0x27,0xa8,0xe9,0x7e,0x45,0xda,0x7e,0x61,0x78,0x78,0x34,0xe8,0x8f,0xed,0xfd, - 0xfa,0xb7,0xf8,0xd7,0xc3,0x50,0xa5,0xcf,0x1f,0x5b,0xfd,0x50,0x5c,0x5d,0x58,0xfe, - 0x5a,0xc0,0x3f,0x72,0x7f,0xd8,0x58,0xed,0x69,0xd4,0xdf,0x32,0x44,0x1f,0x65,0x0f, - 0xf2,0x5d,0xd8,0x79,0x3d,0xc5,0x28,0xee,0x29,0x51,0x1f,0x65,0x0f,0xc6,0x4a,0x51, - 0x7d,0xb8,0xe0,0x8f,0x2d,0xe8,0xa3,0x3e,0xb6,0xe4,0xb6,0x68,0x6c,0xf0,0x36,0xf7, - 0xc7,0x9e,0x27,0xc5,0xa7,0x69,0x08,0xd7,0x87,0x33,0x7c,0x98,0x92,0xf5,0x0c,0x8d, - 0x59,0x35,0x5a,0x1f,0x9e,0xd3,0x16,0x78,0x26,0xd8,0xce,0xb6,0x49,0xf8,0x1f,0x35, - 0x80,0x7f,0xb8,0xfe,0xc1,0x5f,0x1f,0x87,0xf2,0x5d,0xa2,0x3e,0xca,0x59,0x6f,0xa5, - 0xd8,0x36,0xce,0xeb,0xe3,0x04,0x7f,0x6c,0x49,0x0d,0x55,0x6b,0xe1,0xfa,0x28,0x5e, - 0x1f,0x17,0x43,0xfd,0x6a,0x02,0xf5,0x71,0xde,0xf5,0x82,0x3e,0x7c,0xcc,0x05,0x42, - 0x05,0xf4,0xe1,0x82,0x3e,0xea,0x22,0x2c,0x37,0x53,0x28,0xfe,0xe1,0xf5,0x6b,0x31, - 0x5f,0x7d,0x1c,0xaa,0xe7,0xe1,0xfe,0xd8,0x06,0xe5,0x7f,0x36,0xd2,0xd3,0x5f,0xbd, - 0xc3,0x3e,0xfd,0x51,0xbf,0x44,0xee,0x8f,0x2d,0xe0,0x1f,0x3a,0x3b,0xab,0x5c,0x9a, - 0xef,0xbe,0x40,0x7d,0xdc,0x0d,0x7c,0x76,0xda,0x19,0x58,0xe1,0x09,0x81,0xa4,0xf9, - 0x56,0xa3,0xfe,0xd8,0x64,0xb0,0xd2,0xd4,0xa4,0xeb,0xdd,0x7e,0xb2,0xaf,0xcd,0x15, - 0xf4,0x51,0x9c,0xff,0x19,0xb7,0x07,0xe5,0x88,0x3e,0xbc,0x45,0xe8,0x0f,0x0b,0x9d, - 0xf2,0xec,0x50,0x3d,0xd8,0x8f,0x39,0xfe,0x11,0xfb,0xad,0xbc,0x40,0xe3,0x89,0xfa, - 0x43,0x7a,0xd7,0x67,0xe4,0x7e,0x28,0x8d,0xf8,0xef,0xbb,0x8b,0xaf,0xff,0xd8,0xce, - 0xf0,0xb2,0x41,0x6f,0x70,0xdb,0x79,0x9d,0xaf,0x1f,0x81,0xff,0xb1,0x07,0x0a,0xaa, - 0x8f,0x3a,0x18,0xe2,0x8f,0x04,0x75,0x5d,0x98,0x3e,0xfc,0x5b,0x42,0x7d,0x9c,0xba, - 0x5e,0x76,0xa3,0x95,0xf5,0xe1,0xee,0x1b,0x3a,0xaf,0x8f,0xb3,0x6c,0xfc,0x23,0x3d, - 0xad,0xa8,0xbe,0x91,0xd7,0x43,0x75,0x75,0xdd,0xe3,0xf1,0x3f,0x3f,0x23,0x68,0x27, - 0x23,0xeb,0xc3,0xdf,0xf7,0xfb,0x63,0x6b,0xb2,0x5e,0xa8,0xc9,0xaa,0xc3,0xf7,0x13, - 0xb6,0x3f,0xa8,0xbf,0x96,0x4e,0x2b,0x23,0x3d,0x55,0x8d,0xf9,0x03,0x78,0xf1,0x91, - 0xf4,0x51,0x7b,0xa1,0xa6,0x0b,0xf7,0x07,0xe0,0xfe,0xd8,0xd6,0xb3,0xd2,0x7f,0xa1, - 0x90,0x3f,0xa4,0x4f,0x1f,0x65,0x2d,0xc6,0xf6,0x1f,0xd1,0x1f,0x5b,0x9c,0x9d,0x1a, - 0x72,0x7e,0x09,0xfe,0x00,0x31,0xac,0x5e,0x3b,0xbc,0x3e,0x6e,0xa1,0xfe,0x6b,0x4d, - 0xdc,0xbd,0x2d,0x54,0x1f,0x9e,0x0b,0xe0,0x1f,0xef,0xb4,0xca,0xa0,0xe7,0x57,0xd0, - 0x1f,0xbb,0xcc,0x6d,0xe3,0xc5,0xfd,0x7c,0x42,0xfa,0xc3,0x8a,0xfa,0x28,0x12,0x1f, - 0xdc,0x2f,0x9a,0xfb,0x63,0x3f,0x2e,0xe8,0xa3,0x3e,0x34,0xe9,0x8b,0x36,0x52,0xff, - 0x55,0xcd,0xea,0xe3,0x24,0x7d,0x54,0x6a,0xa5,0x85,0x9d,0x5f,0x73,0x78,0xbd,0xaa, - 0x9b,0xff,0x1a,0xa9,0x70,0x57,0xcb,0xa6,0xf2,0x7d,0x08,0x7f,0x18,0xc8,0x7f,0x9d, - 0x74,0x6c,0x91,0x3a,0xed,0x17,0xa5,0x7d,0x2d,0xf6,0x40,0x93,0xf1,0xcf,0xb8,0x50, - 0x9f,0x4b,0x27,0x35,0xe9,0x4e,0xb3,0x76,0x6d,0x09,0xc6,0xff,0x04,0xfc,0x01,0x86, - 0xdd,0xe8,0x55,0x98,0xda,0x40,0x32,0x18,0xff,0x29,0xb6,0x1e,0x0c,0x67,0xfd,0xb4, - 0x55,0x0c,0xcc,0x99,0xb0,0x81,0x62,0xe3,0x18,0x49,0xc4,0xe8,0x81,0xf8,0xf8,0xfc, - 0x01,0x9a,0x4c,0x8f,0xfd,0xcb,0x17,0xe5,0x0f,0xd0,0xd8,0x26,0xa5,0xd5,0x34,0xff, - 0xf7,0x4b,0xfe,0x00,0x0e,0xff,0x83,0x2d,0x1b,0xac,0x3e,0xce,0xc9,0x7f,0x59,0xde, - 0x31,0x6d,0xa2,0x7c,0x45,0xc0,0x1f,0xc9,0xeb,0x8e,0xf1,0x60,0x1b,0x5a,0x2f,0xc6, - 0xfd,0x01,0x1e,0x20,0xf5,0x71,0x5a,0xa3,0x55,0xee,0xa2,0x9d,0xf1,0xca,0x3f,0x8b, - 0xf6,0x47,0xe2,0xf9,0xaf,0x09,0x87,0x08,0x72,0x07,0x32,0xfe,0xf1,0xfb,0x03,0xb4, - 0x7b,0xcb,0xb2,0x0d,0x5d,0x9f,0xa7,0x43,0xfc,0x21,0xd5,0x3a,0xb3,0x28,0x7f,0xec, - 0x9a,0x8c,0x16,0x89,0x7f,0xfc,0xfe,0x00,0xac,0xcc,0x27,0x8d,0xfb,0x4d,0xc9,0xfe, - 0x00,0xe7,0xc9,0xb6,0xe0,0xa2,0x9d,0x4c,0x21,0xfc,0xe3,0xe6,0xbf,0xea,0x0a,0xe0, - 0x1f,0xb6,0xfe,0x49,0xfe,0xab,0x77,0x50,0xea,0x76,0x5a,0xd8,0x1f,0x20,0x69,0xa2, - 0x32,0xef,0x50,0x7f,0x80,0x42,0xd7,0xfb,0xeb,0xe3,0x8c,0x56,0xaf,0x3b,0x86,0xeb, - 0x17,0x54,0xc0,0x1f,0x80,0xc8,0xc2,0x57,0x47,0xcc,0xf7,0xac,0xec,0x0f,0xa0,0xb2, - 0x6e,0x20,0xcd,0xe8,0x7c,0x57,0xcb,0xfe,0x00,0x57,0xa0,0xf9,0x60,0x42,0xee,0xaf, - 0xaa,0xfb,0xfc,0x04,0x02,0xfe,0x48,0xbe,0xb2,0x38,0xab,0x80,0x3f,0x40,0x8b,0xe6, - 0xd2,0x3e,0x77,0x3b,0xd3,0x34,0x0a,0xf9,0x23,0x79,0xf1,0x5c,0x53,0xc8,0x1f,0xc9, - 0xed,0x8f,0x96,0xf6,0xee,0x7f,0x16,0x5a,0x1f,0xc7,0xf5,0xc9,0x0e,0xff,0xd3,0xe2, - 0xfd,0xb7,0x0d,0x8b,0x4f,0x35,0xe7,0x1f,0x52,0x2e,0xdf,0xe8,0x45,0x3b,0xc6,0x84, - 0xfa,0x21,0xf9,0x2f,0xc2,0xff,0x74,0xd6,0x71,0xb4,0x53,0xe2,0x0c,0x96,0xf9,0xfc, - 0x01,0xbc,0x0f,0xd5,0x87,0xf7,0x92,0x87,0xc2,0x94,0x1e,0x13,0x99,0x7f,0xe6,0xf8, - 0xc7,0xf0,0xfb,0x03,0xdc,0x40,0x07,0x1d,0x33,0xc2,0xf2,0x5f,0xcc,0x1f,0x40,0xa1, - 0xb0,0x67,0x9c,0xc2,0x9e,0x6b,0xd6,0xec,0xc2,0xf5,0x71,0x74,0xf7,0x78,0xd3,0xe1, - 0x43,0x2c,0xf2,0x97,0xd5,0xe1,0xf9,0x2f,0xd2,0x0d,0xe4,0xaa,0x69,0x0f,0x4e,0x27, - 0x5e,0x89,0xfb,0x3a,0xc6,0xda,0x83,0x51,0xbf,0x3f,0xd2,0x70,0x6a,0x53,0xfc,0x67, - 0x16,0x69,0x14,0xa2,0xb9,0xb4,0x4f,0x3e,0xd2,0x1f,0x89,0x97,0xc5,0x79,0x83,0x9c, - 0x78,0x3d,0xe7,0x7f,0xee,0x9b,0x4b,0x64,0xcf,0x14,0x46,0x4a,0x78,0x52,0xde,0x7f, - 0x02,0xfd,0xd1,0xbe,0xed,0x6e,0x9b,0xcd,0xd9,0xb4,0xc3,0xff,0xf8,0xf2,0x5f,0x01, - 0x7f,0xa4,0x3a,0x21,0xfb,0x23,0xef,0xb7,0x43,0x54,0x31,0x2e,0xf9,0x03,0x18,0x2b, - 0x37,0x39,0xb0,0x27,0xac,0xde,0x39,0x2f,0xfa,0x23,0xa9,0x34,0xbf,0x33,0x50,0x45, - 0xcf,0x5f,0xfc,0xfc,0x1a,0xf3,0xf3,0x3f,0x10,0x79,0xde,0x21,0xf5,0x71,0x4e,0x58, - 0x54,0x1e,0x16,0xa9,0x90,0x59,0xa8,0x8f,0xd3,0x6c,0xfc,0xa3,0x34,0xd2,0xb2,0x2c, - 0xeb,0x32,0xac,0x1c,0xad,0x7c,0x19,0xc3,0x7b,0xec,0xfd,0x5d,0xf0,0x07,0x98,0x20, - 0xfe,0xc6,0x47,0x2a,0x2f,0x54,0x4f,0x7b,0x07,0x59,0xb4,0x3f,0x00,0xf3,0x97,0x38, - 0x5b,0x18,0xff,0x70,0xb4,0xb3,0xae,0x68,0x7f,0xc8,0x88,0x41,0xb4,0x3f,0x52,0xa4, - 0x3f,0x00,0xea,0x8f,0xe4,0x1f,0xe4,0xc2,0xfc,0x91,0x42,0x06,0x85,0xfc,0x91,0x22, - 0xf1,0x4f,0x11,0xf7,0x5f,0xc8,0x1f,0xdb,0x3f,0x98,0x0c,0xf7,0xc7,0xa6,0xfd,0x52, - 0x23,0xfd,0x21,0x35,0x11,0xed,0x50,0x7f,0x6c,0x2b,0xc8,0xff,0x78,0xe1,0x94,0xfd, - 0x91,0x14,0x5a,0x0d,0x57,0xac,0x3f,0xa4,0x97,0xa8,0x45,0xde,0x5f,0x22,0xfd,0x91, - 0xa2,0xf0,0xcf,0x10,0xe2,0x8f,0x54,0xa4,0x3f,0x64,0xc4,0x40,0xc0,0x3f,0xff,0x8a, - 0xf5,0x87,0xfd,0x32,0xfc,0x91,0xe2,0xd4,0x48,0x70,0xd5,0x75,0xf9,0x23,0xd9,0x83, - 0x75,0x5f,0xae,0x3f,0x12,0x3e,0xe0,0xf8,0x67,0x9f,0xe8,0x8f,0xe4,0xb4,0x05,0xa9, - 0x2e,0x88,0x7f,0x0a,0xf1,0x1b,0x82,0x3f,0xd2,0x0e,0x99,0xff,0xc1,0xf1,0x12,0xda, - 0x1f,0xd6,0x45,0x3b,0xeb,0xa2,0xfd,0x21,0x61,0x46,0xc4,0x34,0x8b,0xf5,0xc7,0x2e, - 0xa2,0x3f,0x88,0xd0,0x0d,0x24,0x1a,0xff,0xc4,0x16,0x15,0x11,0x1f,0x09,0xff,0xa8, - 0x53,0x2a,0x8b,0x76,0xed,0x75,0xe8,0x7f,0x28,0xda,0x69,0x5f,0x87,0xfb,0x23,0x79, - 0x9f,0xd4,0xd6,0x62,0xf6,0x1f,0x8e,0x7f,0xfa,0x44,0xfc,0x73,0x17,0xc8,0x6d,0xe2, - 0x11,0xfc,0xb3,0x4b,0x63,0xfa,0x1f,0x8a,0x76,0x4e,0x55,0x16,0xed,0x0f,0x80,0xef, - 0xb7,0xcb,0x64,0xfc,0x23,0x9d,0x5f,0x97,0x7b,0x1b,0xf3,0xe9,0xa9,0xd8,0x81,0xc0, - 0xf9,0x25,0xe1,0x1f,0x93,0xdf,0x6d,0x26,0x3d,0xa1,0x4d,0x55,0x05,0x1c,0x9f,0x84, - 0xfe,0xb0,0xba,0xaf,0x3e,0x2e,0xa7,0x4d,0xce,0x0c,0xee,0x60,0x58,0x7f,0x58,0x96, - 0xef,0xa0,0xb6,0xd8,0x72,0xbd,0x21,0xc7,0x3f,0x9b,0x65,0xbe,0xeb,0x66,0x1b,0xff, - 0x2c,0xd9,0x1d,0xd8,0x48,0x8f,0x85,0xfb,0x63,0x6f,0x08,0x04,0x6a,0xbb,0xc8,0xff, - 0x64,0xfd,0xfe,0x48,0x05,0xf0,0xcf,0x56,0xd4,0x1f,0x3b,0x0a,0xff,0x14,0x71,0xde, - 0x55,0xf9,0xf5,0x3f,0x4e,0x7c,0xb4,0xbd,0x5a,0xfa,0x8d,0xb2,0xa5,0x1d,0x08,0x1e, - 0x60,0xeb,0xd3,0x12,0xeb,0xe3,0x2e,0x1b,0x4d,0x27,0xb7,0xbf,0xe4,0x18,0x25,0x15, - 0xc6,0x3f,0x74,0x30,0x61,0xe3,0x99,0xe9,0xcc,0x35,0xb7,0xd1,0x27,0x86,0x7f,0xa6, - 0x33,0xc7,0x8d,0x66,0x6e,0x8b,0x94,0x18,0xa7,0x42,0xe8,0xbd,0x63,0x21,0xfa,0x9f, - 0x1d,0xff,0x03,0x65,0xa3,0xb5,0xdc,0x16,0xbb,0x74,0x97,0x3d,0x78,0x45,0x4b,0x66, - 0x05,0xfc,0xd3,0xc2,0xf3,0x5f,0x47,0xa0,0x93,0xca,0x7e,0x5c,0x3c,0x6c,0xbf,0x98, - 0x93,0x46,0xa8,0xfb,0x0d,0xd9,0xb8,0x46,0xd0,0xff,0xa8,0x69,0xe2,0xa6,0x98,0xd7, - 0x06,0x3d,0x1a,0x2d,0x43,0x07,0xfd,0x21,0xf9,0xaf,0xbf,0x9a,0xf7,0x77,0xd6,0x51, - 0x73,0xc1,0x79,0x27,0xed,0xa2,0x34,0x65,0x13,0xa4,0x91,0xeb,0xe5,0x4c,0x58,0x7f, - 0x90,0x4c,0x6c,0x17,0x85,0xc1,0x1b,0xa6,0x68,0x34,0xea,0xb2,0x95,0x79,0x7b,0x70, - 0x65,0x97,0x4f,0x1f,0xc5,0xbe,0x7f,0x54,0x6f,0x87,0xc3,0xd0,0x70,0x3a,0xe1,0xc6, - 0x3f,0x5b,0x99,0xb1,0x5f,0x43,0x8e,0xa8,0x4d,0x59,0xd1,0x88,0x49,0xd0,0x3f,0xdb, - 0xfb,0x4f,0x4f,0xac,0x61,0xd4,0xc1,0xc3,0xa6,0x7d,0xb7,0xbb,0xed,0xc1,0x5b,0x39, - 0x39,0x91,0x27,0xf0,0x3f,0xb0,0x1e,0x3a,0xec,0x20,0xdc,0xed,0x44,0xe3,0xd6,0x6c, - 0x59,0xca,0x1e,0x74,0xf8,0x5e,0x1c,0xce,0xf3,0xfe,0xb0,0xfa,0x77,0xa1,0xa3,0xe3, - 0x85,0xb1,0xc7,0xd8,0xe9,0xbf,0x51,0xb9,0x0a,0x3f,0xf5,0x11,0x23,0x62,0xfe,0x6b, - 0x0d,0x95,0x3d,0x97,0x32,0xb4,0x63,0x6c,0x99,0x80,0x83,0x24,0xa3,0x2a,0xf1,0x3f, - 0x72,0xfe,0xeb,0xce,0x43,0x2e,0x3f,0xd6,0x44,0xe2,0x33,0x11,0xc0,0xcf,0x3c,0xff, - 0x45,0xf4,0x3f,0x97,0xa4,0x6e,0xb0,0x24,0xfe,0x97,0xc0,0xd7,0x1f,0x96,0xf9,0x3f, - 0x8c,0xcc,0x7f,0xd6,0xb1,0x05,0x68,0x75,0x77,0x8f,0x8a,0x36,0x3a,0xa8,0x96,0x88, - 0xf4,0xf3,0x8c,0x7f,0x36,0xcc,0x9f,0xe8,0x7b,0xac,0xdb,0xf2,0x8b,0xd9,0xec,0x1e, - 0xa0,0xc6,0x08,0xb2,0x51,0xb6,0xa8,0xff,0x79,0xdc,0x0e,0xda,0xce,0xbc,0xe6,0x95, - 0xe5,0x96,0x92,0xf5,0xf6,0x2b,0xab,0x5f,0x8a,0xa7,0xd8,0x1f,0x76,0x0a,0xae,0xc2, - 0x5d,0x99,0x9a,0x54,0x3c,0xe7,0xa0,0x9d,0x3c,0x6d,0x14,0x9b,0xb4,0x42,0xfa,0xc3, - 0xd2,0xfc,0xd7,0x8a,0x45,0x4f,0xb4,0xcb,0xc7,0x90,0xbf,0x3f,0x08,0x8b,0x8f,0xbe, - 0x33,0x79,0xd8,0x49,0x7b,0x2d,0x22,0x0b,0xc9,0x4c,0x3c,0x1b,0x77,0x14,0x2f,0x42, - 0xa2,0x64,0x96,0x98,0xff,0x5a,0x03,0xdd,0xab,0xd2,0x84,0x7f,0x58,0x04,0x6f,0xc0, - 0x52,0x8f,0x88,0x18,0x94,0x18,0x1e,0x8e,0x7f,0x48,0xfe,0xab,0xa7,0xb4,0xd6,0xb9, - 0x9e,0xf4,0xf3,0x72,0xf2,0x65,0x66,0xbf,0x89,0xf7,0x87,0x25,0xfa,0x9f,0x76,0xf8, - 0x9e,0x39,0x5f,0x2f,0x55,0xe1,0x49,0xb8,0xd5,0x74,0x88,0x20,0x33,0x13,0xd2,0x1f, - 0x76,0x73,0x79,0x9b,0x9a,0x53,0x9a,0x20,0x6d,0x29,0x86,0xe8,0xcf,0xfc,0x90,0x68, - 0x14,0xa0,0x08,0xf9,0xaf,0xd9,0x9f,0xc0,0x95,0x55,0x2b,0xbd,0xee,0x1e,0x2e,0x9e, - 0xf9,0xcc,0x8f,0x67,0x78,0xfe,0x6b,0xde,0x98,0x71,0x11,0xea,0xcd,0x84,0x4e,0xe3, - 0xb3,0xd4,0x09,0xcb,0x27,0x3e,0xa3,0x24,0xc9,0x1f,0x52,0x5f,0x6e,0x26,0xa1,0xcb, - 0x52,0xda,0x60,0x17,0x31,0x0a,0xc8,0x52,0xfe,0xc7,0x30,0x44,0x46,0xe8,0x18,0xdb, - 0x7f,0x48,0xfe,0xeb,0x97,0xd9,0x6a,0xf3,0xcf,0x5b,0x95,0x6f,0xc3,0x56,0xa8,0x31, - 0x4b,0x5a,0xc9,0x34,0x53,0x86,0x3d,0x71,0x03,0xd3,0xff,0xcc,0xdd,0x09,0xff,0xa1, - 0x3e,0xd7,0x52,0x32,0xaa,0xfc,0x13,0xfc,0x02,0xea,0xcc,0xd2,0x51,0x12,0x46,0xc3, - 0x20,0xf1,0xbc,0x8f,0xe3,0x49,0xef,0xfa,0x0c,0xc1,0x6f,0xab,0xea,0x5b,0x6b,0xf4, - 0x32,0xd5,0xbe,0xff,0x65,0xa6,0xe3,0x8f,0x64,0xca,0x8c,0x1f,0xe7,0xdb,0x73,0xb3, - 0x9f,0x37,0xcf,0x3d,0xdd,0xb4,0xb6,0xe2,0xc9,0x08,0x7d,0x94,0xd0,0x1f,0x56,0xd3, - 0x33,0xb1,0x29,0xe5,0x21,0x3d,0x61,0x95,0x19,0x30,0xa5,0x37,0xd9,0x07,0xe9,0x6a, - 0x43,0x9f,0x32,0x06,0xed,0x5f,0x24,0xce,0x52,0x63,0x62,0x7f,0xd8,0x5d,0xd4,0x56, - 0x45,0xcb,0xb4,0x10,0x20,0xb4,0xa8,0xa3,0x3c,0x13,0x7f,0x00,0x0e,0xac,0x4f,0x86, - 0xf5,0x87,0xfd,0x5f,0xf6,0xae,0x3e,0x36,0xae,0xea,0xca,0x9f,0x3b,0x73,0x9f,0xf3, - 0xec,0x8c,0x9d,0x37,0xf6,0x4c,0x18,0xc0,0x89,0x9e,0xed,0x10,0x4c,0x30,0x66,0x92, - 0x90,0x90,0x26,0x10,0x3f,0x8f,0x3f,0x70,0x42,0x80,0x69,0x3e,0xbd,0x95,0x57,0x7a, - 0x64,0xbd,0xbb,0x41,0x62,0x91,0x93,0x4a,0x4b,0x76,0xa9,0xda,0x3b,0x66,0x48,0x4d, - 0x48,0xc5,0x28,0x44,0x10,0xb4,0xd1,0xd6,0xd0,0xb4,0x65,0x51,0xda,0x0d,0x9f,0x81, - 0xa6,0x4b,0xc6,0x51,0x1c,0x4c,0x1b,0xba,0x11,0x9b,0x56,0xd1,0x2a,0x02,0x47,0xf2, - 0x4a,0xd9,0x12,0x08,0x6c,0x61,0x9b,0x90,0x26,0xd9,0x7b,0xdf,0xe7,0xbd,0xef,0x63, - 0x3c,0x66,0xcb,0x2e,0x95,0x98,0xbf,0x7e,0xba,0x73,0xfd,0x7c,0xdf,0x9d,0xfb,0xce, - 0xfd,0xbd,0xdf,0x39,0xf7,0x1c,0xbc,0x0a,0xb3,0x30,0x95,0x79,0x76,0xf5,0x0a,0x6a, - 0x9f,0x63,0xd4,0x70,0xa9,0x6e,0x62,0xf9,0x6b,0x05,0xff,0x57,0xb6,0x17,0x0e,0x68, - 0x4d,0x60,0xd4,0x4b,0x7d,0x95,0x3e,0xad,0x95,0x9b,0x22,0x7d,0xf0,0x2f,0xd0,0x70, - 0x5c,0x1e,0x00,0xf3,0xf9,0xbd,0xd3,0xe3,0xff,0x82,0x17,0xc9,0x33,0xe3,0xad,0x5b, - 0xa3,0x4c,0x08,0x9a,0x35,0x1e,0xeb,0x31,0xc0,0xfc,0xf1,0x16,0xcb,0x23,0x66,0xfa, - 0xbf,0xec,0xf1,0x57,0xb1,0xf3,0x08,0xa8,0x15,0xaa,0x59,0xf4,0xe0,0x67,0x8c,0xed, - 0x40,0xd4,0xa8,0x7f,0x71,0x5c,0xf0,0x7f,0xb9,0xf5,0x61,0xf3,0x6f,0xb0,0x30,0xce, - 0x89,0x7a,0xa6,0xff,0x5c,0x22,0x6d,0xfa,0xe3,0x67,0x0c,0x21,0x68,0xe1,0x40,0x8c, - 0xcf,0x0f,0xc9,0xf9,0xbf,0x76,0xb3,0x65,0x10,0x1b,0x62,0xd1,0x3b,0x2f,0x43,0x75, - 0x0f,0x0b,0xec,0x61,0xf5,0x3e,0x3a,0xe5,0x87,0x02,0xfd,0x5f,0x94,0xff,0xec,0xa5, - 0xdb,0xc4,0x0d,0x03,0x3b,0x59,0xb7,0x9b,0xb4,0x7f,0xe8,0x89,0x9c,0x52,0x0e,0x40, - 0x83,0x2e,0x73,0x89,0x6d,0x79,0xff,0xd7,0x76,0xca,0x51,0x5a,0xd4,0x4a,0x66,0x7f, - 0xf6,0xb3,0xd5,0x05,0x14,0xbc,0xa0,0x34,0x0a,0x89,0xc7,0x5d,0x7b,0xb5,0x2f,0xf9, - 0x21,0x79,0x9f,0x2c,0x3f,0x5f,0x3d,0x44,0x9f,0xa6,0xdf,0x31,0x6b,0x63,0xdc,0x66, - 0x96,0x25,0x4a,0x0a,0xf6,0x7f,0x0d,0xc1,0x45,0xb2,0x5c,0x36,0xca,0x52,0x53,0xeb, - 0x54,0x98,0xf1,0xb2,0x39,0x3f,0xda,0x0c,0x2b,0x5f,0xcd,0x88,0xc7,0xff,0xb5,0x0f, - 0xde,0x65,0xb2,0x52,0x11,0xfd,0x17,0xb9,0x02,0x0b,0x09,0x7d,0x30,0xa9,0x19,0x7f, - 0xb6,0xad,0x33,0xb8,0x3e,0xec,0x33,0x78,0x13,0x6c,0x87,0x16,0x90,0xf3,0xb5,0xa7, - 0xd5,0x9f,0xc1,0xe2,0xdd,0xd3,0x9f,0xa4,0xdb,0xd6,0x6b,0xe3,0xad,0x5a,0xf5,0x7e, - 0x08,0xf1,0x7f,0x3d,0x8d,0xe8,0xee,0xb6,0x8d,0x3e,0x7d,0xaf,0x43,0x23,0x58,0x89, - 0x02,0x5a,0xed,0xc0,0x21,0x8b,0xff,0xd8,0xeb,0x41,0x4e,0xc8,0xd4,0xfe,0xb4,0xc2, - 0x12,0xba,0xd5,0xb1,0xfa,0xb9,0xe0,0x14,0xa6,0xb9,0x2f,0xd8,0xff,0x55,0x7d,0xbf, - 0x7c,0x12,0xd1,0xdd,0x96,0xdd,0xef,0xeb,0x4c,0xf6,0x2c,0x18,0xf7,0x7b,0x7b,0xb1, - 0x66,0xff,0xc3,0xae,0x7f,0xc7,0xb1,0x3f,0xcf,0xc6,0xcf,0xc3,0x1f,0xe0,0x76,0x98, - 0x51,0xa4,0xa4,0xe5,0x0f,0xd0,0x06,0xc6,0xfd,0x3e,0x48,0x6f,0x93,0xbf,0xdf,0x33, - 0x73,0xfc,0xfa,0xcf,0x34,0x46,0x7b,0x8c,0x42,0xc3,0x1f,0xc2,0xfb,0xe5,0xe9,0x3f, - 0xaf,0xdb,0x85,0xd2,0x1e,0xdb,0x56,0x96,0xfe,0xf3,0x82,0x19,0x98,0x71,0xd6,0x97, - 0x1f,0xa9,0xa4,0xfe,0x53,0x71,0x56,0x29,0x27,0x3f,0x36,0xfd,0xf6,0x02,0x31,0x8f, - 0x1d,0x29,0x66,0xc4,0x0e,0x0a,0xe0,0x3f,0x82,0xfe,0x73,0xa9,0x30,0x15,0xfd,0x67, - 0x1f,0xab,0xe7,0xf8,0x85,0xea,0x3f,0x2f,0x80,0x75,0x70,0x69,0x52,0xff,0x97,0xa9, - 0x7e,0xbc,0x42,0xcc,0xfa,0x68,0xe4,0xc0,0x70,0x09,0xfd,0xc7,0xf5,0x76,0x7d,0x0c, - 0xb7,0x8d,0x98,0xfa,0xcf,0x70,0x19,0xfe,0x2f,0x3a,0x3f,0x8a,0x49,0x7b,0xb4,0x8b, - 0x4a,0x59,0xfa,0x4f,0xe8,0xfc,0x84,0xe8,0x3f,0xaf,0x4c,0xae,0xff,0x08,0xf9,0xb1, - 0x5f,0x99,0xa2,0xfe,0xf3,0x42,0x19,0xfa,0x8f,0x71,0xfe,0xab,0xf5,0xf3,0xe9,0x3f, - 0xaf,0x85,0xbd,0x8f,0x97,0xa8,0x8f,0x76,0xcf,0xa4,0xfa,0x0f,0x9e,0x5c,0x7f,0xf8, - 0xbf,0xd3,0x7f,0x4c,0xff,0x57,0xf0,0x31,0x37,0x17,0x84,0xd4,0x47,0xbb,0x34,0xb9, - 0xfe,0xe3,0x89,0xff,0x99,0x1d,0xdc,0x3f,0xa8,0x3e,0x48,0x80,0xec,0x33,0x49,0x7e, - 0xec,0x2f,0x5e,0xff,0x21,0xa1,0xfa,0x8f,0xa3,0x3f,0x08,0xe7,0xbf,0xb4,0x50,0xfd, - 0xc7,0xbe,0xbe,0x90,0x1f,0x9b,0x45,0x5b,0x3d,0xce,0x02,0xd1,0xa7,0x90,0x1f,0xfb, - 0xce,0xe1,0x6b,0xfc,0x19,0xb3,0x03,0xf3,0x63,0x3b,0x4f,0x47,0xcc,0xd7,0x52,0x2a, - 0x3f,0xf6,0xf9,0x88,0x4f,0x3f,0x09,0xcb,0x8f,0x6d,0x80,0xf3,0x51,0x6f,0x4b,0x78, - 0x7e,0x6c,0x14,0x62,0x4f,0x42,0xf2,0x63,0x5f,0x2c,0x2c,0x30,0x0b,0xa5,0x1d,0xf2, - 0xc5,0xff,0x78,0xfc,0x5f,0xe6,0x68,0x7f,0x3f,0xdc,0x70,0x76,0xfa,0x12,0xd3,0x8c, - 0x14,0x4b,0xfa,0xbf,0xcc,0x6f,0x59,0x19,0x38,0xca,0xee,0xfc,0xf9,0xc0,0xc3,0xf2, - 0x63,0x13,0xeb,0x3c,0x8b,0x2f,0x3f,0xb6,0xbf,0x3e,0x2c,0xbb,0xbb,0x83,0xb2,0xfd, - 0xda,0x1e,0xb1,0x76,0x34,0x3f,0xff,0x09,0xac,0x8f,0x16,0x1e,0xff,0xe3,0xcd,0x8f, - 0x6d,0xc7,0x73,0x1a,0x69,0x91,0x1c,0x53,0x3f,0x59,0x7d,0xb4,0x29,0xe4,0xc7,0xb6, - 0xc0,0x5c,0xb7,0xe5,0xda,0x90,0xfa,0x20,0x56,0x18,0xcc,0x2d,0x99,0xb7,0xd5,0x83, - 0x29,0xd3,0xdf,0x8a,0x4a,0xe7,0x47,0xba,0x28,0x2f,0x1f,0x9b,0xf1,0x6a,0xf4,0x1c, - 0xb9,0xa8,0x8a,0xf1,0xf0,0x21,0xf9,0xb1,0x7f,0xcf,0xea,0x5b,0xfd,0xdc,0x10,0x2e, - 0xc2,0xeb,0xa3,0xd1,0xc6,0xe2,0xc2,0x63,0xb1,0xe3,0x7c,0xd8,0xcf,0xa7,0x85,0xa6, - 0x23,0xb1,0x10,0xfe,0x73,0x8e,0xcd,0xc6,0x0e,0x79,0x37,0xef,0xf6,0x7a,0x0d,0x9a, - 0x4e,0x54,0x85,0xf0,0x9f,0xb7,0xe9,0x6d,0x3e,0x37,0x46,0x5f,0x33,0x8f,0xc1,0x42, - 0xfb,0xc6,0xe9,0x15,0x84,0xc2,0x28,0x02,0xff,0x51,0x58,0xbd,0x5d,0xfa,0xb6,0x25, - 0xcc,0xe7,0xb3,0x42,0x3c,0x15,0xcf,0x7f,0x58,0xb6,0xa8,0xa5,0xc5,0x96,0xd7,0x85, - 0x65,0xa0,0x2f,0x10,0x02,0x51,0xbc,0xfc,0x67,0x91,0x27,0x2c,0xea,0x72,0x61,0x79, - 0x7f,0x18,0xff,0xd9,0xcb,0x2e,0xa2,0x79,0xc2,0x5a,0xb4,0x05,0x02,0x3f,0x17,0xf8, - 0x0f,0x39,0x98,0xad,0xd1,0x9e,0x13,0xc2,0x96,0x5e,0x82,0xc6,0x6f,0x05,0xeb,0x3f, - 0x94,0xff,0xe0,0x83,0x24,0xe6,0x71,0x13,0xbf,0x08,0xe2,0xfb,0x82,0x8f,0xff,0xec, - 0x15,0xc3,0x60,0x7e,0x4e,0xe8,0xfb,0x48,0x38,0xff,0x91,0x97,0x7b,0xc3,0x9e,0x71, - 0x5a,0x6b,0x99,0x9c,0xff,0x18,0xc0,0x3c,0x8f,0xf9,0x46,0x7f,0x18,0xff,0xa1,0xf3, - 0x4f,0x96,0x16,0x2b,0x58,0x59,0x10,0x27,0x8d,0xdb,0x67,0xb0,0xe0,0x24,0x3f,0x63, - 0x22,0xff,0x39,0x64,0xa6,0xa5,0xe5,0x02,0x29,0x5f,0x05,0xf5,0x88,0x1c,0xc2,0x7f, - 0x9e,0xa4,0x37,0xd5,0xac,0x57,0x2d,0x89,0xcc,0xb6,0x8f,0x7d,0xbd,0x0b,0x87,0x86, - 0x44,0xfd,0xc7,0xcb,0x7f,0xd4,0x4e,0x79,0x49,0xc6,0x32,0xec,0xfb,0xd9,0x63,0x45, - 0x1a,0x27,0xe4,0x10,0xfe,0xb3,0x9d,0x8e,0x76,0xd9,0x70,0xcd,0xb3,0xd1,0x66,0xf8, - 0xad,0x4d,0x7b,0x2e,0xc3,0x02,0x8f,0xfe,0x63,0x8f,0x87,0xf2,0x1f,0xed,0xbc,0xe6, - 0xa7,0x01,0x6f,0x08,0x11,0x41,0x22,0xff,0x79,0xcb,0x13,0xf6,0xcc,0x3c,0x20,0x62, - 0xa2,0x6c,0x81,0xff,0xc8,0x8f,0x6e,0x6c,0xe5,0xd5,0x9b,0x68,0x3f,0xdd,0xa6,0x1b, - 0xb3,0xcd,0xa1,0xfc,0xe7,0xd1,0x48,0x8b,0xa0,0xf6,0x18,0x11,0x41,0x59,0x39,0x94, - 0xff,0xe4,0xb4,0x16,0x27,0xfe,0x87,0x7e,0x0b,0x9d,0xf0,0x35,0x4d,0x4c,0x14,0x29, - 0xf2,0x9f,0x31,0x4a,0x2a,0x5a,0x38,0xb7,0x17,0xdb,0x7f,0x5f,0x14,0x12,0x45,0xf2, - 0xfc,0xe7,0xd3,0xc8,0x05,0x68,0xcb,0xce,0x38,0xc1,0x6f,0xeb,0x9f,0x42,0x5b,0x36, - 0x8c,0xff,0x7c,0x02,0x6f,0x6b,0x6d,0xbd,0x9e,0xb0,0x61,0xed,0xf6,0xad,0x31,0x2e, - 0x51,0x00,0xcf,0x7f,0x4e,0xd3,0x3d,0xa0,0x15,0x9a,0x05,0xda,0xf3,0x33,0xd2,0xaa, - 0x36,0x87,0xf0,0x9f,0xb7,0x21,0xa7,0xb6,0x9c,0x94,0x13,0x9e,0xb4,0x90,0xd9,0x79, - 0xa1,0xfc,0xe7,0x51,0x68,0xed,0xf1,0xc7,0x53,0x55,0x85,0xf1,0x1f,0x56,0x0d,0x64, - 0x93,0x30,0x7e,0x74,0x21,0xbb,0x5c,0x6b,0x0d,0xe1,0x3f,0x79,0xf9,0x42,0xc4,0x17, - 0xf6,0x43,0x6e,0xd3,0xaa,0x4b,0xf0,0x9f,0x34,0x54,0x93,0x69,0xc2,0x7a,0x5b,0x20, - 0xc7,0x42,0xf9,0xcf,0x1b,0xea,0x0f,0x0a,0xde,0xb0,0xe7,0xb6,0xfd,0x30,0x9c,0x09, - 0xe5,0x3f,0xea,0x49,0xef,0x31,0x01,0x95,0x6e,0xa1,0xc1,0xfc,0x27,0x41,0x1f,0x3a, - 0x6f,0x5a,0xd7,0x43,0xe4,0xa6,0x8c,0x1c,0xca,0x7f,0xfe,0x9b,0xa4,0xc7,0xab,0xad, - 0xf8,0x9f,0x71,0x2b,0xfe,0xc7,0xd0,0x7f,0x02,0xf9,0xcf,0xde,0x80,0x6d,0xfd,0x0a, - 0x59,0xac,0x85,0xf3,0x9f,0xb7,0xc9,0x32,0x9d,0xee,0x56,0x82,0xdb,0x6b,0xa1,0x79, - 0x90,0xe7,0x5c,0x10,0xff,0xf9,0x2e,0x34,0x68,0xf2,0x00,0x4f,0xdb,0x0e,0xe1,0x06, - 0x21,0x10,0x51,0xe4,0x3f,0x79,0xb8,0x41,0x93,0x3d,0x65,0x8c,0xf6,0x0a,0x33,0x20, - 0xf2,0x9f,0x87,0x59,0x9a,0x5f,0x91,0x46,0x2a,0x73,0xb5,0xe6,0x10,0xfe,0xf3,0x53, - 0xf8,0x25,0x2c,0x65,0x61,0xbd,0x1c,0x11,0xba,0x02,0x8b,0x8b,0x2d,0x4c,0x01,0x7b, - 0x3f,0x80,0xff,0x68,0x17,0x1d,0x99,0xc8,0x75,0x0c,0x2d,0xcd,0x72,0x2d,0x4d,0x3c, - 0xff,0x39,0x4b,0xad,0xd9,0xed,0xc3,0x31,0xfb,0x18,0x94,0x2d,0x83,0x4c,0xf0,0x89, - 0x22,0x7d,0xfc,0x87,0xf8,0xe2,0x79,0x36,0xc9,0x21,0xfc,0xa7,0x95,0x3d,0x14,0x47, - 0x7c,0xfd,0x85,0x08,0x58,0x1f,0xff,0xe1,0xcb,0x56,0x02,0x05,0x91,0x58,0xf1,0x39, - 0x9e,0x0f,0xc4,0x9d,0xe9,0xa7,0xfc,0xe7,0x23,0xfe,0x58,0x93,0x9d,0x56,0x45,0x28, - 0x54,0xea,0xf2,0x9f,0xbd,0xb3,0xfc,0x6a,0x46,0xc0,0xf9,0xf7,0xb0,0xf8,0x9f,0x85, - 0xe3,0xd3,0x4b,0xd7,0x07,0x29,0x8a,0xf1,0x3f,0xf3,0x04,0xd9,0xc7,0xe5,0x3f,0xee, - 0xf9,0x2f,0xe9,0x98,0xfc,0x92,0x4b,0x7b,0xc4,0xb0,0xba,0xc9,0xf5,0x9f,0x79,0x21, - 0xf1,0x3f,0x8e,0x7d,0xf0,0xd4,0x47,0x5b,0x50,0x0c,0xe4,0xc3,0x61,0xe7,0xbf,0x42, - 0xf3,0xff,0x7c,0xee,0xf8,0x1f,0xf1,0xfc,0xd7,0xe4,0xfa,0xcf,0x19,0xfe,0xfd,0x8b, - 0x7b,0x4d,0x88,0x59,0x1e,0x52,0xb3,0xe5,0x63,0xd7,0xff,0x15,0x14,0xff,0xe3,0x8f, - 0x7f,0xe6,0xfc,0x5f,0x31,0xcd,0x1b,0xed,0x13,0x90,0xff,0xc7,0xf5,0x7f,0x59,0xfc, - 0x67,0x7a,0xc9,0xf5,0xe3,0xfa,0xbf,0x04,0xfd,0x27,0xb4,0x5e,0xcf,0xe1,0xd2,0xf1, - 0x3f,0xb2,0xe5,0x76,0x0f,0x38,0xff,0x45,0x78,0xfd,0xe7,0xc7,0x61,0xf7,0x1b,0x58, - 0x1f,0xa4,0x04,0xe0,0xfc,0x5f,0x71,0x2e,0xfe,0xe7,0xb7,0x61,0x42,0x10,0xe7,0xff, - 0x2a,0x33,0xfe,0xc7,0x1e,0xbf,0xa9,0xff,0x2c,0xb5,0xdf,0xee,0x97,0x06,0xbf,0xef, - 0xfb,0xcf,0x7f,0xd5,0x4c,0x49,0xff,0x99,0x17,0xbc,0x4d,0x4f,0x58,0xa5,0xbe,0x2a, - 0x7e,0xe5,0xd3,0x7f,0xaa,0x78,0x19,0xc4,0x97,0x2f,0xda,0xf5,0x7f,0x99,0xfa,0xcf, - 0x52,0xf7,0xee,0x6a,0xca,0xd3,0x7f,0x82,0x8e,0x7d,0x05,0xfa,0xbf,0xa4,0x12,0xdd, - 0xa6,0xae,0xff,0x9c,0x31,0xc0,0x46,0xce,0xff,0x55,0x8e,0xfe,0xb3,0x91,0xcb,0x8f, - 0x5d,0x9e,0xfe,0xe3,0xfa,0xbf,0xca,0x8c,0xff,0xb1,0xc7,0x3f,0x49,0xfe,0x9f,0xff, - 0xf4,0xfa,0xbf,0x9a,0x3d,0xf9,0xb1,0xa1,0x2a,0xf0,0xfc,0x57,0xb8,0xfe,0xe3,0x07, - 0x8f,0x95,0xd4,0x7f,0x02,0xcf,0xe3,0x94,0xac,0x8f,0x66,0x80,0xbf,0x11,0x5a,0x5c, - 0xff,0x97,0x4f,0xff,0xa9,0xd9,0xda,0xe4,0x12,0xa1,0x4a,0xc7,0xff,0x65,0xaf,0x37, - 0x5e,0xff,0xc1,0x66,0x34,0x4b,0x5d,0x80,0x3d,0xe1,0xe2,0x3f,0xf9,0xdd,0xaa,0xd0, - 0x36,0x5e,0x75,0x21,0x7a,0x59,0x3b,0x47,0x96,0x85,0x9d,0xff,0xba,0x7a,0x8f,0x11, - 0xb6,0x64,0x8d,0xf6,0xe6,0x33,0x55,0xac,0x50,0xd1,0xe3,0x9e,0x42,0x45,0xa2,0xff, - 0xcb,0xbd,0x4d,0x74,0xf3,0xd8,0x10,0xed,0x2f,0xff,0x73,0x89,0xf3,0x5f,0xe2,0xec, - 0x8d,0x5c,0xc3,0xc0,0xc3,0x30,0x47,0xd4,0x7f,0xdc,0xf1,0xf0,0xe7,0x67,0xd9,0x41, - 0x66,0x39,0xc8,0x90,0x86,0xe9,0x3f,0xae,0x3e,0xb6,0x34,0x4c,0xff,0x81,0x60,0x33, - 0x7e,0xb3,0xd0,0xe2,0xfa,0xbf,0x48,0x59,0xf1,0x3f,0x21,0xe7,0xbf,0xb8,0x63,0x5f, - 0x0f,0x88,0x7a,0x51,0x88,0xfe,0x83,0x9c,0xb0,0xe7,0xfb,0x8d,0x16,0xcc,0xbe,0x8a, - 0xa6,0x41,0xf0,0x7f,0x09,0xbf,0xfe,0x58,0x4d,0xd0,0xfe,0xc2,0xe9,0x3f,0xd5,0xc2, - 0x6d,0x2e,0x3f,0x12,0xbc,0xbf,0xbb,0xe7,0xbf,0x90,0x9f,0xed,0x98,0x8e,0xb0,0xe0, - 0xf3,0xef,0xbe,0xf8,0x67,0xc1,0x11,0x36,0xd5,0xf8,0x67,0x1c,0xa2,0xff,0x84,0x84, - 0x51,0x95,0x1d,0xff,0xec,0x75,0xc4,0x78,0xcf,0x7f,0x99,0xf5,0x2f,0xfc,0x0b,0x03, - 0x59,0x0a,0x61,0x89,0xf8,0xe7,0x1a,0xee,0xfa,0x2d,0xb2,0x8f,0xff,0x78,0xfc,0x5f, - 0xcb,0xf9,0xf1,0xd7,0xdd,0xef,0xe7,0x3f,0xbe,0xf8,0xe7,0x2a,0xce,0x71,0xe3,0x2c, - 0x15,0x9f,0xfe,0x73,0xfa,0x5a,0x73,0xf7,0xbf,0x81,0x73,0x0c,0x9d,0x77,0xf3,0xe1, - 0x84,0xf8,0xbf,0x7e,0x47,0xaf,0xe6,0xe6,0x3f,0xdc,0x1f,0x8d,0x95,0xab,0xff,0x88, - 0x20,0xd8,0xff,0xd5,0x51,0x62,0xfe,0x3f,0x7f,0xfc,0x73,0x50,0x7d,0x58,0xbf,0x23, - 0x2c,0xc8,0xff,0x95,0x09,0x58,0x6f,0x76,0xe2,0x85,0xd2,0xf5,0x61,0x29,0x18,0xfa, - 0x42,0xe2,0x9f,0xcb,0x38,0xff,0x35,0xec,0x8d,0x7f,0x9e,0x84,0xff,0x78,0xea,0x83, - 0xfc,0xd1,0xfd,0x5f,0x29,0x5f,0x7d,0xd8,0x32,0xce,0x7f,0xf9,0x6e,0xd3,0xeb,0x08, - 0x0b,0xaf,0x0f,0x6b,0x82,0x8f,0xf9,0x96,0x69,0x7c,0xfc,0x73,0xea,0xcb,0xe6,0xff, - 0x32,0xea,0xa9,0xf9,0x7e,0x56,0xe2,0xe5,0x3f,0xf6,0xfa,0x1c,0x02,0x9b,0xff,0x08, - 0x65,0x41,0x86,0x4b,0xf9,0xbf,0xce,0x04,0x4c,0xbb,0x70,0xfe,0xab,0xc3,0x73,0xfe, - 0x2b,0x80,0xf6,0x38,0x89,0x80,0x1e,0x30,0xf4,0x1f,0x64,0xaf,0x87,0x30,0xfe,0x63, - 0x3a,0x6e,0xb0,0x19,0xa8,0x50,0x51,0xe2,0xfc,0x97,0xa5,0xff,0x08,0xfc,0xa1,0x36, - 0xe8,0xfc,0x97,0x18,0xf6,0x3c,0xdf,0x06,0x37,0x4d,0x25,0xfe,0xd9,0x2e,0x8c,0x15, - 0x98,0xff,0x30,0x18,0xdc,0x3c,0x31,0xe3,0x82,0xff,0xfc,0x97,0x3d,0xda,0xdb,0xb9, - 0x61,0xff,0x7d,0xe3,0x64,0xfe,0x2f,0x11,0xd8,0xf9,0x7f,0xee,0x1c,0xa8,0x2d,0x11, - 0xff,0xcc,0xf4,0x67,0x78,0x89,0x88,0x86,0xc8,0x77,0xfe,0x6b,0x92,0xf7,0x6b,0xff, - 0xf9,0x2f,0x0f,0xed,0x51,0xc4,0xfe,0xff,0xe1,0xf1,0x7f,0x89,0xd1,0xbf,0xb7,0xf9, - 0xe3,0x9f,0xfb,0x4b,0xf8,0xbf,0xa2,0x7e,0x46,0xc4,0xeb,0x3f,0xfe,0x6f,0xfd,0x0a, - 0x40,0x70,0xfc,0xb3,0x3d,0x3f,0xd6,0x0a,0xe4,0xf3,0xff,0x38,0xb3,0x0f,0x95,0xf7, - 0xfb,0xa2,0xc1,0x5b,0x4c,0xc0,0xd5,0x87,0xf5,0xc4,0x3f,0x07,0xcb,0x1a,0xee,0xfe, - 0x55,0xe7,0xea,0x3f,0x23,0x93,0xac,0x9f,0x41,0xaf,0xfe,0x03,0x3f,0xb5,0x49,0xce, - 0x03,0x01,0x44,0xc8,0xc7,0x7f,0xc6,0x84,0x7c,0x08,0x38,0x84,0x08,0xb9,0xf6,0x67, - 0x3c,0xb1,0x2f,0x31,0x95,0xf3,0x5f,0x12,0x2e,0x67,0xfd,0xb8,0xfa,0xcf,0x33,0x6e, - 0xfe,0xe7,0x6f,0xf9,0xf9,0x0f,0x4b,0x84,0x38,0xf2,0xf8,0x47,0x7f,0xe1,0xf2,0x9f, - 0x71,0xd8,0x87,0x4d,0x6f,0x6c,0x99,0xfa,0x0f,0x76,0x7f,0x7d,0xb9,0x9c,0xf3,0xef, - 0xbe,0xf5,0x10,0x04,0x5c,0xfe,0x73,0x1c,0x78,0xfd,0xc7,0x0a,0xfb,0x21,0x4e,0x05, - 0x31,0x3f,0xff,0x49,0xf1,0xfc,0x87,0xdc,0x76,0x96,0x82,0x5f,0x11,0x96,0x08,0x28, - 0x24,0xfe,0xa7,0x7e,0x1f,0x3c,0x14,0x74,0x9b,0x47,0x84,0xf9,0x74,0xec,0x4f,0x73, - 0x59,0xf3,0xcf,0xf1,0x1f,0x65,0x6a,0xfc,0xc7,0x97,0xff,0x67,0xd2,0xf8,0x9f,0x1d, - 0x65,0xcc,0xe7,0x3b,0xdc,0xfa,0x7c,0x0e,0x7f,0x86,0x96,0xe7,0xca,0x8f,0xff,0x09, - 0xc8,0xff,0x23,0x97,0xe0,0x3f,0x10,0xf8,0xbe,0x8f,0xc2,0xe3,0x7f,0xca,0xe1,0x33, - 0x9c,0xfe,0xe3,0xed,0xff,0x98,0x01,0x22,0xa1,0xf9,0x9f,0x95,0x52,0xfc,0x07,0xfb, - 0xf8,0x4f,0xaf,0x5c,0x0e,0xff,0xe1,0xf4,0x9f,0x64,0x20,0xcd,0xab,0x08,0xe5,0x3f, - 0xd5,0x9e,0xfe,0xa6,0x1b,0x08,0x3b,0x2d,0xad,0xa2,0xfe,0x63,0xe5,0x3f,0x14,0x69, - 0x8f,0x1c,0xce,0x7f,0x74,0xc8,0x4f,0x89,0xff,0xbc,0x86,0x83,0xf9,0x4f,0x4d,0x08, - 0xff,0x11,0xea,0xc3,0xba,0x20,0x12,0xa6,0xff,0x8c,0xc1,0x5e,0xec,0xeb,0xaf,0x78, - 0x81,0xcb,0x7f,0xe4,0xa0,0xf5,0x56,0xaa,0x3e,0x6c,0x62,0x52,0xfd,0x47,0xf0,0x7f, - 0xf9,0xf7,0xa3,0xd2,0xfa,0x0f,0x02,0x9e,0xff,0x44,0x42,0x9e,0x5f,0xd7,0xff,0x25, - 0x93,0x60,0xfe,0x23,0x80,0x0e,0xd7,0xff,0xc5,0xe5,0x43,0x0e,0xb7,0x27,0x0b,0x39, - 0xfe,0x13,0x7b,0x43,0xe3,0xf4,0x9f,0x65,0xa7,0xcd,0x40,0xa0,0xd0,0xf8,0x9f,0xe7, - 0x61,0x8f,0x9b,0x6d,0xec,0x20,0x51,0x59,0x3c,0x0f,0xbd,0xcd,0x61,0x7e,0xfc,0x9b, - 0x39,0xfe,0x33,0x0c,0x4e,0x7d,0x58,0x4a,0xf3,0x54,0x3b,0xdf,0xa3,0x1a,0xa6,0xff, - 0x68,0x62,0xfe,0x1f,0x27,0x9f,0x36,0x37,0x9f,0x8f,0xf1,0xfe,0x2f,0x59,0xb0,0x9f, - 0x88,0xf1,0x99,0x88,0x78,0xbf,0x23,0x1e,0xfd,0xc7,0xed,0x6f,0xb1,0xc1,0xa6,0x92, - 0xf1,0x3f,0x7c,0xbd,0x03,0xe3,0x3c,0xaf,0x08,0xbc,0xfe,0xaf,0x91,0x84,0xc8,0x5e, - 0x46,0x78,0xd9,0xe1,0xac,0x52,0x9a,0xff,0x2c,0xf3,0x6e,0x7c,0xb2,0x5f,0xff,0x01, - 0x7e,0xbd,0xa9,0x3e,0x10,0xf1,0xc4,0xff,0x44,0x80,0xd7,0x7f,0x8a,0x46,0x18,0xfc, - 0x07,0xda,0xc5,0xe3,0xac,0xc5,0x8d,0xef,0x75,0xf5,0x9f,0x41,0x3e,0xff,0xcf,0xc5, - 0x25,0x6d,0xbf,0xa0,0xe0,0x72,0xfe,0xca,0xae,0x50,0xff,0x97,0xa5,0x1f,0xfe,0xeb, - 0xf9,0x8e,0x00,0xfe,0xa3,0xf8,0xe3,0x7f,0x52,0x1f,0x2a,0xd6,0x21,0x2f,0x1b,0x04, - 0xf0,0x9f,0xf3,0x62,0x7d,0x58,0xa9,0x79,0xe4,0x4e,0x3b,0xcc,0xdb,0xb3,0x1e,0x4c, - 0x46,0xc4,0x9d,0xff,0x92,0xf6,0x29,0x07,0x31,0x9b,0xf6,0xb9,0x25,0xf8,0xcf,0x79, - 0x6e,0x7f,0xdc,0x67,0xc8,0x80,0xf7,0xec,0xaf,0x33,0xf5,0x52,0x6e,0x19,0xd4,0x39, - 0x89,0x80,0x46,0x9c,0xf1,0x9f,0x2e,0x84,0x9f,0x7f,0xcf,0x70,0xfa,0x98,0x7d,0x7d, - 0x53,0xff,0x31,0x69,0xb6,0x9b,0x56,0xe8,0x60,0x28,0xff,0xf9,0x05,0x66,0xf9,0x7f, - 0x96,0x16,0x8d,0xb4,0xe1,0x9e,0x61,0x67,0xce,0x62,0x5f,0xfe,0xc3,0x71,0x64,0xbf, - 0x7f,0xad,0xf6,0x97,0x65,0x74,0xc0,0x47,0xce,0xdd,0xea,0x68,0x76,0xdc,0xda,0xf4, - 0xff,0x11,0x85,0xf2,0x01,0xbe,0x3e,0xac,0xc5,0x7f,0xe6,0x77,0xb8,0x6e,0x2f,0x9f, - 0x47,0x8c,0xab,0x0f,0xcb,0xf4,0x1f,0xf4,0x50,0x91,0x4f,0xfb,0x73,0xd6,0x97,0x1f, - 0xdb,0xad,0x0f,0x6b,0xe8,0x3f,0x78,0x32,0xfe,0x13,0xec,0xff,0x52,0xc2,0xf9,0x8f, - 0xab,0xbf,0x59,0xfc,0xe7,0xce,0xad,0x99,0x12,0xfc,0xa7,0xe8,0xd3,0x7f,0xae,0x2d, - 0xa9,0xff,0xf8,0xeb,0x5f,0x4c,0xc2,0x7f,0x82,0xea,0x5f,0x94,0xd2,0x7f,0xb8,0xfc, - 0xcf,0xe5,0xe9,0x3f,0x76,0x7f,0xdf,0xf9,0xf7,0x49,0xf2,0x3f,0xfb,0xf8,0xcf,0x1f, - 0x43,0xff,0x69,0xe4,0xce,0xbf,0xcb,0xfe,0x68,0xdb,0x92,0xf5,0x61,0xcb,0x3a,0xff, - 0xee,0xe6,0x7f,0x0e,0xe6,0x4b,0x6f,0x19,0x81,0xe2,0x1d,0x6e,0x7f,0xd7,0xff,0x15, - 0xc4,0x7f,0x8c,0x83,0x60,0xc1,0xf9,0x9f,0x21,0xe9,0xbf,0xcd,0x09,0x76,0x22,0x55, - 0x68,0xe1,0xfc,0x5f,0xc8,0xe5,0x3f,0x6e,0x20,0xfa,0x3f,0x85,0xe7,0x3f,0xcc,0x07, - 0xf1,0x1f,0x6f,0xa2,0x6f,0xb7,0x5e,0xe7,0xf3,0xc1,0xfa,0x8f,0x87,0x2f,0xb9,0xf9, - 0x9f,0xe7,0xf1,0xfc,0x87,0x1d,0xc4,0x9b,0xec,0xfc,0x3b,0xaf,0xff,0xfc,0x7b,0x18, - 0xff,0x71,0xdf,0xaf,0x9b,0x93,0x9c,0xfe,0x63,0x95,0x89,0xf1,0x9f,0xbf,0xe0,0xea, - 0x5f,0xb8,0xfa,0xcf,0x65,0x78,0x2a,0xe4,0xf9,0x6d,0xe4,0xf4,0x1f,0x98,0x6d,0x1f, - 0x7b,0xbf,0x0c,0x6f,0x86,0x11,0x21,0xae,0xfe,0x85,0xa8,0x87,0x78,0xf2,0x69,0xd8, - 0x16,0x78,0x0a,0xfa,0x8f,0x01,0xb8,0xfa,0xb0,0xc8,0xcc,0xff,0xe3,0x8c,0x76,0x86, - 0x0d,0x2a,0xdd,0xf1,0x47,0x9f,0x77,0xd6,0xc3,0xce,0xb2,0xde,0xd7,0x3c,0xf5,0x2f, - 0x22,0xd6,0xec,0x3d,0xc1,0x4f,0x23,0x1f,0x61,0x55,0x70,0xea,0x5f,0xa8,0x1e,0xfd, - 0x67,0x24,0xd0,0x7e,0xba,0xfa,0x4f,0xde,0x1b,0xff,0xec,0xf8,0x83,0xa6,0x0b,0x7f, - 0x68,0x5f,0x3f,0x67,0xc5,0x3f,0x3f,0x1e,0xb0,0xdf,0x35,0x05,0x9c,0x7f,0x1f,0x61, - 0xfa,0x0f,0xe2,0xb6,0xad,0x1a,0xcf,0xfe,0x6b,0x64,0x04,0x3a,0xdd,0x6e,0xff,0x5e, - 0x04,0xfb,0xd5,0x1e,0x07,0xec,0xf3,0xeb,0x3f,0x31,0x81,0xff,0xe0,0x20,0x7f,0xeb, - 0xb5,0xc2,0xf9,0x77,0xb8,0x5f,0x3e,0x68,0xb8,0x41,0x03,0xa6,0x65,0x9f,0xbd,0x11, - 0xbb,0xf5,0x61,0xf7,0x32,0xfe,0x83,0x66,0x4c,0x16,0xff,0xd3,0x3d,0xe0,0xfc,0x07, - 0xa1,0xfa,0xde,0xb1,0xe6,0x85,0x55,0x5f,0xa6,0x7a,0x88,0xc7,0xa6,0x50,0x0f,0x51, - 0xb6,0x40,0x6c,0xec,0xab,0x7a,0x88,0x9f,0x7f,0xfe,0x43,0xea,0x21,0x82,0xdb,0xa2, - 0x4d,0xa9,0x1e,0xe2,0xb1,0xa9,0xd5,0x43,0xcc,0x4d,0x71,0xfe,0x1b,0xbe,0xaa,0x87, - 0x38,0xc5,0xcf,0x97,0xab,0xfe,0xe0,0x97,0xaf,0xff,0x97,0xec,0x79,0x9c,0xf2,0xf5, - 0x65,0x12,0x51,0x8f,0x0d,0x41,0xa3,0x01,0xc0,0xa8,0x3b,0xe4,0x82,0x3f,0x61,0x7b, - 0xf8,0xcd,0xff,0x47,0x7b,0xc8,0xac,0x5f,0x90,0x61,0x34,0x76,0xa8,0xaf,0xea,0xc3, - 0x4e,0xfa,0xf9,0xca,0x1e,0xfe,0xc9,0xf6,0x1f,0x6d,0x8f,0x0e,0x68,0xa7,0x94,0x5b, - 0x41,0x1a,0x31,0x01,0x96,0xbe,0x1b,0xdd,0xac,0xf5,0x29,0x57,0x25,0xaa,0x47,0xa7, - 0x51,0x90,0xbd,0x0a,0x57,0x17,0xe7,0x3b,0xfd,0xbb,0x3a,0xa5,0xcd,0xa8,0x4f,0xdb, - 0x40,0x17,0xbb,0x01,0xd6,0x29,0x89,0x23,0x66,0x4b,0x2a,0x79,0x14,0x99,0x5f,0x25, - 0x8b,0xf3,0x6d,0x3e,0x4c,0x6d,0x13,0x52,0x49,0x8f,0x5a,0x2b,0xe3,0x41,0x1f,0xd8, - 0xc6,0x80,0x4e,0x01,0x51,0x9d,0xeb,0x13,0x40,0x3a,0xf4,0xc2,0x4c,0xd8,0x45,0x2c, - 0x90,0xcc,0xa3,0x7b,0x73,0xbd,0xb0,0x5e,0x91,0x08,0xba,0x17,0xf5,0xaa,0xeb,0x41, - 0xe2,0xfa,0x77,0xf5,0x5e,0xb7,0x18,0xdd,0x45,0xd6,0xb4,0xe3,0x1d,0xd2,0x16,0xd4, - 0x57,0xdc,0xa0,0x26,0xc7,0xa4,0x6f,0xa2,0x3e,0x62,0x80,0x2d,0x39,0x03,0x70,0xe3, - 0x19,0xd5,0x34,0x55,0x91,0x71,0x04,0xd1,0xff,0xa4,0x43,0x4a,0xa9,0x00,0x64,0x00, - 0xa0,0x20,0x6f,0x03,0xe2,0xde,0xef,0x68,0x0f,0xde,0x88,0x52,0xa4,0x9b,0x5a,0x58, - 0xdc,0x88,0x64,0x92,0x01,0x65,0x08,0x37,0x50,0x8b,0x91,0x51,0x95,0x3c,0x56,0x91, - 0x0c,0x99,0xb4,0xc2,0xf7,0x5f,0x29,0xad,0xce,0xad,0x1d,0x5e,0xd7,0x8c,0x6b,0xa4, - 0x4c,0x2e,0x3b,0xbc,0x56,0x96,0xaa,0x24,0x8d,0x64,0xd5,0x44,0x73,0x32,0x62,0x82, - 0x96,0x24,0x70,0xf3,0x53,0x8f,0xa6,0xc1,0xba,0x62,0x32,0x8b,0x63,0x68,0x03,0xac, - 0x23,0xf1,0x01,0xa9,0x0f,0xad,0x81,0xb5,0xc5,0x64,0x5a,0xfa,0x73,0x14,0x65,0x60, - 0x09,0x76,0x5e,0xbf,0xa8,0xf5,0x61,0x16,0xa0,0x16,0x30,0xa1,0xc6,0x86,0x5a,0x3e, - 0x0d,0xa9,0x74,0x2c,0x1d,0xa0,0x10,0xac,0x20,0x4c,0x4d,0x03,0x03,0xd0,0xee,0xf6, - 0x1f,0xd5,0x23,0x32,0x0c,0x82,0x4a,0x52,0xaa,0x01,0x1a,0x88,0xac,0x5a,0x2d,0x72, - 0x43,0x85,0x05,0xda,0xb9,0xf9,0x51,0xa4,0x39,0xe8,0xcf,0x60,0xbd,0x56,0x4f,0xa4, - 0x7e,0x0a,0x9e,0xd4,0x66,0x15,0x24,0x1d,0x9d,0x84,0xbf,0x85,0x64,0x41,0x52,0x4d, - 0xc0,0xdf,0xaf,0x16,0xd5,0xe1,0x24,0x2c,0x86,0x18,0x99,0x66,0xfc,0x5e,0xaa,0x44, - 0xa2,0x1b,0x51,0x2f,0x99,0xc9,0x2a,0x38,0x6d,0x04,0x13,0x70,0xeb,0x27,0x83,0xd3, - 0x8f,0xc4,0xd4,0x0e,0xfa,0x9f,0x2b,0xe8,0x58,0xd5,0xa8,0xac,0x1c,0xc6,0xe9,0x1c, - 0x6b,0x51,0x0e,0x03,0x05,0x69,0x0a,0xb8,0xdf,0x8b,0x7e,0xd2,0xf4,0x9d,0x2a,0xca, - 0x56,0x86,0x05,0x8a,0x36,0x18,0x73,0x5a,0xb8,0xf5,0x13,0x41,0x69,0xb2,0x4a,0xad, - 0x93,0x13,0x83,0x26,0x88,0x25,0x0e,0xa3,0x74,0x71,0x55,0x7a,0x8d,0x8c,0x7f,0x89, - 0xd2,0x23,0xab,0x54,0x0a,0xb8,0xfe,0xa3,0x19,0x49,0xcf,0xd1,0x45,0xc5,0x96,0xa5, - 0x09,0x92,0x83,0x92,0x3e,0xd2,0x9b,0xa6,0xe0,0x61,0xa4,0x9a,0x80,0xc4,0xdd,0xf9, - 0xc9,0xb0,0x09,0x73,0xa6,0x90,0x81,0xc3,0x14,0xc4,0xe8,0x8d,0xc0,0x20,0xb6,0x00, - 0x7f,0xbf,0xab,0xb1,0x9e,0x4b,0xa9,0xdd,0x3d,0xb0,0x13,0xf4,0xdc,0xd5,0x6a,0x77, - 0x8c,0xde,0x6f,0x3f,0xbb,0xdf,0x9e,0xf8,0x4e,0xac,0x9a,0x80,0xef,0xaf,0x4b,0xbd, - 0x68,0x3d,0x5d,0x08,0x74,0x6d,0x59,0x80,0xb5,0x74,0x43,0x9c,0xac,0xd3,0x25,0x19, - 0x18,0x48,0x6a,0xdc,0xfa,0xa9,0x40,0x5f,0x27,0x6b,0x75,0x69,0x37,0xae,0x40,0xed, - 0x24,0xab,0xe3,0x94,0x64,0x82,0x04,0x07,0x9c,0xd7,0x65,0xda,0xbf,0xd6,0xd8,0x46, - 0x22,0x1a,0xec,0xa4,0x8f,0x40,0x7b,0x83,0xf1,0x2c,0xe0,0x3c,0x7d,0x28,0x7a,0x70, - 0x2d,0x6d,0x31,0x00,0xd7,0x7f,0xb4,0x3b,0x12,0x27,0x79,0xbd,0x41,0x81,0xee,0x28, - 0xfb,0x47,0xc9,0x54,0x35,0x03,0x27,0xf4,0x45,0x14,0x4c,0xb3,0x00,0x37,0x9e,0xd1, - 0x6e,0x69,0x73,0xae,0x4f,0xdf,0x90,0x92,0x8e,0x52,0xb0,0x47,0xff,0xeb,0xd4,0x2c, - 0x06,0x4e,0xe9,0x0f,0x52,0xfb,0x60,0x83,0xa2,0x7b,0xfe,0xa5,0xab,0x1b,0x6d,0x26, - 0xa7,0xf4,0x5b,0x53,0xd5,0x47,0xa3,0x26,0x90,0x18,0xe8,0xd3,0xaf,0xa2,0x2d,0xd3, - 0x2c,0x50,0x44,0x5c,0x7f,0xf3,0xfa,0xbd,0x70,0xd4,0xfa,0x47,0x0a,0x03,0x31,0xbd, - 0x83,0x5e,0x1f,0x1a,0x72,0xf5,0x0c,0x14,0xe3,0xdc,0xfa,0x41,0x2a,0xf4,0xd0,0x27, - 0x06,0x6c,0xb3,0x23,0x1d,0xa6,0xa0,0x4f,0xbd,0xca,0x34,0x44,0xab,0x18,0x20,0xae, - 0xff,0x94,0x4e,0xe3,0xbd,0xa4,0x57,0x9f,0x99,0x4a,0x6c,0x03,0x06,0x2a,0x52,0xc9, - 0x6d,0xcc,0xfe,0xe8,0xeb,0x53,0xd2,0x36,0xa9,0xc1,0x04,0xc4,0xbd,0x7a,0xbb,0xb6, - 0x28,0x8d,0x56,0xc1,0x1a,0xc0,0x45,0x69,0x00,0xf5,0xc1,0x06,0x48,0x72,0x20,0x6d, - 0x01,0x77,0x3c,0xed,0x1d,0x44,0x1d,0x96,0x9b,0x23,0x55,0x74,0xfd,0xe8,0xf4,0xa1, - 0xac,0x90,0x11,0x07,0x54,0x13,0x10,0x6e,0x7e,0x56,0xe6,0xf5,0x67,0xe8,0xfa,0xa9, - 0x62,0xab,0x2b,0x27,0xab,0x19,0x59,0xe1,0x80,0x6e,0x02,0xbe,0x7f,0x46,0xca,0x8e, - 0xac,0x5d,0xb0,0x4e,0x7e,0x84,0x5a,0x9b,0x5c,0x56,0xa5,0xf6,0x87,0x82,0x3c,0x35, - 0x3b,0x72,0x32,0x8a,0xb2,0xc4,0x00,0xc0,0xcd,0x4f,0x15,0xca,0x8e,0xad,0x4d,0x27, - 0x65,0xdc,0x81,0xb2,0xc5,0xb5,0x6a,0x32,0x26,0x19,0x20,0x4d,0x41,0x06,0x0c,0x20, - 0x4b,0xce,0xec,0xb0,0x8f,0xa6,0x29,0x0a,0xc6,0x88,0x32,0xce,0x0c,0xb3,0x36,0x86, - 0x09,0x34,0x01,0xb8,0x80,0x1b,0x4f,0xa4,0x91,0x90,0x61,0xb5,0x67,0x77,0x24,0x02, - 0x84,0xe5,0xb1,0x92,0x5d,0x50,0x61,0x01,0x6e,0x3c,0x5d,0xda,0x34,0x1d,0x51,0x6b, - 0x1f,0x4d,0x10,0x89,0x81,0x99,0x30,0x8b,0xd8,0xf6,0xc7,0x05,0xee,0xfd,0x8e,0x6a, - 0xe6,0x36,0x11,0xcd,0x93,0x28,0x05,0x68,0x31,0x48,0xc5,0xa8,0x8e,0xfb,0xe0,0x2a, - 0x66,0x7f,0x54,0x30,0x01,0x3f,0x7e,0xcb,0x68,0x10,0x82,0x19,0xe8,0xa0,0xcf,0x13, - 0x4e,0xa3,0x14,0x7d,0xb0,0x94,0x22,0xa8,0x0c,0x60,0x0a,0xdc,0x0f,0x36,0xfb,0x6b, - 0xf4,0xa9,0x99,0x0f,0x31,0x2d,0xda,0x0b,0xbb,0xe0,0x16,0xa8,0x84,0x88,0x06,0x27, - 0x60,0x0e,0x03,0xcc,0x22,0x71,0xfd,0x73,0xf3,0xb5,0x55,0xd9,0xba,0xc2,0xae,0x51, - 0x44,0x81,0x56,0x97,0x48,0x50,0xd0,0xbe,0x2a,0xbb,0x26,0x81,0x8f,0xda,0x80,0xef, - 0xdf,0x24,0x6d,0x1a,0xf9,0x46,0x7a,0xfd,0x90,0xd4,0x84,0xef,0x63,0x60,0x47,0xf2, - 0x07,0x66,0xcb,0x8e,0xe4,0x8f,0x91,0x05,0x88,0x30,0x1e,0x83,0xfa,0x6b,0x26,0x19, - 0xcc,0x46,0xb2,0x74,0x3c,0x73,0xcc,0xf1,0x14,0xb0,0x35,0x1e,0xe1,0x7e,0x3b,0xf5, - 0x78,0x0a,0x77,0xd3,0xdf,0xab,0xd3,0xdc,0xc8,0xe2,0x43,0x78,0x63,0x3c,0x95,0xef, - 0x6e,0x88,0x93,0x7e,0x1b,0x70,0xdd,0xd1,0x5f,0x66,0xe3,0x6b,0xf1,0x3a,0x84,0x35, - 0xe9,0xeb,0x06,0x90,0x3a,0xbb,0xb2,0xb0,0x16,0x27,0x21,0xa9,0x75,0x65,0xd3,0x14, - 0xa0,0x24,0xbf,0x1e,0xe4,0x86,0x88,0xac,0x0d,0x2a,0x6a,0x5e,0x6e,0xc8,0xc8,0x59, - 0xba,0x36,0x1f,0x91,0x51,0xa6,0x39,0x3b,0x98,0x50,0x25,0xb9,0x61,0xb5,0x9c,0xdd, - 0x9e,0x50,0x1f,0xe1,0x87,0x53,0x85,0x23,0x39,0x6d,0x58,0x6b,0x56,0xaa,0x50,0x84, - 0x68,0xc3,0x4a,0x33,0xae,0x8a,0x53,0xb0,0x9f,0x01,0xd5,0x6a,0xe1,0xfb,0xc7,0x2a, - 0xea,0xd0,0xae,0xe2,0xbd,0xe9,0xd4,0xaa,0x28,0xdd,0x16,0x0f,0x2f,0x4a,0x57,0x33, - 0x70,0xa2,0xc8,0xc0,0xdc,0x3a,0x03,0x7c,0x8f,0x1f,0x4f,0xa5,0xb4,0xa5,0xbd,0xaf, - 0x60,0xee,0xfe,0x68,0x0f,0xdd,0xfd,0x67,0x31,0x70,0xaa,0xf0,0xa0,0xd9,0x72,0x8a, - 0x50,0xc0,0xcf,0xff,0xf4,0x95,0x99,0xdf,0x14,0x5e,0xd9,0x7b,0x53,0xe5,0x8d,0x0c, - 0xbc,0xbc,0xf7,0xa6,0x15,0xd3,0x57,0xaf,0x3c,0xbe,0xf3,0x95,0x39,0x3f,0xa9,0x9c, - 0x9e,0x59,0x79,0x82,0x81,0x1b,0xf8,0xf1,0x2c,0xfb,0xce,0xdd,0x57,0xfe,0xed,0xd0, - 0x27,0x1f,0x5c,0x68,0x63,0xe0,0xc0,0x27,0xe7,0x2e,0x2c,0xbb,0x7c,0xcf,0x7b,0x4f, - 0x5c,0x99,0xb8,0x74,0x61,0xd9,0xb7,0xef,0xb9,0xc2,0xc0,0x25,0xf8,0x5f,0x7c,0x96, - 0x3f,0x5d,0x39,0x37,0xb3,0xa2,0xb0,0xb3,0xff,0xba,0x0b,0x33,0x7e,0xd4,0x71,0xa5, - 0xf0,0x59,0xff,0xf2,0xef,0xaf,0xf8,0xce,0x3b,0x2b,0x0a,0x4f,0x5d,0x6a,0xbb,0xb2, - 0xe2,0xfa,0x77,0x56,0x7c,0xf2,0xd4,0x04,0xdf,0xbf,0xed,0xdb,0x77,0xbf,0xf7,0xc4, - 0x81,0x89,0x0f,0xdc,0x61,0x98,0x03,0x9b,0x38,0x47,0xfb,0xdf,0xfd,0x9e,0x31,0x42, - 0xbe,0x7f,0xd3,0xec,0x9e,0xf7,0x76,0xde,0x3a,0xb1,0xe3,0xde,0x65,0xec,0x0f,0x5f, - 0x98,0xf8,0xe0,0x34,0x05,0xef,0xd6,0x1d,0xc8,0x7f,0x70,0xa1,0x29,0x65,0x80,0xb3, - 0x7f,0x27,0x0c,0x68,0x70,0x40,0xdb,0xa3,0x5c,0xaf,0x54,0x17,0x29,0x3f,0xdc,0x03, - 0x8b,0x71,0xe5,0x9b,0x91,0x01,0xad,0x5e,0xb9,0x3e,0x51,0x39,0x1a,0x19,0x68,0xdf, - 0xc3,0x00,0x3f,0x9f,0xd8,0xe2,0x87,0xb9,0x23,0xd7,0xcd,0xa7,0x60,0x8d,0x92,0x64, - 0xfc,0xf0,0x14,0xa3,0x85,0x16,0x51,0x54,0x84,0xf9,0xe7,0xf8,0xa1,0xce,0xd1,0x42, - 0xb5,0x36,0x65,0x13,0xc5,0x14,0x26,0xc2,0x80,0x0c,0x92,0x16,0xcf,0x39,0xb4,0xcd, - 0x01,0xdb,0xdc,0x16,0xf7,0x23,0x77,0x6e,0xa9,0x8c,0x0d,0x76,0x20,0x18,0xeb,0x5c, - 0x80,0xea,0xf3,0x77,0xa8,0xf1,0x31,0xbc,0x05,0xd5,0x13,0x13,0x80,0x01,0x8a,0xc2, - 0xf5,0x37,0xb2,0x3d,0x51,0x22,0x39,0xca,0xba,0xc4,0xeb,0x5b,0x40,0x16,0xae,0x0f, - 0xd4,0xde,0xd1,0xc7,0x6a,0x13,0xe5,0x87,0x1b,0x19,0x3f,0x54,0x95,0xdd,0x78,0x0e, - 0x03,0x5b,0x95,0x3d,0x98,0x3d,0xaa,0x19,0x5d,0x78,0x47,0xbb,0x19,0xaf,0xcc,0xcd, - 0x1c,0xee,0x7a,0x2d,0x7e,0x03,0xfe,0x46,0xae,0x76,0xb8,0xf3,0xb9,0xf8,0x3c,0xdc, - 0x53,0xb4,0xc0,0x4a,0x62,0x00,0x6e,0xf4,0xc5,0x19,0x50,0x07,0x89,0xe3,0xd2,0x2e, - 0xa8,0xa1,0x46,0x2b,0x71,0x1c,0x9c,0xdd,0xc6,0x00,0x28,0xc1,0x80,0xe6,0xfe,0x41, - 0x31,0x46,0xdf,0x64,0xe9,0x9b,0x71,0x2f,0xb0,0x33,0x3a,0xec,0x4d,0x14,0x29,0xd0, - 0x89,0x62,0xb4,0x05,0xcd,0x34,0x5f,0x9a,0x35,0xe4,0xba,0x8f,0xe4,0x62,0x4f,0xa4, - 0x16,0x88,0xa2,0x62,0xf3,0x4d,0x55,0xb1,0x5e,0x30,0xf3,0xe2,0x2b,0x27,0xd7,0x5f, - 0xc3,0xba,0x69,0x2d,0x99,0xa1,0x4f,0x51,0x8b,0x8f,0x88,0xd5,0x12,0x77,0x81,0xd3, - 0x5f,0x41,0x5a,0x44,0x87,0xdd,0x30,0x97,0xd9,0x2c,0x13,0x54,0x32,0x90,0x32,0x00, - 0x58,0x2d,0x83,0xce,0xf0,0x35,0xc6,0x0f,0x29,0x29,0x6a,0x5f,0x45,0xf7,0x3b,0x9b, - 0x16,0x52,0xb0,0xc3,0xe1,0x87,0x0c,0xb8,0xfb,0x29,0xbb,0x73,0x3f,0x3f,0x5c,0x60, - 0x01,0xcd,0x69,0x71,0xae,0x4f,0xef,0x29,0x6d,0xb1,0x35,0x1b,0x1c,0x66,0xd9,0x3c, - 0x4d,0x60,0xb5,0xb8,0x7c,0x83,0x8d,0xc7,0xe0,0x6f,0x74,0x77,0xb6,0x40,0x9c,0x82, - 0x11,0x1b,0x98,0x2d,0x2e,0x3f,0xd4,0x90,0x9f,0x1f,0x32,0x50,0x2f,0xb4,0xb8,0xeb, - 0x21,0x8b,0xec,0xeb,0x03,0x7f,0x7d,0xba,0xad,0x0b,0xd7,0xe7,0xe6,0x47,0xc3,0x59, - 0x94,0x80,0x2e,0x4a,0xfd,0x2d,0x10,0xa7,0x00,0x3a,0x0d,0x30,0xc7,0x6a,0xc9,0x38, - 0xe3,0xe9,0xa1,0xeb,0xb6,0x9d,0xd4,0xeb,0x52,0x8a,0x3e,0x1d,0x9b,0x89,0x42,0xf9, - 0x21,0x62,0x2d,0x22,0x70,0x97,0x4f,0x0f,0x0b,0x29,0xa1,0xbf,0xb9,0x29,0x61,0x10, - 0xba,0x5e,0x8c,0x77,0xa5,0x9c,0xf9,0xd2,0x24,0x19,0xfc,0x50,0xee,0x04,0x6e,0x3c, - 0xeb,0x29,0x1b,0xcc,0xeb,0xd7,0x65,0x61,0x3d,0x25,0x8a,0xbf,0x36,0x68,0xa1,0xc3, - 0x0f,0x91,0xcd,0x0f,0xdd,0xfd,0x1d,0x75,0xe3,0xcd,0x94,0xa4,0x6d,0x48,0xc5,0x8f, - 0x1a,0xe0,0x8e,0x20,0xc0,0xfd,0x5e,0xa8,0x3b,0xb2,0x99,0xec,0xd1,0xaf,0x4f,0x55, - 0x1e,0x35,0xc0,0xad,0x26,0xa8,0x77,0x5b,0xae,0x4f,0x71,0xfb,0x7b,0xd6,0xe6,0x87, - 0x29,0x8b,0x1f,0xae,0x31,0x69,0xe7,0x0e,0x7d,0x83,0x09,0xd8,0x57,0x89,0xc3,0xdc, - 0xfa,0xa9,0x45,0x06,0x3f,0xa4,0xbb,0x27,0xb5,0x36,0x2b,0xd4,0x99,0xcc,0x10,0xcd, - 0xa1,0x3f,0x53,0x6d,0x0f,0x2e,0x18,0xf6,0x47,0x61,0xfc,0xd0,0x5d,0x3f,0x73,0x29, - 0x2d,0x4c,0xe9,0x15,0xbb,0xe1,0x47,0x14,0x5c,0x43,0xf9,0x21,0x62,0x44,0x51,0xb6, - 0x41,0x8a,0x01,0xb7,0x3f,0xe5,0xf3,0x78,0x2b,0xaa,0x81,0x8e,0x41,0x18,0xce,0x2f, - 0x41,0xb3,0xa1,0x83,0xc4,0xc7,0x69,0xcb,0x6c,0xb8,0x83,0x03,0xdc,0x7a,0x46,0xab, - 0x41,0x67,0xfc,0x70,0x25,0xec,0x24,0x2a,0xb9,0x3a,0x1d,0x61,0xb4,0xb0,0x9f,0xd1, - 0xc2,0x1e,0xb4,0xd3,0x26,0x8a,0xdc,0x78,0xe8,0xfa,0x51,0x73,0xa9,0x66,0xca,0x0f, - 0xb7,0xb3,0x65,0x33,0xdc,0x2d,0xf0,0x43,0x0b,0xf0,0xeb,0x27,0x83,0xb5,0xb7,0x12, - 0x0b,0xba,0x64,0x25,0x82,0xb3,0x39,0x25,0xdd,0x25,0xc7,0x23,0x58,0xa3,0xcf,0x7d, - 0xa7,0x01,0x72,0x06,0x00,0x6e,0x7e,0xa8,0x7d,0x2e,0x26,0xd2,0xf4,0xcd,0xe3,0x31, - 0x4a,0x90,0x12,0xc3,0x28,0x86,0x3a,0x20,0x4b,0x68,0x0b,0x05,0x6a,0xb6,0x68,0x00, - 0x8d,0x9b,0x1f,0x19,0x14,0x93,0x1f,0x82,0x46,0xdf,0x46,0x01,0x19,0xfc,0x10,0x99, - 0x44,0x51,0xb3,0xf9,0x21,0xca,0xba,0xe3,0x69,0x8c,0x30,0x7e,0x58,0x45,0xa2,0x8d, - 0x94,0x93,0x35,0x36,0xf0,0xfc,0xd0,0x06,0xa0,0xb8,0xf3,0xa3,0xe5,0x0d,0x23,0x13, - 0xb5,0xec,0x8f,0x60,0x76,0x1c,0xe0,0x48,0x82,0xb4,0xff,0x60,0x3f,0x3c,0x0d,0x15, - 0x1d,0x72,0x61,0x50,0xc7,0x4f,0xc3,0x5f,0x99,0xf6,0x47,0x66,0x66,0xa7,0xe0,0x58, - 0x24,0x6e,0x7e,0x74,0xbc,0xc4,0xf8,0xbd,0x08,0xfb,0xbd,0x6a,0xe4,0x0e,0xa2,0x8c, - 0xc3,0x12,0xb4,0x1d,0x18,0x30,0xbf,0x22,0x9c,0xfd,0xc9,0xd2,0x1b,0xfc,0x5a,0xb6, - 0x66,0x6d,0xf4,0x49,0xf8,0xa1,0x99,0xe6,0x15,0xc3,0x08,0x05,0x32,0x03,0x6f,0x52, - 0x80,0x19,0xe0,0xd6,0x33,0xe5,0x6f,0x8b,0x8a,0xd5,0xd9,0x28,0xa3,0x6d,0xf3,0xb5, - 0x6a,0x2d,0x9a,0x80,0x51,0x4a,0x2c,0xe5,0x2c,0x05,0xbf,0xa6,0x2d,0x31,0x06,0x0e, - 0x73,0xe3,0xe9,0x60,0xd6,0x26,0xdd,0x9d,0x82,0x87,0x0d,0x50,0x11,0x8b,0x9b,0xa0, - 0x3b,0x16,0x7f,0xca,0x06,0xbc,0xfd,0xd1,0xa0,0x89,0x5a,0xe9,0x08,0xf6,0x9a,0x70, - 0x11,0xb8,0xeb,0xa7,0xc7,0xe6,0x87,0xf9,0x4e,0xca,0x06,0x71,0x45,0x43,0x7c,0xa8, - 0xd3,0xa2,0x85,0xbb,0xb1,0x8f,0x1f,0x52,0xfb,0xd3,0xb9,0x36,0x9e,0xec,0xec,0x6a, - 0x57,0x94,0xfe,0x6c,0x3c,0x81,0x25,0x14,0xd7,0x3a,0xb3,0x4a,0x02,0x9b,0x86,0x88, - 0xb6,0x74,0xd1,0x16,0x77,0x3c,0x98,0x2d,0x40,0x47,0x77,0x50,0x06,0xbb,0xe8,0x92, - 0x04,0x73,0x6d,0x22,0x07,0xb8,0x8f,0x0b,0x60,0x46,0x0b,0x81,0xf2,0x43,0xa8,0x02, - 0xc6,0x06,0xa1,0x99,0xb5,0xe4,0x18,0xe8,0x74,0x18,0x23,0x35,0x7e,0xce,0x78,0xee, - 0x8a,0xae,0xd1,0xf2,0xc7,0x1b,0x6e,0x81,0xbb,0x22,0x75,0xda,0x09,0x0a,0xaa,0xef, - 0x42,0x6b,0x28,0x98,0x4f,0x41,0x94,0x81,0x45,0xb7,0x70,0xf6,0x87,0xde,0xaf,0xb6, - 0xa5,0xbd,0xbe,0x70,0x47,0x63,0xfc,0xad,0x4e,0x97,0x06,0x50,0xb0,0x81,0x02,0x70, - 0xf8,0x80,0xbb,0xa2,0x6f,0xb4,0xf9,0xe1,0xf4,0x95,0x2b,0x19,0x3f,0xfc,0xc9,0x7d, - 0x37,0x1a,0xfc,0x70,0xaf,0xc1,0x0f,0x7f,0xc3,0xc0,0x8a,0xff,0x69,0xdf,0xfe,0x51, - 0x10,0x86,0xa1,0x38,0x8e,0x47,0xfc,0x83,0x83,0x9b,0xbb,0x8b,0x1e,0x20,0xce,0x1d, - 0x2a,0x38,0xb9,0xd4,0xdd,0xbb,0x68,0x3d,0x82,0x78,0x01,0x3d,0x8d,0x17,0x10,0x5c, - 0x45,0x70,0xd0,0xbd,0x20,0x0e,0x52,0xfb,0x5e,0x5b,0x6d,0x1d,0x0a,0xed,0xa0,0x20, - 0xdf,0xcf,0xd2,0x10,0x92,0xf0,0x96,0xc0,0xef,0x51,0x92,0xa9,0xdf,0xb8,0x69,0x3e, - 0x74,0xfc,0xa9,0xe4,0xc3,0xf0,0xe1,0x6a,0x30,0x0b,0xe2,0x7c,0xb8,0x0f,0x83,0x30, - 0x97,0xc7,0xca,0xd2,0x58,0x78,0x5d,0x45,0xc7,0xde,0x93,0xa0,0x38,0xd8,0x4c,0x64, - 0xa0,0xf9,0x50,0x67,0xe6,0xd9,0xf5,0x1a,0x0b,0x6f,0x67,0x29,0x23,0x0d,0x8a,0xbe, - 0x0e,0xe2,0x7c,0x28,0x33,0xb9,0xbc,0xea,0xa4,0xf9,0xb0,0xdf,0xf3,0x8e,0xeb,0xa1, - 0xac,0x5f,0x78,0xbb,0xae,0x6c,0x7c,0x45,0xcd,0xea,0xd5,0xdb,0xa8,0xc5,0x8a,0xae, - 0x75,0xf4,0x1d,0x77,0xaa,0x9f,0x02,0x00,0x00,0x00,0xe0,0xdf,0x69,0xef,0xd0,0xa0, - 0x77,0x00,0x00,0x00,0x00,0x50,0x4c,0x7b,0x87,0x16,0xbd,0x03,0x00,0x00,0x00,0x80, - 0x62,0xda,0x3b,0xb4,0xb5,0x77,0xf8,0x75,0x29,0x00,0x00,0x00,0x00,0xbe,0xc8,0xca, - 0xfb,0x38,0x73,0xb8,0x58,0xb3,0x94,0x57,0x2b,0x75,0x6b,0x46,0xa5,0xff,0x27,0x24, - 0x7b,0x9b,0xd6,0x6c,0x6b,0xef,0x33,0x4f,0xb3,0xcf,0x75,0x4f,0xaa,0x75,0xf0,0xc5, - 0xf1,0x33,0x01,0x00, + 0x1f,0x8b,0x08,0x08,0x04,0x44,0x9f,0x46,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35, + 0x5f,0x31,0x5f,0x31,0x2e,0x62,0x69,0x74,0x00,0x94,0x9a,0x0f,0x70,0x14,0x55,0x9e, + 0xc7,0x7f,0xfd,0xba,0x93,0x74,0xa6,0x3b,0xe9,0x36,0x7f,0x30,0xb7,0x08,0xd7,0x19, + 0x07,0x76,0xc4,0x61,0x18,0x42,0x80,0x98,0x0d,0x49,0x33,0xa4,0xac,0x71,0xc9,0x1e, + 0xf1,0xce,0xbb,0xe2,0xf6,0xbc,0xdd,0x11,0x71,0x8f,0xbb,0xe2,0x2c,0xd6,0xdd,0xb3, + 0xb8,0x3b,0x4b,0x5f,0x66,0xa2,0x04,0x92,0x92,0x01,0x39,0x37,0xba,0xac,0x35,0x40, + 0x6e,0x8d,0x4a,0x59,0x11,0x75,0x8d,0x82,0xbb,0x4d,0x0c,0x3a,0x60,0xd4,0xb9,0x94, + 0x7b,0x8b,0x7f,0x8e,0x6d,0xd8,0xc0,0x46,0x89,0x3a,0xcb,0xa2,0x06,0x65,0xcd,0xbd, + 0xd7,0x3d,0xdd,0xd3,0x99,0x9e,0x04,0x37,0x5a,0xc5,0x2f,0xaf,0x1f,0x8f,0xf7,0xfb, + 0xcd,0xef,0xfd,0x7e,0x9f,0xfe,0xbe,0x81,0x52,0x29,0x63,0xfe,0x07,0xc0,0xdc,0x06, + 0xd2,0x96,0xcd,0xff,0x56,0x1f,0x5a,0xfe,0xfd,0xa5,0xdf,0x5f,0x1a,0xbc,0xf3,0xf6, + 0x8d,0xb0,0x01,0x84,0xba,0x1f,0x2d,0x0f,0xdd,0xf1,0xe3,0x1f,0x2e,0xad,0xaf,0x87, + 0xdb,0xc9,0x6f,0xa1,0xd0,0xca,0x25,0xe4,0xff,0xa5,0x37,0xc0,0x46,0x28,0x5d,0x5a, + 0xd7,0xb8,0xfc,0x86,0xc6,0xa5,0x2b,0xe1,0x0e,0x60,0x96,0xf5,0x4d,0x91,0x9f,0x27, + 0x1f,0xf9,0xdb,0x1f,0x84,0x00,0x33,0x00,0x50,0x12,0x62,0xa2,0xf4,0x4f,0x21,0xc4, + 0x28,0x0c,0xe0,0x96,0xc5,0x21,0xd0,0xe8,0xef,0x90,0x7d,0x5e,0x1a,0x02,0xc5,0xf9, + 0x3b,0x13,0x02,0x15,0xda,0x41,0xed,0x81,0x0a,0x19,0xae,0xf8,0xc3,0xa8,0x1c,0xb6, + 0xec,0x3f,0x73,0xfe,0xd4,0x09,0x3c,0xe3,0xb4,0xdc,0x4f,0xcb,0x85,0xa4,0x65,0xa2, + 0xd0,0xd7,0x59,0x1f,0xec,0xf5,0xdf,0xfd,0x5a,0xeb,0x7f,0x66,0xad,0xff,0xe7,0xce, + 0x87,0x8a,0xaf,0x31,0x1d,0x80,0xb3,0xf7,0x63,0x86,0x87,0x03,0x06,0x43,0x14,0x64, + 0x28,0xa6,0x86,0x42,0x46,0x10,0x80,0x69,0x18,0xeb,0x0f,0x5b,0xf3,0x87,0x8a,0xbe, + 0x82,0x29,0xdc,0xa2,0x8a,0x1a,0x5b,0x8f,0x76,0xe2,0x16,0x5d,0x4a,0xb1,0x75,0xf0, + 0x16,0x35,0x26,0x59,0xe3,0x11,0x35,0x32,0xb0,0xc5,0x9a,0x5f,0xf3,0x31,0x1c,0xc6, + 0x4b,0xa2,0x91,0x2e,0x4f,0x33,0xbc,0x17,0x0b,0xea,0x42,0x17,0xda,0x0f,0x4f,0x61, + 0x62,0x0c,0x22,0xfa,0xc8,0x30,0x32,0x9c,0x15,0xc5,0x13,0x45,0x3d,0xdc,0x01,0x10, + 0x55,0xbf,0xec,0xe9,0x84,0x18,0x04,0x34,0x41,0xae,0x68,0x85,0x38,0x35,0x42,0x68, + 0x04,0x9e,0x35,0x8d,0x43,0x8c,0xb5,0xbe,0xc6,0x1d,0x84,0xc3,0x10,0x8c,0x96,0xf6, + 0xc6,0xbe,0x89,0x1e,0x85,0xe0,0x51,0xa1,0x17,0xfd,0x1e,0x9e,0x82,0xa0,0x26,0x0c, + 0xa0,0x09,0xfa,0x88,0x18,0xde,0x0c,0x17,0xcd,0xce,0x5f,0x7d,0xd5,0x04,0x9c,0x87, + 0xe6,0x0d,0xa2,0xcc,0x2e,0x14,0x53,0xbb,0x9a,0xef,0x28,0xe9,0x89,0x6f,0x80,0xd7, + 0xa1,0x59,0x93,0x06,0xd8,0x09,0xf8,0xd2,0x34,0xd2,0x9c,0xb5,0x7e,0x92,0x39,0x02, + 0x53,0xd0,0xb4,0xba,0x3c,0x73,0xed,0x08,0x4c,0xf1,0xf7,0xa9,0x25,0x1a,0x3b,0x40, + 0x46,0x5a,0x34,0x29,0xc3,0x5e,0xb6,0x8c,0x71,0xb0,0xd6,0xd7,0xe4,0x83,0x74,0x91, + 0xa8,0xf8,0x73,0x76,0x81,0x7a,0x02,0x35,0xab,0x52,0x62,0xcd,0x59,0x6b,0x59,0x7b, + 0xfd,0x8b,0x9c,0x15,0xd9,0x93,0x45,0x01,0x63,0x93,0xfc,0x41,0xf6,0x9f,0xa0,0x3b, + 0x19,0x8c,0xfc,0x43,0x05,0x7a,0x4d,0x3b,0x6c,0xed,0xff,0xbc,0x69,0x5c,0x20,0xd9, + 0x6f,0xfe,0xa4,0xb8,0x36,0x1a,0x04,0x58,0xc4,0xdd,0x05,0x38,0xce,0x04,0x46,0x05, + 0x40,0x47,0xad,0xb0,0xd8,0xf1,0x99,0x24,0x67,0xc5,0xfc,0xc9,0xc8,0xdf,0x83,0x17, + 0xf0,0xe2,0xa8,0xff,0x9f,0xd1,0x77,0x61,0x5b,0xc7,0x62,0x5d,0x88,0xa0,0x77,0xe9, + 0x88,0x2e,0x6c,0x45,0xa7,0xe0,0x71,0xd3,0xf8,0xca,0x5e,0x3f,0xc2,0xb7,0xc1,0x1f, + 0xa1,0x49,0x2d,0x67,0x1e,0x82,0xd8,0x10,0x34,0x91,0xd5,0x58,0x8d,0x8e,0x68,0x52, + 0x88,0x1d,0x31,0x8d,0xa5,0xec,0x28,0xb2,0x12,0x49,0xad,0xa6,0xf1,0x69,0x51,0xa5, + 0x9b,0xd9,0x0c,0x59,0x86,0x44,0x23,0xcd,0x4e,0xaa,0xf9,0xf1,0x49,0x17,0x5b,0xf1, + 0xe1,0x39,0x23,0x3e,0x29,0x31,0xc6,0xfa,0xb0,0x16,0xa9,0xd3,0x24,0xcc,0x7a,0x5d, + 0xf1,0xff,0xd0,0xce,0x9f,0x54,0xcd,0x5e,0x78,0x01,0x02,0x61,0x3e,0xb4,0x5b,0x54, + 0xee,0x67,0x6a,0x35,0x41,0x0d,0xcb,0xb0,0x0d,0x16,0x6b,0xc2,0x16,0xf4,0x3e,0x79, + 0x64,0x18,0x17,0xec,0xcf,0x57,0x81,0xc7,0x0c,0xef,0xf8,0x4d,0x9e,0x0a,0x78,0x00, + 0xd7,0xea,0x82,0x1e,0x5b,0x01,0xdb,0x2c,0x7f,0xb3,0x8e,0xeb,0x76,0x66,0x6f,0xe2, + 0x7a,0x68,0xd0,0x46,0xfb,0x15,0x54,0x96,0x88,0x47,0xf4,0x31,0xa1,0x7e,0x7f,0x19, + 0xce,0xcf,0xb7,0x51,0x3b,0x3f,0xc7,0xab,0xc7,0xe1,0x0b,0x68,0xc1,0x62,0x92,0xbd, + 0xa1,0xf8,0x44,0xa4,0x0e,0x4b,0x3a,0x6a,0x44,0x27,0xa0,0x19,0x4b,0x49,0x96,0x3e, + 0x32,0x8c,0x2f,0xec,0xfd,0x44,0x98,0x24,0x4c,0x42,0x33,0x48,0xbc,0x70,0x5a,0x9d, + 0x54,0x89,0x81,0x59,0x5d,0x35,0x46,0x88,0x01,0x59,0x63,0x14,0xac,0xf5,0x79,0xb9, + 0x0f,0x2e,0x91,0xf8,0x8b,0xcf,0x55,0x2e,0x0c,0xbf,0x0e,0x75,0xaa,0xb4,0xbb,0x64, + 0x4c,0xbd,0x04,0x34,0x91,0xd8,0x31,0xc8,0x1a,0x43,0xf6,0x7e,0x30,0xb7,0x11,0x5e, + 0x84,0x60,0x7b,0x57,0xc2,0x53,0x02,0x1d,0x09,0xaf,0x4a,0xf2,0xff,0x2c,0x26,0x23, + 0xaa,0x90,0x40,0x63,0xe4,0x51,0x23,0x35,0x74,0xb0,0xaa,0x60,0x43,0x91,0x8f,0xce, + 0x0f,0xfb,0xf7,0x78,0x7c,0xb0,0x1d,0xbc,0xe1,0xb5,0xe6,0x34,0x7b,0xbe,0x61,0xbc, + 0x6a,0xe7,0x83,0x52,0xc5,0xc1,0x33,0x10,0x50,0x79,0x19,0xf9,0xc8,0x31,0x54,0x54, + 0x41,0x46,0xc3,0xc6,0x48,0xd6,0xf0,0x53,0x63,0x88,0xb1,0xf2,0x61,0x6b,0x59,0xd4, + 0x70,0x4a,0xc4,0x82,0x1f,0x52,0x50,0x47,0xbc,0x43,0xb6,0x9b,0xb6,0xf1,0x26,0x6b, + 0xe5,0x67,0x6f,0x11,0x75,0xaa,0xa5,0x7d,0xc9,0x1e,0xf6,0x53,0x62,0xfc,0x4a,0x95, + 0xda,0xd9,0xf7,0x2d,0x37,0x37,0x12,0xa3,0x91,0x1a,0xe7,0x8a,0xad,0x7c,0xa8,0x21, + 0xf3,0xdf,0x81,0x55,0x43,0x62,0x26,0x5e,0xcf,0xbc,0x41,0x13,0x2f,0x5d,0x72,0x11, + 0xf2,0xe3,0xf3,0xaa,0x5d,0x1f,0x1a,0x6a,0x74,0x18,0x84,0xa0,0x1c,0xe9,0x44,0xb5, + 0x6a,0x17,0x17,0x04,0x81,0xee,0x87,0x8c,0x4c,0x33,0xde,0xe4,0xac,0xf8,0x44,0xa0, + 0x93,0x38,0x15,0x54,0xf9,0x10,0xf1,0xb7,0x03,0x7c,0xea,0x5a,0xc3,0x4d,0x26,0xa0, + 0xb2,0x0e,0xc7,0x73,0x9f,0x57,0x2f,0xd7,0x07,0x2f,0x32,0xc1,0x28,0xbf,0x47,0x09, + 0x90,0x78,0x92,0xe8,0x3d,0x5c,0x28,0x9e,0x76,0x3e,0x24,0xab,0xc7,0xc4,0x77,0xb8, + 0xa6,0x4d,0x81,0x44,0x69,0xb1,0x77,0xbb,0xde,0xac,0xae,0x4b,0xa0,0xb3,0xf0,0xef, + 0x79,0xfb,0x1f,0xb7,0xeb,0x4f,0x8a,0xe9,0x83,0x1b,0xe8,0xe0,0x23,0xc2,0x39,0xf5, + 0x52,0xc2,0x78,0xfa,0x7b,0x97,0xbf,0x5f,0xd8,0xf5,0x87,0x97,0x8d,0x7c,0x93,0x45, + 0xb4,0xa6,0x16,0xa5,0xd4,0xe6,0x52,0xa9,0x93,0x3d,0xed,0x8a,0xff,0x09,0xbb,0xfe, + 0xf8,0x8b,0xfc,0xf0,0x12,0x2c,0xe9,0xe7,0x75,0xf4,0x2d,0xfc,0xe0,0xea,0x25,0x0f, + 0x09,0xfb,0xd1,0x97,0xa1,0x97,0x20,0x88,0xe7,0x26,0xd1,0x38,0x50,0x43,0x48,0x92, + 0xfc,0xb6,0xf2,0xc1,0x6f,0xd6,0x9f,0x49,0x8f,0x0f,0x49,0x4a,0xbc,0x8b,0x9c,0x8e, + 0x06,0xf4,0x86,0xef,0x59,0x66,0xfa,0x79,0x39,0x61,0xd7,0x1f,0x2c,0xdf,0x6a,0x1c, + 0x52,0xcf,0x16,0x6f,0x0f,0x6c,0x53,0x17,0x63,0xd6,0x71,0x6c,0x6d,0x63,0xdc,0x5e, + 0xbf,0xab,0xeb,0x94,0xfc,0x39,0x5e,0xa5,0x07,0x1b,0x84,0x39,0xf0,0x1a,0x31,0xa4, + 0xf5,0xe4,0x74,0xd0,0x11,0x61,0x2b,0x7b,0xca,0x30,0xa4,0xad,0xec,0x87,0x76,0xfd, + 0xe1,0xab,0x8d,0x7a,0xa2,0x95,0x0d,0x54,0x6e,0xa4,0x06,0x76,0x96,0x11,0xdb,0x18, + 0xb2,0xeb,0x0f,0x14,0xfd,0x92,0x36,0xa9,0x64,0xf9,0x49,0x76,0xbe,0xfc,0x5a,0x82, + 0x11,0xdb,0xde,0x59,0xf3,0x99,0x3a,0x95,0x98,0xde,0xbf,0x34,0xbb,0xfe,0xf4,0xd7, + 0xec,0x55,0xc9,0x26,0x3b,0xcb,0x6e,0x66,0x6f,0xc5,0xdb,0xa0,0x76,0x8f,0xa7,0x1d, + 0xbd,0x9d,0xbf,0x7f,0xf6,0x49,0xfb,0xf3,0x05,0xbc,0xd7,0xf4,0x57,0x46,0xff,0xe8, + 0x7b,0x90,0xaf,0x6d,0x2d,0x6d,0x7f,0xf5,0x6d,0xee,0x05,0xf8,0xd7,0x69,0xfe,0x6a, + 0x76,0xfd,0x51,0xcc,0xfa,0x93,0xb9,0x49,0x42,0x6d,0xc5,0x31,0x55,0xc1,0xc2,0x7c, + 0x78,0x55,0xcd,0xaf,0xe7,0x5d,0xf6,0x79,0xef,0xaf,0x9e,0xe0,0x89,0x53,0x99,0xf2, + 0xe7,0xd8,0xdb,0xe1,0x75,0xed,0x10,0x33,0xef,0x08,0xf9,0x58,0xbf,0x84,0x7b,0xa7, + 0xd7,0x4f,0x7b,0x3f,0x98,0x31,0xe2,0xd3,0xb6,0xae,0xaa,0x92,0x3c,0x8d,0x34,0x43, + 0xf9,0x00,0xc9,0x87,0xfc,0xf8,0xe4,0xea,0x61,0xad,0x6c,0xf4,0x3b,0x4d,0xcc,0xb0, + 0x7f,0x87,0xdf,0xc0,0x12,0xf4,0xa4,0x49,0x37,0xcf,0xaf,0xe7,0x5a,0xab,0xb5,0x9f, + 0x7d,0xdc,0x66,0xf8,0x29,0x04,0xb7,0xf6,0x1f,0x79,0xe9,0x71,0xe8,0xd7,0x03,0x0a, + 0x3f,0x80,0x7e,0x07,0x87,0xa7,0xf7,0x5f,0xa4,0xdb,0xf5,0x01,0x93,0x7e,0x47,0xba, + 0xb3,0xce,0xef,0x42,0x3e,0xb9,0x5b,0x09,0x2a,0xa5,0x89,0x8a,0x33,0x8a,0x6b,0xbe, + 0x9d,0x0f,0x7c,0x95,0x68,0x04,0x81,0x07,0xd4,0x03,0xfb,0xc8,0x69,0x2d,0x95,0x49, + 0xf4,0xf2,0xe3,0x93,0xab,0x3f,0x50,0xb6,0x99,0xf6,0x77,0x4d,0xc4,0x95,0x3e,0x44, + 0xda,0x0a,0x94,0x25,0x8c,0xf8,0x64,0xfd,0x3d,0x6c,0x1a,0x9a,0x5d,0x7f,0xf6,0x15, + 0x5d,0x86,0xdf,0x12,0xa7,0x96,0x68,0xc4,0xbb,0xcb,0xd0,0x02,0x4f,0x17,0xf2,0xf7, + 0x03,0xbb,0xfe,0x68,0x45,0xd9,0x24,0xd1,0x2b,0x9b,0xe1,0x32,0x5e,0x59,0xdb,0x93, + 0x62,0x2f,0xc0,0x6f,0x67,0xe4,0x1f,0x2c,0x53,0xc8,0x69,0x4c,0x76,0x77,0xb1,0x01, + 0xf8,0x00,0x7b,0xc1,0xd3,0x85,0xf4,0x64,0x77,0x1e,0xff,0xe8,0xb9,0xfa,0x5f,0xd4, + 0x96,0x75,0xaa,0xb8,0x8d,0x56,0x27,0x95,0x38,0x3e,0xec,0xea,0x47,0x43,0x39,0xfe, + 0xa9,0xa6,0xfc,0xb3,0x08,0x93,0xa0,0x05,0xe0,0x09,0x6d,0xd1,0x06,0x4f,0x4f,0xc5, + 0x39,0xa5,0x3b,0x2f,0x9e,0x39,0xfe,0x81,0xaa,0x00,0x8d,0x46,0x72,0xe7,0x13,0xc2, + 0x66,0xc8,0x68,0x4d,0x21,0xbe,0x8b,0xfd,0x9d,0xab,0xff,0x6a,0x76,0xfd,0x39,0x0d, + 0x46,0x7f,0xdf,0x25,0xe9,0xec,0x11,0xf8,0x13,0xac,0x04,0x49,0xab,0x74,0xc7,0x67, + 0xd2,0xc9,0x3f,0xf2,0x7b,0xd0,0x3c,0x22,0xfa,0x0e,0x4c,0xa0,0x14,0x5e,0xa1,0x92, + 0xfa,0x73,0x16,0xd6,0x9a,0xcb,0x6e,0xb6,0xd6,0xcf,0xd8,0xf5,0x27,0xd5,0x6a,0xf0, + 0x4f,0x82,0x1f,0x24,0xbb,0x25,0xfd,0x48,0x2d,0xc7,0x68,0x8c,0x99,0xb6,0xff,0x72, + 0x27,0xff,0x9c,0x31,0xe3,0x93,0xf6,0x28,0xe1,0x11,0x02,0xa8,0x3e,0x20,0xf5,0x59, + 0x97,0x69,0x7c,0x3c,0x05,0xf9,0x67,0x03,0x33,0x9f,0x36,0xfd,0xa4,0x27,0x52,0x7c, + 0x4a,0x2e,0xc2,0xb5,0x8a,0xb0,0x9e,0xf0,0xcf,0x34,0x1e,0xf0,0x6c,0x45,0x27,0x1d, + 0xfc,0x43,0xf3,0xad,0x29,0x5d,0xce,0x6d,0x9b,0x80,0x30,0x54,0x69,0x52,0x05,0x29, + 0xb3,0x71,0x72,0x22,0xca,0x43,0x6c,0x9b,0x05,0x42,0xa3,0x76,0xba,0xa9,0xf3,0x68, + 0x7c,0x56,0xa5,0x17,0xff,0x9a,0x44,0xe3,0x22,0x01,0x83,0x72,0x92,0x3f,0xea,0x94, + 0x3c,0x13,0xff,0xf4,0x17,0x19,0x41,0x96,0x49,0x58,0x48,0xfc,0xa1,0x99,0x21,0xd1, + 0x38,0x33,0x1b,0xff,0x5c,0x65,0xd4,0x13,0x2c,0x00,0x7b,0x2b,0xf7,0x3c,0xda,0x07, + 0x82,0x4a,0x76,0xfb,0xf8,0x8c,0xfc,0xa3,0x99,0xfc,0xb3,0x81,0x60,0xde,0x7c,0xf8, + 0x85,0xb6,0xf8,0xb6,0xb9,0x5b,0xd1,0x67,0x2e,0xfe,0xc9,0xd8,0xe7,0x3d,0x52,0x65, + 0x04,0x2d,0xd3,0x7d,0x0d,0x6a,0xe3,0x9f,0x55,0x95,0xb4,0x50,0x1f,0x7b,0x13,0x0e, + 0xcc,0xc2,0x3f,0xfd,0x14,0x72,0x12,0xd2,0x41,0xd6,0xcf,0x7f,0x06,0xf7,0xc5,0x05, + 0x1d,0x5d,0x52,0xf2,0xf8,0x07,0x39,0xf8,0x07,0x8c,0xa6,0x23,0xb3,0x45,0xb4,0xfb, + 0xdc,0x64,0xb6,0xa1,0xce,0xd9,0xf8,0xc7,0x68,0x6a,0x43,0x65,0x03,0x71,0x1f,0x73, + 0x09,0xd7,0x85,0xa5,0xc4,0xed,0xb4,0x8d,0xce,0xcc,0x3f,0x46,0x93,0x6d,0x17,0xf6, + 0xee,0xf0,0x95,0xbe,0xb8,0x9e,0xf0,0x4f,0xc2,0x6b,0xb6,0x5d,0xc9,0xd1,0x7f,0x73, + 0xfc,0x53,0x93,0xe5,0x1f,0x61,0x37,0xda,0x28,0xbf,0x08,0xfb,0x57,0xcf,0x4d,0xa0, + 0x3e,0x63,0xda,0xdc,0x82,0xfc,0xc3,0x03,0x97,0x6d,0xfa,0x75,0x45,0xc4,0x50,0xda, + 0xe7,0xca,0xe8,0x18,0x47,0x47,0x3c,0x0e,0x1e,0xc8,0xd5,0x9f,0x41,0x3e,0x6a,0x39, + 0x15,0x85,0x41,0xa6,0x02,0x76,0x62,0xd6,0x24,0x40,0xc1,0xe1,0xef,0xc7,0xac,0xb5, + 0x9f,0xde,0x79,0x59,0xa7,0xf6,0x10,0xef,0xfe,0x44,0x78,0x66,0x67,0xfa,0x6f,0xde, + 0xaf,0xc9,0xef,0xef,0xe7,0x4a,0xac,0x78,0xf6,0x56,0x1b,0xbc,0xa4,0x8a,0xe9,0x6d, + 0x63,0xf0,0x29,0x1c,0x6a,0xaf,0x19,0x60,0x17,0xb8,0x78,0xe0,0x9c,0x9d,0x3f,0x0d, + 0x72,0x94,0xa3,0x90,0xe3,0xef,0x44,0x7a,0x62,0x12,0xbc,0x50,0x86,0x11,0x2e,0xc0, + 0x3f,0xb9,0xb7,0xd8,0x56,0xe2,0x9d,0xa8,0xf2,0x35,0x68,0x58,0x79,0x86,0xe9,0x57, + 0xf9,0x04,0xe2,0x18,0x07,0xef,0x65,0xfd,0xcd,0xf1,0x98,0x11,0x3d,0x0d,0x76,0x91, + 0xe8,0x3d,0xc1,0xfb,0xd5,0xed,0x89,0x70,0x9f,0xea,0x8a,0x67,0x8e,0x7f,0x38,0xca, + 0xb7,0xcd,0x61,0x6e,0x2f,0x79,0xfa,0x4c,0xc5,0xbf,0xac,0xe7,0xe7,0xd8,0xfb,0x5f, + 0x53,0x80,0x7f,0xfa,0xc1,0x98,0xbf,0x3a,0xeb,0xdd,0xdd,0x11,0xe9,0x51,0xe2,0x5d, + 0xbe,0xbf,0x1f,0xda,0xf5,0xc7,0x0f,0x26,0xff,0x48,0x78,0x8d,0x22,0xa6,0xda,0x56, + 0x80,0xd4,0xb9,0x46,0x87,0x14,0x9a,0x91,0x7f,0x38,0xca,0x3f,0x8b,0x7b,0x05,0x7d, + 0x87,0xbf,0xf8,0xc1,0xa3,0x5e,0x4a,0x3b,0xe3,0xf0,0x2e,0x49,0x63,0x21,0xc7,0x3f, + 0xec,0x8e,0x1c,0xff,0xfc,0x97,0x51,0x7f,0x06,0x05,0x2f,0x12,0x21,0xae,0xb6,0x1e, + 0xa5,0xc7,0x84,0xbc,0x2b,0x05,0xb4,0x52,0x67,0x7d,0xb6,0xeb,0x4f,0x2d,0x73,0x8d, + 0x79,0x7e,0x37,0xa1,0xf9,0x91,0x6d,0x7c,0x6d,0x6a,0xee,0x16,0x74,0xaa,0xe3,0x27, + 0x70,0xdd,0xb4,0xf3,0x9b,0xcc,0xad,0xcf,0xcf,0x97,0x3f,0xef,0x58,0xb5,0x4f,0xf0, + 0x7b,0x9b,0xf1,0x8d,0x78,0xf9,0x05,0x89,0x62,0xcf,0x6f,0xc8,0xb1,0x95,0x4c,0xfe, + 0x99,0x97,0xc7,0x3f,0x65,0x26,0xff,0x90,0xd3,0x37,0x41,0x4e,0xdf,0x2f,0x53,0xd2, + 0xc0,0x9a,0x8f,0xe4,0x99,0xf9,0x47,0x35,0xfb,0x57,0xb2,0x2c,0xc5,0xde,0x03,0xaf, + 0xe2,0x65,0xfa,0xba,0x49,0x76,0x4a,0x99,0x72,0xf6,0xaf,0x75,0x93,0x95,0xe9,0x1c, + 0xff,0x5c,0x65,0xf0,0x0f,0xe6,0x55,0xd4,0xa4,0xfe,0xaf,0x72,0xdd,0x90,0x44,0xb6, + 0xad,0xe6,0xf3,0x5b,0x8e,0x37,0x12,0x60,0xd4,0xab,0x4e,0x7e,0x0b,0xba,0x06,0x1e, + 0xe6,0x6e,0x33,0xa6,0x29,0xf9,0xf3,0x87,0xed,0xfa,0x13,0xad,0x1a,0xe1,0x49,0xd0, + 0x74,0x1e,0x76,0x04,0x60,0xb7,0xb8,0x28,0x13,0x5b,0x8e,0xde,0x72,0xf5,0xf7,0x93, + 0x76,0x7e,0xfa,0x0d,0xde,0x6b,0x92,0xc5,0x27,0xd9,0x26,0xc2,0x3f,0x3f,0xba,0x28, + 0xbc,0xcc,0x4e,0xa9,0xf9,0xfe,0x9e,0x70,0xec,0xc7,0x18,0xdc,0xf3,0xa0,0xc2,0x1e, + 0x64,0xbe,0xc4,0xd3,0xa7,0xd9,0xc6,0x98,0x5d,0x1f,0x76,0xc9,0x97,0x19,0x52,0xb4, + 0xef,0x12,0xf5,0xca,0x26,0xfe,0x14,0xb3,0x4c,0xbb,0x26,0x53,0x69,0x96,0xf1,0x32, + 0x47,0x3d,0xd7,0xed,0xfd,0x1c,0xed,0xdc,0x4c,0x9b,0x54,0x9a,0xef,0x47,0x07,0x8b, + 0x63,0x8c,0x97,0x74,0x2b,0x30,0xdb,0x96,0xe4,0x78,0x7f,0x3f,0xad,0x5a,0xeb,0x13, + 0xfe,0x91,0xc9,0x53,0xcc,0xf7,0x17,0x07,0x60,0x87,0xe2,0x3d,0xca,0x0f,0x78,0x27, + 0xdc,0xbc,0x94,0xab,0x3f,0x1c,0xed,0x47,0x41,0x1c,0x81,0xf2,0x1e,0x88,0x81,0xa2, + 0xad,0x0d,0x15,0x9b,0x61,0x31,0xfa,0xdd,0x81,0x7c,0xfe,0xc1,0x22,0xed,0xa7,0xcd, + 0x58,0x1c,0x20,0xbc,0xb1,0x83,0x59,0x76,0xf4,0xe4,0x00,0xd9,0x3f,0x75,0x53,0x70, + 0xf8,0x3b,0x6e,0xd7,0x9f,0xe4,0xbc,0xcb,0x32,0xe9,0x5f,0x5a,0x99,0x4a,0xbc,0x9b, + 0x80,0x5f,0x69,0xdf,0x73,0xb8,0x79,0x19,0x3e,0xc9,0xfa,0xcb,0x5a,0xf1,0xd4,0xb2, + 0xfc,0x2c,0x9d,0x61,0xeb,0x60,0x18,0xaf,0xc4,0xa2,0x86,0x1a,0xe1,0x93,0x19,0xf9, + 0x47,0x33,0xf8,0x27,0x98,0x14,0x0e,0x22,0x45,0xee,0xc2,0xde,0x24,0xdf,0x8b,0x9e, + 0x86,0x7c,0xfe,0xc9,0xe9,0x3f,0x29,0x6e,0x84,0x7b,0x16,0x44,0x10,0xfa,0xc2,0x1b, + 0xa1,0x0b,0x6d,0xec,0x28,0x0d,0x55,0xf0,0xae,0x7e,0x74,0x21,0x8f,0x7f,0x8c,0x97, + 0x94,0x3b,0xe9,0xfa,0x89,0xeb,0xe8,0xfa,0x4f,0xcd,0xc8,0x3f,0x6a,0xb5,0x11,0x84, + 0xb0,0x74,0x2d,0x0a,0xc7,0xb4,0xd4,0x8a,0x8e,0xb2,0x9e,0xf8,0xb5,0xca,0xf9,0x2b, + 0xe8,0x3f,0x2d,0x37,0x4a,0xe3,0x95,0x83,0x84,0x0f,0xef,0xd1,0xca,0x35,0xf6,0xa2, + 0x41,0x8c,0xce,0xfe,0x3e,0xe1,0xd2,0x7f,0x48,0x91,0xe9,0x83,0x94,0x6c,0x7c,0x10, + 0x63,0xf8,0x8a,0xfa,0xcf,0x6d,0x42,0x27,0xe1,0xb7,0x6e,0xec,0x1d,0x27,0x85,0xf7, + 0x98,0x2b,0x1f,0x72,0xfc,0x33,0x6e,0xf1,0xe1,0xf5,0x28,0x06,0xb1,0xa4,0xff,0x03, + 0xbe,0xd4,0x3b,0xab,0xfe,0x93,0xe5,0x1f,0x61,0x3c,0xdc,0x08,0x0f,0x24,0xf6,0x25, + 0xf9,0x4d,0xde,0xd1,0x9c,0xfe,0x93,0x35,0x2e,0x4f,0xe3,0x1f,0x02,0x39,0x20,0xc9, + 0x6c,0xa7,0x77,0x48,0x6e,0xd0,0x02,0x4a,0xbe,0xfe,0x53,0x12,0x72,0xea,0x3f,0x06, + 0xff,0xb4,0x80,0xd4,0x5e,0x79,0x12,0xbe,0x92,0xbf,0xd5,0x29,0xfd,0xa1,0x00,0x3f, + 0xbb,0xf8,0x27,0x42,0x82,0xa0,0xc0,0x93,0x50,0xa7,0xf5,0x60,0xd2,0x94,0xf2,0xe2, + 0xbf,0xc6,0xc5,0x3f,0x43,0xc2,0x16,0x4f,0x0d,0x3c,0x00,0xfb,0x34,0x3e,0x8a,0x12, + 0x6e,0xfd,0xc7,0x8e,0x3f,0x36,0xf9,0x27,0x2a,0xac,0x8f,0xcd,0xe1,0x7f,0x8e,0x95, + 0x8f,0x78,0x3f,0xba,0x5b,0x7e,0x3c,0x5f,0xff,0xb1,0xe3,0x9f,0xe5,0x9f,0xbf,0x16, + 0xe4,0x0a,0x0f,0xc4,0x38,0x25,0xed,0xaf,0x8f,0x1d,0x53,0x66,0xd3,0x7f,0xfa,0x4d, + 0xc8,0x89,0xb2,0x8d,0xf2,0xc7,0x5b,0xea,0x70,0x60,0x4c,0xf8,0x4f,0xfc,0xe1,0xcc, + 0xfa,0x0f,0xd8,0x4d,0xe7,0x74,0x78,0x52,0x6d,0xae,0x20,0xc6,0x3e,0xee,0x8a,0xfc, + 0xa3,0x49,0x7b,0xe3,0x0b,0xe1,0x78,0xc7,0x40,0xab,0xf8,0x0d,0x02,0xb9,0x57,0xd4, + 0x7f,0x56,0x0b,0xbd,0xe1,0x05,0xd0,0xa1,0x79,0x27,0x3d,0x89,0x8a,0x6f,0x1a,0xfa, + 0x4f,0xf9,0x6c,0xfc,0x43,0x06,0x3d,0x9c,0xba,0xbd,0xd6,0x4b,0xfa,0xbb,0xa7,0x0f, + 0xe7,0xe9,0x15,0x15,0x0e,0xfe,0xe1,0x0c,0xfe,0x89,0x0a,0x35,0xa8,0x08,0x3a,0x40, + 0x21,0xd8,0x53,0xde,0x09,0x33,0xf3,0x4f,0x43,0x99,0xcd,0x3f,0xa4,0xa4,0x33,0x75, + 0x54,0x08,0x4a,0x4e,0xd7,0x1f,0x4a,0x30,0xfb,0x26,0x63,0xeb,0x3f,0xf3,0xb2,0xfe, + 0xde,0xc2,0x5e,0x44,0xcf,0x43,0x73,0xbb,0xf4,0xb6,0x70,0x8b,0xe1,0x66,0xb9,0x93, + 0x67,0xb8,0x1c,0x6f,0x18,0xfc,0xa3,0x49,0xe9,0xb8,0x0f,0x8e,0x41,0x5d,0x44,0x4c, + 0xb3,0xf5,0x6e,0xfd,0xc7,0xc1,0x3f,0x59,0xc8,0x49,0x22,0x1e,0x4e,0x92,0x54,0xe3, + 0xef,0x27,0xdd,0x76,0x66,0xfe,0x89,0x14,0xd9,0x4e,0xb5,0xd6,0x6e,0x47,0x4a,0xbb, + 0x47,0x0e,0x73,0x90,0xcf,0x3f,0xa3,0x39,0xfe,0xa9,0xee,0xb3,0x82,0xdc,0xba,0xfa, + 0xa7,0xb2,0x57,0xf5,0x3c,0x8c,0xfe,0x7b,0x76,0xfd,0x87,0x6e,0xf2,0x87,0x52,0x42, + 0xf8,0x01,0x3a,0x7e,0xa6,0x4e,0x5d,0x94,0x60,0x1d,0x9f,0xef,0x8b,0xf9,0xfc,0x33, + 0xce,0xf4,0x71,0x97,0xe8,0x79,0xf9,0x06,0x7b,0x10,0x2e,0xc5,0x8e,0xa8,0x65,0x35, + 0x39,0x37,0x0b,0xe8,0x3f,0x7e,0xd9,0xe2,0x9f,0x78,0x2d,0x9c,0xe4,0xe7,0x90,0xf8, + 0xb3,0x8a,0x72,0x45,0xfd,0x67,0x0f,0xc1,0xf8,0x45,0xe4,0x7c,0x79,0x71,0x38,0x59, + 0xb9,0xd5,0x92,0x7d,0x0a,0xe9,0x3f,0xd9,0xf7,0x2f,0x81,0x41,0x25,0xc3,0x0f,0x81, + 0x6f,0x12,0x42,0xc5,0xa5,0xae,0xfa,0x93,0xd3,0x7f,0x92,0x26,0xff,0xa8,0x64,0xf0, + 0x1a,0xe6,0x27,0xbc,0x82,0x3c,0xa1,0xe2,0x5b,0x99,0x99,0xf5,0x9f,0x7e,0x7e,0x3e, + 0x81,0x1c,0x42,0x3b,0x11,0x61,0x0e,0xfc,0x1a,0x2f,0xf7,0x8a,0xeb,0xd9,0x0a,0x4b, + 0xf6,0x29,0xa4,0xff,0xcc,0x33,0xea,0xad,0x4a,0xaa,0xc7,0xd9,0xe2,0xa7,0x4c,0x63, + 0x0c,0xde,0x9b,0x45,0xff,0xa1,0x4d,0x6a,0x55,0x5f,0xf9,0xf8,0x9a,0x6f,0xc1,0xb1, + 0x7d,0xcb,0xa2,0x81,0x49,0xb6,0x19,0xa6,0xf2,0xfa,0x97,0xe6,0xe4,0x1f,0xba,0xc9, + 0x39,0xfc,0x86,0xf0,0x55,0xf8,0x7e,0xe5,0x3a,0xd5,0x00,0x9b,0x99,0xf9,0x07,0x4c, + 0xfe,0x39,0xfa,0x5d,0x0d,0xd5,0x54,0xdd,0xdf,0x74,0x1b,0xe6,0x6f,0x41,0x55,0xae, + 0xf9,0x0e,0xfd,0xc7,0xac,0x3f,0x54,0x6f,0xf4,0x40,0x07,0xf6,0x03,0xdf,0x40,0x0e, + 0x5a,0x7e,0x3c,0x53,0x0e,0xfd,0xc7,0xec,0x2f,0xe4,0x74,0x5f,0xef,0x3d,0x9e,0xa8, + 0x6b,0x0f,0x0c,0x74,0xd7,0xba,0x78,0xe6,0x7c,0x4e,0xff,0x31,0xf9,0x07,0x49,0x49, + 0xe1,0x03,0xb8,0xa4,0x12,0x83,0xa6,0x8d,0x5b,0xff,0xb1,0xd6,0x67,0xe4,0xcb,0xa6, + 0x9e,0xaf,0xb1,0x17,0x94,0x11,0xa6,0x1e,0x44,0x99,0x0d,0x29,0x33,0xeb,0x3f,0x18, + 0x0c,0xfe,0x89,0xde,0xd4,0xf7,0x4a,0x12,0x25,0x87,0xbc,0xbc,0x3f,0x81,0x16,0x16, + 0xe0,0x19,0x07,0xff,0x30,0x74,0x3e,0x19,0x4c,0xe1,0xed,0x38,0x78,0x13,0xff,0x4c, + 0x85,0xb7,0xf6,0x4a,0xfc,0x13,0x80,0x52,0x85,0x04,0xad,0x1f,0xfc,0x54,0x88,0xe6, + 0xae,0xa0,0xff,0x18,0xf9,0x80,0x49,0xb7,0x4a,0x31,0xcd,0x10,0xa0,0xe7,0x2b,0xdf, + 0xdf,0x9c,0xfe,0x43,0xf8,0xc7,0xf0,0xb7,0x2c,0xca,0x1e,0x21,0xfd,0xfd,0x05,0x58, + 0x92,0x26,0xfd,0xdd,0x75,0xbf,0x83,0x6c,0xde,0xb8,0xea,0x2b,0x94,0xbd,0xed,0xda, + 0x0d,0x13,0x78,0x99,0xd2,0x33,0xc2,0x36,0xe1,0x4f,0xf0,0xaa,0x94,0x78,0x31,0x97, + 0x48,0x19,0xbb,0x3e,0x60,0xf8,0xd8,0xa2,0x9d,0x0d,0xd0,0x85,0x57,0x28,0x04,0xdb, + 0x5a,0x54,0x32,0x92,0x21,0x85,0x28,0x68,0xeb,0x3f,0xf6,0x79,0xe4,0x8b,0x46,0x20, + 0x0e,0x7e,0xea,0x14,0x86,0x43,0xb0,0x08,0x78,0x44,0x5e,0x34,0x08,0xff,0xa4,0xf9, + 0x43,0x48,0xcc,0xf9,0x6b,0xc5,0x9f,0xf2,0x4f,0x56,0x2d,0xd9,0xc0,0x3f,0x8a,0xef, + 0xf4,0xee,0x48,0x90,0x68,0xd1,0x11,0xff,0x2e,0x14,0x28,0xc0,0x3f,0xa4,0xff,0x66, + 0xd5,0x86,0x03,0x90,0xc1,0x0d,0xb5,0xe2,0xcf,0x4a,0x03,0x70,0x1e,0xdd,0xa3,0x89, + 0x8f,0x0a,0x01,0x37,0xff,0xe8,0x26,0xff,0xd0,0x20,0x64,0x48,0x2a,0xad,0x84,0x5c, + 0x58,0x26,0x0b,0xea,0x3f,0x70,0xd0,0x3a,0x7d,0xfb,0xd4,0x13,0x77,0xd5,0x55,0x49, + 0x7d,0xac,0xb9,0xac,0x98,0x10,0x82,0xd6,0x3f,0xed,0xd0,0x7f,0x8a,0x44,0x35,0xbb, + 0x49,0x0d,0x76,0x84,0xe7,0x28,0x6b,0x07,0xd0,0xcf,0xf0,0x61,0x58,0x32,0x5a,0x13, + 0xf2,0x04,0x2c,0xd7,0x72,0xfc,0xa3,0x17,0x7d,0xc7,0x0a,0x42,0x4c,0xc1,0x9a,0x2f, + 0xba,0x36,0x89,0xa4,0xc0,0x43,0x4c,0x60,0x92,0x24,0x86,0x88,0xe2,0xf9,0xfc,0x13, + 0x35,0xf9,0x87,0x36,0xfd,0x51,0xb5,0x13,0x2f,0x20,0x86,0xd7,0xbc,0x21,0xf2,0xff, + 0x3d,0x7a,0xcc,0x12,0x46,0x1c,0xfa,0x0f,0x88,0x16,0xed,0x60,0xd0,0xd4,0xfa,0x56, + 0xa9,0x9e,0x35,0x47,0xf8,0x5d,0x82,0x08,0xaf,0x64,0xf5,0x9f,0x69,0xfc,0x73,0x5f, + 0x36,0x3e,0x1e,0xaa,0xff,0xec,0xb4,0xe3,0xf3,0x3f,0xec,0xad,0x33,0xf2,0x8f,0x01, + 0xe1,0x48,0x67,0x56,0xa8,0x3b,0x07,0xd8,0x8f,0x92,0xaf,0x13,0x02,0x37,0x88,0x7d, + 0x26,0xfd,0x87,0x16,0x8d,0x93,0x70,0x3f,0xaa,0x55,0x89,0xf1,0x7f,0x98,0xf0,0x8f, + 0xee,0x2c,0x44,0x2e,0xfd,0xc7,0xa4,0x9d,0xa7,0xf1,0x82,0x28,0x31,0xde,0x34,0xdc, + 0x24,0x85,0xc5,0x0e,0x85,0x4b,0xff,0x31,0x8a,0xb6,0x12,0x8b,0x24,0xff,0x20,0xac, + 0x40,0x23,0x46,0x18,0xf9,0x7a,0x8f,0x38,0x0b,0xff,0x24,0xd9,0x4b,0xf8,0x5c,0x74, + 0xe5,0x11,0xe9,0x1c,0xc1,0x9e,0x13,0xd0,0x84,0xc5,0x71,0xc1,0x5f,0x88,0x7f,0xf2, + 0x6e,0x1f,0x76,0x62,0xf6,0xa8,0xd1,0xa1,0x96,0x74,0xc4,0x67,0xe6,0x1f,0xda,0xd4, + 0xce,0xc2,0xf1,0x64,0x5d,0x54,0x4a,0x20,0x1f,0x7c,0x00,0xcd,0xad,0x62,0x15,0xbb, + 0x10,0xcf,0xc4,0x3f,0xb4,0xc9,0x0e,0x2b,0x4f,0x84,0x57,0xb4,0x0a,0xb4,0xfe,0x6c, + 0x27,0x15,0x86,0x4f,0x78,0x17,0xce,0xc6,0x3f,0x59,0xbd,0x91,0x74,0xf3,0x3e,0xfc, + 0x04,0x15,0x5a,0xe9,0x3f,0xe4,0xd6,0x7f,0xb8,0x5c,0xf7,0x17,0x0f,0x80,0x4f,0x15, + 0xaa,0x2a,0x44,0x02,0x42,0xa4,0x62,0x57,0x79,0xb8,0x42,0xfc,0xb3,0x29,0xe7,0xaf, + 0x79,0xff,0x45,0xf8,0x67,0x9c,0x84,0x25,0x40,0x1a,0x71,0x81,0xfb,0xaf,0xbf,0xb0, + 0xfd,0x7d,0xdb,0xd0,0x7f,0xa4,0x34,0x71,0xfc,0x92,0x01,0x42,0x0e,0xfe,0x71,0xdc, + 0x7f,0x5d,0x84,0x77,0xac,0xf9,0x6f,0xc0,0xd5,0x86,0x81,0x8f,0x43,0x4b,0x54,0x7a, + 0x9f,0xad,0x47,0xc7,0x0b,0xf0,0x0f,0xd7,0x65,0x42,0xce,0xb8,0xc1,0x3f,0x42,0x0c, + 0xe9,0xc8,0x18,0xe1,0x91,0x02,0x5d,0xf9,0xfc,0xc3,0x13,0xfe,0xd9,0x65,0xd1,0xce, + 0x76,0xc6,0xa7,0xce,0x95,0x63,0xc7,0xa8,0xbf,0xed,0x42,0x15,0x29,0xbc,0x1d,0x2e, + 0xfd,0x87,0xf0,0xcf,0x76,0x8b,0x76,0x1e,0x01,0xef,0x8d,0xc2,0xc3,0x46,0x60,0x83, + 0x74,0x9a,0xcf,0x7a,0xe4,0xe4,0x9f,0x61,0x6b,0xff,0xc7,0xe0,0x68,0x64,0x85,0x89, + 0x31,0xc6,0xb6,0x1f,0x16,0x7c,0x70,0xdc,0xa5,0xff,0x30,0x7d,0x0e,0xda,0xe9,0xa5, + 0xf7,0x65,0xec,0x70,0x76,0x44,0x28,0xa4,0xff,0xc8,0x36,0x6d,0x9e,0x96,0x53,0xd0, + 0x08,0x7f,0x49,0xef,0x97,0x53,0xc6,0x8d,0x64,0x2e,0xfe,0x4e,0xfe,0x69,0x50,0xb2, + 0x90,0x33,0xc9,0x3d,0xa8,0x53,0xfd,0xc7,0xd3,0x80,0x76,0xc0,0x92,0x1e,0x0f,0x25, + 0xc6,0x0f,0xdd,0xfc,0xf3,0x57,0x4a,0xf6,0x50,0xbc,0x11,0x8d,0x0f,0x19,0x85,0x5a, + 0xa4,0xdf,0x4f,0xd0,0xc9,0x5f,0x13,0x67,0xe4,0x1f,0x7a,0x48,0xd3,0x68,0x27,0x57, + 0xab,0x91,0xd3,0x57,0x45,0xde,0x5f,0xc8,0xfc,0x1f,0xa3,0x79,0x96,0x90,0x9b,0xcf, + 0x3f,0x06,0xe4,0x8c,0xc2,0x6b,0xf8,0x86,0xa8,0x70,0x89,0x9d,0x0f,0xaf,0x75,0xac, + 0x4a,0x06,0xd6,0x0b,0xf3,0x0b,0xf1,0x4f,0x7f,0xae,0x89,0xff,0x91,0x23,0xc6,0x33, + 0x66,0x7f,0xc7,0x65,0x7b,0x0a,0xf2,0x4f,0xf5,0x17,0xc6,0xb7,0x35,0xc8,0xb2,0x17, + 0xc8,0x6b,0xfb,0x52,0xbd,0x6d,0x2b,0x6d,0x5b,0xf4,0xfe,0xeb,0xfd,0x5c,0xff,0x72, + 0xf2,0x4f,0xaf,0xfa,0x1b,0xb2,0xc9,0x72,0xb2,0x7f,0x52,0x76,0x96,0x6b,0x9e,0x2d, + 0x16,0xcf,0xdc,0x1c,0xab,0x2a,0xc4,0x3f,0xbd,0xd9,0xb7,0xb3,0x8a,0x0c,0x3c,0x2e, + 0xd7,0x86,0xf9,0x0c,0x2d,0x53,0xdc,0x62,0x5c,0xba,0x35,0x57,0xaf,0x9c,0xfc,0x93, + 0x82,0x87,0x4c,0x35,0xe3,0x28,0xc4,0xa3,0xbe,0x34,0x09,0x63,0xb6,0xbf,0xd7,0xe7, + 0x1a,0xbd,0x83,0x7f,0x8a,0xfa,0xad,0x26,0xa2,0xc3,0x7e,0xb5,0x4e,0x17,0x3f,0x5b, + 0x9b,0x2d,0x9b,0x83,0xb9,0xfe,0xe5,0xb8,0xff,0x22,0xb5,0xc3,0x1c,0xbc,0xf6,0xb4, + 0xf2,0xa5,0xfa,0x1f,0x61,0x69,0x20,0x3e,0x9e,0x1d,0x89,0x17,0xe2,0x1f,0x92,0x22, + 0x9f,0x58,0xfd,0xee,0x2d,0x58,0x16,0x25,0x46,0x3d,0x2d,0xe3,0x03,0x65,0xed,0x6c, + 0x33,0x9e,0x82,0xab,0xa7,0xf3,0x4f,0x07,0xf7,0xed,0x70,0xb6,0x49,0xbd,0xc2,0x75, + 0x6b,0xde,0x8d,0x02,0xbd,0x38,0x36,0x14,0x89,0x44,0xae,0xff,0xea,0x0e,0xfd,0x47, + 0x51,0xb2,0xea,0xc4,0x19,0xa5,0x7b,0xbb,0x97,0x1a,0x4f,0xd3,0x69,0x6a,0x76,0xfe, + 0xc2,0x7c,0xfe,0x01,0x43,0xfd,0x98,0x1b,0x22,0x41,0xa3,0xef,0x5f,0xa4,0x3f,0x76, + 0x19,0xc4,0x28,0xc8,0xdf,0xe6,0x0a,0xf0,0x8f,0x18,0x95,0xcf,0x5b,0x4e,0xbd,0x0e, + 0x87,0xd4,0x75,0x99,0x35,0x49,0xea,0x26,0x94,0x6d,0x31,0xfa,0xcb,0x8a,0x3c,0xfe, + 0xf9,0x4e,0xc2,0x52,0x33,0xd2,0x9e,0xcf,0x09,0x9a,0x10,0x63,0x8b,0x9b,0x7f,0xdc, + 0xf7,0x5f,0x93,0xec,0xbd,0x70,0x39,0xb6,0x4c,0x27,0xa0,0x78,0xaf,0x8b,0x9f,0xf3, + 0xef,0xbf,0x82,0xa7,0x09,0xe4,0x04,0x61,0x10,0x7b,0xe9,0xf7,0x7f,0x6c,0xec,0xc9, + 0xdd,0x7f,0x39,0xea,0x8f,0xdd,0x8f,0xda,0x60,0x10,0x91,0xf3,0x05,0xa8,0xad,0x00, + 0xef,0xe5,0xe9,0x3f,0x24,0x68,0xc5,0x01,0x18,0x1c,0x5e,0xa4,0x91,0xf5,0x03,0x2e, + 0xfe,0x74,0xdc,0x7f,0x55,0x67,0x3f,0xf4,0xd0,0xd5,0x9b,0xe5,0x0c,0x6e,0xd4,0xa4, + 0xbe,0x92,0xcd,0xd3,0xf9,0x50,0x28,0x70,0xff,0x65,0x44,0x83,0xa0,0xf1,0x0b,0x9a, + 0x84,0x4b,0x2e,0xcf,0x7e,0xff,0x45,0x16,0x69,0xa4,0xc7,0x70,0x02,0xc6,0x55,0x62, + 0x3c,0x97,0x4b,0x4b,0x3b,0xdf,0x1c,0xfc,0xc3,0x99,0xbb,0x5d,0xfb,0x32,0x9a,0xa8, + 0x1a,0xd4,0x48,0x3e,0xcc,0x29,0xb0,0x7f,0x27,0xff,0xd0,0x68,0x90,0xb0,0x34,0x91, + 0x68,0x24,0x65,0x5e,0x13,0x50,0xb6,0xec,0x14,0xbe,0xff,0x72,0xf0,0xcf,0x29,0xe6, + 0xf9,0x74,0xad,0xde,0x1d,0xc9,0x61,0x80,0xad,0x87,0x9c,0xcc,0xd3,0x7f,0x1a,0x4c, + 0xb5,0x47,0xa7,0x86,0x8f,0x15,0xf3,0xbe,0xff,0x53,0x40,0xff,0xd1,0x0c,0xec,0xf9, + 0x94,0x46,0xe3,0x34,0xeb,0x8e,0x4f,0x41,0xfe,0x99,0x80,0x0c,0xcd,0x46,0xcc,0xba, + 0xe3,0x53,0x90,0x7f,0xe8,0xdb,0x13,0xfd,0xfe,0x0f,0xda,0xeb,0x7a,0x9f,0x2a,0xc4, + 0x3f,0xc5,0xa7,0xe0,0x17,0xda,0x02,0xdd,0x53,0x53,0xc0,0xdf,0x82,0xfc,0x33,0xc2, + 0x3f,0x8b,0x15,0x4d,0x08,0xc4,0x7a,0x5c,0xf9,0x56,0x90,0x7f,0xc6,0xe1,0x33,0x7c, + 0x37,0x2e,0x1f,0x43,0xfe,0xdc,0xc8,0xcc,0xfa,0x4f,0xa7,0xf5,0xf6,0xdd,0xc1,0xba, + 0xbf,0x0f,0xe3,0xe6,0x1f,0xa6,0x97,0xf6,0x3b,0x8d,0xf4,0x47,0xf9,0xfa,0xd9,0xf5, + 0x9f,0xac,0xc8,0xb0,0xcb,0x50,0x1b,0xbc,0x6a,0xb7,0x03,0x63,0x0a,0xe9,0x3f,0x9c, + 0xf9,0xb4,0xd4,0x78,0xca,0x2f,0xa4,0x7f,0xd1,0xc7,0xcc,0xfc,0xfd,0x1f,0x3e,0xfb, + 0xfd,0x1f,0x52,0x7f,0xa8,0xfa,0x01,0xaa,0x50,0xe3,0x71,0xeb,0x21,0x0e,0xfe,0x29, + 0x35,0xf5,0x9f,0x32,0xd3,0xbb,0x15,0xcc,0x4e,0x2c,0x28,0x2e,0x7f,0x3f,0xce,0xf1, + 0x4f,0xb5,0x43,0xcd,0x78,0x99,0x18,0x3b,0xdf,0x2e,0xa0,0x6f,0x38,0xf9,0x27,0xcb, + 0x03,0x69,0x96,0xde,0x7f,0x11,0x63,0x34,0xee,0x73,0xeb,0x45,0x6e,0xfd,0xc7,0x50, + 0x7b,0x48,0xe9,0x11,0x3a,0x67,0xd5,0x7f,0x80,0x1b,0x76,0x79,0xd7,0x5a,0x40,0xef, + 0x2a,0xa0,0xff,0x64,0xa3,0xb7,0x7b,0xd6,0xef,0xff,0xec,0xaf,0xea,0x9b,0xee,0xdd, + 0xba,0x3d,0xdd,0x1b,0x0d,0xd9,0xc7,0xb1,0x7f,0xe4,0xba,0xff,0xca,0xce,0xef,0x27, + 0x86,0xcc,0xf6,0xb9,0xe2,0x53,0x90,0x7f,0x68,0xb4,0x1b,0x41,0x8a,0xb3,0x49,0x57, + 0xfc,0xf3,0xef,0xbf,0x48,0xb7,0xd2,0x09,0x84,0x3c,0xa6,0x12,0xfe,0x19,0x47,0xfe, + 0x2b,0xeb,0x3f,0x9a,0xf0,0xff,0xec,0x5d,0x6f,0x70,0x1c,0x45,0x76,0xef,0x9d,0x1d, + 0xcb,0x63,0x69,0xa5,0x1d,0xdb,0x12,0x25,0x62,0xe3,0x5b,0xaf,0x05,0xa7,0xa3,0xd6, + 0x6b,0x59,0x0a,0x3e,0xfe,0x08,0x69,0x2c,0xa8,0x94,0x8c,0x55,0xe5,0x2d,0xc2,0x07, + 0x92,0xa2,0xa8,0x2d,0xca,0x1f,0x9c,0x2a,0x1d,0x51,0x25,0xf9,0xe0,0xba,0x23,0x66, + 0x2c,0x0b,0x22,0x63,0x5d,0xd0,0x01,0x97,0x38,0x09,0xa1,0xd6,0x2e,0x7f,0x30,0x57, + 0xae,0x8a,0x64,0x63,0x63,0xd9,0x17,0xdd,0x58,0x08,0x4e,0x18,0x63,0x94,0x40,0x11, + 0x03,0x2e,0x6e,0x21,0x22,0x27,0x40,0xe7,0x08,0x63,0x1b,0xdb,0xc8,0x76,0xba,0x7b, + 0xa6,0xbb,0x5f,0xcf,0xf4,0xec,0x8e,0x8f,0x4a,0x8a,0xaa,0xa0,0x4f,0xaf,0x76,0xbb, + 0xd6,0xd3,0xcf,0x33,0xef,0xfd,0xe6,0xf7,0x7e,0xef,0x75,0x0a,0x3f,0x1d,0x43,0x0e, + 0x0e,0x44,0x4b,0xb5,0xe0,0xf3,0x72,0xdc,0x5f,0xff,0x72,0xfe,0x89,0x3c,0xad,0x3f, + 0x77,0xf0,0xf3,0xeb,0x28,0xf8,0x93,0x69,0x58,0xff,0x72,0x41,0x4e,0x67,0xfc,0x43, + 0xfd,0xbc,0x7d,0x07,0x36,0x16,0xbf,0x60,0x96,0xe5,0x7f,0xdc,0xfa,0xd7,0x8d,0x31, + 0x6c,0x20,0x95,0xfe,0x47,0x63,0xfe,0xb1,0xe6,0x5d,0xb5,0x68,0x92,0xda,0x14,0x6b, + 0xb3,0xae,0xd8,0x3f,0x9c,0x4a,0x9e,0x52,0xf0,0x3f,0x93,0xb5,0x3e,0xfe,0x87,0x5c, + 0xe4,0x52,0x74,0x90,0xc4,0x9f,0xfc,0xb6,0x87,0x4a,0xd4,0xbf,0x6c,0xf4,0xbc,0x49, + 0x3f,0xb4,0xb4,0xa5,0xb1,0x83,0xe8,0x66,0x67,0xc9,0x03,0x8a,0x78,0x25,0xd5,0xbf, + 0x3c,0x7f,0x56,0x24,0xd0,0xb0,0x91,0x72,0x96,0xd4,0x0b,0x37,0x72,0xe3,0x3d,0x5f, + 0xfd,0x8b,0xee,0x37,0x83,0x2e,0xd9,0x38,0x7e,0xf6,0xc5,0xf7,0x05,0xf4,0x2d,0xc7, + 0x01,0x1f,0xee,0x39,0x61,0x0f,0xfe,0xf6,0x52,0x0e,0x1b,0x83,0x55,0xdd,0x01,0xff, + 0x4c,0xf9,0xf9,0x1f,0x22,0xe3,0x9c,0x23,0xef,0x23,0xc4,0x9f,0xad,0x81,0x78,0x2e, + 0xf0,0xd2,0x31,0xbd,0xdb,0x4d,0x52,0x7b,0x7a,0x67,0xf4,0x11,0x1b,0x27,0xb2,0x81, + 0xa7,0x82,0xf9,0x0b,0xd4,0xbf,0xbc,0x7c,0x87,0x6f,0xaa,0x19,0x34,0xd2,0x8f,0x8d, + 0xbd,0x8a,0x7c,0x17,0xe0,0x7f,0xdc,0xfb,0x0d,0x1b,0xc7,0x28,0xde,0x2e,0xc1,0xff, + 0x18,0x5e,0x36,0x19,0x24,0xfb,0xd5,0xa8,0x91,0x09,0xd4,0x43,0x8b,0x7e,0xfe,0xc7, + 0x49,0x16,0xe3,0x73,0xc6,0x79,0xb6,0xf1,0x48,0xf8,0xe7,0x2a,0xc2,0xf7,0x4f,0x11, + 0x7f,0xcb,0xef,0x9f,0xb9,0xd4,0x5b,0x21,0xf5,0x2f,0x02,0x72,0x66,0xec,0x11,0x82, + 0x7f,0xae,0x70,0xfc,0xb3,0xe8,0x4d,0xed,0x0d,0xaf,0xfe,0x55,0xc1,0xeb,0x5f,0xf3, + 0xba,0x0c,0xb6,0x3b,0xfc,0xa2,0xd1,0xe0,0xc0,0xfd,0x8e,0xef,0x7e,0x36,0xa4,0xfe, + 0xe5,0x7a,0x0f,0xff,0xbe,0x43,0x85,0x40,0xde,0x27,0x53,0x69,0x0f,0x9a,0xce,0x0a, + 0x7c,0x52,0x07,0xf3,0xaf,0x4d,0xd1,0x60,0x26,0xc6,0xdc,0x62,0x7d,0x10,0x52,0xff, + 0x92,0xbc,0xc1,0x8d,0x0b,0x5a,0x98,0xfe,0xd9,0xa9,0xe1,0xde,0x6e,0xda,0x26,0xf2, + 0x7b,0xca,0x83,0xee,0x5f,0x48,0xf5,0xaf,0xcf,0xf9,0xff,0xbe,0x99,0x75,0x76,0xcc, + 0x8a,0xeb,0x3f,0xc3,0xf8,0x9f,0x0b,0x81,0xfa,0x97,0x8b,0x76,0x2c,0xec,0x8d,0xdb, + 0x84,0x7f,0x3e,0x61,0xfc,0xcf,0x2c,0xcf,0x77,0xa4,0xfe,0x25,0x57,0x7f,0x00,0x0d, + 0xf2,0x2e,0xe3,0x7f,0xe6,0xb8,0xfe,0x73,0x9d,0x91,0xb0,0xbe,0x74,0xd5,0x3e,0x04, + 0xed,0x2c,0x25,0x68,0x87,0xe1,0x9f,0x7b,0xc6,0x53,0x9c,0xff,0x61,0xeb,0xad,0x1b, + 0x81,0x7f,0x08,0x90,0x7e,0xfa,0xfc,0x0e,0xee,0x1f,0x4e,0x24,0x4e,0xf2,0xf8,0xf0, + 0x0b,0x88,0x7f,0x2e,0xa3,0xe6,0x63,0xc9,0xfd,0xf1,0x19,0x71,0x7f,0x7a,0xfe,0x19, + 0x13,0xf8,0xe7,0x67,0x52,0xb4,0x3c,0x28,0x85,0x91,0xd3,0xf8,0x55,0xeb,0x0e,0x8a, + 0x7f,0x38,0xbe,0xb2,0xad,0x17,0x0c,0x80,0x76,0x96,0x17,0xab,0x7e,0x5c,0xc1,0x61, + 0xcf,0x49,0xcd,0xdb,0xef,0x84,0x0a,0xff,0xcc,0xa0,0x03,0x76,0x83,0x78,0xac,0x76, + 0x60,0x23,0xed,0x51,0x91,0xef,0x23,0x35,0xfe,0x31,0x9b,0x25,0xd8,0x73,0x09,0x1d, + 0x67,0xf8,0x87,0x5d,0x3f,0xa8,0x7f,0x61,0x23,0x27,0xa7,0x21,0x22,0x84,0xbe,0xd3, + 0xc5,0x3f,0xec,0xfa,0x01,0xff,0x43,0x68,0x81,0x66,0x2b,0xf9,0x07,0xb4,0x3e,0x02, + 0x89,0x02,0x82,0x7f,0xd8,0xf5,0x03,0xfe,0x67,0x0a,0x6d,0x37,0x88,0xfe,0xb9,0x43, + 0xe0,0x9f,0xd4,0xf6,0x12,0xfc,0xcf,0x14,0xe5,0x7f,0xd6,0x03,0xbc,0x34,0x6e,0x7a, + 0xeb,0x4f,0xf2,0xfb,0x0d,0x09,0xfe,0xe7,0x55,0xfc,0x72,0x48,0xf5,0xcf,0xe2,0x13, + 0xcd,0xe3,0x43,0x8e,0xcf,0x63,0xcb,0x41,0xfd,0x8b,0xf3,0x3f,0x04,0xff,0xac,0x61, + 0x9f,0xf8,0xf8,0x9f,0x53,0x37,0x89,0xfd,0x6a,0xe7,0xd1,0x28,0xc6,0x03,0x22,0xad, + 0x9f,0xf7,0x8c,0xc5,0xfe,0xfa,0x97,0xa7,0x8e,0x3e,0x4f,0xd4,0xd1,0x93,0xdb,0xf8, + 0x27,0xef,0xa2,0x00,0xff,0xb3,0xd9,0x2c,0xea,0x00,0xed,0xec,0x26,0xf8,0x87,0xc3, + 0x9e,0xff,0xb4,0x19,0xff,0xc3,0xe3,0x8f,0x01,0xea,0x5f,0xa9,0x11,0xbb,0x51,0x02, + 0x42,0xaf,0xa6,0xb6,0x32,0xfd,0x33,0xf3,0xbf,0x84,0x7f,0x8e,0x12,0x3e,0x8d,0x18, + 0x77,0xb8,0x08,0x93,0xfb,0xf3,0x35,0xbe,0xbe,0x50,0x07,0xae,0x9f,0xa8,0xbb,0xe7, + 0x03,0x18,0xf3,0x5b,0x27,0xc0,0xff,0x4c,0x4b,0xfc,0x8f,0xc3,0x8c,0x98,0xe7,0x31, + 0xef,0xab,0xb3,0x21,0xf8,0xc7,0x6e,0x8e,0x6d,0x80,0xf7,0x9b,0xed,0xf9,0x7f,0xcc, + 0x57,0xff,0xf2,0xd0,0xce,0x21,0xb4,0xdb,0x05,0x42,0xde,0x27,0x97,0xd0,0x53,0xa1, + 0xf8,0xa7,0xc9,0x3c,0xa1,0xef,0x27,0xef,0x0b,0xb7,0xf7,0xf2,0x27,0xe8,0x24,0x6b, + 0x54,0x79,0x43,0xc5,0xff,0x9c,0xb6,0x47,0x0d,0x82,0x1f,0x7a,0xc9,0xf3,0x5b,0x4d, + 0x19,0xa1,0x94,0x57,0xc8,0x2e,0xf2,0xf8,0xb0,0xb7,0x7f,0x19,0x43,0x3b,0xbf,0xb1, + 0x2f,0xd8,0xab,0x89,0xfe,0x99,0xcb,0x7e,0x3e,0xb4,0x7e,0xed,0x7e,0xf5,0x71,0x50, + 0xff,0xe3,0xc6,0x93,0x36,0xe7,0xe9,0x02,0x12,0x69,0x4e,0x63,0xf8,0x47,0xbc,0xff, + 0x32,0xfc,0x83,0xf3,0x97,0x79,0xce,0x6e,0x29,0x56,0xfd,0x49,0x95,0x9b,0xbf,0xde, + 0xba,0xb8,0xe2,0x02,0x6b,0xe4,0x11,0xfc,0x8c,0xa7,0xff,0x71,0xa3,0xcd,0x41,0x13, + 0x5f,0x7f,0x2e,0xce,0x77,0x74,0xca,0xf2,0xae,0xff,0xb3,0x0a,0xb6,0x1e,0x39,0x4b, + 0x0d,0xbe,0xfe,0x97,0x68,0x17,0x5e,0x2f,0xf0,0xde,0xbb,0xac,0x70,0x1f,0xa8,0x7f, + 0xb9,0x61,0x67,0x88,0xf8,0xd3,0x04,0xf9,0x9d,0xc5,0x73,0x11,0xaf,0xf6,0xd6,0xf1, + 0xfd,0xce,0xa1,0xb3,0x6e,0xff,0x08,0xcf,0x2f,0x6f,0xb2,0xf8,0xf9,0x99,0xbf,0xfe, + 0xe5,0xf9,0x27,0x35,0x4a,0xd6,0x0b,0xff,0x30,0x61,0x86,0x54,0xff,0x32,0x78,0x3c, + 0xbf,0x8a,0x7e,0xe8,0x24,0x1d,0x28,0xf3,0x78,0xcb,0x35,0x26,0x00,0xff,0xd3,0x2d, + 0xf2,0xef,0x11,0xfb,0x56,0x67,0xc7,0x40,0x2f,0xd7,0xff,0x14,0xd1,0x8e,0x79,0xf4, + 0xab,0x69,0xa8,0xff,0x81,0xeb,0x6f,0x71,0x76,0xf4,0x6b,0x33,0x31,0x96,0xaf,0xcd, + 0x1d,0xa1,0xf8,0x87,0xf8,0xe7,0x08,0x89,0xc6,0x68,0x11,0xd7,0xff,0x4c,0x33,0xff, + 0x8c,0xf1,0xf8,0x83,0x7e,0x0a,0xd0,0xdd,0x11,0x74,0x83,0xf3,0x34,0xdb,0x6f,0xd5, + 0x10,0xce,0x47,0xc4,0x3f,0x1b,0x86,0x16,0x3b,0x42,0xff,0x53,0x0d,0xd2,0x3a,0xed, + 0xdf,0x71,0x54,0xf8,0x67,0x2b,0xf3,0x27,0xc7,0x3f,0x13,0xf1,0xab,0xfa,0xb5,0x86, + 0x16,0x09,0x36,0x87,0xf3,0x3f,0x84,0xf6,0x39,0x83,0x0e,0x4f,0xa6,0x25,0xda,0x27, + 0x9c,0xff,0xb1,0xaa,0x1a,0xb5,0x13,0xd8,0x2d,0x29,0x09,0xe6,0x85,0xf3,0x3f,0x39, + 0x82,0xaf,0xf0,0x6b,0x6c,0x5a,0x82,0x91,0xe1,0xfa,0x9f,0x9e,0x64,0x3f,0x71,0x4b, + 0x47,0xb3,0x04,0x0b,0x39,0x7e,0x0e,0xd4,0xbf,0x72,0x14,0x16,0xce,0x99,0xbf,0x52, + 0x03,0x21,0x3f,0xff,0x83,0x83,0x12,0xfe,0x7d,0xfd,0x27,0x56,0x88,0xde,0x0c,0xd6, + 0xbf,0x32,0x2e,0xfb,0xb7,0x13,0xdf,0xa8,0xc3,0xbe,0xcb,0x0e,0xe5,0x7f,0x48,0x5b, + 0x9c,0xc2,0x2d,0xa5,0xf8,0x9f,0x07,0x31,0x1e,0x38,0xe8,0xa3,0x41,0x42,0xf9,0x1f, + 0x0c,0x72,0x4c,0x82,0x7f,0xac,0xd6,0x09,0x48,0xfb,0x84,0xf3,0x3f,0xc8,0x85,0xcd, + 0x66,0x08,0x50,0x0c,0xf0,0x3f,0xc5,0xc4,0xa0,0xc2,0x2d,0x25,0xf8,0x1f,0x23,0x47, + 0xe2,0x8f,0xef,0x35,0x2a,0x94,0xff,0x59,0x55,0x34,0x1e,0xec,0x08,0x6e,0x33,0x9c, + 0xff,0xb9,0xdf,0xb8,0x01,0x7b,0x6f,0xd8,0x0e,0xf1,0xa7,0x9f,0xff,0x69,0x2f,0x24, + 0x66,0x30,0xec,0xb9,0x9a,0xc8,0xda,0x4f,0x03,0xfc,0x43,0x8c,0xac,0x92,0xff,0xd1, + 0xff,0xc5,0xa5,0x7d,0x6a,0x64,0xfc,0x53,0xa2,0xfe,0xf5,0x0c,0x4e,0x73,0x5f,0xe8, + 0xcd,0x6b,0xe1,0x6b,0x7e,0xb8,0xfe,0x87,0xb1,0x0d,0xbb,0x25,0xda,0xa1,0xa4,0xfe, + 0xa7,0xd4,0x7a,0x75,0xfd,0x0b,0x0d,0xc7,0x82,0xfd,0x5f,0xe1,0xfa,0x1f,0xb2,0xbb, + 0x66,0xf5,0x7e,0x41,0xfd,0x8b,0xe2,0x9f,0xbb,0x29,0x9f,0xa3,0x5f,0xb3,0xe4,0x6d, + 0x2a,0xf9,0x1f,0xd2,0xff,0xd5,0xb6,0x36,0x81,0xd7,0x9b,0x97,0x8c,0x66,0xf5,0xfa, + 0xa0,0xfe,0xc7,0x20,0x32,0x6c,0x8a,0x7f,0xd4,0xfd,0x5f,0x72,0xfd,0x2b,0x4b,0x64, + 0x06,0x64,0x77,0xa1,0xfb,0xf5,0xf1,0x3f,0x1d,0x8d,0xae,0x8c,0x3c,0xbd,0x56,0xed, + 0x4f,0x49,0xff,0x83,0xaf,0x3f,0x97,0x78,0x8e,0xc0,0x36,0x2b,0xe4,0xfa,0x03,0xf5, + 0xaf,0x75,0xee,0xfd,0x50,0x08,0xf1,0x4f,0x80,0xff,0x31,0x5d,0x6f,0x5b,0x21,0xfe, + 0xf7,0xeb,0x7f,0x32,0x6e,0x91,0xf2,0x08,0xc1,0x3f,0x80,0xf6,0x29,0xc5,0xff,0xb8, + 0x34,0x45,0xea,0x98,0xf2,0x79,0x51,0xe1,0x1f,0x0c,0x7b,0x0e,0xa0,0xe5,0x4e,0x99, + 0xfe,0x2f,0x5e,0xff,0xc2,0xb0,0xc7,0xf8,0x8a,0xe0,0x1f,0x40,0xfb,0x94,0xe2,0x7f, + 0x4a,0xc6,0x13,0xbf,0xfe,0xa7,0x7d,0x2a,0x79,0x4a,0xdb,0x62,0xfd,0x6a,0xf0,0x80, + 0x3a,0x7f,0x05,0xf4,0x3f,0x04,0xf6,0x3c,0x84,0x5e,0x6e,0x5a,0xad,0x8e,0x3f,0xb2, + 0xfe,0x87,0x14,0xf5,0x96,0x4c,0x6a,0x18,0x08,0x69,0x37,0xb3,0x65,0xb2,0xde,0x3b, + 0x80,0x7f,0xce,0x2e,0xa9,0xad,0xe8,0xd2,0x0f,0x0c,0x86,0xe4,0x3b,0x59,0xff,0xf3, + 0x39,0x6a,0x1b,0x4b,0xd6,0x12,0xd8,0x63,0x91,0xf7,0x77,0x6d,0xc6,0xad,0x38,0xa8, + 0xfb,0xbf,0x20,0xfe,0xf9,0x3a,0x15,0xe2,0x9f,0x80,0xfe,0x87,0xe8,0xeb,0x5a,0x71, + 0xb4,0x6f,0x51,0xc7,0x73,0x27,0x88,0x7f,0x06,0x35,0x92,0x88,0x49,0xfe,0xed,0x50, + 0xe8,0x99,0x03,0xf8,0xa7,0xd2,0xad,0x76,0x85,0xe4,0x6b,0x05,0xfe,0x31,0x29,0xcd, + 0x58,0x0c,0xc3,0x03,0xdc,0xfd,0xae,0xfe,0xc7,0xa9,0x19,0xa4,0xb0,0xd0,0x9f,0xdf, + 0xc3,0xf4,0x3f,0x4e,0x32,0xa7,0xd8,0x66,0x39,0xfe,0xe7,0x1a,0xe1,0x7f,0x88,0x0c, + 0x86,0xf7,0x7f,0x05,0xf8,0x1f,0xdb,0x0c,0xa0,0x9d,0x8e,0x6b,0x96,0xab,0x08,0x4a, + 0xcf,0xd8,0xa4,0x11,0xbe,0x26,0xa4,0xfe,0xc5,0x8d,0x81,0xd8,0xb3,0x8c,0x11,0xda, + 0x16,0x82,0x7f,0x7c,0x6e,0xac,0xf2,0x0c,0x93,0x94,0x1a,0x2b,0x15,0xf8,0x87,0x79, + 0x63,0x8d,0x6b,0x30,0xbd,0x9c,0xf9,0x46,0x09,0xfd,0x0f,0xf1,0xc6,0xf7,0x22,0xe2, + 0x1f,0xc9,0xdb,0x99,0xd4,0x07,0x5a,0x19,0xfc,0x03,0xae,0x7f,0x3f,0x7e,0x5f,0x88, + 0x80,0x7f,0x80,0x7f,0x12,0xe8,0x59,0xce,0x60,0x94,0xaa,0x7f,0xa1,0x97,0xfb,0x56, + 0x7e,0x8c,0x8d,0x65,0x56,0x04,0xfc,0x83,0xd1,0x8e,0xfe,0xa5,0xd6,0x3a,0x9e,0x6c, + 0x5a,0x91,0xb0,0xde,0x2e,0x5b,0xff,0x12,0xde,0xe8,0x89,0x5f,0xb9,0xf7,0x1a,0x5a, + 0x15,0xa5,0xfe,0x75,0x14,0x6d,0xc1,0x68,0x5c,0xd0,0x3e,0x65,0xeb,0x5f,0x31,0xda, + 0x6d,0xfa,0xd3,0x12,0xfd,0xef,0x92,0xfe,0xe7,0xe5,0xde,0x95,0xc5,0x1d,0x9b,0x6f, + 0xf9,0xd0,0xfe,0x9b,0xbe,0xf2,0xf5,0x2f,0xaf,0xad,0x60,0x09,0xbe,0xdf,0xfc,0xf3, + 0x16,0x6e,0x09,0xa9,0x7f,0x31,0xa3,0x54,0xff,0xbb,0xc4,0xff,0xc4,0x68,0x21,0x2c, + 0x58,0x8f,0x50,0xea,0x7f,0xa6,0x5c,0x19,0x0c,0x11,0x8a,0xbc,0x1e,0x11,0xff,0xc4, + 0x68,0xff,0xf5,0x27,0xc6,0x7b,0x51,0xf1,0xcf,0xa3,0x6e,0xe1,0x6c,0x7b,0x44,0xfc, + 0xe3,0x1a,0x27,0x98,0x42,0xe6,0xd5,0x70,0xfc,0xc3,0xbb,0xbd,0x28,0xff,0xe0,0xef, + 0x3f,0xf2,0xe3,0x1f,0x79,0x77,0x9f,0x94,0xc1,0x3f,0xe0,0x5b,0xaa,0x17,0x3a,0x57, + 0x78,0x1d,0x5f,0x76,0x35,0xc4,0x3f,0xba,0x1f,0xff,0xb8,0x68,0x27,0x46,0x8d,0x8f, + 0xd0,0x29,0xf7,0x93,0x8f,0x6d,0xf7,0xab,0xd8,0xdf,0x4a,0xf8,0x87,0xed,0x77,0x01, + 0x35,0x9a,0xd2,0xe3,0x68,0x6b,0x2c,0x63,0x2d,0x30,0x49,0x47,0x58,0x78,0xfd,0xab, + 0xc2,0xf3,0xa7,0x2b,0x04,0x92,0xfd,0xf9,0x24,0x8f,0x0f,0x80,0xff,0x99,0xd2,0x2f, + 0x69,0x9e,0x9e,0xe7,0x75,0xb4,0x45,0xba,0xfe,0x69,0xe4,0xc3,0x3f,0x6c,0xbf,0xcb, + 0x98,0xb1,0xa5,0x7c,0xfd,0xab,0xe0,0x0d,0x22,0x10,0xb4,0x8f,0xc0,0x3f,0xfc,0xfe, + 0x97,0xf8,0x9f,0x23,0x5a,0xb6,0x70,0x1f,0xe9,0x67,0x7c,0xaa,0x3c,0xfe,0x69,0x72, + 0xcb,0x5e,0xe3,0x37,0x36,0xf5,0x72,0x9a,0x42,0xd4,0xbf,0x74,0x15,0xff,0x43,0x8c, + 0x62,0x55,0x8e,0xd2,0xb6,0x65,0xf1,0xcf,0xe6,0xf8,0x0b,0xd4,0xa8,0xde,0x14,0x3f, + 0x89,0x7e,0x5d,0x1e,0xff,0xd0,0xe8,0xa1,0xb5,0x3a,0x35,0x80,0xdf,0xb8,0x1a,0x8a, + 0x7f,0x00,0xda,0x39,0xb5,0xf8,0x02,0x7a,0xbc,0x3c,0xfe,0xa1,0x57,0xbb,0xf0,0x47, + 0x13,0x55,0x0f,0x78,0xfd,0xef,0x0b,0xc8,0x27,0xbf,0x75,0xbf,0xfa,0x5c,0xc2,0x3f, + 0x12,0x3a,0x5a,0x92,0x0f,0xf6,0xcb,0x87,0xf1,0x3f,0xd4,0x40,0x5e,0x7f,0xf7,0x02, + 0xd0,0xdf,0x14,0xd0,0x3f,0x83,0x68,0x09,0xf6,0x3b,0x57,0x0e,0xff,0x10,0xa3,0x6f, + 0x3e,0xf8,0xe4,0x73,0x35,0xfe,0xb9,0x8b,0x47,0xef,0x7c,0xd2,0x89,0x9f,0x67,0x61, + 0xfc,0xb1,0x12,0xf8,0xc7,0xcb,0x56,0x56,0xcd,0x80,0x36,0x65,0x97,0xc3,0x3f,0xb7, + 0x12,0xbd,0x0a,0xfd,0x76,0xa2,0x6a,0x27,0xfe,0xdf,0x8f,0x80,0x7f,0x3c,0xff,0x58, + 0x95,0xe6,0xa2,0x89,0x32,0xf8,0xe7,0xa8,0x84,0x06,0x6d,0xa1,0xf7,0xee,0x2e,0x81, + 0x7f,0xbc,0xfd,0x5a,0x35,0x4e,0x2c,0xd8,0xbf,0x03,0xf0,0x4f,0x9d,0x54,0xff,0xba, + 0xab,0x73,0x40,0xc9,0xff,0xc4,0xb8,0xff,0x21,0xfe,0x39,0x6c,0xa7,0xbb,0x8c,0x28, + 0xfc,0x4f,0xa3,0xbb,0xbb,0xfd,0xe8,0xd6,0x8e,0x46,0x35,0xde,0xe3,0xfa,0xe7,0x79, + 0x00,0xff,0x1c,0x46,0xe9,0xbc,0x51,0x86,0xff,0x81,0xf9,0xf7,0x52,0xae,0x31,0x9f, + 0x50,0xe1,0xc3,0x30,0xfc,0x63,0xb7,0xa3,0x72,0xf8,0x07,0x81,0xfb,0xf3,0xe2,0xbd, + 0x6d,0x56,0x02,0xe2,0x2b,0x05,0xfe,0xa9,0x03,0xf8,0x67,0xc8,0xc9,0x76,0x36,0x46, + 0xe4,0x7f,0x28,0x5f,0xea,0x36,0x0e,0x9c,0x60,0xf8,0xa7,0x8c,0xfe,0x07,0x1d,0x1a, + 0x5b,0xb9,0xa9,0x33,0x22,0xff,0x43,0xd0,0xce,0x6c,0x67,0x9b,0x95,0x21,0xc6,0xdb, + 0xee,0x20,0x20,0x15,0xfe,0xa9,0x16,0xfe,0x21,0xc4,0x69,0x67,0x34,0xfe,0xc7,0xf3, + 0x3f,0x8e,0xde,0x88,0xb9,0xa5,0xa6,0x3c,0xfe,0x79,0x09,0xad,0x44,0x46,0x14,0xfe, + 0xc7,0xdb,0xdd,0x41,0x7b,0x55,0xde,0x88,0xc4,0xff,0x78,0xfe,0xec,0xc8,0x9e,0x33, + 0xa2,0xf0,0x3f,0x1e,0xda,0xb9,0x5a,0x68,0x1f,0xcc,0xf8,0xf8,0x9f,0x10,0xfc,0xe3, + 0x96,0x21,0x3a,0xda,0xb4,0x0d,0x11,0xf9,0x1f,0x9a,0xdd,0x1a,0xb1,0xff,0xaf,0x87, + 0xff,0x69,0xa0,0x32,0xe6,0xeb,0xe0,0x7f,0xb2,0x9d,0xca,0xf5,0xa1,0xfc,0x4f,0x26, + 0xd7,0x78,0x5d,0xfc,0x4f,0x1b,0x1a,0x88,0xc2,0xff,0x78,0xbb,0xbb,0x12,0xbb,0x3b, + 0x17,0x81,0xff,0x11,0xeb,0x51,0x7b,0xce,0x88,0xc6,0xff,0x54,0x11,0x3c,0x30,0x4d, + 0x1a,0xe1,0xcb,0xf3,0x3f,0xee,0xa6,0x3a,0x88,0x91,0xcd,0x19,0x91,0xf8,0x1f,0xe2, + 0xb4,0x3d,0xb1,0x17,0x53,0xd9,0x0e,0xb5,0x3f,0xfd,0xfd,0x5f,0xee,0xd5,0x8e,0xac, + 0x6b,0xcd,0x25,0x22,0xf1,0x3f,0xde,0xb7,0xbd,0x6d,0x7f,0x11,0x8d,0xff,0xf1,0xbc, + 0x6d,0xb5,0x99,0x35,0x51,0xf8,0x9f,0xac,0xbd,0x83,0xa0,0x9d,0x51,0xb4,0xaa,0xdf, + 0x88,0xc8,0xff,0x90,0xa7,0x63,0xd8,0xc8,0xe4,0x2a,0x55,0xcf,0x8b,0x52,0xff,0x7c, + 0x1a,0x1d,0xd4,0x57,0x3a,0xca,0xe7,0x57,0x89,0x7f,0x3e,0x44,0xe7,0xed,0xd6,0x7c, + 0x4d,0x44,0xfe,0x87,0xc6,0x13,0x9d,0xf6,0x7f,0x95,0xe4,0x7f,0x40,0xfe,0xd2,0x5b, + 0x9f,0x59,0x9d,0xe2,0xf9,0xab,0x3a,0x14,0xff,0x7c,0xc5,0xaf,0x3f,0x77,0x9b,0xa1, + 0xba,0x7e,0x14,0xe8,0xff,0xf2,0xd6,0xc7,0xbf,0xaf,0x8e,0x57,0x70,0xfe,0x0f,0x05, + 0x39,0x2e,0x8d,0x36,0x6c,0x35,0x20,0x65,0xbe,0x83,0xfa,0xe7,0x7d,0xb4,0x48,0xe1, + 0x76,0x73,0x9f,0xba,0xa5,0x4f,0x99,0xbf,0x42,0xf0,0x0f,0xbe,0x5b,0x86,0xca,0xf1, + 0x3f,0xc8,0x0d,0xda,0x35,0xb3,0x54,0xff,0xd3,0x62,0x27,0xca,0xf0,0x3f,0xb5,0x02, + 0xff,0xe8,0xc3,0x63,0x8d,0x7b,0xfd,0xf9,0xeb,0x16,0x35,0xff,0xe3,0x7e,0x6b,0x3f, + 0x52,0xec,0x57,0xf2,0x45,0x12,0xfe,0xe1,0xd9,0x6d,0x44,0xbf,0xd5,0xf1,0xc7,0xe7, + 0x06,0x35,0xff,0xe3,0xed,0xb7,0xd9,0xc9,0x94,0xe1,0x7f,0x40,0xfd,0x4b,0x3f,0x7f, + 0x1d,0xfc,0xcf,0x29,0x57,0xf6,0x9c,0x4a,0x74,0xc6,0xdb,0xcc,0x08,0xf8,0x67,0x67, + 0x3c,0x8b,0x8e,0xf6,0x66,0x53,0x95,0x7b,0xa3,0xe9,0x9f,0x07,0xb5,0x2e,0x7c,0x63, + 0x64,0x71,0x42,0x50,0xe8,0xeb,0xe4,0xfe,0x2f,0x8f,0x7f,0xa3,0x8e,0x6d,0xaa,0x7c, + 0x4e,0x0b,0x30,0x42,0x1d,0x0a,0xfe,0xc7,0x8c,0x93,0x41,0x49,0xad,0xa9,0x2e,0x57, + 0x3f,0xb6,0x45,0x9a,0x0f,0xa0,0xc0,0x3f,0x9e,0x2c,0x0a,0x25,0x8b,0x02,0x06,0x87, + 0xf0,0x3f,0x1f,0xb8,0x7c,0x2c,0x7d,0x30,0x73,0x4a,0x7d,0x6f,0x38,0xff,0x63,0x55, + 0xa5,0x62,0xdd,0x62,0x7e,0x42,0xa9,0xfa,0x17,0x75,0x8b,0x8d,0xdf,0x17,0x82,0x7a, + 0xb0,0x90,0xfa,0x17,0x6d,0x84,0x9f,0xa9,0xa0,0x13,0x11,0xc9,0xd8,0x9f,0x50,0xfc, + 0x93,0x21,0xfe,0xc1,0xbf,0xaf,0x3d,0x86,0x36,0x98,0x71,0x57,0x11,0x14,0x82,0x7f, + 0x6e,0x82,0xfe,0x89,0x3d,0x6e,0x27,0xff,0x2d,0x1a,0xfe,0xf1,0xf8,0x6a,0x3b,0xd9, + 0x5f,0x5a,0xff,0x1c,0x63,0xfc,0x33,0x89,0x1e,0xda,0x4a,0xbb,0x2a,0xaf,0xd0,0x4f, + 0x02,0xfc,0x63,0xbe,0x20,0xed,0x97,0xcc,0x3b,0x8a,0xaa,0x7f,0xc6,0x46,0xf7,0x44, + 0x55,0xab,0xc2,0x9f,0xa1,0xfc,0x4f,0xbb,0x9d,0x2c,0xee,0x88,0xa4,0x7f,0x16,0xb2, + 0xe7,0x6d,0x45,0xb4,0x39,0x32,0xff,0x63,0x25,0x77,0x5e,0x4f,0xfd,0x8b,0x14,0x52, + 0xaf,0x0b,0xff,0x84,0xcc,0xeb,0x2b,0xc9,0xff,0x94,0xc4,0x3f,0xf3,0xf2,0x81,0x6c, + 0x5b,0x12,0xff,0x30,0x3c,0x30,0x19,0xf7,0x1a,0xdb,0x73,0x51,0xf1,0x0f,0x95,0x3d, + 0xaf,0xdd,0x30,0x49,0x85,0x34,0xe5,0xf1,0x8f,0x96,0xa2,0x46,0x0d,0x33,0x28,0xfe, + 0x99,0x0e,0xc5,0x3f,0x83,0x9e,0xec,0x59,0x18,0xe5,0xf0,0x8f,0xfb,0x1f,0x51,0x29, + 0xe9,0xcf,0x5f,0xa4,0x46,0x87,0x02,0xff,0xd4,0xbb,0x97,0x9d,0xab,0xfa,0x3b,0xc5, + 0xf5,0x2b,0xf0,0xcf,0xf3,0xae,0xec,0xb9,0x93,0x16,0xc2,0x22,0xeb,0x9f,0x43,0x8c, + 0x20,0xfe,0xf1,0xd0,0x4e,0x0d,0x19,0xd4,0x13,0x19,0xff,0x50,0x03,0xe8,0x7f,0x4a, + 0xe1,0x9f,0xcd,0xec,0x69,0xdd,0x18,0x0d,0xff,0xf4,0x28,0x60,0x4f,0x59,0xfe,0x87, + 0xf1,0xf9,0x65,0xeb,0x5f,0x24,0x49,0xb5,0xb1,0x44,0xa6,0xa8,0x7f,0xe9,0x10,0xff, + 0x78,0x43,0x0e,0x1f,0x22,0x6d,0x5c,0x44,0xd8,0x5c,0xba,0xfe,0xe5,0xed,0x77,0x56, + 0x11,0xa6,0x4a,0xf1,0x3f,0xb7,0xbb,0x6d,0x3e,0xef,0xa8,0xeb,0x5f,0x3c,0x3e,0x70, + 0xfe,0xe7,0x30,0x93,0x95,0x16,0x14,0xfa,0x8d,0xcf,0x83,0xfa,0x67,0xee,0x8d,0xbd, + 0x8b,0x5d,0x63,0xbe,0xfb,0x49,0x56,0x5d,0xff,0x9a,0xef,0x45,0xef,0x31,0x22,0x0c, + 0x96,0xe3,0xf9,0x86,0xd9,0x15,0x8e,0xe5,0xe7,0x7f,0xd6,0xf1,0x6c,0x55,0xe8,0x8d, + 0x52,0xff,0xa2,0xdf,0xd2,0x46,0xb0,0xc1,0x8a,0x19,0x23,0xb0,0x5e,0x67,0xf7,0x03, + 0xe3,0x7f,0xc4,0x74,0x29,0x44,0x0c,0xbd,0x5c,0xfd,0x0b,0xb2,0x5b,0x91,0xf0,0x4f, + 0x8f,0xaa,0xfe,0x15,0x2b,0x51,0xff,0x9a,0xbf,0x05,0xcd,0x99,0x2d,0x4d,0x89,0x88, + 0xfa,0x1f,0xca,0xff,0x58,0x69,0x5b,0xc9,0xff,0xcc,0x72,0xff,0x37,0xc2,0xfa,0xd7, + 0x90,0x99,0x36,0x94,0xef,0xe3,0xa1,0xfa,0xe7,0xdd,0x05,0x54,0x9a,0xff,0x41,0x74, + 0xfe,0xb0,0x87,0x2e,0x46,0xec,0xa6,0x66,0x5d,0xe9,0x1f,0x7e,0xfd,0xbb,0x4c,0xc0, + 0xff,0xe0,0xf8,0x6c,0xaf,0x52,0xe2,0x43,0x90,0x7f,0xc5,0xf3,0xa8,0x5f,0x4a,0xdc, + 0x99,0x52,0xe2,0x73,0xa1,0x7f,0x66,0xfd,0x5f,0x2e,0x7f,0x95,0x48,0xf7,0x29,0xf9, + 0x2b,0xa1,0x7f,0x76,0x20,0x1f,0x78,0xc4,0x4e,0x2d,0x54,0xbe,0x7f,0xcd,0xf2,0xdb, + 0x21,0x8f,0x20,0xff,0x63,0xaf,0x28,0x54,0xaa,0xf8,0x90,0x39,0xbe,0x5e,0xe2,0x7f, + 0xce,0xa2,0xc3,0x7a,0x8d,0x52,0xff,0x53,0xc1,0xd6,0x5b,0x4b,0x21,0x3f,0x66,0xfe, + 0xeb,0x13,0xd5,0x5f,0x28,0xf1,0x0f,0xdb,0xaf,0x01,0xf9,0x9f,0xaf,0xed,0x66,0xa4, + 0x8e,0x57,0x42,0xff,0x09,0xf9,0x1f,0xda,0x7f,0x51,0x9a,0xff,0x41,0x90,0xff,0x39, + 0xd0,0xbf,0xbc,0x49,0xa9,0xff,0x81,0xfa,0x67,0x10,0xcf,0xf7,0x5b,0xe9,0x07,0x95, + 0xf1,0xe7,0x7d,0x81,0x7f,0x74,0x86,0x7f,0x70,0xd0,0xbe,0x8a,0xbe,0x1c,0x4a,0x2a, + 0xf9,0x1f,0xf1,0xfb,0x52,0x3e,0xea,0x0c,0xc9,0x47,0x42,0x4f,0xeb,0xce,0x7f,0x16, + 0x7a,0xd7,0xdc,0x09,0x25,0xff,0xc3,0xd7,0xdb,0xba,0xc8,0xb6,0xe6,0x88,0x1d,0xc6, + 0xff,0xb0,0xf0,0xc3,0xfb,0xbf,0xf8,0x74,0xbe,0xfe,0x32,0xfc,0x4f,0x2d,0xc4,0x3f, + 0x56,0x26,0x8c,0x0f,0x61,0xbf,0xcf,0xfa,0xbf,0xe8,0xee,0x2e,0xa3,0x65,0xa4,0xed, + 0x3d,0xb8,0x5f,0xd1,0xff,0x75,0x18,0xf2,0x21,0xd7,0xac,0x76,0xeb,0x69,0xd5,0x7e, + 0xcf,0xf0,0xf8,0x73,0x7b,0x1d,0xf0,0xcf,0x5f,0x1b,0x2d,0x6a,0x3d,0xcc,0x19,0xfe, + 0xfc,0xd6,0x23,0xa0,0x7f,0xbe,0x88,0xd2,0xc6,0x12,0x15,0xff,0x23,0xf4,0xc9,0x96, + 0xde,0x07,0x76,0x67,0x14,0x3a,0x94,0x78,0xef,0xdf,0x63,0x6c,0x7d,0xbd,0xbe,0x07, + 0xa2,0x9d,0x74,0x88,0x9e,0x8a,0x3f,0xef,0xde,0xfc,0x43,0x8f,0xff,0x19,0x6c,0xc6, + 0xdf,0xaa,0xf8,0x1f,0x7e,0x3d,0xd3,0x52,0xff,0x97,0xdd,0xd6,0xa3,0xdc,0xef,0x65, + 0x81,0x67,0x10,0xb8,0xdf,0xa6,0xad,0x66,0xc4,0xfd,0x5f,0xad,0xc4,0x3f,0x86,0x0e, + 0xf0,0xcf,0xe8,0xe4,0x8a,0x5d,0x4a,0xfe,0x67,0x8c,0x3f,0x5d,0xc6,0xcf,0xc1,0xf3, + 0x32,0x82,0x52,0x5b,0x79,0x7c,0x86,0x81,0x28,0xd8,0xff,0x45,0x9f,0xd6,0x43,0xc6, + 0xf2,0x47,0x42,0xf8,0x10,0x76,0xbf,0x35,0xd6,0x73,0xfd,0xf3,0x87,0xfa,0xdc,0x93, + 0x2d,0x1f,0x25,0x18,0xec,0xa9,0x06,0xf8,0xe7,0x38,0x8f,0x3f,0x92,0xfe,0xf9,0x22, + 0x1a,0x2d,0xc7,0xff,0xe4,0xf5,0x51,0x91,0xad,0xe6,0xec,0x96,0x86,0xe4,0x25,0x45, + 0xfe,0x9a,0x14,0x7a,0x63,0x04,0xf4,0xcf,0x2f,0xd5,0x2f,0xef,0x52,0xc5,0x9f,0x45, + 0x9f,0x89,0xe7,0x51,0xf0,0x3f,0xcf,0xa3,0xe7,0xd0,0x72,0x6b,0x7d,0x4f,0x45,0x70, + 0xbf,0xaf,0x59,0xfc,0x7e,0xab,0x75,0xdf,0xee,0xe3,0x34,0xdf,0x39,0xa9,0x9e,0x1d, + 0xaa,0xf8,0x33,0x09,0xf0,0xaa,0xbb,0xdf,0xef,0x0d,0xc5,0xf6,0xa1,0x23,0x83,0xcd, + 0x7f,0x15,0x57,0xed,0xf7,0xa4,0xa8,0xb7,0x2e,0x84,0xdd,0x5e,0xd6,0xe8,0x03,0x4a, + 0xff,0x4c,0xeb,0x02,0xff,0x80,0x78,0xfe,0x35,0x35,0xb4,0xe0,0xfb,0xfe,0x34,0xe7, + 0x7f,0x8e,0x49,0xf5,0x2f,0x27,0xdb,0xa3,0xd2,0xf3,0xa4,0x8b,0xc1,0xfe,0x2f,0xfa, + 0x6d,0x7f,0x76,0x16,0x1b,0xdd,0x0a,0xfe,0x87,0xdd,0x3f,0x86,0xe9,0xab,0x7f,0xa9, + 0xe2,0x73,0x87,0xb8,0x3f,0x51,0xbd,0xdc,0xdd,0x66,0xc1,0xb2,0x97,0xe0,0xbb,0x2a, + 0xb8,0xfe,0xb9,0xce,0x57,0xff,0x52,0xf3,0x3f,0x7f,0x14,0xa2,0xff,0x69,0x77,0x12, + 0xeb,0x14,0xfd,0x83,0x00,0xff,0xd4,0x4b,0x68,0x67,0xd5,0x69,0xa3,0x77,0x51,0x90, + 0xff,0x11,0xf8,0x47,0xd6,0xff,0xe8,0xdd,0xaf,0x18,0x2a,0x7e,0x03,0x9c,0x7f,0x01, + 0xeb,0x5f,0x47,0xb5,0x47,0x1d,0xa3,0x74,0xff,0xbb,0x4f,0xff,0xd3,0x96,0xef,0x1a, + 0xb8,0x27,0xc8,0x3f,0x8c,0xf3,0xeb,0xf7,0xf5,0x7f,0xb5,0x6d,0x54,0xeb,0xc3,0x95, + 0xf8,0x07,0x1b,0xad,0x6b,0xbb,0xfa,0xe2,0x99,0x80,0xbe,0xe5,0x5c,0x38,0xff,0x63, + 0xd8,0xf1,0x47,0x6d,0xff,0xfc,0xea,0xb3,0x00,0xff,0x74,0x49,0x78,0x18,0xaf,0xd7, + 0x6a,0x02,0xe7,0x83,0x00,0xfc,0xe3,0x9e,0x7f,0xc1,0xb3,0x7f,0xde,0x38,0xa5,0x3d, + 0x1c,0x98,0x87,0x0c,0xf1,0x4f,0x97,0xcb,0xff,0x50,0xb4,0x63,0xb6,0x5a,0x89,0x86, + 0x78,0x42,0x7b,0x05,0xc9,0x42,0x68,0x80,0x7f,0xea,0xa0,0x7f,0xf4,0xf6,0x8d,0xd8, + 0x38,0x5d,0x0a,0xff,0xd4,0xc9,0x6a,0xbd,0x89,0x84,0x8a,0xff,0x19,0x0b,0xeb,0x7f, + 0xcf,0x8c,0x19,0x4e,0xfc,0xa1,0x20,0xfe,0xe1,0xcf,0x7b,0x0a,0xe2,0x1f,0x7a,0x10, + 0x46,0xa7,0xf6,0x70,0x09,0xfc,0xb3,0x89,0xf3,0x3f,0x1d,0xd4,0x28,0xf6,0xdf,0xa6, + 0x98,0xb7,0xf0,0xbe,0x82,0xff,0x99,0x4f,0xd1,0xce,0xde,0xcc,0x74,0x7c,0x53,0x29, + 0xfc,0x13,0x0b,0x64,0x7f,0x3a,0xf6,0x27,0x2b,0xe3,0x1f,0x91,0x8f,0x24,0xfc,0x43, + 0x0e,0xc2,0x60,0x69,0x0e,0x02,0x83,0x90,0xfe,0xaf,0x11,0x04,0xf0,0xcf,0x32,0x91, + 0x7f,0xd3,0x45,0xfe,0xff,0x7b,0xbb,0x9f,0xff,0x31,0xa8,0x70,0x25,0x16,0x86,0x7f, + 0x1a,0x6b,0x65,0xfe,0x27,0x67,0xd4,0x7a,0x30,0xa0,0x52,0x8d,0x7f,0x60,0xfd,0xeb, + 0x30,0x36,0x78,0xfe,0x95,0xe6,0x3f,0xcf,0x67,0xeb,0x77,0xfa,0xf4,0x3c,0xb9,0xe4, + 0xec,0x3d,0x0a,0x3c,0x13,0x57,0xf6,0x7f,0x61,0x63,0x23,0xf6,0x4f,0xf0,0xfc,0x8b, + 0x33,0xe0,0xfc,0x0b,0xd0,0xed,0x8e,0xdd,0xfe,0x87,0x9e,0x10,0xda,0x8f,0x7f,0xd8, + 0xff,0x6f,0xa7,0x84,0x7f,0x50,0xa6,0xd3,0x58,0xd4,0x1b,0xc4,0x3f,0x6f,0x73,0x7e, + 0xbb,0x1e,0xf9,0xfd,0xb9,0xd3,0x9d,0xa7,0xbd,0x36,0x04,0xff,0xc8,0xfd,0x5f,0x5b, + 0xac,0x06,0x25,0xfe,0x89,0xb1,0xf5,0x13,0xa2,0xfe,0xb5,0x91,0x8c,0x81,0xb2,0xde, + 0x1a,0x54,0xf4,0xbf,0x5f,0x06,0xf7,0x8f,0xc4,0xff,0xb4,0xc6,0x36,0xf4,0x45,0xe7, + 0x7f,0x3e,0x83,0xb0,0x27,0xa9,0xc4,0x3f,0x80,0xff,0x71,0x0d,0x3e,0x8f,0x57,0x7a, + 0x1f,0x17,0xe7,0x5f,0x2c,0x04,0xf8,0xc7,0x9b,0xf6,0xf3,0x0e,0xed,0xff,0xaa,0x04, + 0xcf,0xef,0x84,0x38,0xff,0x02,0xd6,0xbf,0x5e,0xf6,0xda,0xbe,0xc4,0xf9,0x17,0x2f, + 0x07,0xf0,0x0f,0x8e,0xff,0x3f,0x11,0xef,0xfb,0x38,0xfb,0x1c,0x8a,0x07,0xe7,0xfb, + 0xc1,0xfa,0xd7,0xa8,0x94,0xad,0x26,0xde,0xba,0xb2,0x2d,0x98,0xbf,0x4e,0x09,0xfc, + 0x63,0xc2,0xf8,0xa3,0x53,0xa3,0xd6,0x13,0x22,0x8a,0xeb,0xff,0x98,0xaf,0xf7,0xeb, + 0x7f,0xc6,0xab,0x7a,0x5e,0x0b,0xc6,0xab,0xd7,0x6c,0xb6,0x3e,0x55,0x2b,0x55,0x37, + 0xb2,0x84,0x08,0xba,0xb7,0x04,0xfe,0xf1,0xe9,0x7f,0x68,0x74,0x0d,0xe6,0xf7,0x89, + 0x12,0xfc,0xcf,0x50,0x7c,0x9f,0xff,0x93,0x7b,0x04,0xfe,0x59,0x6e,0xfa,0xb2,0x5b, + 0x62,0x76,0x5b,0x9b,0x15,0xe8,0x7f,0x97,0xce,0xbf,0x80,0xf9,0xeb,0x58,0xe5,0x90, + 0x57,0x7f,0x49,0xaa,0xf1,0x8f,0x2f,0xdf,0x91,0x44,0xa6,0xea,0x7f,0xe7,0xf8,0xa7, + 0x36,0x90,0xfd,0x2b,0x06,0x02,0x78,0x3b,0x84,0xff,0x21,0x6c,0x98,0x37,0xf6,0x47, + 0x9e,0xff,0x5c,0xac,0xe0,0xfc,0x8f,0x0f,0xff,0xb8,0x85,0xbf,0x40,0x7e,0xff,0x7e, + 0x0f,0xff,0x07,0xb4,0x3e,0xb4,0x0b,0x35,0x92,0xf0,0x17,0x6e,0x20,0xf8,0xa7,0x23, + 0x7c,0x75,0x16,0x32,0x4b,0x19,0xf0,0xaf,0x0f,0x2d,0x47,0x86,0xa5,0x99,0xa5,0x8c, + 0x6f,0xf2,0xfb,0xe4,0x58,0x33,0x83,0x9d,0x6f,0x16,0x62,0x80,0xbf,0xd2,0x0b,0x5d, + 0xe3,0x9b,0xfc,0xfe,0xf5,0xfe,0x7d,0xcb,0xfc,0x6f,0x92,0xb3,0xfc,0x4e,0xa0,0xbf, + 0x44,0x4b,0x9d,0x12,0x86,0xfe,0x7b,0xff,0xfe,0xff,0xb2,0xff,0x75,0xd3,0x8e,0xe0, + 0xf3,0x18,0x8f,0x3f,0xd7,0xfb,0xd7,0xda,0x1a,0x65,0x55,0x32,0xf9,0x7b,0xfe,0xfc, + 0xff,0xc1,0x5f,0xfb,0xb5,0x6b,0xd7,0x9c,0x32,0xc6,0xff,0xe7,0xf5,0xdf,0xb2,0xe7, + 0xf1,0xbb,0x78,0xf8,0x5d,0x3c,0xfc,0x06,0xfe,0xff,0x2e,0x1e,0x96,0xfb,0xfb,0xb6, + 0xc5,0x9f,0x6f,0xd7,0x7a,0xc8,0x8f,0xc5,0xae,0xd9,0x2d,0xbb,0x12,0x17,0x5d,0xe1, + 0x74,0x84,0xfa,0xe0,0x82,0xa3,0xf6,0xee,0x62,0xf5,0x90,0x76,0xb5,0x14,0x3f,0x86, + 0x06,0x12,0x07,0x62,0x19,0xd6,0x76,0x9a,0xf6,0xf4,0x60,0xb1,0x50,0x7e,0xac,0x4e, + 0x62,0x23,0xd3,0xce,0x02,0x05,0x3f,0x09,0xf4,0x51,0xb1,0x5a,0xf0,0x76,0x70,0x20, + 0xd6,0xf4,0x8e,0xb2,0x7e,0xb7,0x35,0x96,0xf2,0xd6,0xef,0x42,0x90,0xff,0xa9,0x6c, + 0xcf,0x7b,0xb0,0xf9,0xf1,0x32,0xfc,0x58,0x0d,0x7d,0x0d,0x89,0xb5,0x4d,0x56,0xe3, + 0x9f,0x75,0xfc,0xbf,0x7f,0x4e,0x5d,0x1f,0x3c,0x6a,0x65,0x7b,0xb1,0x31,0x17,0x4d, + 0x1f,0x4e,0x8c,0x6e,0x84,0x8d,0x37,0x4b,0xd5,0x07,0xa5,0xfe,0x38,0xfb,0x47,0x96, + 0xb2,0x5e,0x26,0xd5,0x07,0xd9,0x7c,0xa4,0x01,0xc2,0x86,0x4d,0x56,0xc3,0xfa,0xa0, + 0x7e,0x20,0xd6,0xea,0x6c,0x68,0x5a,0x0c,0xf8,0x31,0x5f,0x7f,0x1c,0xd5,0x87,0x07, + 0xe6,0xc9,0x0b,0x7e,0x8c,0xf0,0xdb,0x1f,0xa0,0x35,0x4e,0xb5,0xeb,0x8d,0xdb,0x89, + 0x3e,0xff,0x77,0x29,0x3f,0x7f,0x08,0xf8,0x31,0xe9,0xfd,0x14,0xdd,0x86,0xdf,0x77, + 0xb4,0x13,0x76,0xf8,0xf9,0x68,0x48,0xe6,0xc7,0x56,0x2c,0xa7,0xfa,0x70,0x3f,0x1f, + 0x08,0xeb,0x83,0xd2,0xfb,0x69,0x43,0x02,0xb6,0xa5,0x84,0xf0,0x63,0xef,0xa3,0x35, + 0x76,0xb5,0xcb,0x86,0xdd,0x55,0x18,0x28,0xd0,0xf9,0xd8,0x84,0x16,0x8b,0xa9,0xf8, + 0x31,0xa9,0x3f,0xce,0x0a,0xab,0x0f,0x02,0x7e,0x03,0xb0,0x25,0x77,0x14,0xbc,0xfe, + 0xf1,0xed,0x01,0x7d,0x14,0x5b,0xcf,0xe7,0x43,0x0e,0x6a,0x53,0xfa,0x70,0x7f,0x7a, + 0x23,0x65,0xb7,0x5e,0x2c,0x3b,0x1f,0x12,0xcc,0x07,0x48,0x4f,0xd9,0xfe,0xf5,0x82, + 0x1f,0x23,0xe9,0x54,0x3e,0x0d,0xb6,0x36,0x3d,0x8e,0x9f,0x0a,0x5f,0x7d,0x90,0xcf, + 0x27,0xd9,0x6c,0xe4,0xe1,0xee,0x9a,0xc9,0x69,0x20,0x44,0x86,0x14,0x3a,0x1f,0x12, + 0xea,0xc3,0xbf,0x70,0xe7,0x5d,0x07,0xfb,0xe3,0xce,0x48,0xf3,0x91,0xde,0x13,0xfa, + 0xf0,0xbb,0xac,0xe4,0xcf,0xe2,0xe7,0x52,0xfe,0xfe,0xc1,0x33,0xd2,0x7c,0x6c,0xc0, + 0x86,0xa5,0xed,0xf5,0x76,0x7c,0x97,0xd6,0x1f,0xca,0x8f,0x59,0xf3,0xc6,0x7d,0xfb, + 0x5d,0xd4,0x31,0xce,0xc6,0x62,0x83,0xf3,0x61,0x99,0xff,0x77,0xca,0xf3,0x21,0xe9, + 0xf9,0x74,0x7b,0xd0,0x82,0xf0,0xfa,0x60,0x1d,0xb8,0xfe,0x2f,0xd0,0x9d,0x54,0x0f, + 0xaf,0xaf,0xd3,0xe4,0x7e,0x37,0x50,0x1f,0x8c,0xed,0x91,0x4e,0x8f,0xfd,0xb3,0xa4, + 0x98,0x8f,0xcd,0xd7,0xcf,0x07,0xf5,0x41,0xa9,0x3f,0x2e,0x45,0x8d,0xe0,0x7c,0x4e, + 0xc8,0x8f,0xed,0x05,0xf5,0xc1,0x42,0xd6,0x5e,0x5f,0xd0,0xee,0x4a,0x85,0xd7,0x07, + 0x1b,0xfb,0xb8,0x5e,0x37,0x41,0xe6,0xb3,0xe5,0xb1,0x91,0xb4,0x79,0x47,0x4f,0x80, + 0x1f,0x5b,0x8e,0x64,0x99,0x50,0x2e,0xfe,0x63,0x85,0x70,0x48,0xf0,0x63,0x8d,0x62, + 0x3e,0xd2,0x0b,0x3a,0x19,0x8b,0x34,0xff,0xe2,0xb6,0x1b,0x02,0xfa,0x28,0xc0,0x8f, + 0x2d,0x05,0xf1,0xfc,0x32,0xf1,0xc6,0xf0,0xfa,0x52,0xf5,0x41,0x0b,0xd6,0x77,0xce, + 0xdb,0xab,0xf3,0x03,0x17,0xef,0x29,0xc9,0x8f,0x49,0xf3,0x91,0x2c,0x1a,0x7f,0x4c, + 0x7c,0xd9,0x77,0xb8,0x9f,0x7c,0xc5,0xf4,0x51,0xfc,0x79,0xb4,0x25,0x3d,0xc3,0xcd, + 0xe3,0x0b,0x7a,0x14,0xe7,0x83,0x8c,0xf3,0xfa,0x20,0x99,0x0f,0xd9,0xc2,0xa2,0xcd, + 0x6a,0xb4,0xb1,0x07,0xc7,0x1f,0x84,0xfc,0xfe,0x04,0xf5,0x41,0x2f,0x7f,0x55,0x91, + 0x63,0xc8,0x2e,0xa3,0x35,0xf9,0xea,0xd9,0x2a,0xc3,0xbf,0x5f,0x0d,0xce,0x87,0x14, + 0xfe,0x21,0x07,0xcb,0x76,0x61,0xe3,0x53,0xb1,0x9e,0x29,0x88,0x02,0xf5,0xc1,0x9a, + 0x59,0x7a,0x1e,0x68,0xcb,0xbd,0xd5,0xee,0xa0,0x6c,0x39,0x9e,0x4f,0x81,0xfa,0x20, + 0xc8,0x5f,0xc3,0x76,0xca,0x32,0x86,0xb4,0x4f,0x03,0xe7,0x73,0x85,0xf1,0x63,0x5b, + 0x1f,0x71,0x6e,0x1c,0xd2,0x7e,0x87,0xfc,0xf5,0x20,0xc0,0x8f,0x41,0x3d,0xcc,0x01, + 0xed,0x11,0x6b,0x27,0x19,0x94,0xed,0x8b,0xcf,0xb0,0x3e,0xe8,0xd7,0x87,0x57,0xf7, + 0xe0,0xc7,0xc4,0x9f,0x5f,0x8a,0x1c,0x72,0x4b,0xfd,0x71,0xf4,0x7c,0xc6,0xd9,0xe0, + 0xf9,0x56,0xf3,0x45,0x7d,0x70,0x0c,0xde,0x3f,0x5f,0xd9,0xed,0x4e,0xa6,0x93,0xd6, + 0x07,0x6f,0x7b,0x5d,0xc2,0x3f,0xfc,0x3c,0x91,0x31,0x43,0x56,0x43,0xf5,0x54,0xf7, + 0x57,0x66,0x0a,0x47,0xed,0x15,0xb3,0x6a,0xfc,0x33,0x81,0xa4,0x7c,0xd4,0x78,0x2f, + 0xa9,0x0f,0xe2,0xe7,0xab,0x61,0x32,0x44,0x1f,0xa5,0xb3,0xfa,0x20,0x39,0x66,0x4e, + 0xcb,0x76,0x78,0xf5,0xc1,0x74,0x48,0x7d,0x70,0xa1,0xa4,0xcf,0x41,0xad,0xa6,0x31, + 0x20,0xc6,0x86,0x2b,0xf4,0x51,0x85,0x85,0xfc,0xfc,0x0b,0x5a,0x1f,0x84,0xf3,0xa3, + 0xb4,0x92,0xf5,0x41,0x6d,0x46,0x27,0xf3,0x19,0xa8,0xfe,0xfc,0x0d,0xa3,0xed,0x15, + 0x08,0xb4,0xe4,0xf9,0x90,0xa0,0x5f,0x20,0x3d,0x61,0x2c,0xc0,0xd7,0xbf,0xa2,0x73, + 0xd5,0xa9,0x6a,0xa5,0x3e,0xaa,0x28,0xdd,0x0f,0xa8,0xc1,0xe9,0x6c,0xc4,0xc6,0x62, + 0x27,0x83,0x81,0xe2,0xa2,0xae,0x20,0xfe,0x99,0x35,0x21,0xfe,0xe9,0xdf,0x95,0x37, + 0xa6,0x9f,0x74,0xeb,0x65,0x0b,0x94,0xf8,0x67,0x53,0xbd,0xa7,0x8f,0x5a,0x8d,0x61, + 0xcf,0x01,0xb3,0xc9,0xca,0x34,0xe0,0xcb,0x26,0xfd,0x71,0x09,0x01,0x84,0x34,0x70, + 0x3e,0x6c,0xad,0x8c,0x7f,0x2c,0x7a,0x90,0xee,0x7f,0xa3,0xf6,0x71,0x09,0xff,0xcc, + 0x63,0xfb,0x35,0x74,0x89,0x9d,0x7e,0xcc,0x62,0x83,0x92,0x26,0x13,0x4a,0xfc,0x73, + 0xc2,0xf0,0xf5,0xdb,0x26,0xac,0x38,0xf9,0x24,0x73,0xc2,0xe8,0xe9,0x60,0xf1,0x24, + 0xbe,0x1f,0xd6,0x07,0x4d,0x88,0xee,0x66,0xd7,0x6d,0x4e,0x53,0x63,0xca,0x50,0xe2, + 0x9f,0x2e,0x5d,0xee,0x3e,0x98,0x6c,0x6c,0xd5,0xf6,0xd1,0x4f,0x0c,0x35,0xfe,0xd1, + 0x65,0x7d,0x78,0xa1,0xfa,0x23,0x6a,0xb4,0xda,0x99,0x08,0xfa,0x28,0x72,0x50,0xd1, + 0x56,0x05,0x10,0x7a,0x46,0x5d,0x1f,0xfc,0x14,0xb5,0x6e,0xca,0xfc,0x43,0xdc,0x1d, + 0x0b,0x59,0x13,0xa9,0x3e,0x98,0x33,0x76,0x6a,0x53,0xc6,0x76,0x74,0xe7,0xfd,0x86, + 0x84,0x7f,0xd8,0x1f,0xab,0x0f,0xba,0xf3,0xb1,0x2d,0xbc,0x9e,0x0e,0x8a,0x5c,0x4b, + 0x85,0xcd,0x0a,0xfc,0x93,0x82,0xf5,0x41,0x32,0x16,0xc0,0x20,0x63,0x01,0xb6,0x22, + 0x7a,0x50,0x91,0xa2,0x3e,0xb8,0xf9,0x26,0xb6,0x29,0xaa,0xbe,0x5e,0x46,0xfb,0xd3, + 0xe9,0x7c,0x00,0xd8,0xa8,0x75,0x66,0xbe,0x52,0x1f,0x75,0xc9,0x1d,0x44,0x46,0xc7, + 0x1e,0xc2,0x46,0xb9,0xc5,0x50,0x1f,0x45,0x3e,0x5c,0xe3,0x76,0xd3,0xe3,0xf8,0xfc, + 0x48,0x82,0x08,0xcb,0xdf,0x44,0xed,0xf7,0x25,0x94,0xf8,0xa7,0x1e,0x81,0xfe,0xb8, + 0x8b,0x68,0x8d,0x99,0x29,0x68,0x45,0x32,0x16,0xd2,0x34,0xd4,0xf5,0x41,0x24,0xd5, + 0x07,0x53,0x79,0x7c,0x1b,0x8c,0xd3,0xb1,0x90,0x86,0x1a,0xff,0xd4,0x8a,0xfe,0x38, + 0x0c,0x3b,0x2b,0xf2,0xd8,0x9f,0xe3,0xda,0x76,0x24,0x0b,0xd5,0x64,0x7d,0xd4,0x08, + 0xbd,0x48,0xfa,0x6d,0xb3,0xd5,0xba,0xd3,0xfb,0xff,0xcd,0x28,0xf1,0xcf,0x84,0xbf, + 0x5e,0x5c,0xf3,0x8f,0x9e,0x11,0x5e,0x1f,0x9c,0x66,0xf8,0x67,0x1a,0xe3,0x9f,0x95, + 0xb4,0x3e,0x68,0xb4,0x19,0x19,0x25,0xfe,0x91,0xf4,0x51,0x87,0x9c,0x55,0xcf,0x19, + 0x64,0x3e,0xe4,0x68,0x6a,0xd5,0xa0,0xa1,0xd6,0x47,0xe9,0x72,0xf5,0xbc,0x68,0x34, + 0x3d,0x89,0x0d,0x87,0x18,0xde,0x8b,0xc3,0xfa,0xa6,0xb4,0xc0,0x3f,0xc8,0x04,0xd5, + 0xb1,0x83,0xd6,0xca,0x31,0x23,0x97,0x3a,0x6d,0x1f,0x44,0x2b,0x7b,0x81,0x50,0x6a, + 0x91,0xc0,0x3f,0xc6,0xce,0x87,0x05,0xda,0xf9,0x2f,0x57,0x16,0xf5,0x1b,0xe7,0x82, + 0xdd,0x5a,0x4c,0xa8,0xf1,0x4f,0xdd,0x3e,0x31,0x5d,0xf6,0x22,0x89,0x4e,0x83,0xd4, + 0x58,0x63,0x87,0xe8,0xa3,0xfa,0x46,0x4d,0x6f,0x9a,0x0d,0xed,0x6f,0x2a,0x24,0x26, + 0x68,0xda,0x6a,0x29,0xe8,0x6e,0xfe,0xba,0x8b,0xe2,0x1f,0x51,0x8f,0xf3,0xc5,0x1f, + 0xbb,0x3a,0x47,0x81,0xcd,0x0f,0x4c,0x03,0x54,0x0c,0x85,0x3e,0xca,0x5f,0x1f,0x1c, + 0x34,0xf2,0x9a,0x3b,0xd8,0x7f,0x81,0xb2,0x3e,0x68,0xf9,0xe2,0x8f,0xdd,0x48,0x07, + 0xb5,0xa1,0x46,0xf4,0x83,0x10,0x7d,0x14,0x17,0x75,0xd3,0xfc,0xe5,0x18,0x36,0x0e, + 0xb3,0x97,0xf1,0x8d,0xe4,0xbd,0x51,0x52,0xe9,0xc5,0x84,0xe8,0x47,0x58,0x08,0xfb, + 0x07,0xc9,0xc1,0x9d,0x7d,0x54,0x28,0x85,0xe3,0xc9,0x50,0x4c,0xd4,0x07,0xf9,0xfd, + 0xbf,0x9c,0xe2,0x1f,0x6f,0x3e,0x00,0x99,0x97,0x98,0x20,0xf9,0xee,0xa4,0xdd,0x96, + 0x8f,0x50,0x1f,0x24,0xe7,0xb9,0x37,0x3e,0x85,0x8d,0x5f,0xe4,0xb3,0x79,0x50,0x1f, + 0x5c,0x04,0xf1,0x4f,0xb7,0x09,0xdf,0xee,0x0b,0xf7,0xf5,0x6b,0x03,0xa8,0x3f,0x95, + 0xed,0x8f,0xa4,0x8f,0xca,0xa6,0xfa,0x51,0xc5,0x09,0xf2,0xfe,0x85,0xfe,0x54,0x5d, + 0x1f,0x84,0xfa,0x28,0x52,0x1f,0xac,0x20,0xfe,0x99,0x08,0xaf,0x0f,0xfe,0x5c,0xaa, + 0x06,0xde,0xed,0x54,0x93,0xfd,0x9e,0xf7,0x09,0xa5,0x44,0x7d,0xd0,0x79,0x42,0xd6, + 0x47,0xa5,0xca,0xcc,0x87,0x1c,0x93,0xf5,0x51,0xd9,0x14,0x19,0xe4,0x18,0xe4,0x7f, + 0xf8,0x7c,0xda,0xe3,0x68,0xc0,0x84,0xf7,0x03,0x52,0xea,0x75,0x05,0xfe,0x29,0x72, + 0xfc,0xe3,0x7a,0x0f,0xa9,0xe7,0x43,0xf2,0xfc,0xb8,0xd6,0xa7,0x8f,0xba,0x41,0xa9, + 0x97,0x0b,0x9f,0x8f,0x6d,0xab,0xf5,0x63,0xa1,0xf3,0x91,0x72,0xca,0xdf,0x0f,0xc3, + 0x3f,0x66,0xc8,0x7c,0x48,0x81,0x7f,0x26,0xa4,0xf8,0x63,0xca,0x6e,0x01,0xfd,0x71, + 0xec,0x7e,0x9b,0x95,0xf4,0x51,0x4f,0xc8,0x34,0x88,0xc0,0x3f,0x7c,0x3e,0x76,0xa7, + 0xd1,0x65,0x09,0x35,0x78,0xaa,0xd5,0x56,0xce,0x87,0x7c,0x5f,0xcc,0xc7,0xae,0xfb, + 0xa5,0x59,0xde,0x3f,0x62,0x3e,0x76,0x23,0xc4,0x3f,0x5f,0xda,0x4d,0x84,0xff,0x39, + 0x13,0xc0,0xe7,0x80,0xff,0xa9,0x0f,0xf2,0x3f,0x73,0xe8,0x3f,0xfc,0xfc,0x8f,0xd0, + 0x3f,0xf8,0xf8,0x9f,0x7c,0x19,0xfe,0x67,0x93,0x1c,0x7f,0x1a,0x66,0x29,0xff,0xe3, + 0x9f,0xb7,0x20,0xfa,0xd7,0xa6,0xeb,0x24,0x35,0x78,0xcb,0x9e,0x84,0xe0,0x7f,0x60, + 0x7f,0x1c,0xbb,0xfe,0xce,0x98,0x8c,0x7f,0xf4,0x10,0x7d,0x38,0xbb,0x7e,0xbf,0x3e, + 0x5c,0xad,0x7f,0x0e,0xc3,0x3f,0x76,0x56,0xad,0x4f,0x16,0xfc,0x4f,0x40,0x1f,0xa5, + 0x34,0x4e,0xaa,0xf1,0xcf,0xb0,0x2d,0x8f,0x45,0xe2,0x78,0x40,0xcc,0xc7,0xde,0xec, + 0x9f,0x0f,0x10,0xb5,0x3f,0x8e,0xd0,0x20,0xb4,0x3f,0x4e,0xb1,0xdf,0x15,0xca,0xf9, + 0xd8,0x04,0xff,0x78,0x86,0x9f,0xff,0x01,0xfd,0x71,0xf5,0x41,0x35,0x78,0x91,0xcd, + 0x47,0x12,0xf3,0x01,0x2a,0x42,0xf0,0x8f,0x6b,0x14,0x4a,0xf0,0x3f,0xfa,0x1e,0xbf, + 0xf7,0xd2,0xe3,0x81,0xf9,0x48,0xd2,0x7c,0x6c,0x43,0xe8,0xc3,0xf9,0xf5,0xfb,0xf9, + 0x1f,0xbe,0x5f,0xa2,0x8f,0x1a,0x41,0x21,0xb7,0x01,0xe7,0x7f,0xce,0x82,0xfb,0x07, + 0xf0,0x3f,0xd3,0x7c,0x50,0xa4,0xcf,0xff,0x21,0xf3,0xb1,0x47,0x7d,0xb4,0x0f,0x33, + 0xee,0x07,0xfd,0x71,0x22,0xfe,0x0c,0xa0,0x5d,0x34,0xfe,0x54,0xb8,0x13,0x5d,0x3c, + 0xbd,0x4a,0xb7,0x23,0xe9,0xc3,0x6d,0x88,0x7f,0x5e,0xa2,0x46,0xfa,0xb4,0xfd,0xf7, + 0xbe,0xe7,0x57,0xf4,0x43,0xf5,0xf7,0x3f,0xcc,0xf9,0x1f,0xf4,0x09,0x1b,0x94,0xed, + 0xe7,0x7f,0xc0,0x7c,0xec,0x3a,0x39,0xbf,0x93,0x6c,0x0e,0xe2,0xed,0x07,0xac,0xdf, + 0x84,0xc7,0x07,0xa8,0x0f,0xbf,0x32,0xd8,0x5e,0xac,0xb9,0x18,0xbf,0x06,0xf3,0xd7, + 0xaa,0xa9,0xe4,0x25,0x38,0x1f,0xdb,0x00,0xfc,0xcf,0x21,0xb4,0xf2,0x35,0x02,0x7b, + 0x82,0xe7,0x83,0x88,0xf9,0xd8,0x82,0xff,0x79,0x1e,0xc3,0xa4,0x3f,0x97,0x64,0x60, + 0xae,0xb1,0xbe,0x27,0x0d,0xe7,0x03,0x80,0xf8,0x33,0xec,0x7b,0xed,0x02,0xfd,0x71, + 0xfc,0x7a,0x44,0xfe,0xda,0x47,0xf6,0x5b,0xac,0x01,0x63,0x91,0x54,0xf3,0x01,0x62, + 0x92,0x7e,0x3e,0xa4,0x5f,0xac,0xe8,0xc3,0x3f,0x5e,0xf4,0x9e,0x0b,0x9b,0x0f,0x29, + 0xe6,0x63,0xef,0x42,0x0c,0xff,0xe0,0xeb,0x19,0xb2,0x6e,0x55,0xe7,0xaf,0x90,0xf9, + 0xd8,0x23,0x46,0xd9,0xf9,0x90,0x95,0x3a,0xe8,0x8f,0xdb,0xef,0xa3,0xc5,0x04,0xfe, + 0x11,0xf3,0xb1,0x6f,0xea,0x86,0xfb,0xa5,0xf3,0x21,0x83,0xfe,0x71,0x56,0x70,0xfc, + 0xf3,0xcf,0x7c,0x53,0xe4,0x7c,0xd8,0xbb,0x95,0xfb,0xfd,0x63,0xf1,0x3c,0xfe,0x0f, + 0x7b,0xd7,0x1e,0x1c,0xc5,0x71,0xe6,0x7b,0x1e,0x2b,0x8d,0xb4,0x2b,0x34,0x7a,0x2c, + 0xac,0x1d,0x20,0xa3,0x07,0xa0,0x73,0x84,0x58,0x0b,0xbf,0x72,0x70,0x30,0x5a,0x01, + 0x11,0x8f,0x98,0x8d,0xc1,0xa0,0xa4,0x54,0x57,0x63,0x17,0x55,0xf1,0x1f,0x9c,0x4b, + 0x38,0x57,0x17,0xe7,0x1e,0x76,0xaf,0x1e,0x80,0x2d,0xe7,0xbc,0xc1,0x9c,0xad,0x3b, + 0x53,0x75,0x22,0x21,0x39,0xd7,0x95,0xcf,0x07,0xc4,0x0f,0xce,0x76,0xd9,0x23,0x59, + 0x38,0x32,0xa7,0xc3,0x9c,0x8f,0x72,0x11,0x9b,0x32,0xb2,0x8b,0x4a,0x54,0x65,0xfb, + 0xac,0xe3,0xc8,0x19,0x12,0x1b,0xae,0x7b,0x5e,0xdd,0x33,0xd3,0xbd,0x3b,0x6b,0xec, + 0x4b,0x72,0xf6,0xfe,0xf5,0x63,0xb6,0x19,0x75,0x7f,0xdb,0xf3,0xf5,0x6f,0xbe,0xa7, + 0x59,0x15,0x66,0x3b,0x05,0xf3,0xe3,0xc0,0x13,0x72,0x90,0xed,0x14,0xac,0x8f,0x24, + 0x4f,0x86,0xac,0x7f,0x36,0x78,0xd4,0xc7,0xf7,0x98,0xf9,0x71,0x5c,0xe0,0xeb,0x8f, + 0xa6,0x04,0xa4,0xd1,0xe4,0x02,0x52,0x38,0xcb,0xf4,0xd5,0x07,0x78,0xd1,0x2f,0x0d, + 0x31,0xbc,0x1f,0x0a,0xd7,0x87,0x0c,0x83,0x42,0xf5,0x21,0x83,0x60,0xb4,0x50,0x7d, + 0x48,0x47,0x50,0xc4,0x22,0xed,0xf2,0x1f,0xf7,0xf7,0x0d,0xf8,0xbf,0x58,0xe0,0x4b, + 0x9c,0xfe,0xb0,0x7e,0xda,0x33,0xce,0xa9,0x0f,0x99,0x7c,0x3e,0x24,0x0d,0xaa,0xc2, + 0x7c,0xe1,0xfa,0x48,0xb8,0x2c,0xc3,0x2e,0x96,0x7c,0xb8,0xfd,0xd1,0x22,0xd6,0xc7, + 0xa6,0x56,0xb7,0xde,0xb2,0xff,0x44,0xa8,0x0f,0xc9,0x78,0xac,0x8a,0xd7,0x07,0xe0, + 0x00,0x5e,0x7d,0x48,0x1e,0x28,0x54,0x1f,0x80,0xcd,0x7f,0xdc,0xf1,0xe1,0xfa,0x00, + 0xa5,0xd5,0x47,0x2a,0xad,0x3e,0x76,0x84,0xfa,0x00,0x91,0xf8,0x0f,0xc7,0xff,0xc5, + 0x03,0x9d,0xdc,0xfa,0x90,0x14,0xa0,0xeb,0x2b,0xf2,0xfa,0xa3,0xf1,0x00,0xab,0x3e, + 0x92,0xb3,0xba,0x47,0xd9,0xeb,0xf5,0xe6,0x13,0xea,0x8f,0x16,0x00,0xb3,0x02,0xf5, + 0x91,0x82,0xfd,0xd1,0x82,0xf3,0x9f,0x6f,0xf3,0x1f,0x77,0x7f,0xfa,0xfb,0xa3,0xf1, + 0x00,0xb1,0x3f,0x14,0xad,0x0f,0x70,0x03,0xa7,0x3f,0x1a,0x2b,0x2d,0x8e,0xaa,0x0f, + 0xe0,0x7e,0xc2,0xf5,0x01,0x02,0xc0,0xaa,0x57,0x43,0xea,0x63,0x6b,0x42,0xd8,0xdb, + 0x15,0x06,0x94,0xff,0x4b,0x99,0x5f,0xc1,0x2d,0x0b,0x80,0xc1,0xf5,0x08,0x34,0x1d, + 0xe3,0xd5,0x07,0xb8,0x87,0xad,0x6f,0x29,0xff,0x57,0x32,0xca,0xf9,0x75,0x82,0xd4, + 0x47,0xba,0x8a,0xd2,0x3f,0xbf,0xa4,0x0a,0xd5,0x8e,0xf3,0xeb,0x63,0x17,0x5f,0x2f, + 0xe5,0xff,0x92,0x29,0xe9,0x05,0xdd,0xee,0x93,0x4e,0x04,0x3e,0x65,0x7f,0x6e,0x09, + 0xd5,0x87,0x0c,0x82,0xd1,0x8d,0x07,0xeb,0x8e,0xb1,0xeb,0x23,0xf9,0xf2,0xe5,0x37, + 0x52,0xff,0x91,0xd1,0x1f,0x2d,0x44,0x03,0xbe,0x4c,0xae,0xd4,0x11,0xfb,0x0f,0xae, + 0x0f,0xb0,0x8c,0x79,0x7e,0x49,0x1c,0xff,0xd7,0x76,0xf0,0x68,0xa1,0xf3,0x6e,0x56, + 0xc0,0xfe,0x03,0xc2,0xd9,0x61,0x0c,0xfe,0x43,0xec,0x3f,0x4a,0x38,0x5a,0xfe,0xbd, + 0x70,0x7c,0xb8,0xe8,0xf1,0x9f,0x79,0xbc,0xf5,0x7a,0xe0,0xc1,0x19,0x69,0xba,0x9c, + 0x97,0x1f,0x17,0xb9,0x3f,0x48,0x54,0xfe,0xc3,0xa8,0x8f,0xcd,0x5a,0xef,0x15,0xf0, + 0x9f,0x08,0xfc,0x64,0x82,0x57,0x1f,0x9b,0x03,0x3e,0x4b,0xfe,0x53,0xa0,0x3e,0x24, + 0x17,0xcc,0x94,0xc2,0x7f,0xf8,0xf5,0x21,0xb9,0xe0,0x8d,0x02,0xf5,0xb1,0x99,0xf6, + 0x1f,0x9a,0xff,0x84,0xba,0xf5,0x7d,0x9a,0xfc,0x67,0x14,0x44,0x59,0x2f,0xc5,0x7f, + 0xf6,0x7e,0xbe,0xf9,0x0f,0xa7,0x9f,0xc5,0x27,0xe6,0x3f,0x47,0xfc,0xfc,0x67,0xfe, + 0xa7,0xc2,0x7f,0xa8,0xfa,0x48,0xc3,0x5c,0xfe,0x53,0xfd,0xa9,0xf0,0x1f,0x10,0xe4, + 0x3f,0xc5,0xfa,0x83,0xd4,0x14,0xe1,0x3f,0xc1,0xfe,0xb0,0xc9,0x28,0xf3,0xa7,0xf8, + 0x8f,0xf0,0x29,0xf3,0x9f,0xc8,0xf9,0x71,0x9f,0x90,0xff,0xb4,0xfa,0xed,0x3f,0xfb, + 0x69,0xfe,0x13,0x0c,0xdb,0x63,0xf0,0x1f,0x5f,0x7d,0x48,0x2e,0xe0,0xf2,0x1f,0x0e, + 0x20,0xfc,0xc7,0xa4,0xfa,0xa3,0x45,0xe2,0x3f,0x91,0xf4,0x0f,0xe1,0x3f,0xaa,0xdb, + 0x1f,0xb6,0x30,0xff,0xf1,0x7e,0x2f,0x23,0xd2,0xfb,0x17,0xe1,0x3f,0x46,0x98,0xff, + 0x88,0xe1,0xf5,0x1e,0xf7,0xe6,0x33,0xc0,0xc8,0x8f,0xa3,0x81,0x1c,0xb0,0xff,0x98, + 0x5c,0xfe,0xe3,0xf3,0x7f,0x6d,0xa3,0xf9,0x4f,0xf1,0xf3,0xab,0x40,0x7e,0x5c,0x18, + 0xac,0x3f,0x58,0xcb,0x8b,0xff,0xe1,0xf2,0x01,0x6f,0x7f,0xc2,0x2a,0x1e,0xff,0x89, + 0x10,0xff,0xc3,0x03,0x75,0xd3,0x22,0xc5,0x7f,0x14,0x7b,0x93,0x74,0xd2,0x81,0x40, + 0xda,0xd2,0xf1,0x04,0x93,0xff,0x8c,0x0d,0x33,0x69,0x8f,0xd9,0x74,0x42,0xe1,0xf9, + 0xbf,0x58,0xcb,0xd4,0xb5,0x6e,0xda,0x30,0xc8,0x8a,0xff,0xf1,0x8b,0xf1,0x87,0x3a, + 0x5d,0x68,0x88,0xef,0xff,0xb2,0xc1,0x7f,0x83,0x5e,0x9d,0x2e,0xa4,0xf9,0xef,0x45, + 0xfb,0xc3,0xae,0xf0,0xfb,0x07,0x8b,0xf2,0x9f,0x76,0x93,0x8e,0x6f,0x99,0x09,0xf9, + 0xbf,0x24,0xdf,0xfc,0x5f,0x1c,0x69,0x7f,0x9d,0x9e,0x3f,0x5d,0x1f,0x89,0xa9,0x7f, + 0xa0,0x36,0x45,0xcb,0x87,0xf4,0x87,0xbd,0x10,0xa8,0x0f,0xe0,0x82,0xfd,0x53,0x74, + 0x3c,0x8c,0xcf,0xff,0xe5,0x06,0xf9,0xf8,0x68,0x4f,0xda,0x2e,0x94,0xed,0xd9,0x7f, + 0x28,0xff,0x17,0x53,0x3e,0xcb,0x7c,0xfe,0x62,0xe2,0xff,0x0a,0xc4,0xff,0x38,0xe0, + 0x43,0xd0,0xde,0xed,0xd3,0x57,0x5e,0xfd,0xcf,0xc9,0x14,0x53,0xff,0xc0,0x86,0x8c, + 0xdf,0xff,0xe5,0xca,0x33,0x54,0x1f,0x80,0x34,0x8a,0x65,0xfa,0xbf,0xb6,0xcb,0xcc, + 0xfd,0x06,0x1a,0xcf,0xfa,0xf4,0x0f,0xcf,0xff,0xe5,0x80,0x73,0x80,0x34,0x8a,0xcd, + 0x15,0xf4,0x7f,0xb9,0xe0,0x85,0x48,0xfe,0x2f,0x0f,0xe4,0xdb,0x75,0x2a,0xbe,0xa5, + 0xbc,0x40,0x7d,0x00,0x07,0x88,0x77,0xb7,0x94,0xe2,0xff,0xd2,0x17,0xfa,0x0a,0x65, + 0xf3,0xfc,0x5f,0x04,0x34,0x3b,0x85,0xb2,0x25,0xab,0x94,0x74,0x71,0xff,0xd7,0xd3, + 0x76,0x20,0x90,0x13,0x1a,0xc4,0xf6,0x7f,0x51,0x40,0x5f,0xe6,0x2b,0x94,0x4d,0xf9, + 0xbf,0xa8,0xf1,0x2a,0x71,0x84,0xc1,0x95,0xbd,0x74,0xfc,0x0f,0xb3,0x3e,0xa4,0xe1, + 0xa3,0x3d,0x5a,0x4b,0x74,0xff,0x17,0x38,0x14,0x28,0x0c,0xc5,0x8c,0xff,0xf1,0xff, + 0x10,0xe3,0x0a,0xdb,0xff,0xc5,0xe3,0x6f,0x86,0x2f,0xfe,0x87,0xf8,0xbf,0x6a,0xd8, + 0xfc,0x67,0xf9,0xed,0x4b,0xa8,0x2b,0x4c,0xff,0x57,0x80,0xf6,0xd0,0xf1,0x3f,0x2c, + 0xff,0x17,0xa0,0x68,0xcf,0x0b,0xea,0x92,0x7c,0x0b,0xbb,0x3e,0xa4,0xa7,0x7f,0x74, + 0x9f,0x7e,0x6e,0x9d,0xa1,0xf5,0x0f,0xc7,0xff,0x45,0x80,0xb2,0x38,0xdb,0xc2,0xf3, + 0x7f,0x31,0x69,0xcf,0xf2,0xa9,0x56,0xae,0xff,0xeb,0x2f,0x02,0xa7,0xb9,0xa5,0x46, + 0x74,0x9f,0x3e,0x21,0xef,0xbf,0x7b,0x5f,0x08,0x55,0x33,0xbe,0x04,0x2e,0xc1,0x9f, + 0x4e,0xd1,0xe7,0x97,0x49,0xf8,0xa7,0x9d,0x7f,0x31,0xea,0x9f,0xff,0xd3,0xa0,0x69, + 0x55,0x8b,0x8f,0xff,0xb8,0xe3,0xd9,0xf6,0x9f,0xa7,0x41,0x83,0x4e,0x17,0x86,0xa2, + 0xeb,0x43,0xb2,0xf4,0xcf,0x61,0x2f,0xf1,0xc7,0xbe,0xf2,0x0a,0x55,0x1f,0x20,0xe4, + 0xbf,0x60,0x9c,0x2f,0x1c,0xff,0x17,0xed,0x28,0xf4,0x05,0x66,0x70,0xfc,0x5f,0xa4, + 0x50,0x92,0x89,0x0b,0x05,0x30,0xfd,0x5f,0x4c,0xfe,0xf3,0x2f,0x46,0x5b,0x96,0x3e, + 0xbf,0x38,0xfe,0x2f,0x0f,0xa0,0x6d,0x66,0xd2,0xe3,0xa9,0xfa,0xd8,0xe1,0xfa,0x00, + 0x96,0x7c,0x5a,0x75,0xaa,0x90,0x78,0x86,0xf2,0x7f,0xf1,0xf8,0x0f,0xa0,0xe5,0x43, + 0xea,0x43,0xee,0x0f,0xd6,0x07,0xb0,0x03,0xa1,0x85,0x60,0x3d,0x28,0x86,0xfd,0xe7, + 0x9e,0xdf,0x47,0xfb,0x4f,0xb0,0x3e,0x12,0x1b,0x70,0xfb,0xa3,0xfd,0x5f,0xd9,0x7f, + 0xe4,0x2b,0xb3,0xff,0x14,0xf7,0x7f,0x55,0x5d,0x91,0xfd,0xa7,0x50,0x7f,0xb4,0xa2, + 0xf6,0x9f,0x08,0xf2,0xf9,0x14,0xfd,0x5f,0xd1,0xfa,0xc3,0x7e,0x6e,0xed,0x3f,0xbf, + 0x1d,0xff,0x57,0xe1,0xfe,0x68,0x85,0xec,0x3f,0x7c,0xff,0x17,0x27,0xfe,0xe7,0x4a, + 0xfd,0x5f,0xd1,0xfa,0xc3,0x46,0xb6,0xff,0x90,0xfa,0x48,0x62,0x41,0xfb,0x8f,0x67, + 0x7f,0x88,0x68,0xff,0x71,0xef,0x7f,0x85,0xf5,0xb1,0xb9,0xf6,0x1f,0xdd,0x1b,0x5f, + 0x9a,0xfd,0x27,0xd8,0x1f,0x8d,0x0d,0x38,0xfd,0x41,0x4a,0xaf,0x8f,0x5d,0xd4,0xfe, + 0x13,0xee,0x8f,0x16,0xb1,0x3f,0x6c,0x44,0xfb,0x0f,0x9b,0xff,0x04,0xe3,0x9d,0x0a, + 0xf5,0x47,0x63,0x01,0x56,0x7f,0x34,0x91,0x0a,0x84,0x7e,0x33,0xa8,0x3f,0x0b,0xf4, + 0x47,0x23,0xa0,0x9c,0xc1,0x7f,0x28,0xff,0x57,0x81,0xc0,0x06,0x7e,0x7f,0xb4,0x12, + 0xed,0x3f,0x9c,0x78,0x21,0x7e,0x7f,0x34,0xdc,0xbf,0x32,0x20,0x1f,0x89,0x5b,0x1f, + 0x29,0xd8,0x36,0x97,0xc1,0x7f,0x22,0xd9,0x7f,0xf8,0xfd,0x61,0x09,0xd8,0x96,0x38, + 0x4f,0x0a,0x45,0x06,0xf9,0xcf,0x2c,0x1f,0xdb,0xb9,0x13,0x3c,0xd7,0x77,0x27,0x54, + 0x7e,0x4c,0x1a,0x85,0x14,0xe3,0x3f,0x3f,0xc2,0xf9,0x14,0xb5,0x5e,0xa3,0x90,0x4c, + 0x61,0xfe,0x63,0xfd,0x22,0x3b,0x5b,0xf2,0xa4,0x51,0x48,0x71,0xfe,0xd3,0x06,0x13, + 0x0f,0xc5,0xbd,0x47,0xa9,0x28,0xff,0x91,0x57,0xc2,0xea,0xee,0xf8,0x5f,0x96,0xc0, + 0x7f,0x54,0xc4,0x3f,0x5b,0xd5,0xa8,0xfc,0x07,0xbd,0xad,0x29,0x07,0x2b,0xed,0xaf, + 0x86,0xa2,0xf1,0x1f,0x45,0xad,0x2c,0x21,0xfe,0x67,0xc9,0x54,0xcb,0x37,0x49,0xe3, + 0x8c,0x53,0xaa,0x7b,0x7f,0x3e,0xff,0x49,0x1c,0x8c,0x27,0xa2,0xf3,0x1f,0x7f,0x20, + 0x59,0x14,0xfe,0x93,0xc8,0xc7,0x5b,0x4b,0xe1,0x3f,0x4a,0xd6,0x4b,0xa4,0x6d,0x64, + 0xf3,0x9f,0x94,0x6f,0xbd,0x95,0xcb,0xc9,0x7a,0x23,0xf0,0x9f,0x93,0x95,0xd7,0x91, + 0x78,0xaa,0xe2,0xfc,0x67,0xc9,0xc8,0xac,0x69,0xa9,0x85,0xd8,0x7f,0xdc,0xf9,0x70, + 0xf8,0x8f,0xb8,0x02,0x2c,0x86,0xfd,0xa5,0xf0,0x9f,0x4c,0x62,0x6f,0xbc,0x39,0x3a, + 0xff,0x69,0xc5,0xf9,0x47,0xcd,0xa5,0xf0,0x1f,0x45,0x25,0xe3,0x8b,0xf3,0x1f,0xf4, + 0x7e,0x57,0x5f,0x89,0xbe,0x12,0x23,0xf3,0x9f,0x56,0x2a,0x11,0xbb,0x38,0xff,0xf9, + 0x2b,0xbd,0xfa,0x64,0x49,0xfc,0x27,0x5b,0x7d,0x5a,0x6a,0x2e,0x81,0xff,0x68,0xf1, + 0xdd,0xa4,0x51,0x48,0x24,0xfe,0x53,0x2f,0xca,0x25,0xf0,0x9f,0xae,0x38,0x2d,0xcf, + 0x20,0xff,0xe9,0x78,0x30,0x4c,0x63,0x86,0x87,0x9a,0x4b,0xe2,0x3f,0x7b,0x4a,0xe4, + 0x3f,0x03,0x44,0xfe,0x2c,0xfe,0x93,0x09,0xd3,0x9e,0x96,0x92,0xf8,0xcf,0x4d,0xe4, + 0x79,0x89,0xc4,0x7f,0x66,0xfa,0xe6,0xba,0xa6,0x95,0x48,0xfc,0xa7,0x3b,0x6e,0x7f, + 0xb5,0xf1,0xee,0x4e,0x1e,0xff,0x21,0xf6,0x1f,0x74,0x0c,0xd5,0x97,0xc8,0x7f,0x4e, + 0x7b,0xe7,0x57,0x53,0x24,0xfe,0xe3,0xe8,0x9f,0xf1,0xf8,0x8e,0x28,0xf1,0x3f,0x63, + 0x48,0xed,0xcc,0x8d,0xce,0x7f,0xd0,0x41,0xd0,0x6e,0xc9,0x73,0x3b,0x8f,0xff,0xf8, + 0xf5,0x27,0x52,0xb3,0x4f,0x5a,0xfa,0xf3,0x1e,0x7c,0xe5,0xdd,0x48,0xfc,0x87,0x65, + 0xff,0x61,0xc5,0xff,0x58,0x1a,0x7e,0x2c,0x91,0x95,0x96,0x83,0x12,0xf8,0x4f,0x65, + 0x9e,0x14,0x7e,0x8c,0xe2,0xff,0x52,0xe8,0xf1,0x7c,0xfe,0xe3,0x81,0x4a,0xea,0xbc, + 0xe3,0xf2,0x1f,0x0b,0xd8,0x12,0x4b,0xf4,0x92,0x42,0xc4,0x2c,0xfe,0xd3,0xe9,0x3f, + 0xdf,0xf9,0xfc,0x47,0xbd,0x0c,0x6f,0x8c,0x1c,0xff,0x63,0x62,0xfe,0x03,0x1a,0x8b, + 0xd9,0x7f,0x3c,0xfb,0xf3,0x44,0xcc,0x0b,0xa2,0x8b,0x6a,0xff,0x11,0x82,0xd9,0xee, + 0x04,0xb8,0xa9,0x76,0xc4,0xff,0x65,0xf1,0x1f,0x91,0xd3,0x46,0x87,0x61,0xff,0xe1, + 0xf9,0xbf,0xa2,0xe6,0x7f,0x15,0xb3,0xff,0x9c,0x62,0xef,0x87,0x82,0xf6,0x9f,0xe7, + 0x8a,0xbe,0x2f,0x50,0xfe,0xaf,0x68,0xf1,0x3f,0x94,0xff,0x2b,0x9a,0xfd,0xc7,0xf3, + 0x7f,0x05,0xfa,0xc3,0x72,0xec,0x3f,0xde,0xf3,0x18,0xcd,0xfe,0xc3,0xad,0x8f,0xcd, + 0xb3,0xff,0x78,0xfa,0x0d,0xfa,0xed,0x3f,0x7f,0x62,0x81,0x8a,0x42,0xfd,0x41,0x22, + 0xf9,0xdf,0x41,0x31,0xfe,0xc3,0xcd,0xff,0x8a,0x68,0xff,0x71,0xe7,0x1f,0xd5,0xfe, + 0xe3,0xce,0xff,0xb3,0xb1,0xff,0x1c,0xf7,0xf3,0x1f,0xbd,0x98,0x3d,0x84,0xf8,0xbf, + 0x3e,0x23,0xfb,0x8f,0x3f,0xff,0x4b,0x0f,0x0c,0x53,0xbc,0x0c,0xa9,0xef,0x7d,0x42, + 0xfb,0x0f,0xf1,0x7f,0x61,0xfe,0xa3,0x05,0x96,0x59,0x11,0xea,0x0f,0xe2,0xed,0x9f, + 0xc2,0xf6,0x1f,0x85,0x95,0xff,0x45,0xec,0x3f,0xdc,0xc4,0x2e,0xc2,0x7f,0xa6,0x23, + 0xd9,0x7f,0xce,0x95,0x68,0xff,0xe1,0xe4,0x7f,0x7d,0x36,0xf6,0x1f,0xa5,0xf8,0xf3, + 0x4b,0xfc,0x5f,0xd1,0xec,0x3f,0xef,0xd0,0xfc,0x47,0xf9,0x8d,0x5a,0x54,0x9f,0x10, + 0x7e,0x12,0xbb,0x24,0x5c,0xfe,0xc1,0xca,0xa9,0xf2,0x22,0xf6,0x1f,0x57,0x3e,0xbe, + 0xfe,0xb0,0x7c,0xfb,0x0f,0xc9,0xff,0xf2,0xf3,0x9f,0x05,0xec,0xf1,0x3e,0xfe,0xa3, + 0x50,0x61,0xcf,0x09,0x8e,0xfd,0x87,0xca,0xff,0x7a,0x5c,0x59,0x49,0x56,0xb7,0x90, + 0x63,0x3f,0x27,0xfc,0x47,0xbf,0x72,0xfe,0x53,0x28,0xff,0x0b,0x46,0xb2,0xff,0x14, + 0xf3,0x7f,0xb9,0x40,0x29,0xce,0x7f,0xd6,0x87,0xe4,0xb3,0x3e,0xc0,0x7f,0x98,0xfe, + 0x41,0x0c,0xbc,0x7c,0x7f,0x9a,0xff,0x7c,0xfd,0xa3,0x9a,0x52,0xed,0x3f,0x97,0xe0, + 0xd2,0xe6,0xc4,0x64,0x79,0x3b,0x98,0x84,0xd7,0x6a,0x55,0x93,0xd2,0xec,0x22,0xfe, + 0xaf,0x67,0x61,0x23,0x50,0xfa,0x44,0x6d,0x64,0xb7,0x82,0x00,0xc8,0x2c,0xb4,0x68, + 0xcf,0x2c,0xae,0xff,0xeb,0x59,0xc1,0x50,0x94,0x5a,0x51,0x86,0x10,0x34,0x6a,0x0a, + 0xa8,0x95,0x83,0xfb,0x21,0x60,0xff,0x79,0x56,0x46,0xb7,0x55,0xc5,0x55,0x60,0x37, + 0x40,0x00,0xa2,0xd7,0xae,0x82,0xf1,0xcf,0xea,0x6f,0x40,0xbb,0xd1,0xba,0x5b,0x6a, + 0x04,0xaf,0xc0,0xc3,0x30,0x71,0xb0,0xba,0x25,0x6c,0x1f,0x0b,0xe4,0x7f,0xbd,0xb8, + 0xaa,0x7a,0x54,0x3a,0xa8,0x7f,0xac,0xae,0x84,0xb3,0x66,0xe6,0x5c,0x08,0x15,0x12, + 0x0f,0xda,0x7f,0xfe,0xdc,0x48,0x0c,0x4b,0x0b,0xd5,0x57,0x60,0x3b,0x4c,0x1c,0x91, + 0x5a,0x42,0xf9,0xdd,0x7e,0xfb,0x0f,0x62,0xfb,0x86,0x32,0x8c,0xa6,0x7d,0x1f,0xd4, + 0xa0,0x72,0xa4,0xb6,0xc5,0x5f,0x0f,0x2a,0x64,0xff,0x39,0x0c,0xae,0x81,0x8a,0x26, + 0x2a,0xe0,0x7e,0xa0,0xe1,0xfe,0x20,0xb2,0x2a,0x59,0x62,0x51,0x27,0xdd,0xd2,0x01, + 0x7e,0xfb,0xcf,0xd3,0x70,0xf1,0x88,0x72,0x87,0xf8,0x25,0xb0,0x13,0xe7,0x83,0x77, + 0x89,0x37,0x84,0xf2,0xc1,0xfd,0xfe,0xaf,0x73,0xe0,0x0f,0x91,0x58,0xca,0x5b,0xc1, + 0x31,0x90,0xd6,0x13,0x20,0x2e,0xe3,0xfe,0x20,0x05,0xfc,0x5f,0x97,0x9c,0xb6,0x71, + 0xc2,0x25,0x5c,0x36,0xc1,0x94,0xfe,0xa7,0xb8,0xff,0x6b,0x2a,0xf1,0x58,0x27,0x12, + 0x0b,0xb4,0xf2,0x13,0x8f,0x89,0x41,0xf9,0x84,0xed,0x3f,0x2d,0x46,0x65,0x4a,0xdc, + 0x05,0xf6,0x63,0xed,0x71,0x0a,0xec,0x2a,0xea,0xff,0x52,0xee,0x16,0xe7,0x83,0x47, + 0xec,0xb0,0x9f,0x37,0x42,0xeb,0x0d,0xd8,0x7f,0xf4,0x56,0xb3,0x0b,0x67,0xcf,0x3d, + 0x84,0x89,0xf4,0x57,0x6b,0x5f,0x31,0x83,0xfd,0x56,0x02,0xf6,0x1f,0x75,0x45,0x3e, + 0x31,0x22,0x29,0xe0,0x0d,0xbd,0x1d,0x56,0x1f,0x90,0xde,0x65,0xe4,0xbf,0xbb,0xf3, + 0x41,0xfc,0x47,0xb5,0xca,0xfe,0x58,0x65,0x00,0x15,0xab,0x3f,0xc8,0x4c,0x34,0xff, + 0xd7,0x2f,0x20,0x4e,0xeb,0x4e,0xb0,0xf9,0x8f,0xdf,0xfe,0x73,0x67,0x36,0xbe,0x57, + 0xfc,0x25,0xb8,0x4f,0x6f,0xd3,0x2b,0xf7,0xd6,0x15,0xe7,0x3f,0x4b,0xf4,0xf8,0x09, + 0xf1,0x3c,0xf8,0x3e,0x02,0x0a,0x06,0xc5,0xfc,0x5f,0x8b,0x7b,0xe3,0x3d,0xe2,0x87, + 0x60,0xd0,0x5c,0x9c,0xad,0xec,0x11,0x4f,0x16,0xf5,0x7f,0xb5,0x82,0x6a,0xd0,0x64, + 0x22,0x35,0xbf,0x02,0x87,0xfd,0x84,0xd7,0x5b,0x38,0xfe,0x39,0x7c,0xe2,0x07,0xed, + 0x3f,0x2b,0xf5,0xc4,0x49,0xe9,0x57,0xb8,0xfe,0x8f,0x99,0x38,0x21,0x5d,0xe7,0x1f, + 0xbf,0x8b,0x11,0xff,0xac,0xe0,0x6a,0x36,0xea,0x11,0xa4,0x1f,0xaa,0xa0,0x18,0xea, + 0x0f,0xd2,0x18,0xb2,0xff,0x64,0x70,0xb4,0x0f,0x3c,0x34,0x4b,0x43,0xa0,0x2f,0x6c, + 0x01,0x0b,0xda,0x7f,0x5a,0xed,0x6a,0x3f,0x87,0x40,0xa3,0x5e,0x91,0x16,0xc3,0x8c, + 0x28,0x9c,0xff,0x95,0xd8,0x6b,0x95,0x79,0x3c,0x8c,0x7f,0xdf,0x66,0x06,0xff,0x71, + 0xf7,0xa7,0x93,0xff,0x95,0x59,0x52,0x90,0xff,0x30,0xe2,0x9f,0x07,0xe2,0x0d,0xe8, + 0xd8,0x64,0xd7,0x3f,0xec,0x0c,0xe6,0x7f,0x2d,0xf9,0x61,0x7c,0x4a,0xbc,0x09,0xfc, + 0x35,0x68,0x43,0x40,0xba,0x3b,0xd0,0x31,0x96,0x19,0xff,0x7c,0x5d,0x5f,0x02,0xf4, + 0x83,0xb6,0xa9,0xf5,0xe9,0x5a,0xa5,0x00,0xff,0x71,0xf2,0xbf,0x74,0xdc,0xa6,0xb9, + 0x66,0xd0,0x36,0x9b,0x74,0x17,0xce,0xff,0x42,0x24,0x67,0xf1,0x48,0xf5,0xb4,0xd4, + 0x0e,0x5e,0xc6,0x6c,0x67,0x5a,0xba,0xba,0x78,0xfc,0x33,0x5e,0xdd,0x7b,0xb8,0xed, + 0xb2,0x89,0xc0,0x74,0x01,0xff,0x17,0xce,0xff,0x3a,0x43,0x9f,0x56,0xb3,0x2e,0x48, + 0xbf,0x0e,0x9d,0x5f,0xa1,0xfc,0xaf,0x71,0xdc,0x9f,0x5a,0x7f,0x0a,0x2c,0x19,0x55, + 0xb2,0x48,0xff,0x78,0xf3,0xf7,0xea,0x1f,0xba,0xf7,0xc7,0xfc,0xc7,0xf1,0x76,0x9d, + 0xc0,0xf9,0xf2,0x66,0xa5,0x21,0xfe,0xbc,0x50,0xfc,0xb3,0x9b,0xff,0xa5,0x22,0xe9, + 0x1d,0xc4,0x66,0x10,0x80,0xa4,0x41,0xe4,0x69,0x37,0x42,0x3d,0xe5,0xcb,0xff,0x7a, + 0x93,0xf8,0xbf,0xac,0x42,0xbb,0xef,0x42,0x7e,0xfc,0xb3,0x63,0xff,0xd1,0xed,0x6f, + 0x75,0xeb,0x5b,0x4a,0x3e,0x76,0x46,0x58,0xd3,0xdb,0x41,0xfe,0x03,0xab,0xa7,0x84, + 0x19,0x2c,0x8d,0xe9,0xaa,0xf3,0x12,0x3e,0xef,0x96,0xf8,0xf4,0x39,0x95,0xff,0x65, + 0xe7,0xbf,0x83,0xf5,0xb8,0x4d,0xed,0x73,0x23,0x56,0x18,0xcf,0x74,0xd8,0x9f,0x65, + 0x10,0xfe,0xb3,0x5d,0xb0,0x2e,0x1e,0xc2,0xdf,0x6a,0x6d,0x7a,0x05,0x73,0x3c,0x33, + 0xfe,0x59,0x45,0xd2,0xd0,0x95,0xb4,0x25,0x9f,0xed,0xb6,0x7c,0x96,0x86,0xec,0x3f, + 0x8a,0x6b,0xe4,0x29,0x9f,0xb2,0x16,0x5e,0xe5,0xae,0xb7,0x58,0xfe,0x57,0xe7,0xf3, + 0x76,0xfd,0xba,0x19,0xe9,0x42,0x98,0xff,0x90,0xfc,0xaf,0xef,0x5f,0x00,0xaf,0x82, + 0xa5,0xf4,0x6e,0xe9,0x2c,0x68,0xff,0x41,0xf2,0x1f,0x2a,0x6e,0xff,0xf1,0x7e,0xdf, + 0x09,0xf0,0x80,0xda,0x2f,0x97,0x60,0xff,0x91,0x9f,0xa8,0x1d,0xd2,0x16,0x72,0xed, + 0x3f,0x62,0xb0,0xfe,0xa1,0xfc,0x04,0x62,0x23,0x4f,0x47,0xb6,0xff,0xe4,0xc0,0x93, + 0x68,0x51,0xcb,0x3c,0x69,0x8c,0x62,0xa0,0xb9,0xf2,0x49,0x85,0xf9,0x0f,0xc0,0xf7, + 0x6f,0x77,0xef,0xc6,0x30,0x34,0x8d,0xfa,0xf8,0xcf,0x85,0xfa,0x85,0xd9,0xa1,0xe1, + 0x90,0xfd,0x8a,0x6b,0xff,0x31,0xe5,0xc5,0x60,0xc8,0xd4,0x7c,0xd2,0x38,0x5e,0x20, + 0xfe,0x67,0x06,0xcc,0x17,0x73,0x81,0xe8,0xdf,0xb7,0x34,0x7e,0xfe,0xd7,0x1d,0x60, + 0x31,0x18,0x03,0x07,0x5d,0xb6,0x73,0x5d,0xd0,0xfe,0xa3,0x06,0xf9,0x4f,0xfd,0xe3, + 0xfc,0xb2,0x12,0x44,0x9e,0x9e,0xfe,0x51,0xe4,0x03,0x89,0x63,0x44,0x3e,0x45,0xe3, + 0x7f,0xa6,0xd5,0x7d,0xe8,0x19,0xe6,0xb4,0x85,0x65,0xd6,0x7f,0x7e,0x58,0xde,0xd5, + 0xb7,0xbf,0x84,0xf8,0x9f,0x7f,0x06,0x39,0x5d,0x2b,0xb2,0xdf,0x08,0xff,0x99,0x90, + 0x9f,0x85,0xc7,0xa9,0x68,0x67,0x07,0x88,0x7c,0xfe,0x33,0x22,0x06,0xdb,0xc2,0xbe, + 0xad,0x14,0xe0,0x3f,0xe0,0x27,0xc6,0x28,0x68,0xf7,0x9f,0xfe,0x05,0xf9,0xcf,0x02, + 0x78,0xdf,0x54,0xa3,0xd3,0x1f,0xd6,0x39,0x76,0x61,0x01,0xfe,0x23,0x37,0x8b,0x43, + 0x6a,0xa0,0x8d,0xa9,0xfe,0x55,0x91,0x5f,0xff,0x39,0x26,0xe6,0xf4,0x91,0xc8,0xf1, + 0x3f,0xdd,0x8a,0x89,0xf4,0x53,0x3b,0xc3,0xdf,0xc7,0xb3,0xff,0x20,0x1a,0x13,0xb4, + 0xe7,0x84,0xf9,0x8f,0x97,0x7f,0x91,0xaa,0xfa,0x55,0xdf,0xbf,0x19,0x7e,0xf9,0x84, + 0xfb,0xa3,0xbd,0x4c,0xd5,0x3f,0x9c,0x80,0xbb,0xb5,0x46,0xbf,0xd9,0x47,0xe6,0xc7, + 0xff,0x18,0x60,0x10,0xe6,0x0c,0x2d,0x72,0xfc,0xcf,0x11,0xc4,0x67,0xee,0xd3,0x39, + 0x6d,0x61,0x59,0xfc,0x47,0xfe,0x31,0x78,0x05,0xd1,0x1e,0x6b,0xb6,0x11,0xec,0x3f, + 0x13,0x60,0xa0,0xac,0x94,0xf8,0x1f,0x05,0xec,0x6f,0x34,0xc3,0xf2,0xe7,0xc6,0xff, + 0x28,0x03,0x5f,0x45,0xb4,0xa7,0xd1,0x67,0xed,0xb9,0xa8,0xf3,0xed,0x3f,0x8a,0x5c, + 0x0d,0xfa,0x60,0xb1,0xe7,0x85,0xf0,0x1f,0x01,0xcc,0x5d,0xb8,0x53,0x2f,0xf6,0xfc, + 0x12,0xff,0x97,0x02,0xaf,0x46,0xaf,0xd5,0x87,0x7c,0x6c,0xe7,0xf5,0x02,0xf1,0x3f, + 0x2d,0xf2,0x01,0x86,0x35,0xc3,0xbd,0xa2,0x86,0xf9,0x8f,0xfc,0x42,0xd7,0x24,0xf4, + 0x9d,0x5f,0xd2,0x1b,0xe0,0x83,0x3e,0x5e,0xfc,0xcf,0x3f,0x82,0xe7,0xdf,0xd9,0x69, + 0xbf,0x76,0x79,0xb3,0x3d,0xa5,0xbb,0xef,0x5f,0x72,0x28,0xfe,0x67,0x04,0x0c,0xab, + 0x3b,0x03,0xfa,0xea,0x64,0x28,0xf1,0x8d,0xd8,0x7f,0x70,0x7f,0xd8,0xfe,0x80,0x3c, + 0xcd,0x50,0xbf,0x4b,0xe2,0xff,0x52,0xd0,0xf9,0x75,0x6c,0x77,0x50,0x7f,0x06,0x1b, + 0xc1,0xd3,0xf1,0x3f,0x8f,0x63,0xa5,0xe4,0x7c,0x2b,0x58,0x20,0xd0,0x3f,0xee,0xcb, + 0x3e,0xfb,0x0f,0x38,0xd2,0x72,0x2e,0x54,0xf6,0xe7,0x4c,0x80,0x0f,0x10,0xff,0xd7, + 0xa8,0xbc,0x20,0xff,0x1c,0xf4,0x9f,0x5f,0x63,0xce,0xfb,0x7b,0xa3,0x7b,0xa5,0x9d, + 0xee,0x0f,0xdb,0x02,0x8e,0x04,0xc6,0x4f,0xeb,0x81,0x8c,0xf8,0x0c,0x65,0xff,0x51, + 0x13,0xe8,0x7d,0x7f,0xa4,0x88,0x7c,0x28,0xfe,0x33,0xbc,0x1d,0x6d,0xf2,0xc3,0x01, + 0xf9,0xbc,0x49,0xef,0x87,0x72,0xda,0xfe,0x03,0xc3,0xf1,0xcf,0x9d,0x81,0xfa,0xcf, + 0x0f,0x32,0xe2,0x7f,0x26,0xac,0xdd,0xf2,0x2a,0x06,0x33,0xc5,0xe3,0x9f,0xfb,0xda, + 0xb6,0x59,0x6c,0x67,0x08,0xb6,0xcd,0xc4,0x9f,0x67,0xf0,0x9f,0x50,0x7f,0xd8,0x51, + 0xdc,0xaf,0x53,0xe9,0x17,0x5a,0x4f,0xc4,0x9b,0x19,0xcf,0xd7,0xb9,0x60,0xfc,0x8f, + 0x8e,0xa5,0x9d,0x41,0x62,0x9f,0xb0,0x89,0x25,0xdf,0xfe,0x43,0xfa,0x5f,0x58,0x65, + 0xf7,0x5e,0xab,0x3e,0xd2,0x14,0x3e,0x7f,0x47,0xbd,0xf9,0xbf,0x8d,0xfb,0x5f,0x88, + 0xf7,0x9a,0xf6,0x32,0xb1,0x5b,0xf9,0x20,0xcb,0x3e,0xc6,0xee,0x0f,0x6b,0x99,0x35, + 0x46,0x3c,0xb7,0x63,0x8d,0x17,0xba,0x4f,0xf8,0xcf,0x31,0xb9,0xd5,0x2a,0x53,0x39, + 0x74,0xb8,0xf6,0xb8,0xb3,0x6d,0x32,0xad,0x2a,0xe1,0x6f,0xc1,0xfc,0xaf,0x77,0x04, + 0xcf,0xfe,0xfc,0x2a,0xec,0xcf,0xe1,0xfa,0x90,0x99,0xb0,0x87,0x74,0xc6,0xdb,0x0e, + 0xb7,0x0b,0xf3,0x65,0xdc,0x16,0x16,0x9f,0xfe,0x99,0x5d,0x36,0x08,0x7b,0xc4,0x7c, + 0xfd,0x2f,0x9c,0xfa,0xcf,0x9d,0x93,0xc6,0x4b,0xca,0x72,0x58,0xad,0x79,0x61,0x3f, + 0x9d,0xac,0xfe,0xb0,0x56,0xfc,0xcf,0x32,0x4c,0x9b,0x4f,0xeb,0x97,0xd5,0x95,0xe3, + 0xd5,0xff,0x45,0xc9,0x47,0xf7,0xec,0x3f,0xee,0x7a,0x9d,0xfa,0x5d,0x53,0xe8,0xb5, + 0x65,0x12,0xbc,0x04,0x91,0xa2,0xce,0xb3,0xfa,0xc3,0x12,0xfd,0xef,0xd4,0xdf,0x50, + 0xb0,0x1a,0xd9,0x05,0x1a,0xf0,0xe9,0x13,0x8e,0x28,0x38,0x47,0xf1,0x4f,0x6c,0xff, + 0x69,0x9d,0xaa,0xb4,0xcb,0x1e,0x36,0x8c,0xc4,0xbb,0x18,0xeb,0xa5,0xfc,0x5f,0xf6, + 0xfb,0xd7,0xb8,0x95,0x6d,0xd1,0x0f,0x90,0x22,0xba,0x4a,0xa4,0xdf,0x38,0x1c,0xff, + 0x57,0x30,0xfe,0x67,0xa4,0x4c,0x43,0x2f,0xa1,0xc7,0xc4,0x9f,0xa2,0x17,0xa5,0xb8, + 0x15,0xf6,0x03,0xcb,0x7d,0xfc,0xc7,0xbb,0xbf,0xe3,0xff,0x7a,0x10,0xd1,0x1e,0xfd, + 0x02,0x58,0xce,0xf3,0x7f,0xb9,0xe3,0x3d,0xfb,0xcf,0xdf,0x49,0xcd,0xe8,0xa0,0x6c, + 0xd3,0x37,0xa8,0x94,0x7d,0x40,0xf5,0xf8,0x8f,0x3b,0x9e,0xf2,0x7f,0x2d,0x02,0xb8, + 0xec,0x70,0x55,0xbe,0x32,0xec,0xe1,0x9a,0xf6,0x7e,0x5f,0xd2,0xff,0xe2,0xea,0x85, + 0xc0,0x29,0x53,0x1c,0x1e,0x4f,0xf9,0xbf,0x80,0x6b,0xfd,0x28,0x93,0x6b,0x71,0x19, + 0xc0,0x0a,0x55,0x0c,0xd9,0x43,0x1a,0xa9,0xfc,0x77,0xc5,0xb0,0xda,0xc2,0xa2,0x45, + 0xb5,0xe0,0xb2,0xab,0xd8,0xfe,0x13,0xee,0xbf,0x40,0xea,0x3f,0xdb,0xf6,0x9f,0x95, + 0xd9,0xea,0x7c,0xd3,0x79,0x1b,0x90,0xb0,0x9f,0x3a,0x56,0xfe,0xbb,0xed,0x3f,0xca, + 0x54,0x9f,0x90,0xfe,0x14,0xbc,0x8f,0x41,0xbe,0x3f,0xcc,0x07,0xa8,0xfe,0x17,0x4e, + 0xfd,0xc3,0x21,0xc4,0x76,0x70,0xdb,0x0b,0x35,0x3e,0xc0,0xf2,0x7f,0x91,0xfa,0xbd, + 0x6e,0xfc,0x4f,0x5a,0x0c,0xb7,0xf9,0xb0,0xc1,0x7a,0x35,0xf3,0x9a,0xe0,0x8e,0x4f, + 0xc5,0x6c,0x6b,0xcf,0x50,0x5e,0xfc,0x05,0x96,0xa7,0x21,0xe5,0x81,0x2b,0xc6,0x5a, + 0x4e,0xfd,0x67,0x67,0x92,0x76,0xbf,0xd7,0xf2,0x87,0x05,0x06,0xff,0x21,0xfe,0x0e, + 0x2f,0x1f,0x50,0xd8,0x56,0xc0,0xff,0xc5,0xe8,0x7f,0x51,0x37,0xd5,0x88,0xe4,0x2f, + 0x4c,0x52,0x61,0x3f,0x96,0x29,0x32,0x10,0xff,0x33,0xe0,0xf9,0xbf,0x7e,0x0e,0xef, + 0xd7,0xda,0xa0,0x32,0x22,0xdd,0x41,0xd9,0x7f,0xc4,0x36,0x5e,0x7f,0xd8,0xc6,0xe3, + 0x42,0x3f,0xb4,0xda,0x74,0x86,0x33,0x98,0xa8,0xfe,0x17,0x5e,0xfc,0xcf,0x5d,0xa7, + 0xd1,0xf3,0x8b,0x1e,0xcc,0x9b,0x18,0xfc,0x27,0x64,0xff,0x99,0xda,0x78,0xf7,0xa6, + 0xb7,0xc0,0xcf,0x72,0x7f,0x34,0xd5,0x86,0x0b,0x21,0x7e,0xe8,0x34,0x8a,0x55,0xc3, + 0xf5,0x9f,0xe7,0xb9,0xf9,0x5f,0x4d,0x93,0x22,0xd6,0x1e,0x55,0xac,0x7e,0xe8,0xbe, + 0xfe,0x17,0x56,0xfe,0x57,0xe2,0xc2,0xa6,0xb7,0x6a,0x5f,0xed,0xc3,0xc0,0x09,0xfb, + 0xd9,0x78,0xa1,0xee,0x92,0x9b,0x1a,0xe6,0xeb,0x7f,0xe1,0xea,0x9f,0xd3,0x70,0xd0, + 0x06,0x44,0xff,0xb8,0x85,0x10,0x89,0xfd,0xed,0x07,0xb6,0xff,0x6b,0x4c,0xd9,0x21, + 0x9e,0x56,0x10,0x4d,0x3a,0x81,0x14,0x4b,0x58,0x5f,0x11,0xfb,0x8f,0xd5,0x9f,0x5a, + 0xc0,0xf6,0xe7,0xda,0x49,0xdc,0x66,0x65,0x54,0x49,0xdf,0xef,0xea,0x9f,0x5a,0x57, + 0x9e,0x8d,0x54,0xfd,0xe7,0xe4,0xe3,0xf8,0x10,0x99,0x6a,0x45,0xfa,0xd3,0x32,0x9b, + 0xe3,0xb0,0xd2,0xd0,0x7a,0x8f,0x7b,0xfa,0x30,0x0f,0xde,0x4b,0xd8,0x17,0x9b,0x3e, + 0x00,0xb8,0x5e,0x34,0xeb,0x7d,0xb3,0x89,0xf4,0x87,0xcd,0xa9,0x1f,0x29,0x97,0xcb, + 0xd0,0xc5,0x99,0xba,0x8f,0xc0,0xab,0xf8,0xfe,0x0c,0x7f,0x50,0xf9,0x01,0x8a,0xff, + 0x6c,0x77,0x8a,0xd4,0x65,0x3e,0x90,0x87,0x02,0x69,0x5c,0x2c,0xfb,0x0f,0x3e,0xef, + 0xf0,0xdb,0xfd,0xb0,0xf8,0x9f,0x1a,0xe2,0x03,0x9c,0xf1,0xcc,0xfa,0x3f,0x65,0x98, + 0xf6,0x30,0xeb,0x43,0x52,0xf9,0xef,0x74,0xfd,0x9f,0x7f,0x95,0x57,0x98,0xcc,0xfe, + 0x56,0x23,0x65,0xee,0x7c,0x2c,0xfb,0x8f,0x68,0xd3,0x1e,0x95,0xef,0xff,0x5a,0xd8, + 0xeb,0xfd,0x05,0xbb,0xe9,0xde,0x77,0x2a,0xe7,0x8e,0x21,0x30,0xd9,0xb2,0xb4,0xf2, + 0x77,0xa2,0x1f,0xa2,0xdd,0x74,0x4f,0x98,0x2c,0x7e,0x7f,0x05,0x8a,0x74,0x77,0xbc, + 0xa5,0xd8,0x65,0xf6,0x45,0x3f,0xc4,0x4f,0x2c,0xff,0x70,0x3f,0x44,0x56,0x87,0x44, + 0xb9,0xc0,0xfd,0xe7,0x9a,0xa5,0xf5,0x43,0x54,0x4b,0x94,0xbf,0x5a,0x48,0xfe,0x8c, + 0x7e,0x88,0x09,0x33,0x24,0xf3,0x2f,0xfa,0x21,0x16,0x06,0x9f,0xe7,0xf1,0xbf,0x63, + 0xcf,0xe3,0x27,0xeb,0x0f,0xeb,0x44,0x0e,0x04,0xc0,0xef,0x8d,0x3e,0x9c,0x24,0xd2, + 0xfe,0x4e,0x40,0xfe,0x93,0xbf,0x2d,0x7d,0x68,0xdd,0xed,0x8b,0xfe,0xb0,0x81,0xcf, + 0x17,0xfa,0xf0,0xff,0xf9,0xf8,0xa3,0x1d,0x52,0xaf,0x7e,0x5a,0xbd,0x11,0x54,0x8d, + 0x5a,0x60,0x91,0x1c,0xfb,0x99,0xb4,0xc3,0xec,0x51,0xe7,0xd4,0x57,0x1d,0xc5,0x20, + 0x3b,0x47,0xae,0x32,0xaf,0xf5,0xc6,0xaf,0x5e,0x25,0xef,0x10,0x7a,0xf4,0xad,0x2a, + 0x18,0x8f,0xd9,0x20,0x49,0x80,0xe0,0x00,0xf3,0x5a,0x97,0x0f,0x03,0x28,0x0a,0x1a, + 0xec,0xd2,0x6a,0x15,0xd0,0xe7,0x00,0x99,0x02,0x0d,0xb0,0xcb,0x40,0xc0,0x6b,0x2f, + 0x83,0xb7,0xb8,0xd0,0x0b,0xba,0xc1,0x6c,0x30,0x08,0x05,0xc3,0x02,0xc9,0x01,0xe1, + 0x36,0xa1,0x1b,0x6c,0x49,0xc5,0x76,0x0a,0x06,0x06,0x20,0x46,0x8d,0x3f,0xda,0x1d, + 0xbb,0x41,0xf8,0x3a,0xdc,0xd4,0x21,0xef,0x8e,0xdd,0x25,0xf4,0xc0,0xad,0x5a,0x72, + 0xc2,0x03,0x02,0x02,0x23,0x08,0x50,0xf3,0x39,0xaa,0xeb,0x5a,0x56,0x91,0xc5,0x18, + 0xfa,0x4b,0x06,0x48,0x81,0x32,0x20,0x10,0x20,0xbb,0x80,0xac,0xf7,0x68,0x97,0x7c, + 0xbb,0x90,0x82,0x6b,0x34,0x70,0x9f,0xdc,0x28,0x28,0xf9,0x0c,0x50,0x77,0xcb,0x0d, + 0x82,0x02,0x32,0x9a,0x3a,0x20,0x6b,0x36,0xa0,0xc7,0xaf,0x8b,0xdd,0x32,0xba,0x79, + 0xe4,0xd6,0xd6,0xfa,0x59,0xb1,0x4c,0x2e,0x9b,0xdf,0xac,0xc4,0x2a,0x63,0x3a,0xcc, + 0x6a,0xf5,0x2d,0x49,0xd1,0x06,0xcb,0x93,0x80,0x92,0xcf,0x5c,0xa1,0x1c,0xdc,0x6a, + 0x26,0xb3,0x72,0x42,0xd8,0x8a,0x40,0x4d,0x6f,0xac,0x47,0xd8,0x04,0x36,0x9b,0xc9, + 0x74,0xec,0x8f,0x05,0x09,0x83,0x9b,0x64,0xaf,0xfc,0x2a,0x1a,0xaf,0xe9,0x0a,0xa8, + 0x05,0x32,0x44,0xca,0x06,0x69,0x3e,0x5d,0xd0,0x90,0x0a,0xec,0x84,0x2a,0x94,0x55, + 0x41,0x46,0xaa,0x01,0x03,0xd0,0x41,0xc9,0xc7,0x10,0x91,0xe8,0x81,0x86,0x54,0x87, + 0x05,0x1a,0xec,0x50,0x2c,0x7c,0x45,0xd1,0xca,0x1c,0xd0,0x41,0xc9,0x27,0x1b,0x6b, + 0x16,0xbe,0x09,0xb6,0xe8,0xf5,0x30,0xb6,0xcd,0x02,0xf3,0xf2,0x31,0x43,0x38,0x05, + 0xfe,0x0c,0x24,0xf3,0x31,0xcd,0x06,0xf4,0x7a,0xf5,0xb8,0x01,0x4e,0x81,0x1b,0xb0, + 0xe1,0xc4,0xfa,0xbd,0xb4,0x24,0x94,0x6e,0x07,0xdd,0x70,0x36,0xa8,0x22,0x80,0xda, + 0x3f,0x9d,0x72,0x3a,0x97,0xd0,0x3a,0xd1,0x5f,0x96,0xd3,0x30,0xa1,0x49,0x8a,0x3a, + 0x56,0x9f,0x1e,0xc5,0x57,0xd4,0x97,0x80,0x03,0xa8,0xdf,0x0b,0x7d,0xd2,0xe8,0x9d, + 0x4a,0xc2,0x3b,0xc3,0x01,0xa6,0x0b,0x26,0xbc,0x2b,0x94,0x7c,0x24,0x21,0x0d,0x37, + 0x68,0x75,0x78,0x77,0x59,0x20,0x51,0x3f,0x26,0xa4,0x73,0x1b,0xd2,0x9b,0x14,0xf9, + 0x98,0x0b,0xa8,0xf1,0x47,0x33,0x31,0x23,0xd7,0xad,0x6d,0x41,0xe3,0x1d,0x10,0x43, + 0x60,0x14,0x83,0x64,0xbf,0xa0,0xd9,0x00,0x52,0xf2,0xc9,0x58,0x92,0xf3,0x44,0x88, + 0xc0,0x18,0x02,0x78,0x21,0x68,0x45,0x0e,0xa0,0xd7,0x7b,0x8b,0x6c,0xe4,0x52,0xda, + 0x9a,0x2e,0xb0,0x07,0x81,0xab,0xb4,0x35,0x09,0x30,0x26,0x6f,0xcb,0x25,0xd2,0x9d, + 0x5d,0x35,0x7b,0x64,0xcd,0x06,0xb4,0x3c,0x8d,0x58,0xb7,0xb0,0x05,0xdc,0x0a,0xeb, + 0x35,0x07,0xc8,0xe8,0x0a,0x58,0x03,0x6a,0x60,0xd2,0x88,0xa5,0x6c,0xa0,0x53,0xfb, + 0xa7,0x4c,0xf8,0x06,0xec,0x31,0x92,0xc3,0xb1,0x32,0xa1,0x03,0xaa,0x86,0x9c,0x8a, + 0x95,0x81,0x0e,0x98,0x35,0xea,0x53,0xd6,0x15,0x0b,0x10,0x73,0x11,0x30,0x6b,0xad, + 0xbd,0x50,0xab,0xcb,0xb5,0x02,0x80,0x1d,0x9a,0x8a,0x9e,0x85,0x1a,0x79,0x40,0xd7, + 0xd4,0x2e,0xeb,0x8a,0x05,0xd0,0x31,0xe6,0xcd,0x67,0x8d,0x58,0x03,0x07,0x8c,0x05, + 0xaa,0xb0,0x46,0xfa,0x06,0xdc,0x6c,0x24,0x53,0x55,0x18,0x9c,0x34,0xae,0x47,0xa0, + 0xdc,0x01,0xd4,0x7c,0xc6,0xd7,0xc4,0x76,0xf4,0xf5,0x18,0x5b,0x53,0xc9,0x97,0x63, + 0x3b,0x72,0xfb,0x8c,0x6f,0xa7,0xe6,0x61,0x70,0xda,0xf8,0xae,0x7d,0xc5,0x02,0xb4, + 0x3e,0x59,0x23,0xec,0x80,0xa7,0x8d,0x1b,0x53,0x55,0x2f,0x4b,0x36,0x10,0x30,0xe8, + 0x31,0xe6,0xd8,0x57,0x2c,0x60,0xd6,0x50,0xe3,0xd1,0x4d,0xd0,0xfd,0xbb,0xc1,0xcb, + 0x36,0x48,0xa9,0x18,0x24,0x8c,0x4e,0x74,0x7f,0xd0,0x60,0x03,0xb3,0x86,0xda,0x3f, + 0x82,0x06,0xba,0xd0,0x13,0xe3,0xe9,0x9f,0xd8,0x18,0x02,0x3d,0xda,0x1c,0x5b,0x11, + 0x59,0x00,0x52,0xbb,0xad,0x4c,0xb8,0x0d,0x76,0x1b,0xb3,0x53,0xc9,0x9d,0x1e,0x00, + 0xb7,0xe5,0xba,0x0d,0x4b,0xff,0x34,0xd8,0x80,0x1a,0xbf,0x5a,0x4f,0xa6,0x85,0x0d, + 0x60,0x13,0x90,0x61,0xac,0x57,0xe8,0x01,0x5b,0x41,0xd2,0xf4,0x80,0x90,0x76,0x00, + 0x99,0xcf,0x6a,0xb4,0x7f,0x46,0x94,0x16,0xb1,0x12,0xed,0x1f,0x03,0xa6,0xd0,0x23, + 0x28,0x78,0xa0,0x1f,0xed,0x1f,0x0b,0x40,0x6a,0xbd,0xeb,0x64,0x63,0x3f,0xda,0x3f, + 0x95,0x78,0x77,0xe5,0x14,0x3b,0xc0,0xcb,0x03,0x86,0x0d,0xe8,0xf1,0x9d,0x0b,0xb2, + 0xa3,0x9b,0xdb,0x6f,0x55,0x06,0x91,0xb6,0xc9,0x65,0x35,0xa4,0x7f,0x10,0x18,0x40, + 0x6a,0x47,0x41,0xfa,0x27,0x0b,0x2d,0x00,0x28,0xf9,0x54,0x0a,0xd9,0x89,0xcd,0xe9, + 0xa4,0x22,0x77,0x0a,0x59,0x13,0x81,0x44,0x2c,0x0c,0x74,0x4a,0x3e,0x40,0x37,0x54, + 0x55,0x96,0x05,0xc4,0x38,0x33,0x58,0xdb,0x58,0x2a,0xd0,0x06,0x80,0x00,0x32,0x9f, + 0x8c,0xd8,0x08,0xe1,0x88,0xd6,0x35,0x2c,0x8a,0x00,0xc2,0xb4,0xa6,0x28,0x16,0xd0, + 0x10,0x90,0xca,0x2c,0x90,0x50,0xa8,0xf9,0xac,0xd6,0xcb,0x2d,0x25,0x2f,0x25,0x61, + 0xcc,0xd6,0xf6,0xf3,0xa0,0xab,0x7f,0x08,0x20,0xeb,0x1d,0xd4,0xe7,0x58,0xfa,0x47, + 0x1a,0x84,0x12,0x06,0xe8,0x74,0x30,0x25,0x43,0xee,0x01,0x73,0x90,0xda,0xa9,0xd1, + 0x80,0x0d,0xe8,0xf9,0xcb,0x69,0x21,0x01,0x3a,0xd1,0x5f,0xb6,0x80,0x84,0x9e,0x27, + 0x39,0x0d,0xf0,0x83,0xa5,0x9a,0x40,0x13,0x1c,0x40,0x0d,0xb7,0x95,0x8c,0x8e,0xf4, + 0xcf,0xb5,0x30,0x61,0x48,0xdd,0x60,0x2f,0xb8,0x0e,0x54,0x00,0x51,0x07,0x27,0xf5, + 0x66,0x0c,0xb0,0x46,0xa2,0xc6,0xcb,0xd7,0xea,0x1b,0xb2,0x75,0xf9,0xbd,0x47,0x05, + 0x04,0x3a,0x36,0xd5,0xd7,0x23,0xd0,0xb1,0x21,0xbb,0xa9,0x5e,0x1e,0xcf,0x35,0x60, + 0xa0,0xca,0xf4,0xf8,0x45,0xb1,0x3b,0x46,0xbf,0x95,0xde,0xb2,0x3b,0xf6,0x23,0x0b, + 0xcc,0xde,0x97,0xb4,0xc1,0x96,0x07,0x92,0xff,0x90,0x73,0x80,0x6f,0xfe,0x36,0xe3, + 0xc7,0xf3,0xb1,0xc8,0xa6,0x8e,0xe6,0xd3,0x6c,0xcf,0x27,0x2f,0x3b,0xf3,0xf1,0x8d, + 0xdf,0x66,0xd4,0xa4,0xe4,0x35,0xe8,0xf7,0x5a,0x85,0x0f,0xb2,0x32,0xad,0x66,0xb7, + 0x7c,0x7b,0x4d,0x6a,0x60,0x4d,0x43,0xcd,0xc0,0x2a,0x07,0xd0,0xe3,0xe5,0x8e,0x6c, + 0xcd,0x66,0xf9,0x56,0x74,0x98,0xc4,0x10,0x88,0x25,0x85,0xd8,0xaa,0xd5,0x59,0xb0, + 0x59,0x4e,0x82,0xa4,0xbe,0x3a,0xab,0x6e,0x4e,0x24,0x85,0x24,0xbd,0x1f,0x94,0x06, + 0x51,0xd1,0xfb,0x54,0x6d,0x50,0x69,0xc8,0x28,0xd9,0xbe,0x7a,0x04,0x84,0x4c,0x0a, + 0x83,0x98,0x72,0xdb,0x2d,0xf6,0x15,0x7a,0x3a,0x95,0x40,0x84,0x60,0x04,0xb4,0xa0, + 0x8d,0x27,0x42,0x7d,0x44,0x6d,0x91,0x11,0xc8,0xdb,0xc0,0x14,0x87,0xf5,0x03,0xea, + 0x35,0x34,0xdb,0x06,0x09,0xb1,0x0e,0x0c,0x98,0x0d,0xe9,0xd4,0x06,0x69,0x13,0x38, + 0x39,0x96,0x4c,0x57,0x21,0xa0,0x6e,0x36,0xaf,0x47,0xc0,0xac,0x53,0x4f,0x9a,0xd7, + 0xb7,0x57,0xd1,0xf3,0xa9,0x10,0xee,0xea,0xe8,0xc9,0x6f,0xd5,0xe6,0x61,0x1a,0x30, + 0x17,0x7e,0xdb,0x06,0xfb,0xe0,0x77,0x11,0x1f,0x58,0x73,0x97,0x70,0x1a,0x81,0xbf, + 0xa1,0xe5,0x1f,0x5f,0x97,0x79,0x3d,0xff,0xd4,0x81,0xc5,0x15,0x5f,0xc1,0xe0,0xc9, + 0x03,0x8b,0xd7,0xc6,0x6f,0x59,0x77,0x62,0xcf,0x53,0xcd,0xff,0x54,0x11,0xcf,0xac, + 0x3b,0x89,0xc1,0x1f,0xd0,0xf3,0x59,0x76,0xef,0xcd,0x97,0xff,0xe3,0xc5,0xf3,0xef, + 0x5f,0x5c,0x89,0xc1,0x33,0xe7,0x3f,0xb8,0xb8,0xec,0xd2,0xc6,0x33,0x0f,0x5d,0x3e, + 0xfb,0xf1,0xc5,0x65,0xf7,0x6c,0xbc,0x8c,0xc1,0xc7,0xe0,0x0a,0x3e,0x2b,0xfe,0xb6, + 0x62,0x61,0x66,0x6d,0x7e,0xcf,0xb6,0x05,0x17,0xab,0x7f,0xd2,0x79,0x39,0xff,0xeb, + 0x6d,0x2b,0xfe,0x7e,0xed,0xbd,0xaf,0xad,0xcd,0x3f,0xf2,0xf1,0xca,0xcb,0x6b,0x17, + 0xbd,0xb6,0xf6,0xfc,0x23,0x67,0xe9,0xf1,0x2b,0xef,0xb9,0xf9,0xcc,0x43,0xcf,0x9c, + 0x7d,0x9f,0x4c,0xc3,0x9e,0xd8,0xd9,0x0f,0xd0,0xf8,0x9b,0xcf,0x58,0x33,0xa4,0xc7, + 0x37,0xcd,0xef,0x3a,0xb3,0xe7,0xc6,0xb3,0x0f,0xdc,0xb6,0x0c,0xff,0xc7,0x43,0x67, + 0xdf,0x7f,0x1b,0x81,0xb7,0xea,0x9e,0x19,0x78,0xff,0x62,0x53,0xca,0x02,0xef,0x7d, + 0xcf,0x37,0xa1,0xbe,0x5e,0x7d,0x9f,0xba,0x48,0xbd,0x6f,0xb4,0x11,0x01,0x70,0xa3, + 0x5c,0x71,0x54,0xec,0xd5,0xe7,0xaa,0x8b,0xea,0x2d,0x80,0xbe,0x9a,0x5b,0x41,0xcb, + 0x53,0x1e,0xdc,0x01,0x10,0x09,0xac,0x05,0xe3,0x83,0x98,0x0d,0x6e,0xb2,0xf8,0x21, + 0x38,0xed,0x23,0x8a,0xf4,0x78,0x87,0x1f,0x5e,0x05,0xfa,0x73,0x18,0xcc,0x56,0xe4, + 0x9d,0x2e,0x3f,0xf4,0x00,0xf4,0x4d,0xc8,0x26,0x69,0xb9,0x20,0x7f,0x53,0x69,0x40, + 0x3e,0xca,0xaa,0xbb,0x84,0x04,0xec,0x8c,0xc3,0x89,0x6d,0xed,0xc2,0xdc,0x81,0xaf, + 0x69,0x35,0xc7,0x64,0xbc,0x31,0xbe,0x76,0x53,0xcd,0x84,0x0d,0xb4,0x1a,0xd3,0x7f, + 0x7f,0x55,0x29,0x43,0xfc,0x70,0x10,0xb1,0x2e,0xef,0xfe,0x0a,0x06,0x7d,0xe4,0x2f, + 0x92,0x4f,0x15,0xa2,0x85,0x88,0x1f,0x1a,0x00,0x3d,0x56,0x82,0x02,0x11,0x1b,0x1c, + 0x96,0x9b,0xd1,0x95,0x4c,0xaf,0xba,0x0f,0x33,0x46,0x98,0x31,0x7c,0xef,0x68,0x5f, + 0x91,0xd7,0x0d,0xce,0x7e,0x6c,0xf5,0x11,0x75,0xc9,0xc0,0xb7,0x72,0xb5,0x23,0xab, + 0x1e,0xab,0xb9,0x46,0xee,0x32,0x6f,0xb1,0xc1,0x3a,0xfb,0x0a,0x35,0x7b,0xb3,0x0a, + 0xd4,0x81,0xfa,0x89,0xd8,0xc3,0x60,0x12,0x4a,0xa0,0x1e,0x71,0x1f,0xfb,0xb4,0x31, + 0x63,0x36,0xa8,0xc7,0x40,0x27,0xff,0x01,0xbd,0xaa,0xaa,0x2a,0x7a,0x97,0xed,0x06, + 0xf8,0x29,0xc2,0x6f,0xa2,0x82,0x0a,0x56,0xa1,0x7f,0xc8,0x59,0x61,0xb6,0x6a,0xbd, + 0x34,0xeb,0x82,0xe7,0xbe,0x46,0xf7,0xb7,0x5f,0x57,0x35,0xd9,0xff,0xa6,0x2a,0xfb, + 0x5f,0x39,0xe9,0xf1,0xb2,0x61,0x2b,0x49,0xac,0xe8,0x53,0x48,0xe3,0x23,0xfd,0x69, + 0x08,0xc3,0x16,0x31,0x71,0xbe,0xaa,0x81,0xde,0x78,0x55,0xd0,0x45,0x03,0x0c,0x83, + 0xff,0x6d,0xdf,0x7c,0x5e,0xa4,0xb8,0x82,0x38,0x5e,0x6f,0xe6,0xed,0xa4,0xc5,0xd9, + 0xa5,0x7b,0x33,0x0b,0xad,0x2c,0x32,0xa3,0xab,0x1e,0xbc,0xf4,0x2c,0x0a,0x8a,0x07, + 0x9f,0xbb,0x33,0xeb,0xac,0xb0,0xda,0x44,0x54,0x08,0x39,0xb4,0xc1,0x8b,0xb7,0xec, + 0xcd,0x4b,0xe2,0x9b,0xcd,0x45,0xc4,0xc3,0xa2,0x22,0x0a,0x82,0x7b,0xd0,0xdc,0x84, + 0xfc,0x09,0x33,0x0b,0x19,0x48,0x4e,0x42,0x62,0x6e,0x21,0x1b,0xc8,0xc5,0xbb,0x10, + 0x72,0x90,0xb5,0xea,0xbd,0xfe,0xf1,0x7a,0xc7,0x08,0x7a,0x88,0x20,0xf5,0xbd,0xec, + 0x97,0xda,0x37,0x4d,0x75,0xbf,0x9a,0xea,0x4f,0xf5,0xcc,0x1c,0xa2,0x9e,0x65,0xcd, + 0x2e,0x32,0x61,0x66,0x4c,0x64,0x2d,0x4f,0x5f,0x75,0x17,0x2c,0x1f,0xf6,0x88,0x0f, + 0x0d,0x28,0xfa,0x9b,0x68,0x6e,0x67,0xc6,0xf2,0x61,0x7e,0xbf,0xa0,0x33,0x1f,0xe7, + 0xc3,0xf9,0xd4,0xa8,0x3c,0xa2,0xf2,0xf5,0x15,0xb0,0xd8,0x89,0xd8,0x96,0x9b,0xf9, + 0x41,0x39,0x32,0x28,0xe5,0x63,0xf8,0xad,0x0e,0x6b,0xd6,0x78,0x01,0x9a,0xe1,0x57, + 0xa9,0xb1,0x11,0x5d,0xe4,0x23,0xc6,0xf9,0x70,0xdc,0x14,0xf5,0x10,0x8b,0xb7,0x1e, + 0x1f,0x4f,0xb3,0x74,0x7c,0x27,0x1f,0x85,0x1b,0xd9,0x80,0x2e,0xa2,0x7f,0x6a,0x02, + 0x34,0xb8,0x5f,0x64,0xe6,0xd2,0xc8,0x42,0x9e,0x4f,0x4f,0x11,0x0d,0xce,0x26,0x9f, + 0x85,0xa2,0x06,0xab,0x86,0x0f,0x05,0x45,0xca,0xa6,0x28,0x9f,0x1e,0x7d,0xa5,0x44, + 0x67,0xf3,0x86,0xc6,0x7a,0x41,0x3e,0x14,0xf4,0x95,0x3b,0x6b,0xb4,0x31,0xe0,0xe4, + 0x73,0x09,0x69,0x50,0x27,0xad,0x18,0x2e,0x21,0x28,0xbe,0x30,0x58,0x98,0xf3,0x61, + 0x66,0x54,0x71,0x7f,0x17,0x4b,0x72,0xb5,0x3f,0x9b,0x9c,0x09,0x83,0xd1,0x7f,0x1b, + 0xe7,0xfa,0x23,0x76,0xae,0xea,0x47,0xc9,0x61,0x4b,0x83,0x64,0x76,0x8d,0xf0,0x44, + 0x66,0x8d,0xa9,0xa4,0x91,0x62,0x7d,0x8c,0x7c,0xd8,0x36,0x58,0x28,0x46,0xa9,0x99, + 0x19,0x89,0xd5,0xfe,0x6d,0x34,0x17,0x33,0x62,0x9c,0xd9,0x74,0xea,0x67,0x1a,0xc7, + 0x4c,0xe4,0x43,0x25,0xd7,0x45,0xa2,0x97,0xed,0x58,0x3a,0x87,0xdb,0x34,0xdd,0xc3, + 0x08,0xf5,0x1f,0xdf,0xed,0x3f,0x0a,0xcb,0xf5,0x8a,0x0e,0x93,0xda,0x03,0xf8,0x01, + 0xcd,0xde,0xa4,0x16,0x0a,0xe4,0x43,0xed,0x65,0x26,0x24,0x53,0xac,0x87,0x6e,0x22, + 0xaf,0xb7,0xa6,0xbc,0xc5,0x35,0xd8,0x90,0xc7,0xc5,0x3e,0x1c,0xd5,0x82,0x2d,0x79, + 0x1d,0xcd,0x19,0xc7,0x38,0xf5,0x2c,0xbe,0x40,0x1a,0xf4,0xa2,0x0a,0xce,0x0b,0x58, + 0x2d,0x7b,0xb0,0x5a,0xb0,0xed,0x5c,0x25,0x2c,0xec,0x89,0x3b,0x19,0x28,0x3a,0xf9, + 0x60,0xfd,0x34,0x4d,0x91,0xc0,0x2d,0xa2,0xc1,0x8d,0xa5,0x12,0x1f,0xa6,0xc6,0xad, + 0x9f,0x05,0xa9,0x86,0x8d,0x66,0xd7,0xf3,0x2b,0x32,0xee,0xfb,0x68,0x82,0x8a,0x54, + 0xda,0x6f,0x76,0x8c,0xe9,0x1b,0x03,0xce,0xf5,0xc1,0xf7,0xcb,0xa0,0x11,0x4d,0x78, + 0xf0,0x4b,0x13,0x06,0x8d,0x1f,0x45,0x5d,0x2c,0x42,0xac,0x31,0x82,0xa6,0x19,0x0f, + 0x8c,0x51,0xce,0xf5,0xf1,0xa8,0xff,0x10,0x1f,0x82,0xc2,0x69,0x14,0x70,0x3e,0xf5, + 0xe4,0x82,0xb0,0xa0,0xa8,0xc6,0xf8,0x10,0xf3,0xd9,0x3f,0x4d,0x7c,0x88,0xcd,0x60, + 0x3f,0x32,0xd9,0x7c,0x0b,0xf9,0x10,0x52,0x3e,0xcc,0x41,0xd1,0xc9,0x47,0xec,0xe8, + 0x3f,0xa5,0xb6,0x93,0x1b,0xe7,0xfa,0xa8,0xca,0x55,0x78,0x08,0x35,0xfa,0xe2,0x40, + 0x32,0xf1,0x30,0x6b,0x3b,0x1e,0x99,0xf5,0xbc,0x23,0x39,0xf9,0x24,0xb8,0x4d,0x53, + 0xb8,0x4d,0x9a,0xf6,0x0b,0x37,0x4e,0xfb,0x5b,0x70,0x5c,0xdc,0xc2,0x48,0xbc,0x95, + 0xfe,0xcb,0xe9,0x3f,0x31,0x9e,0xe0,0x09,0x35,0xf5,0x4d,0xf5,0x91,0x7e,0xba,0x11, + 0xa9,0xba,0x5f,0x95,0x30,0x84,0x48,0x79,0x64,0x7e,0x82,0x34,0xe2,0xd4,0x33,0xbe, + 0x53,0x8f,0xa9,0xc9,0xb8,0x1a,0xcb,0xfb,0xd0,0x3e,0x3d,0xa9,0xaa,0x0d,0x5c,0xd6, + 0x06,0x2f,0x46,0xf3,0x02,0xda,0xaa,0x4e,0x66,0xd3,0xc9,0x67,0x51,0x5e,0x19,0x86, + 0xd1,0x52,0x08,0xdf,0xcb,0x64,0x80,0xa6,0x1e,0xa0,0x19,0x1a,0x73,0x37,0x33,0x6e, + 0xff,0x51,0xc4,0x87,0x83,0x0a,0x3d,0xa7,0xdc,0xf9,0xd4,0xd0,0x89,0x14,0xd7,0xa7, + 0xd7,0x49,0xf6,0x84,0xb5,0x25,0xa1,0x75,0xe7,0x6b,0x1f,0x41,0xb1,0x15,0xdc,0xcc, + 0xb0,0xf0,0x81,0x1c,0xe3,0x43,0xec,0x3f,0x9d,0x8b,0xc1,0x8c,0xec,0x9e,0xf6,0xfd, + 0x4e,0xec,0x37,0x64,0x57,0x04,0xca,0x1a,0x08,0x3a,0x32,0x0e,0x6c,0xc4,0xa9,0x1f, + 0x2a,0xc0,0xfc,0xb9,0x83,0xbf,0x36,0x81,0x25,0x09,0xb6,0x36,0x45,0x6e,0x8a,0x7a, + 0x00,0x69,0xb1,0x50,0x95,0xf9,0xb0,0x9f,0x19,0x1b,0x71,0xeb,0x67,0xa5,0x7a,0x41, + 0xdd,0x7b,0xde,0x3a,0xaa,0x57,0x2a,0x55,0xf5,0xdb,0xf3,0x83,0x47,0x27,0x57,0xc4, + 0x05,0x34,0xc7,0xd0,0x54,0x53,0xe3,0xe4,0x23,0x90,0x07,0x90,0x0f,0xf1,0xa6,0xff, + 0xf3,0x1c,0xdd,0xfd,0x2f,0x37,0x0b,0x0c,0x78,0x2b,0x0f,0x1c,0xc9,0xf8,0x70,0xf7, + 0xd9,0xb3,0xc4,0x87,0xcf,0xae,0x1d,0x31,0x7c,0xf8,0xc4,0xf0,0xe1,0xef,0x64,0x96, + 0x9d,0xe5,0x70,0x2a,0xe3,0xc3,0x93,0x37,0xce,0x13,0x1f,0x6e,0xbf,0x3e,0x65,0xc0, + 0xec,0x95,0xe5,0xc3,0x5f,0xb7,0x5f,0x6d,0x97,0x78,0xec,0x7d,0x65,0xb0,0xf0,0xe5, + 0x3a,0x1e,0xf6,0xdf,0x14,0x14,0xe7,0x1e,0x2f,0x93,0x31,0x7c,0x68,0x22,0xdf,0xba, + 0xeb,0x0d,0x16,0xfe,0xf3,0x37,0xa5,0x91,0x81,0xe2,0x0d,0x63,0x2c,0x1f,0x52,0xa4, + 0xc4,0xab,0x27,0x33,0x3e,0x3c,0xb0,0xef,0xdc,0x9f,0x77,0xda,0xb4,0xfe,0xbb,0x73, + 0xa3,0xcf,0xe9,0x85,0x39,0x6a,0x7e,0x78,0xf6,0x11,0x8e,0x58,0xf8,0xb6,0xc6,0xbf, + 0x8b,0xf5,0x0f,0x3f,0x0a,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0xfa,0xd4, + 0x65,0x66,0x07,0xc9,0xb3,0x03,0x8b,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x7a, + 0xb7,0xcc,0xec,0x50,0xe3,0xd9,0x81,0xc5,0x62,0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62, + 0xbd,0x5b,0x66,0x76,0xf0,0xcc,0xec,0xf0,0xb1,0x53,0x61,0xb1,0x58,0x2c,0x16,0x8b, + 0xc5,0x62,0xb1,0x58,0xff,0xa3,0x22,0xfa,0x7d,0x1c,0x3c,0xfb,0x23,0x02,0x4d,0xbf, + 0x5a,0xa9,0x46,0xa0,0xde,0xfb,0xf3,0x84,0xf4,0xb5,0x13,0x11,0x6c,0x88,0xe2,0x98, + 0x7f,0x7d,0xb9,0x73,0xdd,0x1b,0x3b,0x1c,0x29,0xc2,0xf0,0x33,0x01,0x00, -- cgit v1.1 From ea9f6bce383cc9fbcdee28b5836109b1a6dba574 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Jul 2007 08:37:01 +0200 Subject: ppc4xx: Update 440EPx lwmon5 board support - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese --- board/lwmon5/sdram.c | 37 +++++++++++++------------------------ 1 file changed, 13 insertions(+), 24 deletions(-) (limited to 'board') diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index b6863b6..f906b85 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -473,7 +473,7 @@ static void program_ecc(u32 start_address, blank_string(strlen(str)); } else { /* ECC bit set method for cached memory */ -#if 1 /* test-only: will remove this define later, when ECC problems are solved! */ +#if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* * Some boards (like lwmon5) need to preserve the memory * content upon ECC generation (for the log-buffer). @@ -486,6 +486,11 @@ static void program_ecc(u32 start_address, current_address = start_address; while (current_address < end_address) { + /* + * TODO: Th following sequence doesn't work correctly. + * Just invalidating and flushing the cache doesn't + * seem to trigger the re-write of the memory. + */ ppcDcbi(current_address); ppcDcbf(current_address); current_address += CFG_CACHELINE_SIZE; @@ -514,19 +519,6 @@ static void program_ecc(u32 start_address, } #endif -static __inline__ u32 get_mcsr(void) -{ - u32 val; - - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; -} - -static __inline__ void set_mcsr(u32 val) -{ - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); -} - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -534,8 +526,6 @@ static __inline__ void set_mcsr(u32 val) ************************************************************************/ long int initdram (int board_type) { - u32 val; - #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* CL=3 */ mtsdram(DDR0_02, 0x00000000); @@ -640,14 +630,6 @@ long int initdram (int board_type) * Perform data eye search if requested. */ denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20); - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - val = get_mcsr(); - set_mcsr(val); #endif #ifdef CONFIG_DDR_ECC @@ -657,5 +639,12 @@ long int initdram (int board_type) program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); #endif + /* + * Clear possible errors resulting from data-eye-search. + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + set_mcsr(get_mcsr()); + return (CFG_MBYTES_SDRAM << 20); } -- cgit v1.1 From d2f68006627eda6cb6c7f364bddf621dbfd2fc68 Mon Sep 17 00:00:00 2001 From: Eugene OBrien Date: Tue, 31 Jul 2007 10:24:56 +0200 Subject: ppc4xx: Update AMCC Bamboo 440EP support Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien Signed-off-by: Stefan Roese --- board/amcc/bamboo/bamboo.c | 321 ++++++++++++++++++++++++++++++------------- board/amcc/bamboo/init.S | 3 +- board/amcc/bamboo/u-boot.lds | 2 - board/amcc/common/flash.c | 18 ++- 4 files changed, 240 insertions(+), 104 deletions(-) (limited to 'board') diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index caf6690..00c793a 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -unsigned char cfg_simulate_spd_eeprom[128]; +#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) +/************************************************************************* + * + * Bamboo has one bank onboard sdram (plus DIMM) + * + * Fixed memory is composed of : + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data + * + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module + * + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +const unsigned char cfg_simulate_spd_eeprom[128] = { + 0x80, /* number of SPD bytes used: 128 */ + 0x08, /* total number bytes in SPD device = 256 */ + 0x07, /* DDR ram */ +#ifdef CONFIG_DDR_ECC + 0x0C, /* num Row Addr: 12 */ +#else + 0x0D, /* num Row Addr: 13 */ +#endif + 0x09, /* numColAddr: 9 */ + 0x01, /* numBanks: 1 */ + 0x20, /* Module data width: 32 bits */ + 0x00, /* Module data width continued: +0 */ + 0x04, /* 2.5 Volt */ + 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ +#ifdef CONFIG_DDR_ECC + 0x02, /* ECC ON : 02 OFF : 00 */ +#else + 0x00, /* ECC ON : 02 OFF : 00 */ +#endif + 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ + 0, + 0, + 0, + 0x01, /* wcsbc = 1 */ + 0, + 0, + 0x0C, /* casBit (2,2.5) */ + 0, + 0, + 0x00, /* not registered: 0 registered : 0x02*/ + 0, + 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ + 0, + 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ + 0, + 0x50, /* tRpNs = 20 ns */ + 0, + 0x50, /* tRcdNs = 20 ns */ + 45, /* tRasNs */ +#ifdef CONFIG_DDR_ECC + 0x08, /* bankSizeID: 32MB */ +#else + 0x10, /* bankSizeID: 64MB */ +#endif + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 +}; +#endif -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ { @@ -291,73 +452,12 @@ int checkboard(void) return (0); } -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) -/************************************************************************* - * - * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -static void init_spd_array(void) -{ - cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */ - cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */ - -#ifdef CONFIG_DDR_ECC - cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */ - cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */ -#else - cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */ - cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */ - cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */ -#endif - - cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */ - cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */ - cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */ - cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */ - cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/ - cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */ - cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */ - cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */ - cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */ - cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */ - - cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */ - - cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */ - - cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */ -} -#endif long int initdram (int board_type) { #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; - /* - * First write simulated values in eeprom array for onboard bank 0 - */ - init_spd_array(); - dram_size = spd_sdram(); return dram_size; @@ -371,11 +471,12 @@ int testdram(void) { unsigned long *mem = (unsigned long *)0; const unsigned long kend = (1024 / sizeof(unsigned long)); - unsigned long k, n; + unsigned long k, n, *p32, ctr; + const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024; mtmsr(0); - for (k = 0; k < CFG_KBYTES_SDRAM; + for (k = 0; k < CFG_MBYTES_SDRAM*1024; ++k, mem += (1024 / sizeof(unsigned long))) { if ((k & 1023) == 0) { printf("%3d MB\r", k / 1024); @@ -399,6 +500,34 @@ int testdram(void) } } } + + /* + * Perform a sequence test to ensure that all + * memory locations are uniquely addressable + */ + ctr = 0; + p32 = 0; + while ((unsigned long)p32 != bend) { + if (0 == ((unsigned long)p32 & ((1<<20)-1))) + printf("Writing %3d MB\r", (unsigned long)p32 >> 20); + *p32++ = ctr++; + } + + ctr = 0; + p32 = 0; + while ((unsigned long)p32 != bend) { + if (0 == ((unsigned long)p32 & ((1<<20)-1))) + printf("Verifying %3d MB\r", (unsigned long)p32 >> 20); + + if (*p32 != ctr) { + printf("SDRAM test fails at: %08x\n", p32); + return 1; + } + + ctr++; + p32++; + } + printf("SDRAM test passes\n"); return 0; } @@ -1211,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | init_default_gpio +----------------------------------------------------------------------------*/ -void init_default_gpio(void) +void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) { int i; @@ -1281,7 +1410,7 @@ void init_default_gpio(void) | +----------------------------------------------------------------------------*/ -void update_uart_ios(uart_config_nb_t uart_config) +void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) { switch (uart_config) { @@ -1409,7 +1538,7 @@ void update_uart_ios(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | update_ndfc_ios(void). +----------------------------------------------------------------------------*/ -void update_ndfc_ios(void) +void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ @@ -1427,7 +1556,7 @@ void update_ndfc_ios(void) /*----------------------------------------------------------------------------+ | update_zii_ios(void). +----------------------------------------------------------------------------*/ -void update_zii_ios(void) +void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ @@ -1477,7 +1606,7 @@ void update_zii_ios(void) /*----------------------------------------------------------------------------+ | update_uic_0_3_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_0_3_irq_ios(void) +void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; @@ -1495,7 +1624,7 @@ void update_uic_0_3_irq_ios(void) /*----------------------------------------------------------------------------+ | update_uic_4_9_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_4_9_irq_ios(void) +void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; @@ -1516,7 +1645,7 @@ void update_uic_4_9_irq_ios(void) /*----------------------------------------------------------------------------+ | update_dma_a_b_ios(). +----------------------------------------------------------------------------*/ -void update_dma_a_b_ios(void) +void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; @@ -1537,7 +1666,7 @@ void update_dma_a_b_ios(void) /*----------------------------------------------------------------------------+ | update_dma_c_d_ios(). +----------------------------------------------------------------------------*/ -void update_dma_c_d_ios(void) +void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; @@ -1562,7 +1691,7 @@ void update_dma_c_d_ios(void) /*----------------------------------------------------------------------------+ | update_ebc_master_ios(). +----------------------------------------------------------------------------*/ -void update_ebc_master_ios(void) +void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; @@ -1580,7 +1709,7 @@ void update_ebc_master_ios(void) /*----------------------------------------------------------------------------+ | update_usb2_device_ios(). +----------------------------------------------------------------------------*/ -void update_usb2_device_ios(void) +void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; @@ -1611,20 +1740,21 @@ void update_usb2_device_ios(void) /*----------------------------------------------------------------------------+ | update_pci_patch_ios(). +----------------------------------------------------------------------------*/ -void update_pci_patch_ios(void) +void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) { gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; } /*----------------------------------------------------------------------------+ - | set_chip_gpio_configuration(unsigned char gpio_core) + | set_chip_gpio_configuration(unsigned char gpio_core, + | gpio_param_s (*gpio_tab)[GPIO_MAX]) | Put the core impacted by clock modification and sharing in reset. | Config the select registers to resolve the sharing depending of the config. | Configure the GPIO registers. | +----------------------------------------------------------------------------*/ -void set_chip_gpio_configuration(unsigned char gpio_core) +void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) { unsigned char i=0, j=0, reg_offset = 0; unsigned long gpio_reg, gpio_core_add; @@ -1778,11 +1908,12 @@ void configure_ppc440ep_pins(void) CORE_NOT_SELECTED /* PCI_PATCH */ }; + gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; /* Table Default Initialisation + FPGA Access */ - init_default_gpio(); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); + init_default_gpio(gpio_tab); + set_chip_gpio_configuration(GPIO0, gpio_tab); + set_chip_gpio_configuration(GPIO1, gpio_tab); /* Update Table */ force_bup_core_selection(ppc440ep_core_selection, &config_val); @@ -1817,7 +1948,7 @@ void configure_ppc440ep_pins(void) /* UIC 0:3 Selection */ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) { - update_uic_0_3_irq_ios(); + update_uic_0_3_irq_ios(gpio_tab); dma_a_b_unselect_in_fpga(); } @@ -1825,21 +1956,21 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(); + update_uic_4_9_irq_ios(gpio_tab); } /* DMA AB Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(); + update_dma_a_b_ios(gpio_tab); dma_a_b_selection_in_fpga(); } /* DMA CD Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) { - update_dma_c_d_ios(); + update_dma_c_d_ios(gpio_tab); dma_c_d_selection_in_fpga(); } @@ -1848,14 +1979,14 @@ void configure_ppc440ep_pins(void) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(); + update_ebc_master_ios(gpio_tab); } /* PCI Patch Enable */ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(); + update_pci_patch_ios(gpio_tab); } /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ @@ -1871,7 +2002,7 @@ void configure_ppc440ep_pins(void) /* USB2.0 Device Selection */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) { - update_usb2_device_ios(); + update_usb2_device_ios(gpio_tab); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; @@ -1904,7 +2035,7 @@ void configure_ppc440ep_pins(void) /* NAND Flash Selection */ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { - update_ndfc_ios(); + update_ndfc_ios(gpio_tab); #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | @@ -1933,7 +2064,7 @@ void configure_ppc440ep_pins(void) /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; mtsdr(sdr_mfr, sdr0_mfr); @@ -1944,7 +2075,7 @@ void configure_ppc440ep_pins(void) /* RMII Selection */ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; mtsdr(sdr_mfr, sdr0_mfr); @@ -1955,7 +2086,7 @@ void configure_ppc440ep_pins(void) /* SMII Selection */ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { - update_zii_ios(); + update_zii_ios(gpio_tab); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; mtsdr(sdr_mfr, sdr0_mfr); @@ -1992,7 +2123,7 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; break; } - update_uart_ios(uart_configuration); + update_uart_ios(uart_configuration, gpio_tab); /* UART Selection in all cases */ uart_selection_in_fpga(uart_configuration); @@ -2014,8 +2145,8 @@ void configure_ppc440ep_pins(void) /* Perform effective access to hardware */ mtsdr(sdr_pfc1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0); - set_chip_gpio_configuration(GPIO1); + set_chip_gpio_configuration(GPIO0, gpio_tab); + set_chip_gpio_configuration(GPIO1, gpio_tab); /* USB2.0 Device Reset must be done after GPIO setting */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index 1459eec..f4d2ae3 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -51,13 +51,12 @@ tlbtab: tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #else tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - /* PCI base & peripherals */ tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds index f6d7183..0375618 100644 --- a/board/amcc/bamboo/u-boot.lds +++ b/board/amcc/bamboo/u-boot.lds @@ -141,8 +141,6 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); - _end = . ; PROVIDE (end = .); } diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index e6429ec..eba0511 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) if (info->flash_id & FLASH_BTYPE) { /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000a000; + info->start[6] = base + 0x0000c000; + info->start[7] = base + 0x0000e000; + for (i = 8; i < info->sector_count; i++) { info->start[i] = - base + (i * 0x00010000) - 0x00030000; + base + ((i-7) * 0x00010000); } } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; for (; i >= 0; i--) { info->start[i] = base + i * 0x00010000; } -- cgit v1.1 From 9e737d8476e7d6a596d16caaf6a3853a9a1190a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:30:44 -0500 Subject: Declared attributes of void __mii_init(void) as an alias for int mii_init(void) Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/mii.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 691b144..68dc04f 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -203,7 +203,9 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -void mii_init(void) +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) { volatile fec_t *fecp; struct fec_info_s *info; -- cgit v1.1 From 6fde84a44b7e575ea80fe0e2d5be3b6f73d1e630 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 03:43:30 -0500 Subject: Moved sync() from board file to include/asm-m68k/io.h Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/m5329evb.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'board') diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index d180b6f..058cda5 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -87,10 +87,3 @@ int testdram(void) return (0); } -#ifdef CFG_FLASH_CFI -void sync(void) -{ - /* This sync function is PowerPC intruction, - coldfire does not have this instruction. Dummy function */ -} -#endif /* CFG_FLASH_CFI */ -- cgit v1.1 From 1a33ce65a4c51a69190dd8c408f9e1c62a66e94f Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Sun, 5 Aug 2007 04:31:18 -0500 Subject: Added NAND support Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/Makefile | 2 +- board/freescale/m5329evb/nand.c | 115 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 board/freescale/m5329evb/nand.c (limited to 'board') diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile index 74c2528..ab0f11e 100644 --- a/board/freescale/m5329evb/Makefile +++ b/board/freescale/m5329evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o mii.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c new file mode 100644 index 0000000..2a4ca71 --- /dev/null +++ b/board/freescale/m5329evb/nand.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +#include + +#define SET_CLE 0x10 +#define CLR_CLE ~SET_CLE +#define SET_ALE 0x08 +#define CLR_ALE ~SET_ALE + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + struct nand_chip *this = mtdinfo->priv; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + u32 nand_baseaddr = (u32) this->IO_ADDR_W; + + switch (cmd) { + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + break; + case NAND_CTL_SETCLE: + nand_baseaddr |= SET_CLE; + break; + case NAND_CTL_CLRCLE: + nand_baseaddr &= CLR_CLE; + break; + case NAND_CTL_SETALE: + nand_baseaddr |= SET_ALE; + break; + case NAND_CTL_CLRALE: + nand_baseaddr |= CLR_ALE; + break; + case NAND_CTL_SETWP: + fbcs->csmr2 |= CSMR_WP; + break; + case NAND_CTL_CLRWP: + fbcs->csmr2 &= ~CSMR_WP; + break; + } + this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); +} + +static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + *((volatile u8 *)(this->IO_ADDR_W)) = byte; +} + +static u8 nand_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + return (u8) (*((volatile u8 *)this->IO_ADDR_R)); +} + +static int nand_dev_ready(struct mtd_info *mtdinfo) +{ + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; + + /* set up pin configuration */ + gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; + gpio->pddr_timer |= 0x08; + gpio->ppd_timer |= 0x08; + gpio->pclrr_timer = 0; + gpio->podr_timer = 0; + + nand->chip_delay = 50; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = nand_hwcontrol; + nand->read_byte = nand_read_byte; + nand->write_byte = nand_write_byte; + nand->dev_ready = nand_dev_ready; + + return 0; +} +#endif + -- cgit v1.1 From 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 8 Aug 2007 09:54:26 +0200 Subject: Coding style cleanup Signed-off-by: Stefan Roese --- board/freescale/m5329evb/m5329evb.c | 1 - board/freescale/m5329evb/nand.c | 103 ++++++++++++++++++------------------ 2 files changed, 51 insertions(+), 53 deletions(-) (limited to 'board') diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 058cda5..242eb1a 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -86,4 +86,3 @@ int testdram(void) return (0); } - diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 2a4ca71..2272a24 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -35,81 +35,80 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -#define SET_CLE 0x10 -#define CLR_CLE ~SET_CLE -#define SET_ALE 0x08 -#define CLR_ALE ~SET_ALE +#define SET_CLE 0x10 +#define CLR_CLE ~SET_CLE +#define SET_ALE 0x08 +#define CLR_ALE ~SET_ALE static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) { - struct nand_chip *this = mtdinfo->priv; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - u32 nand_baseaddr = (u32) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + u32 nand_baseaddr = (u32) this->IO_ADDR_W; - switch (cmd) { - case NAND_CTL_SETNCE: - case NAND_CTL_CLRNCE: - break; - case NAND_CTL_SETCLE: - nand_baseaddr |= SET_CLE; - break; - case NAND_CTL_CLRCLE: - nand_baseaddr &= CLR_CLE; - break; - case NAND_CTL_SETALE: - nand_baseaddr |= SET_ALE; - break; - case NAND_CTL_CLRALE: - nand_baseaddr |= CLR_ALE; - break; - case NAND_CTL_SETWP: - fbcs->csmr2 |= CSMR_WP; - break; - case NAND_CTL_CLRWP: - fbcs->csmr2 &= ~CSMR_WP; - break; - } - this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); + switch (cmd) { + case NAND_CTL_SETNCE: + case NAND_CTL_CLRNCE: + break; + case NAND_CTL_SETCLE: + nand_baseaddr |= SET_CLE; + break; + case NAND_CTL_CLRCLE: + nand_baseaddr &= CLR_CLE; + break; + case NAND_CTL_SETALE: + nand_baseaddr |= SET_ALE; + break; + case NAND_CTL_CLRALE: + nand_baseaddr |= CLR_ALE; + break; + case NAND_CTL_SETWP: + fbcs->csmr2 |= CSMR_WP; + break; + case NAND_CTL_CLRWP: + fbcs->csmr2 &= ~CSMR_WP; + break; + } + this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); } static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) { - struct nand_chip *this = mtdinfo->priv; - *((volatile u8 *)(this->IO_ADDR_W)) = byte; + struct nand_chip *this = mtdinfo->priv; + *((volatile u8 *)(this->IO_ADDR_W)) = byte; } static u8 nand_read_byte(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; - return (u8) (*((volatile u8 *)this->IO_ADDR_R)); + struct nand_chip *this = mtdinfo->priv; + return (u8) (*((volatile u8 *)this->IO_ADDR_R)); } static int nand_dev_ready(struct mtd_info *mtdinfo) { - return 1; + return 1; } int board_nand_init(struct nand_chip *nand) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; + *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; - /* set up pin configuration */ - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; - gpio->pddr_timer |= 0x08; - gpio->ppd_timer |= 0x08; - gpio->pclrr_timer = 0; - gpio->podr_timer = 0; + /* set up pin configuration */ + gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; + gpio->pddr_timer |= 0x08; + gpio->ppd_timer |= 0x08; + gpio->pclrr_timer = 0; + gpio->podr_timer = 0; - nand->chip_delay = 50; - nand->eccmode = NAND_ECC_SOFT; - nand->hwcontrol = nand_hwcontrol; - nand->read_byte = nand_read_byte; - nand->write_byte = nand_write_byte; - nand->dev_ready = nand_dev_ready; + nand->chip_delay = 50; + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = nand_hwcontrol; + nand->read_byte = nand_read_byte; + nand->write_byte = nand_write_byte; + nand->dev_ready = nand_dev_ready; - return 0; + return 0; } #endif - -- cgit v1.1 From 1ded0242e437259366792d52b7e9d1e1931d8fa5 Mon Sep 17 00:00:00 2001 From: Lee Nipper Date: Thu, 14 Jun 2007 20:07:33 -0500 Subject: mpc83xx: Add support for 8360 silicon revision 2.1 This change adds 8360 silicon revision 2.1 support to u-boot. Signed-off-by: Lee Nipper Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 562eb8b..de4ca1e 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -103,7 +103,9 @@ int board_early_init_f(void) /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ if (immr->sysconf.spridr == SPR_8360_REV20 || - immr->sysconf.spridr == SPR_8360E_REV20) + immr->sysconf.spridr == SPR_8360E_REV20 || + immr->sysconf.spridr == SPR_8360_REV21 || + immr->sysconf.spridr == SPR_8360E_REV21) bcsr[0xe] = 0x30; return 0; -- cgit v1.1 From 26d02c9bbac1751c5e19294f000100b48d43a920 Mon Sep 17 00:00:00 2001 From: Jerry Van Baren Date: Wed, 4 Jul 2007 21:27:30 -0400 Subject: mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path(). The new name matches more closely the kernel's name, which is also a much better description. These are the mpc83xx changes made necessary by the function name change. Signed-off-by: Wolfgang Grandegger Acked-by: Gerald Van Baren Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 5 ++--- board/mpc8360emds/pci.c | 20 +++++++++----------- 2 files changed, 11 insertions(+), 14 deletions(-) (limited to 'board') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index de4ca1e..f63d3ae 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -30,8 +30,7 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include -#endif -#if defined(CONFIG_OF_LIBFDT) +#elif defined(CONFIG_OF_LIBFDT) #include #include #endif @@ -683,7 +682,7 @@ ft_board_setup(void *blob, bd_t *bd) int nodeoffset; int tmp[2]; - nodeoffset = fdt_path_offset (fdt, "/memory"); + nodeoffset = fdt_find_node_by_path(fdt, "/memory"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 158effe..8d34dbe 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -20,8 +20,7 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include -#endif -#if defined(CONFIG_OF_LIBFDT) +#elif defined(CONFIG_OF_LIBFDT) #include #include #endif @@ -207,7 +206,7 @@ void pci_init_board(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); + i2c_set_bus_num(1); val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); @@ -311,26 +310,25 @@ ft_pci_setup(void *blob, bd_t *bd) int err; int tmp[2]; - nodeoffset = fdt_path_offset (fdt, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_find_node_by_path(fdt, "/" OF_SOC "/pci@8500"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp)); } } -#endif /* CONFIG_OF_LIBFDT */ -#ifdef CONFIG_OF_FLAT_TREE +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + u32 *p; + int len; - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { p[0] = hose[0].first_busno; p[1] = hose[0].last_busno; - } + } } #endif /* CONFIG_OF_FLAT_TREE */ #endif /* CONFIG_PCI */ -- cgit v1.1 From f57ac7a7b37109245b69db80839ebee26179966a Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Jul 2007 19:25:22 -0500 Subject: mpc83xx: fix 8360 and cpu functions to update fdt being passed ..and not the global fdt. Rename local fdt vars to blob so as not to be confused with the global var with the same three-letter name. Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 4 ++-- board/mpc8360emds/pci.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index f63d3ae..b109317 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -682,11 +682,11 @@ ft_board_setup(void *blob, bd_t *bd) int nodeoffset; int tmp[2]; - nodeoffset = fdt_find_node_by_path(fdt, "/memory"); + nodeoffset = fdt_find_node_by_path(blob, "/memory"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp)); + fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); } #else u32 *p; diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 8d34dbe..8f90471 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -310,11 +310,11 @@ ft_pci_setup(void *blob, bd_t *bd) int err; int tmp[2]; - nodeoffset = fdt_find_node_by_path(fdt, "/" OF_SOC "/pci@8500"); + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); } } #elif defined(CONFIG_OF_FLAT_TREE) -- cgit v1.1 From 1c274c4e05b6dc9b24edc8aa618b02f607ee6eed Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Jul 2007 19:25:33 -0500 Subject: mpc83xx: add support for the MPC8323E RDB MPC8323E based board with 64MB fixed SDRAM, 16MB flash, five 10/100 ethernet ports connected via an ICPlus IP175C switch, one PCI slot, and serial. Features not supported in this patch are SD card interface, 2 USB ports, and the two phone ports. Signed-off-by: Michael Barkowski Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/Makefile | 50 +++++++ board/freescale/mpc8323erdb/config.mk | 28 ++++ board/freescale/mpc8323erdb/mpc8323erdb.c | 217 ++++++++++++++++++++++++++++++ 3 files changed, 295 insertions(+) create mode 100644 board/freescale/mpc8323erdb/Makefile create mode 100644 board/freescale/mpc8323erdb/config.mk create mode 100644 board/freescale/mpc8323erdb/mpc8323erdb.c (limited to 'board') diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile new file mode 100644 index 0000000..acc9544 --- /dev/null +++ b/board/freescale/mpc8323erdb/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8323erdb/config.mk b/board/freescale/mpc8323erdb/config.mk new file mode 100644 index 0000000..fe0d37d --- /dev/null +++ b/board/freescale/mpc8323erdb/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8323ERDB +# + +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c new file mode 100644 index 0000000..1886f19 --- /dev/null +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Michael Barkowski + * Based on mpc832xmds file by Dave Liu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#else +#include +#endif + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* UCC3 */ + {1, 0, 1, 0, 1}, /* TxD0 */ + {1, 1, 1, 0, 1}, /* TxD1 */ + {1, 2, 1, 0, 1}, /* TxD2 */ + {1, 3, 1, 0, 1}, /* TxD3 */ + {1, 9, 1, 0, 1}, /* TxER */ + {1, 12, 1, 0, 1}, /* TxEN */ + {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1}, /* RxD0 */ + {1, 5, 2, 0, 1}, /* RxD1 */ + {1, 6, 2, 0, 1}, /* RxD2 */ + {1, 7, 2, 0, 1}, /* RxD3 */ + {1, 8, 2, 0, 1}, /* RxER */ + {1, 10, 2, 0, 1}, /* RxDV */ + {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1}, /* COL */ + {1, 13, 2, 0, 1}, /* CRS */ + + /* UCC2 */ + {0, 18, 1, 0, 1}, /* TxD0 */ + {0, 19, 1, 0, 1}, /* TxD1 */ + {0, 20, 1, 0, 1}, /* TxD2 */ + {0, 21, 1, 0, 1}, /* TxD3 */ + {0, 27, 1, 0, 1}, /* TxER */ + {0, 30, 1, 0, 1}, /* TxEN */ + {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ + + {0, 22, 2, 0, 1}, /* RxD0 */ + {0, 23, 2, 0, 1}, /* RxD1 */ + {0, 24, 2, 0, 1}, /* RxD2 */ + {0, 25, 2, 0, 1}, /* RxD3 */ + {0, 26, 1, 0, 1}, /* RxER */ + {0, 28, 2, 0, 1}, /* Rx_DV */ + {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ + {0, 29, 2, 0, 1}, /* COL */ + {0, 31, 2, 0, 1}, /* CRS */ + + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +int board_early_init_f(void) +{ + return 0; +} + +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + + msize = fixed_sdram(); + + puts("\n DDR RAM: "); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__ ("sync"); + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + __asm__ __volatile__ ("sync"); + return msize; +} + +int checkboard(void) +{ + puts("Board: Freescale MPC8323ERDB\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + mpc83xx_pci_init(1, reg, 0); +} + +#if defined(CONFIG_OF_BOARD_SETUP) + +/* + * Prototypes of functions that we use. + */ +void ft_cpu_setup(void *blob, bd_t *bd); + +#ifdef CONFIG_PCI +void ft_pci_setup(void *blob, bd_t *bd); +#endif + +void +ft_board_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/memory"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(bd->bi_memstart); + tmp[1] = cpu_to_be32(bd->bi_memsize); + fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); + } + + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ -- cgit v1.1 From daab8c67d2defef73dc26ab07f0c3afd1b05d019 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 1 Aug 2007 15:00:15 +0800 Subject: mpc83xx: Consolidate the ECC support of 83xx Remove the duplicated source code of ecc command on the .c, for reused, move these code to cpu/mpc83xx directory. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- board/mpc8349emds/mpc8349emds.c | 327 ---------------------------------- board/mpc8360emds/mpc8360emds.c | 378 ---------------------------------------- 2 files changed, 705 deletions(-) (limited to 'board') diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 071591e..521d1bb 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -29,7 +29,6 @@ #include #include #include -#include #if defined(CONFIG_SPD_EEPROM) #include #endif @@ -258,332 +257,6 @@ void sdram_init(void) } #endif -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) -/* - * ECC user commands - */ -void ecc_print_status(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - - printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); - - /* Interrupts */ - printf("Memory Error Interrupt Enable:\n"); - printf(" Multiple-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); - printf(" Single-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); - printf(" Memory Select Error Interrupt Enable: %d\n\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); - - /* Error disable */ - printf("Memory Error Disable:\n"); - printf(" Multiple-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); - printf(" Sinle-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); - printf(" Memory Select Error Disable: %d\n\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); - - /* Error injection */ - printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", - ddr->data_err_inject_hi, ddr->data_err_inject_lo); - - printf("Memory Data Path Error Injection Mask ECC:\n"); - printf(" ECC Mirror Byte: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); - printf(" ECC Injection Enable: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); - printf(" ECC Error Injection Mask: 0x%02x\n\n", - ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); - - /* SBE counter/threshold */ - printf("Memory Single-Bit Error Management (0..255):\n"); - printf(" Single-Bit Error Threshold: %d\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); - printf(" Single-Bit Error Counter: %d\n\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); - - /* Error detect */ - printf("Memory Error Detect:\n"); - printf(" Multiple Memory Errors: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); - printf(" Multiple-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); - printf(" Single-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); - printf(" Memory Select Error: %d\n\n", - (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); - - /* Capture data */ - printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); - printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", - ddr->capture_data_hi, ddr->capture_data_lo); - printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", - ddr->capture_ecc & CAPTURE_ECC_ECE); - - printf("Memory Error Attributes Capture:\n"); - printf(" Data Beat Number: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); - printf(" Transaction Size: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); - printf(" Transaction Source: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); - printf(" Transaction Type: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); - printf(" Error Information Valid: %d\n\n", - ddr->capture_attributes & ECC_CAPT_ATTR_VLD); -} - -int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - volatile u32 val; - u64 *addr, count, val64; - register u64 *i; - - if (argc > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc == 2) { - if (strcmp(argv[1], "status") == 0) { - ecc_print_status(); - return 0; - } else if (strcmp(argv[1], "captureclear") == 0) { - ddr->capture_address = 0; - ddr->capture_data_hi = 0; - ddr->capture_data_lo = 0; - ddr->capture_ecc = 0; - ddr->capture_attributes = 0; - return 0; - } - } - - if (argc == 3) { - if (strcmp(argv[1], "sbecnt") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBEC_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "sbethr") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBET_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "errdisable") == 0) { - val = ddr->err_disable; - - if (strcmp(argv[2], "+sbe") == 0) { - val |= ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "+mbe") == 0) { - val |= ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "+mse") == 0) { - val |= ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "+all") == 0) { - val |= (ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else if (strcmp(argv[2], "-sbe") == 0) { - val &= ~ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "-mbe") == 0) { - val &= ~ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "-mse") == 0) { - val &= ~ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "-all") == 0) { - val &= ~(ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else { - printf("Incorrect err_disable field\n"); - return 1; - } - - ddr->err_disable = val; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - return 0; - } else if (strcmp(argv[1], "errdetectclr") == 0) { - val = ddr->err_detect; - - if (strcmp(argv[2], "mme") == 0) { - val |= ECC_ERROR_DETECT_MME; - } else if (strcmp(argv[2], "sbe") == 0) { - val |= ECC_ERROR_DETECT_SBE; - } else if (strcmp(argv[2], "mbe") == 0) { - val |= ECC_ERROR_DETECT_MBE; - } else if (strcmp(argv[2], "mse") == 0) { - val |= ECC_ERROR_DETECT_MSE; - } else if (strcmp(argv[2], "all") == 0) { - val |= (ECC_ERROR_DETECT_MME | - ECC_ERROR_DETECT_MBE | - ECC_ERROR_DETECT_SBE | - ECC_ERROR_DETECT_MSE); - } else { - printf("Incorrect err_detect field\n"); - return 1; - } - - ddr->err_detect = val; - return 0; - } else if (strcmp(argv[1], "injectdatahi") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_hi = val; - return 0; - } else if (strcmp(argv[1], "injectdatalo") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_lo = val; - return 0; - } else if (strcmp(argv[1], "injectecc") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - if (val > 0xff) { - printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); - return 1; - } - val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); - - ddr->ecc_err_inject = val; - return 0; - } else if (strcmp(argv[1], "inject") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EIEN; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EIEN; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - return 0; - } else if (strcmp(argv[1], "mirror") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EMB; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EMB; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - return 0; - } - } - - if (argc == 4) { - if (strcmp(argv[1], "test") == 0) { - addr = (u64 *)simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32)addr % 8) { - printf("Address not alligned on double word boundary\n"); - return 1; - } - - disable_interrupts(); - icache_disable(); - - for (i = addr; i < addr + count; i++) { - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* write memory location injecting errors */ - *i = 0x1122334455667788ULL; - __asm__ __volatile__ ("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* read data, this generates ECC error */ - val64 = *i; - __asm__ __volatile__ ("sync"); - - /* disable errors for ECC */ - ddr->err_disable |= ~ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - - /* re-initialize memory, write the location again - * NOT injecting errors this time */ - *i = 0xcafecafecafecafeULL; - __asm__ __volatile__ ("sync"); - - /* enable errors for ECC */ - ddr->err_disable &= ECC_ERROR_ENABLE; - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("isync"); - } - - icache_enable(); - enable_interrupts(); - - return 0; - } - } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", - "status - print out status info\n" - "ecc captureclear - clear capture regs data\n" - "ecc sbecnt - set Single-Bit Error counter\n" - "ecc sbethr - set Single-Bit Threshold\n" - "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" - " [-|+]sbe - Single-Bit Error\n" - " [-|+]mbe - Multiple-Bit Error\n" - " [-|+]mse - Memory Select Error\n" - " [-|+]all - all errors\n" - "ecc errdetectclr - clear Memory Error Detect, flag:\n" - " mme - Multiple Memory Errors\n" - " sbe - Single-Bit Error\n" - " mbe - Multiple-Bit Error\n" - " mse - Memory Select Error\n" - " all - all errors\n" - "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" - "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" - "ecc injectecc - set ECC Error Injection Mask\n" - "ecc inject - enable/disable error injection\n" - "ecc mirror - enable/disable mirror byte\n" - "ecc test - test mem region:\n" - " - enables injects\n" - " - writes pattern injecting errors\n" - " - disables injects\n" - " - reads pattern back, generates error\n" - " - re-inits memory" -); -#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ - #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index b109317..3fa093d 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -1,8 +1,6 @@ /* * Copyright (C) 2006 Freescale Semiconductor, Inc. - * * Dave Liu - * based on board/mpc8349emds/mpc8349emds.c * * See file CREDITS for list of people who contributed to this * project. @@ -19,7 +17,6 @@ #include #include #include -#include #if defined(CONFIG_PCI) #include #endif @@ -288,381 +285,6 @@ void sdram_init(void) } #endif -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) -/* - * ECC user commands - */ -void ecc_print_status(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - - printf("\nECC mode: %s\n\n", - (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); - - /* Interrupts */ - printf("Memory Error Interrupt Enable:\n"); - printf(" Multiple-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); - printf(" Single-Bit Error Interrupt Enable: %d\n", - (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); - printf(" Memory Select Error Interrupt Enable: %d\n\n", - (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); - - /* Error disable */ - printf("Memory Error Disable:\n"); - printf(" Multiple-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); - printf(" Sinle-Bit Error Disable: %d\n", - (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); - printf(" Memory Select Error Disable: %d\n\n", - (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); - - /* Error injection */ - printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", - ddr->data_err_inject_hi, ddr->data_err_inject_lo); - - printf("Memory Data Path Error Injection Mask ECC:\n"); - printf(" ECC Mirror Byte: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); - printf(" ECC Injection Enable: %d\n", - (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); - printf(" ECC Error Injection Mask: 0x%02x\n\n", - ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); - - /* SBE counter/threshold */ - printf("Memory Single-Bit Error Management (0..255):\n"); - printf(" Single-Bit Error Threshold: %d\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); - printf(" Single-Bit Error Counter: %d\n\n", - (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); - - /* Error detect */ - printf("Memory Error Detect:\n"); - printf(" Multiple Memory Errors: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); - printf(" Multiple-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); - printf(" Single-Bit Error: %d\n", - (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); - printf(" Memory Select Error: %d\n\n", - (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); - - /* Capture data */ - printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); - printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", - ddr->capture_data_hi, ddr->capture_data_lo); - printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", - ddr->capture_ecc & CAPTURE_ECC_ECE); - - printf("Memory Error Attributes Capture:\n"); - printf(" Data Beat Number: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> - ECC_CAPT_ATTR_BNUM_SHIFT); - printf(" Transaction Size: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> - ECC_CAPT_ATTR_TSIZ_SHIFT); - printf(" Transaction Source: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> - ECC_CAPT_ATTR_TSRC_SHIFT); - printf(" Transaction Type: %d\n", - (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> - ECC_CAPT_ATTR_TTYP_SHIFT); - printf(" Error Information Valid: %d\n\n", - ddr->capture_attributes & ECC_CAPT_ATTR_VLD); -} - -int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - volatile u32 val; - u64 *addr; - u32 count; - register u64 *i; - u32 ret[2]; - u32 pattern[2]; - u32 writeback[2]; - - /* The pattern is written into memory to generate error */ - pattern[0] = 0xfedcba98UL; - pattern[1] = 0x76543210UL; - - /* After injecting error, re-initialize the memory with the value */ - writeback[0] = 0x01234567UL; - writeback[1] = 0x89abcdefUL; - - if (argc > 4) { - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc == 2) { - if (strcmp(argv[1], "status") == 0) { - ecc_print_status(); - return 0; - } else if (strcmp(argv[1], "captureclear") == 0) { - ddr->capture_address = 0; - ddr->capture_data_hi = 0; - ddr->capture_data_lo = 0; - ddr->capture_ecc = 0; - ddr->capture_attributes = 0; - return 0; - } - } - if (argc == 3) { - if (strcmp(argv[1], "sbecnt") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, " - "should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBEC_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "sbethr") == 0) { - val = simple_strtoul(argv[2], NULL, 10); - if (val > 255) { - printf("Incorrect Counter value, " - "should be 0..255\n"); - return 1; - } - - val = (val << ECC_ERROR_MAN_SBET_SHIFT); - val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); - - ddr->err_sbe = val; - return 0; - } else if (strcmp(argv[1], "errdisable") == 0) { - val = ddr->err_disable; - - if (strcmp(argv[2], "+sbe") == 0) { - val |= ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "+mbe") == 0) { - val |= ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "+mse") == 0) { - val |= ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "+all") == 0) { - val |= (ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else if (strcmp(argv[2], "-sbe") == 0) { - val &= ~ECC_ERROR_DISABLE_SBED; - } else if (strcmp(argv[2], "-mbe") == 0) { - val &= ~ECC_ERROR_DISABLE_MBED; - } else if (strcmp(argv[2], "-mse") == 0) { - val &= ~ECC_ERROR_DISABLE_MSED; - } else if (strcmp(argv[2], "-all") == 0) { - val &= ~(ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | - ECC_ERROR_DISABLE_MSED); - } else { - printf("Incorrect err_disable field\n"); - return 1; - } - - ddr->err_disable = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - return 0; - } else if (strcmp(argv[1], "errdetectclr") == 0) { - val = ddr->err_detect; - - if (strcmp(argv[2], "mme") == 0) { - val |= ECC_ERROR_DETECT_MME; - } else if (strcmp(argv[2], "sbe") == 0) { - val |= ECC_ERROR_DETECT_SBE; - } else if (strcmp(argv[2], "mbe") == 0) { - val |= ECC_ERROR_DETECT_MBE; - } else if (strcmp(argv[2], "mse") == 0) { - val |= ECC_ERROR_DETECT_MSE; - } else if (strcmp(argv[2], "all") == 0) { - val |= (ECC_ERROR_DETECT_MME | - ECC_ERROR_DETECT_MBE | - ECC_ERROR_DETECT_SBE | - ECC_ERROR_DETECT_MSE); - } else { - printf("Incorrect err_detect field\n"); - return 1; - } - - ddr->err_detect = val; - return 0; - } else if (strcmp(argv[1], "injectdatahi") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_hi = val; - return 0; - } else if (strcmp(argv[1], "injectdatalo") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - - ddr->data_err_inject_lo = val; - return 0; - } else if (strcmp(argv[1], "injectecc") == 0) { - val = simple_strtoul(argv[2], NULL, 16); - if (val > 0xff) { - printf("Incorrect ECC inject mask, " - "should be 0x00..0xff\n"); - return 1; - } - val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); - - ddr->ecc_err_inject = val; - return 0; - } else if (strcmp(argv[1], "inject") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EIEN; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EIEN; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - return 0; - } else if (strcmp(argv[1], "mirror") == 0) { - val = ddr->ecc_err_inject; - - if (strcmp(argv[2], "en") == 0) - val |= ECC_ERR_INJECT_EMB; - else if (strcmp(argv[2], "dis") == 0) - val &= ~ECC_ERR_INJECT_EMB; - else - printf("Incorrect command\n"); - - ddr->ecc_err_inject = val; - return 0; - } - } - if (argc == 4) { - if (strcmp(argv[1], "testdw") == 0) { - addr = (u64 *) simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32) addr % 8) { - printf("Address not alligned on " - "double word boundary\n"); - return 1; - } - disable_interrupts(); - - for (i = addr; i < addr + count; i++) { - - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* write memory location injecting errors */ - ppcDWstore((u32 *) i, pattern); - __asm__ __volatile__("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* read data, this generates ECC error */ - ppcDWload((u32 *) i, ret); - __asm__ __volatile__("sync"); - - /* re-initialize memory, double word write the location again, - * generates new ECC code this time */ - ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); - } - enable_interrupts(); - return 0; - } - if (strcmp(argv[1], "testword") == 0) { - addr = (u64 *) simple_strtoul(argv[2], NULL, 16); - count = simple_strtoul(argv[3], NULL, 16); - - if ((u32) addr % 8) { - printf("Address not alligned on " - "double word boundary\n"); - return 1; - } - disable_interrupts(); - - for (i = addr; i < addr + count; i++) { - - /* enable injects */ - ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* write memory location injecting errors */ - *(u32 *) i = 0xfedcba98UL; - __asm__ __volatile__("sync"); - - /* sub double word write, - * bus will read-modify-write, - * generates ECC error */ - *((u32 *) i + 1) = 0x76543210UL; - __asm__ __volatile__("sync"); - - /* disable injects */ - ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; - __asm__ __volatile__("sync"); - __asm__ __volatile__("isync"); - - /* re-initialize memory, - * double word write the location again, - * generates new ECC code this time */ - ppcDWstore((u32 *) i, writeback); - __asm__ __volatile__("sync"); - } - enable_interrupts(); - return 0; - } - } - printf("Usage:\n%s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD(ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", - "status - print out status info\n" - "ecc captureclear - clear capture regs data\n" - "ecc sbecnt - set Single-Bit Error counter\n" - "ecc sbethr - set Single-Bit Threshold\n" - "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" - " [-|+]sbe - Single-Bit Error\n" - " [-|+]mbe - Multiple-Bit Error\n" - " [-|+]mse - Memory Select Error\n" - " [-|+]all - all errors\n" - "ecc errdetectclr - clear Memory Error Detect, flag:\n" - " mme - Multiple Memory Errors\n" - " sbe - Single-Bit Error\n" - " mbe - Multiple-Bit Error\n" - " mse - Memory Select Error\n" - " all - all errors\n" - "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" - "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" - "ecc injectecc - set ECC Error Injection Mask\n" - "ecc inject - enable/disable error injection\n" - "ecc mirror - enable/disable mirror byte\n" - "ecc testdw - test mem region with double word access:\n" - " - enables injects\n" - " - writes pattern injecting errors with double word access\n" - " - disables injects\n" - " - reads pattern back with double word access, generates error\n" - " - re-inits memory\n" - "ecc testword - test mem region with word access:\n" - " - enables injects\n" - " - writes pattern injecting errors with word access\n" - " - writes pattern with word access, generates error\n" - " - disables injects\n" " - re-inits memory"); -#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ - #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ && defined(CONFIG_OF_BOARD_SETUP) -- cgit v1.1 From 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 6 Aug 2007 18:18:34 -0500 Subject: mpc83xx: fix ITX[GP] O=builddir builds make: *** No rule to make target `/work/wd/tmp/board/mpc8349itx/u-boot.lds', needed by `/work/wd/tmp/u-boot'. Stop. Both the ITX and ITX-GP fail when you use "make O= ..." or "BUILD_DIR= ./MAKEALL ..." Signed-off-by: Kim Phillips --- board/mpc8349itx/config.mk | 6 ------ 1 file changed, 6 deletions(-) (limited to 'board') diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk index 1901fdc..79f1765 100644 --- a/board/mpc8349itx/config.mk +++ b/board/mpc8349itx/config.mk @@ -29,9 +29,3 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE TEXT_BASE = 0xFEF00000 endif - -ifneq ($(OBJTREE),$(SRCTREE)) -# We are building u-boot in a separate directory, use generated -# .lds script from OBJTREE directory. -LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds -endif -- cgit v1.1 From 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:25:31 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: READMEs Signed-off-by: Niklaus Giger --- board/netstal/hcu4/README.txt | 59 ++++++++++++++ board/netstal/hcu5/README.txt | 174 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 233 insertions(+) create mode 100644 board/netstal/hcu4/README.txt create mode 100644 board/netstal/hcu5/README.txt (limited to 'board') diff --git a/board/netstal/hcu4/README.txt b/board/netstal/hcu4/README.txt new file mode 100644 index 0000000..1e9c64a --- /dev/null +++ b/board/netstal/hcu4/README.txt @@ -0,0 +1,59 @@ +HCU4 Configuration Details + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xf4000000 - 0xf4000fff + +The 405GPr includes a 4K on-chip memory that can be placed however +software chooses. I choose to place the memory at this address, to +keep it out of the cachable areas. + + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC405GPr +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +0x70000000 + +Chip-Select 3: CAN Interface +---------------------------- +0x7800000 + + +Chip-Select 4: IMC-bus standard +------------------------------- + +Our IO-Bus (slow version) + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +Our IO-Bus (fast, but not yet use) + + +Memory Bank 1 -- SDRAM +------------------------------------- + +0x00000000 - 0x1ffffff # Default 32 MB diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt new file mode 100644 index 0000000..3118da9 --- /dev/null +++ b/board/netstal/hcu5/README.txt @@ -0,0 +1,174 @@ +HCU5 configuration details and startup sequence + +(C) Copyright 2007 Netstal Maschinen AG + Niklaus Giger (Niklaus.Giger@netstal.com) + +TODO: +----- +- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT ! + - Does not occur if both EMAC are connected +- Fix RTS/CTS problem (HW?) + CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after + Switching to interrupt driven serial input mode +- Make vxWorks start from u-boot. Possible reasons + - Does vxWorks need an entry for the Machine Check interrupt like this + tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ? + +Caveats: +-------- +Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c) +see hcu5.c. + + +Memory Bank 0 -- Flash chip +--------------------------- + +0xfff00000 - 0xffffffff + +The flash chip is really only 512Kbytes, but the high address bit of +the 1Meg region is ignored, so the flash is replicated through the +region. Thus, this is consistent with a flash base address 0xfff80000. + +The placement at the end is to be consistent with reset behavior, +where the processor itself initially uses this bus to load the branch +vector and start running. + +On-Chip Memory +-------------- + +0xe0010000- 0xe0013fff CFG_OCM_BASE +The 440EPx includes a 16K on-chip memory that can be placed however +software chooses. + +Internal Peripherals +-------------------- + +0xef600300 - 0xef6008ff + +These are scattered various peripherals internal to the PPC440EPX +chip. + +Chip-Select 2: Flash Memory +--------------------------- + +Not used + +Chip-Select 3: CAN Interface +---------------------------- +0xc800000: 2 Intel 82527 CAN-Controller + + +Chip-Select 4: IMC-bus standard +------------------------------- + +0xcc00000: Netstal specific IO-Bus + + +Chip-Select 5: IMC-bus fast (inactive) +-------------------------------------- + +0xce00000: Netstal specific IO-Bus (fast, but not yet used) + + +Memory Bank 1 -- DDR2 +------------------------------------- + +0x00000000 - 0xfffffff # Default 256 MB + +PCI ?? + +USB ?? +Only USB_STORAGE is enabled to load vxWorks +from a memory stick. + +System-LEDs ??? (Analog zu HCU4 ???) + +Startup sequence +---------------- + +(cpu/ppc4xx/resetvec.S) +depending on configs option +call _start_440 _start_pci oder _start + +(cpu/ppc4xx/start.S) + +_start_440: + initialize register like + CCR0 + debug + setup interrupt vectors + configure cache regions + clear and setup TLB + enable internal RAM + jump start_ram + which in turn will jump to start +_start: + Clear and set up some registers. + Debug setup + Setup the internal SRAM + Setup the stack in internal SRAM + setup stack pointer (r1) + setup GOT + call cpu_init_f /* run low-level CPU init code (from Flash) */ + + call cpu_init_f + board_init_f: (lib_ppc\board.c) + init_sequence defines a list of function to be called + board_early_init_f: (board/netstal/hcu5/hcu5.c) + We are using Bootstrap-Option A + if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot + Setup the GPIO pins + Setup the interrupt controller polarities, triggers, etc. + Ethernet, PCI, USB enable + setup BOOT FLASH (Chip timing) + init_baudrate, + serial_init + checkcpu + misc_init_f #ifdef + init_func_i2c #ifdef + post_init_f #ifdef + init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c + (EYE function removed!!) + test_dram call + + * Reserve memory at end of RAM for (top down in that order): + * - kernel log buffer + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + Save local variables to board info struct + call relocate_code() does not return + relocate_code: (cpu/ppc4xx/start.S) +------------------------------------------------------- +From now on our copy is in RAM and we will run from there, + starting with board_init_r +------------------------------------------------------- + board_init_r: (lib_ppc\board.c) + setup bd function pointers + trap_init + flash_init: (board/netstal/hcu5/flash.c) + /* setup for u-boot erase, update */ + setup bd flash info + cpu_init_r: (cpu/ppc4xx/cpu_init.c) + peripheral chip select in using defines like + CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h + mem_malloc_init + malloc_bin_reloc + spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + env_relocated + misc_init_r(bd): (board/netstal/hcu5.c) + ethaddr mit serial number ergänzen + Then we will somehow go into the command loop + +Most of the HW specific code for the HCU5 may be found in +include/configs/hcu5.h +board/netstal/hcu5/* +cpu/ppc4xx/* +lib_ppc/* +include/ppc440.h + +Drivers for serial etc are found under drivers/ + +Don't ask question if you did not look at the README !! +Most CFG_* and CONFIG_* switches are mentioned/explained there. -- cgit v1.1 From ac982ea5a4f2f993efcf52dca122f5a59df047d8 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:28:44 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: make related Signed-off-by: Niklaus Giger --- board/netstal/hcu4/Makefile | 49 ++++++++++++++ board/netstal/hcu4/config.mk | 29 +++++++++ board/netstal/hcu4/u-boot.lds | 140 ++++++++++++++++++++++++++++++++++++++++ board/netstal/hcu5/Makefile | 49 ++++++++++++++ board/netstal/hcu5/config.mk | 31 +++++++++ board/netstal/hcu5/u-boot.lds | 144 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 442 insertions(+) create mode 100644 board/netstal/hcu4/Makefile create mode 100644 board/netstal/hcu4/config.mk create mode 100644 board/netstal/hcu4/u-boot.lds create mode 100644 board/netstal/hcu5/Makefile create mode 100644 board/netstal/hcu5/config.mk create mode 100644 board/netstal/hcu5/u-boot.lds (limited to 'board') diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile new file mode 100644 index 0000000..d9825a5 --- /dev/null +++ b/board/netstal/hcu4/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2007 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +vpath flash.c ../common +COBJS = $(BOARD).o flash.o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk new file mode 100644 index 0000000..f5a4ce4 --- /dev/null +++ b/board/netstal/hcu4/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: HCU4 boards +# + +TEXT_BASE = 0xFFFa0000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif + diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds new file mode 100644 index 0000000..b6e28f8 --- /dev/null +++ b/board/netstal/hcu4/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : { + /* The start.o file includes the initial jump vector that + must be located in the beginning. It is the basic run- + time function that calls all other functions. */ + cpu/ppc4xx/start.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile new file mode 100644 index 0000000..eee310b --- /dev/null +++ b/board/netstal/hcu5/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2007 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +vpath flash.c ../common +COBJS = $(BOARD).o sdram.o flash.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk new file mode 100644 index 0000000..58ec2af --- /dev/null +++ b/board/netstal/hcu5/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2005 Netstal Maschinen AG +# Niklaus Giger (ng@netstal.com) +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Netstal Maschinen AG: HCU5 boards +# + +TEXT_BASE = 0xFFFa0000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG -g +endif + diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds new file mode 100644 index 0000000..6d255a9 --- /dev/null +++ b/board/netstal/hcu5/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); + +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From e8397fc78c9394d71de233a4d810fbc9047e4c76 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:38:26 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: common files Signed-off-by: Niklaus Giger --- board/netstal/common/flash.c | 528 ++++++++++++++++++++++++++++++++++++++++++ board/netstal/common/nm_bsp.c | 42 ++++ 2 files changed, 570 insertions(+) create mode 100644 board/netstal/common/flash.c create mode 100644 board/netstal/common/nm_bsp.c (limited to 'board') diff --git a/board/netstal/common/flash.c b/board/netstal/common/flash.c new file mode 100644 index 0000000..be2cb37 --- /dev/null +++ b/board/netstal/common/flash.c @@ -0,0 +1,528 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + * + * Modified 6/6/2007 + * Added isync + * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com + * + */ + +#include +#include +#include + +#if CFG_MAX_FLASH_BANKS != 1 +#error "CFG_MAX_FLASH_BANKS must be 1" +#endif +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*-----------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + + /* Init: no FLASHes known */ + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, + &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM + monitor_flash_len - 1, + &flash_info[0]); + flash_info[0].size = size_b0; + + return size_b0; +} + + +/*-----------------------------------------------------------------------*/ +/* + * This implementation assumes that the flash chips are uniform sector + * devices. This is true for all likely flash devices on a HCUx. + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + unsigned idx; + unsigned long sector_size = info->size / info->sector_count; + + for (idx = 0; idx < info->sector_count; idx += 1) { + info->start[idx] = base + (idx * sector_size); + } +} + +/*-----------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("ST Micro "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* (Reduced table of only parts expected in HCUx boards.) */ + switch (info->flash_id) { + case FLASH_MAN_AMD | FLASH_AM040: + printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_MAN_STM | FLASH_AM040: + printf ("MM29W040W (512 Kbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; +} + +/*-----------------------------------------------------------------------*/ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write auto select command: read Manufacturer ID */ + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + asm("isync"); + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + asm("isync"); + + value = addr2[0]; + asm("isync"); + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + printf("Unknown flash manufacturer code: 0x%x at %p\n", + value, addr); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* Calculate the sector offsets (Use HCUx Optimized code). */ + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, + *(A7 .. A0) = 0x02 + * D0 = 1 if protected + */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*-----------------------------------------------------------------------*/ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors not erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf ("Erasing sector %p\n", addr2); /* CLH */ + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* block erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; + for (i = 0; i < 50; i++) udelay (1000); + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* sector erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7 (info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c new file mode 100644 index 0000000..ee1b684 --- /dev/null +++ b/board/netstal/common/nm_bsp.c @@ -0,0 +1,42 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +/* + * Command nm_bsp: Netstal Maschinen BSP specific command + */ +int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__, + flag, argc, argv[0]); + printf("Netstal Maschinen BSP specific command. None at the moment.\n"); + return 0; +} + +U_BOOT_CMD( + nm_bsp, 1, 1, nm_bsp, + "nm_bsp - Netstal Maschinen BSP specific command. \n", + "Help for Netstal Maschinen BSP specific command.\n" + ); +#endif + -- cgit v1.1 From 6e5de26c6e7580faf16e87745cd488b92b492d0c Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:30:33 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: HCU4 files Signed-off-by: Niklaus Giger --- board/netstal/hcu4/hcu4.c | 393 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 393 insertions(+) create mode 100644 board/netstal/hcu4/hcu4.c (limited to 'board') diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c new file mode 100644 index 0000000..deb7d2d --- /dev/null +++ b/board/netstal/hcu4/hcu4.c @@ -0,0 +1,393 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include +#include +#include "../common/nm_bsp.c" + +DECLARE_GLOBAL_DATA_PTR; + +void sysLedSet(u32 value); +long int spd_sdram(int(read_spd)(uint addr)) +#ifdef CONFIG_SPD_EEPROM + #define DEBUG +#endif + +#if defined(DEBUG) +void show_sdram_registers(void); +#endif + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +#define CPC0_CR0 0xb1 /* Chip control register 0 */ +#define CPC0_CR1 0xb2 /* Chip control register 1 */ +/* Attention: If you want 1 microsecs times from the external oscillator + * use 0x00804051. But this causes problems with u-boot and linux! + */ +#define CPC0_CR1_VALUE 0x00004051 +#define CPC0_ECR 0xaa /* Edge condition register */ +#define EBC0_CFG 0x23 /* External Peripheral Control Register */ +#define CPC0_EIRR 0xb6 /* External Interrupt Register */ + + +int board_early_init_f (void) +{ + /*-------------------------------------------------------------------+ + | Interrupt controller setup for the HCU4 board. + | Note: IRQ 0-15 405GP internally generated; high; level sensitive + | IRQ 16 405GP internally generated; low; level sensitive + | IRQ 17-24 RESERVED/UNUSED + | IRQ 31 (EXT IRQ 6) (unused) + +-------------------------------------------------------------------*/ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + + mtdcr(CPC0_CR1, CPC0_CR1_VALUE); + mtdcr(CPC0_ECR, 0x60606000); + mtdcr(CPC0_EIRR, 0x7c000000); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} + +#endif + +enum { + /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + +int checkboard (void) +{ +#define HCU_MACH_VERSIONS_REGISTER ( 0x7C000000 + 0xF00000 ) + unsigned j; + uint16_t *boardVersReg = (uint16_t *) HCU_MACH_VERSIONS_REGISTER; + uint16_t generation = *boardVersReg & 0xf0; + uint16_t index = *boardVersReg & 0x0f; + /* Force /RTS to active. The board it not wired quite + correctly to use cts/rtc flow control, so just force the + /RST active and forget about it. */ + writeb (readb (0xef600404) | 0x03, 0xef600404); + printf ("\nNetstal Maschinen AG "); + if (generation == HW_GENERATION_HCU3) + printf ("HCU3: index %d\n\n", index); + else if (generation == HW_GENERATION_HCU4) + printf ("HCU4: index %d\n\n", index); + /* GPIO here noch nicht richtig initialisert !!! */ + sysLedSet(0); + for (j=0; j < 7;j++) { + sysLedSet(1 << j); + udelay(50*1000); + } + return 0; +} + +u32 sysLedGet(void) +{ + return( ~( (*(u32 *)GPIO0_OR)) >> 23) & 0xff; +} + +void sysLedSet(u32 value /* value to place in LEDs */) +{ + u32 tmp = ~value; + u32 *ledReg; + tmp = (tmp << 23) | 0x7FFFFF; + ledReg = (u32 *)GPIO0_OR; + *ledReg = tmp; +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram or initdram + * used for HCUx + */ +void sdram_init(void) +{ + return; +} + +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } + +#if defined(DEBUG) +void show_sdram_registers(void) +{ + u32 value; + printf ("SDRAM Controller Registers --\n"); + mfsdram(value, mem_mcopt1); + printf (" SDRAM0_CFG : 0x%08x\n", value); + mfsdram(value, mem_status); + printf (" SDRAM0_STATUS: 0x%08x\n", value); + mfsdram(value, mem_mb0cf); + printf (" SDRAM0_B0CR : 0x%08x\n", value); + mfsdram(value, mem_mb1cf); + printf (" SDRAM0_B1CR : 0x%08x\n", value); + mfsdram(value, mem_sdtr1); + printf (" SDRAM0_TR : 0x%08x\n", value); + mfsdram(value, mem_rtr); + printf (" SDRAM0_RTR : 0x%08x\n", value); +} +#endif + +#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ + +/* + * this is even after checkboard. It returns the size of the SDRAM + * that we have installed. This function is called by board_init_f + * in lib_ppc/board.c to initialize the memory and return what I + * found. These are default value, which will be overridden later. + */ + +long int fixed_hcu4_sdram (int board_type) +{ +#ifdef DEBUG + printf (__FUNCTION__); +#endif + /* disable memory controller */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x00000000); + + udelay (500); + + /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besra); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ + mtdcr (memcfga, mem_besrb); + mtdcr (memcfgd, 0xffffffff); + + /* Clear SDRAM0_ECCCFG (disable ECC) */ + mtdcr (memcfga, mem_ecccf); + mtdcr (memcfgd, 0x00000000); + + /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ + mtdcr (memcfga, mem_eccerr); + mtdcr (memcfgd, 0xffffffff); + + /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 + * TODO ngngng + */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, 0x008a4015); + + /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 + * TODO ngngng + */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, 0x00062001); + + /* refresh timer = 0x400 */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, 0x04000000); + + /* Power management idle timer set to the default. */ + mtdcr (memcfga, mem_pmit); + mtdcr (memcfgd, 0x07c00000); + + udelay (500); + + /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x90800000); + +#ifdef DEBUG + printf ("%s: done\n", __FUNCTION__); +#endif + return SDRAM_LEN; +} + +/*---------------------------------------------------------------------------+ + * getSerialNr + *---------------------------------------------------------------------------*/ +static u32 getSerialNr(void) +{ + u32 *serial = (u32 *)CFG_FLASH_BASE; + if (*serial == 0xffffffff) { + return get_ticks(); + } + return *serial; +} + + +/*---------------------------------------------------------------------------+ + * misc_init_r. + *---------------------------------------------------------------------------*/ + +int misc_init_r(void) +{ + char *s = getenv("ethaddr"); + char *e; + int i; + u32 serial = getSerialNr(); + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + if (gd->bd->bi_enetaddr[3] == 0 && + gd->bd->bi_enetaddr[4] == 0 && + gd->bd->bi_enetaddr[5] == 0) { + char ethaddr[22]; + /* [0..3] Must be in sync with CONFIG_ETHADDR */ + gd->bd->bi_enetaddr[0] = 0x00; + gd->bd->bi_enetaddr[1] = 0x60; + gd->bd->bi_enetaddr[2] = 0x13; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, + ethaddr, serial); + setenv ("ethaddr", ethaddr); + } + return 0; +} + +#define DO_UGLY_SDRAM_WORKAROUND +#ifdef DO_UGLY_SDRAM_WORKAROUND + #include "i2c.h" +void set_spd_default_value(unsigned int spd_addr,uchar def_val) +{ + uchar value; + int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ; + if (res == 0 && value == 0xff) { + res = i2c_write(SPD_EEPROM_ADDRESS, + spd_addr, 1, &def_val, 1) ; +#ifdef DEBUG + printf("%s: Setting spd offset %3d to %3d res %d\n", + __FUNCTION__, spd_addr, def_val, res); +#endif + } +} +#endif + +long int initdram(int board_type) +{ + long dram_size = 0; + +#if !defined(CONFIG_SPD_EEPROM) + dram_size = fixed_hcu4_sdram(); +#else +#ifdef DO_UGLY_SDRAM_WORKAROUND + /* Workaround if you have no working I2C-EEPROM-SPD-configuration */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + set_spd_default_value(2, 4); /* SDRAM Type */ + set_spd_default_value(7, 0); /* module width, high byte */ + set_spd_default_value(12, 1); /* Refresh or 0x81 */ + + /* Only correct for HCU3 with 32 MB RAM*/ + /* Number of bytes used by module manufacturer */ + set_spd_default_value( 0, 128); + set_spd_default_value( 1, 11 ); /* Total SPD memory size */ + set_spd_default_value( 2, 4 ); /* Memory type */ + set_spd_default_value( 3, 12 ); /* Number of row address bits */ + set_spd_default_value( 4, 9 ); /* Number of column address bits */ + set_spd_default_value( 5, 1 ); /* Number of module rows */ + set_spd_default_value( 6, 32 ); /* Module data width, LSB */ + set_spd_default_value( 7, 0 ); /* Module data width, MSB */ + set_spd_default_value( 8, 1 ); /* Module interface signal levels */ + /* SDRAM cycle time for highest CL (Tclk) */ + set_spd_default_value( 9, 112); + /* SDRAM access time from clock for highest CL (Tac) */ + set_spd_default_value(10, 84 ); + set_spd_default_value(11, 2 ); /* Module configuration type */ + set_spd_default_value(12, 128); /* Refresh rate/type */ + set_spd_default_value(13, 16 ); /* Primary SDRAM width */ + set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */ + /* SDRAM device attributes, min clock delay for back to back */ + /*random column addresses (Tccd) */ + set_spd_default_value(15, 1 ); + /* SDRAM device attributes, burst lengths supported */ + set_spd_default_value(16, 143); + /* SDRAM device attributes, number of banks on SDRAM device */ + set_spd_default_value(17, 4 ); + /* SDRAM device attributes, CAS latency */ + set_spd_default_value(18, 6 ); + /* SDRAM device attributes, CS latency */ + set_spd_default_value(19, 1 ); + /* SDRAM device attributes, WE latency */ + set_spd_default_value(20, 1 ); + set_spd_default_value(21, 0 ); /* SDRAM module attributes */ + /* SDRAM device attributes, general */ + set_spd_default_value(22, 14 ); + /* SDRAM cycle time for 2nd highest CL (Tclk) */ + set_spd_default_value(23, 117); + /* SDRAM access time from clock for2nd highest CL (Tac) */ + set_spd_default_value(24, 84 ); + /* SDRAM cycle time for 3rd highest CL (Tclk) */ + set_spd_default_value(25, 0 ); + /* SDRAM access time from clock for3rd highest CL (Tac) */ + set_spd_default_value(26, 0 ); + set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */ + /* Minimum row active to row active delay (Trrd) */ + set_spd_default_value(28, 14 ); + set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */ + set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */ + set_spd_default_value(31, 8 ); /* Module bank density */ + /* Command and Address signal input setup time */ + set_spd_default_value(32, 21 ); + /* Command and Address signal input hold time */ + set_spd_default_value(33, 8 ); + set_spd_default_value(34, 21 ); /* Data signal input setup time */ + set_spd_default_value(35, 8 ); /* Data signal input hold time */ +#endif /* DO_UGLY_SDRAM_WORKAROUND */ + dram_size = spd_sdram(0); +#endif + +#ifdef DEBUG + show_sdram_registers(); +#endif + +#if defined(CFG_DRAM_TEST) + bcu4_testdram(dram_size); + printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024)); +#endif + return dram_size; +} + + -- cgit v1.1 From 157cda4d0c3d592ccbb19bbfc07d9251894f0894 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Fri, 27 Jul 2007 11:31:22 +0200 Subject: Add PPC4xx-HCU4 and HCU5 boards: HCU5 files Signed-off-by: Niklaus Giger --- board/netstal/hcu5/hcu5.c | 526 +++++++++++++++++++++++++++++++++++++++++++++ board/netstal/hcu5/init.S | 81 +++++++ board/netstal/hcu5/sdram.c | 299 ++++++++++++++++++++++++++ 3 files changed, 906 insertions(+) create mode 100644 board/netstal/hcu5/hcu5.c create mode 100644 board/netstal/hcu5/init.S create mode 100644 board/netstal/hcu5/sdram.c (limited to 'board') diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c new file mode 100644 index 0000000..59107b9 --- /dev/null +++ b/board/netstal/hcu5/hcu5.c @@ -0,0 +1,526 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void sysLedSet(u32 value); + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ + mtdcr(CPR0_CFGDATA,data); } while (0) +#define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ + data = mfdcr(CPR0_CFGDATA); } while (0) + +#define SDR0_CP440 0x0180 + +/* + * This function is run very early, out of flash, and before devices are + * initialized. It is called by lib_ppc/board.c:board_init_f by virtue + * of being in the init_sequence array. + * + * The SDRAM has been initialized already -- start.S:start called + * init.S:init_sdram early on -- but it is not yet being used for + * anything, not even stack. So be careful. + */ + +int board_early_init_f(void) +{ + u32 reg; + +#undef BOOTSTRAP_OPTION_A_ACTIVE +#ifdef BOOTSTRAP_OPTION_A_ACTIVE + /* Booting with Bootstrap Option A + * First boot, with CPR0_ICFG_RLI_MASK == 0 + * no we setup varios boot strapping register, + * then we do reset the PPC440 using a chip reset + * Unfortunately, we cannot use this option, as Nto1 is not set + * with Bootstrap Option A and cannot be changed later on by SW + * There are no other possible boostrap options with a 8 bit ROM + * See Errata (Version 1.04) CHIP_9 + */ + + u32 cpr0icfg; + u32 dbcr; + mfcpr0(CPR0_ICFG, cpr0icfg); + if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) { + mtcpr0(CPR0_MALD, 0x02000000); + mtcpr0(CPR0_OPBD, 0x02000000); + mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */ + mtcpr0(CPR0_PLLC, 0x40000238); + mtcpr0(CPR0_PLLD, 0x01010414); + mtcpr0(CPR0_PRIMAD, 0x01000000); + mtcpr0(CPR0_PRIMBD, 0x01000000); + mtcpr0(CPR0_SPCID, 0x03000000); + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ + mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); + + /* + * Initiate system reset in debug control register DBCR + */ + dbcr = mfspr(dbcr0); + #define SYSTEM_RESET 0x30000000 + #define CHIP_RESET 0x20000000 + mtspr(dbcr0, dbcr | CHIP_RESET ); + } + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ +#endif + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /* test-only: take GPIO init from pcs440ep ???? in config file */ + out32(GPIO0_OR, 0x00000000); + out32(GPIO0_TCR, 0x7C2FF1CF); + out32(GPIO0_OSRL, 0x40055000); + out32(GPIO0_OSRH, 0x00000000); + out32(GPIO0_TSRL, 0x40055000); + out32(GPIO0_TSRH, 0x00000400); + out32(GPIO0_ISR1L, 0x40000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2H, 0x00000000); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OR, 0x00000000); + out32(GPIO1_TCR, 0xC6007FFF); + out32(GPIO1_OSRL, 0x00140000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x00000000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x05415555); + out32(GPIO1_ISR1H, 0x40000000); + out32(GPIO1_ISR2L, 0x00000000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x00000000); + out32(GPIO1_ISR3H, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ + mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ + + /* PCI arbiter enabled */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); + + pci_pre_init(0); + + /* setup BOOT FLASH */ + mtsdr(SDR0_CUST0, 0xC0082350); + + return 0; +} + +#ifdef CONFIG_BOARD_PRE_INIT +int board_pre_init (void) +{ + return board_early_init_f (); +} + +#endif + +enum { + /* HW_GENERATION_HCU1 is no longer supported */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_HCU5 = 0x30, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + +int checkboard (void) +{ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + unsigned j; + uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER; + uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER; + uint16_t generation = *boardVersReg & 0xf0; + uint16_t index = *boardVersReg & 0x0f; + ulong ecid0, ecid1, ecid2, ecid3; + printf ("Netstal Maschinen AG: "); + if (generation == HW_GENERATION_HCU3) + printf ("HCU3: index %d", index); + else if (generation == HW_GENERATION_HCU4) + printf ("HCU4: index %d", index); + else if (generation == HW_GENERATION_HCU5) + printf ("HCU5: index %d", index); + printf (" HW 0x%02x\n", *hwVersReg & 0xff); + mfsdr(SDR0_ECID0, ecid0); + mfsdr(SDR0_ECID1, ecid1); + mfsdr(SDR0_ECID2, ecid2); + mfsdr(SDR0_ECID3, ecid3); + + printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); + for (j=0; j < 6;j++) { + sysLedSet(1 << j); + udelay(200*1000); + } + return 0; +} + +#define SYS_IO_ADDRESS 0xcce00000 + +u32 sysLedGet(void) +{ + return in16(SYS_IO_ADDRESS) & 0x3f; +} + +void sysLedSet(u32 value /* value to place in LEDs */) +{ + out16(SYS_IO_ADDRESS, value); +} + +/*---------------------------------------------------------------------------+ + * getSerialNr + *---------------------------------------------------------------------------*/ +static u32 getSerialNr(void) +{ + u32 *serial = (u32 *)CFG_FLASH_BASE; + if (*serial == 0xffffffff) { + return get_ticks(); + } + return *serial; +} + + +/*---------------------------------------------------------------------------+ + * misc_init_r. + *---------------------------------------------------------------------------*/ + +#define DEFAULT_ETH_ADDR "ethaddr" +/* ethaddr for first or etha1ddr for second ethernet */ + +int misc_init_r(void) +{ + char *s = getenv(DEFAULT_ETH_ADDR); + char *e; + int i; + u32 serial = getSerialNr(); + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + + for (i = 0; i < 6; ++i) { + gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + if (gd->bd->bi_enetaddr[3] == 0 && + gd->bd->bi_enetaddr[4] == 0 && + gd->bd->bi_enetaddr[5] == 0) { + char ethaddr[22]; + /* Must be in sync with CONFIG_ETHADDR */ + gd->bd->bi_enetaddr[0] = 0x00; + gd->bd->bi_enetaddr[1] = 0x60; + gd->bd->bi_enetaddr[2] = 0x13; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + /* byte[5].bit 0 must be zero */ + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, + ethaddr, serial); + setenv (DEFAULT_ETH_ADDR, ethaddr); + } +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + /* + * USB stuff... + */ + + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ + + sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets*/ + udelay (1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + return 0; +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------+ + * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. + * Workaround: Disable write pipelining to DDR SDRAM by setting + * PLB0_ACR[WRP] = 0. + *-------------------------------------------------------------------*/ + + /*-------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + // mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ + + /*-------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ +// mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + mtdcr(plb4_acr, addr); /* Sequoia */ + + /*-------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; +// addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */ + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ + + // mtdcr(plb0_acr, addr); /* Sequoia */ + mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF + + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) ; + // mtdcr(plb1_acr, addr); /* Sequoia */ + mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*-------------------------------------------------------------+ + * Set up Direct MMIO registers + *-------------------------------------------------------------*/ + /*-------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address + | 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +-------------------------------------------------------------*/ + /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0MA, 0x00000000); + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM0MA, 0xE0000001); + + /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1MA, 0x00000000); + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + /* 512M + No prefetching, and enable region */ + out32r(PCIX0_PMM1MA, 0xE0000001); + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*------------------------------------------------------------------+ + * Set up Configuration registers + *------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*---------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif +/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ + diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S new file mode 100644 index 0000000..6da5f22 --- /dev/null +++ b/board/netstal/hcu5/init.S @@ -0,0 +1,81 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* vxWorks needs this entry for the Machine Check interrupt, */ + /* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ + + /* + * BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for EBC (CFG_CPLD) */ + // tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* CAN */ + tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* IMC + CPLD */ + tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* IMC-Fast */ + tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB for SDRAM will be added by initdram (sdram.c) */ + + tlbtab_end + + diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c new file mode 100644 index 0000000..f7d6865 --- /dev/null +++ b/board/netstal/hcu5/sdram.c @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2007 + * Niklaus Giger (Niklaus.Giger@netstal.com) + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debug output */ +#undef DEBUG + +#include +#include +#include +#include +#include + +void sysLedSet(u32 value); +void dcbz_area(u32 start_address, u32 num_bytes); +void dflush(void); + +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) + +#ifdef CFG_ENABLE_SDRAM_CACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ +#endif + +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); + +#ifdef CONFIG_ADD_RAM_INFO +void board_add_ram_info(int use_default) +{ + PPC440_SYS_INFO board_cfg; + u32 val; + mfsdram(DDR0_22, val); + val &= DDR0_22_CTRL_RAW_MASK; + switch (val) { + case DDR0_22_CTRL_RAW_ECC_DISABLE: + puts(" (ECC disabled"); + break; + case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY: + puts(" (ECC check only"); + break; + case DDR0_22_CTRL_RAW_NO_ECC_RAM: + puts(" (no ECC ram"); + break; + case DDR0_22_CTRL_RAW_ECC_ENABLE: + puts(" (ECC enabled"); + break; + } + + get_sys_info(&board_cfg); + printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000); + + mfsdram(DDR0_03, val); + val = DDR0_03_CASLAT_DECODE(val); + printf(", CL%d)", val); +} +#endif + +/*-------------------------------------------------------------------- + * wait_for_dlllock. + *--------------------------------------------------------------------*/ +static int wait_for_dlllock(void) +{ + unsigned long val; + int wait = 0; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_17); + val = DDR0_17_DLLLOCKREG_UNLOCKED; + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_17_DLLLOCKREG_MASK) == + DDR0_17_DLLLOCKREG_LOCKED) + /* dlllockreg bit on */ + return 0; + else + wait++; + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + + return -1; +} + +/*********************************************************************** + * + * sdram_panic -- Panic if we cannot configure the sdram correctly + * + ************************************************************************/ +void sdram_panic(const char *reason) +{ + printf("\n%s: reason %s", __FUNCTION__, reason); + sysLedSet(0xff); + while (1) { + } + /* Never return */ +} + +#ifdef CONFIG_DDR_ECC +static void blank_string(int size) +{ + int i; + + for (i=0; i> ! */ + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02030602); + mtsdram(DDR0_04, 0x0A020200); + mtsdram(DDR0_05, 0x02020307); + switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { + case 0: + dram_size = 128 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C80D); // 128MB RAM + mtsdram(DDR0_11, 0x000FC800); // 128MB RAM + mtsdram(DDR0_43, 0x030A0300); // 128MB RAM + break; + case 1: + dram_size = 256 * 1024 * 1024 ; + mtsdram(DDR0_06, 0x0102C812); // 256MB RAM + mtsdram(DDR0_11, 0x0014C800); // 256MB RAM + mtsdram(DDR0_43, 0x030A0200); // 256MB RAM + break; + default: + sdram_panic(INVALID_HW_CONFIG); + break; + } + dram_size -= 16 * 1024 * 1024; + mtsdram(DDR0_07, 0x00090100); + // TCPD=200 cycles of clock input is required to lock the DLL. + // CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + mtsdram(DDR0_08, 0x02C80001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000100); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x1D000000); + mtsdram(DDR0_18, 0x1D1D1D1D); + mtsdram(DDR0_19, 0x1D1D1D1D); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); + #define ECC_RAM 0x03267F0B + #define NO_ECC_RAM 0x00267F0B +#ifdef CONFIG_DDR_ECC + mtsdram(DDR0_22, ECC_RAM); +#else + mtsdram(DDR0_22, NO_ECC_RAM); +#endif + + mtsdram(DDR0_23, 0x00000000); + mtsdram(DDR0_24, 0x01020001); + mtsdram(DDR0_26, 0x2D930517); + mtsdram(DDR0_27, 0x00008236); + mtsdram(DDR0_28, 0x00000000); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000006); + mtsdram(DDR0_44, 0x00000003); + mtsdram(DDR0_02, 0x00000001); + wait_for_dlllock(); + mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ + + /* + * Program tlb entries for this size (dynamic) + */ + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); + + /* + * Setup 2nd TLB with same physical address but different virtual + * address with cache enabled. This is done for fast ECC generation. + */ + program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + +#ifdef CONFIG_DDR_ECC + /* + * If ECC is enabled, initialize the parity bits. + */ + program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0); +#endif + + return (dram_size); +} -- cgit v1.1 From 35d22f957a85a22bb3cd1ad084fa5404620d1c42 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 10 Aug 2007 10:42:25 +0200 Subject: Coding style cleanup Signed-off-by: Stefan Roese --- board/netstal/common/nm_bsp.c | 1 - board/netstal/hcu4/config.mk | 1 - board/netstal/hcu4/hcu4.c | 80 ++++++++++--------- board/netstal/hcu5/config.mk | 1 - board/netstal/hcu5/hcu5.c | 177 +++++++++++++++++++++--------------------- board/netstal/hcu5/init.S | 4 +- board/netstal/hcu5/sdram.c | 23 +++--- 7 files changed, 147 insertions(+), 140 deletions(-) (limited to 'board') diff --git a/board/netstal/common/nm_bsp.c b/board/netstal/common/nm_bsp.c index ee1b684..1e06780 100644 --- a/board/netstal/common/nm_bsp.c +++ b/board/netstal/common/nm_bsp.c @@ -39,4 +39,3 @@ U_BOOT_CMD( "Help for Netstal Maschinen BSP specific command.\n" ); #endif - diff --git a/board/netstal/hcu4/config.mk b/board/netstal/hcu4/config.mk index f5a4ce4..376609a 100644 --- a/board/netstal/hcu4/config.mk +++ b/board/netstal/hcu4/config.mk @@ -26,4 +26,3 @@ TEXT_BASE = 0xFFFa0000 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG -g endif - diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index deb7d2d..252aaa7 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -27,10 +27,30 @@ DECLARE_GLOBAL_DATA_PTR; +#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000) + +#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } +#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } + +#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ + +#define DO_UGLY_SDRAM_WORKAROUND + +enum { + /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; + void sysLedSet(u32 value); -long int spd_sdram(int(read_spd)(uint addr)) +long int spd_sdram(int(read_spd)(uint addr)); + #ifdef CONFIG_SPD_EEPROM - #define DEBUG +#define DEBUG #endif #if defined(DEBUG) @@ -86,26 +106,15 @@ int board_pre_init (void) { return board_early_init_f (); } - #endif -enum { - /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ - HW_GENERATION_HCU2 = 0x10, - HW_GENERATION_HCU3 = 0x10, - HW_GENERATION_HCU4 = 0x20, - HW_GENERATION_MCU = 0x08, - HW_GENERATION_MCU20 = 0x0a, - HW_GENERATION_MCU25 = 0x09, -}; - int checkboard (void) { -#define HCU_MACH_VERSIONS_REGISTER ( 0x7C000000 + 0xF00000 ) - unsigned j; - uint16_t *boardVersReg = (uint16_t *) HCU_MACH_VERSIONS_REGISTER; - uint16_t generation = *boardVersReg & 0xf0; - uint16_t index = *boardVersReg & 0x0f; + unsigned int j; + u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER; + u16 generation = *boardVersReg & 0xf0; + u16 index = *boardVersReg & 0x0f; + /* Force /RTS to active. The board it not wired quite correctly to use cts/rtc flow control, so just force the /RST active and forget about it. */ @@ -117,24 +126,26 @@ int checkboard (void) printf ("HCU4: index %d\n\n", index); /* GPIO here noch nicht richtig initialisert !!! */ sysLedSet(0); - for (j=0; j < 7;j++) { + for (j = 0; j < 7; j++) { sysLedSet(1 << j); - udelay(50*1000); + udelay(50 * 1000); } + return 0; } u32 sysLedGet(void) { - return( ~( (*(u32 *)GPIO0_OR)) >> 23) & 0xff; + return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; } void sysLedSet(u32 value /* value to place in LEDs */) { u32 tmp = ~value; u32 *ledReg; - tmp = (tmp << 23) | 0x7FFFFF; - ledReg = (u32 *)GPIO0_OR; + + tmp = (tmp << 23) | 0x7FFFFF; + ledReg = (u32 *)GPIO0_OR; *ledReg = tmp; } @@ -147,13 +158,11 @@ void sdram_init(void) return; } -#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } -#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); } - #if defined(DEBUG) void show_sdram_registers(void) { u32 value; + printf ("SDRAM Controller Registers --\n"); mfsdram(value, mem_mcopt1); printf (" SDRAM0_CFG : 0x%08x\n", value); @@ -170,8 +179,6 @@ void show_sdram_registers(void) } #endif -#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ - /* * this is even after checkboard. It returns the size of the SDRAM * that we have installed. This function is called by board_init_f @@ -244,9 +251,10 @@ long int fixed_hcu4_sdram (int board_type) static u32 getSerialNr(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; - if (*serial == 0xffffffff) { + + if (*serial == 0xffffffff) return get_ticks(); - } + return *serial; } @@ -260,12 +268,14 @@ int misc_init_r(void) char *s = getenv("ethaddr"); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = getSerialNr(); + for (i = 0; i < 6; ++i) { gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; if (s) s = (*e) ? e + 1 : e; } + if (gd->bd->bi_enetaddr[3] == 0 && gd->bd->bi_enetaddr[4] == 0 && gd->bd->bi_enetaddr[5] == 0) { @@ -288,13 +298,14 @@ int misc_init_r(void) return 0; } -#define DO_UGLY_SDRAM_WORKAROUND #ifdef DO_UGLY_SDRAM_WORKAROUND - #include "i2c.h" +#include "i2c.h" + void set_spd_default_value(unsigned int spd_addr,uchar def_val) { uchar value; int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ; + if (res == 0 && value == 0xff) { res = i2c_write(SPD_EEPROM_ADDRESS, spd_addr, 1, &def_val, 1) ; @@ -387,7 +398,6 @@ long int initdram(int board_type) bcu4_testdram(dram_size); printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024)); #endif + return dram_size; } - - diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk index 58ec2af..cfd5744 100644 --- a/board/netstal/hcu5/config.mk +++ b/board/netstal/hcu5/config.mk @@ -28,4 +28,3 @@ PLATFORM_CPPFLAGS += -DCONFIG_440=1 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG -g endif - diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 59107b9..23df081 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -29,12 +29,34 @@ void sysLedSet(u32 value); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -#define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ - mtdcr(CPR0_CFGDATA,data); } while (0) -#define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \ - data = mfdcr(CPR0_CFGDATA); } while (0) +#undef BOOTSTRAP_OPTION_A_ACTIVE + +#define SDR0_CP440 0x0180 + +#define SYSTEM_RESET 0x30000000 +#define CHIP_RESET 0x20000000 + +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +#define SYS_IO_ADDRESS 0xcce00000 + +#define DEFAULT_ETH_ADDR "ethaddr" +/* ethaddr for first or etha1ddr for second ethernet */ + +enum { + /* HW_GENERATION_HCU1 is no longer supported */ + HW_GENERATION_HCU2 = 0x10, + HW_GENERATION_HCU3 = 0x10, + HW_GENERATION_HCU4 = 0x20, + HW_GENERATION_HCU5 = 0x30, + HW_GENERATION_MCU = 0x08, + HW_GENERATION_MCU20 = 0x0a, + HW_GENERATION_MCU25 = 0x09, +}; -#define SDR0_CP440 0x0180 /* * This function is run very early, out of flash, and before devices are @@ -50,7 +72,6 @@ int board_early_init_f(void) { u32 reg; -#undef BOOTSTRAP_OPTION_A_ACTIVE #ifdef BOOTSTRAP_OPTION_A_ACTIVE /* Booting with Bootstrap Option A * First boot, with CPR0_ICFG_RLI_MASK == 0 @@ -64,27 +85,26 @@ int board_early_init_f(void) u32 cpr0icfg; u32 dbcr; - mfcpr0(CPR0_ICFG, cpr0icfg); - if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) { - mtcpr0(CPR0_MALD, 0x02000000); - mtcpr0(CPR0_OPBD, 0x02000000); - mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */ - mtcpr0(CPR0_PLLC, 0x40000238); - mtcpr0(CPR0_PLLD, 0x01010414); - mtcpr0(CPR0_PRIMAD, 0x01000000); - mtcpr0(CPR0_PRIMBD, 0x01000000); - mtcpr0(CPR0_SPCID, 0x03000000); - mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ - mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ - mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); + + mfcpr(CPR0_ICFG, cpr0icfg); + if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { + mtcpr(CPR0_MALD, 0x02000000); + mtcpr(CPR0_OPBD, 0x02000000); + mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ + mtcpr(CPR0_PLLC, 0x40000238); + mtcpr(CPR0_PLLD, 0x01010414); + mtcpr(CPR0_PRIMAD, 0x01000000); + mtcpr(CPR0_PRIMBD, 0x01000000); + mtcpr(CPR0_SPCID, 0x03000000); + mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ + mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ + mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); /* * Initiate system reset in debug control register DBCR */ dbcr = mfspr(dbcr0); - #define SYSTEM_RESET 0x30000000 - #define CHIP_RESET 0x20000000 - mtspr(dbcr0, dbcr | CHIP_RESET ); + mtspr(dbcr0, dbcr | CHIP_RESET); } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif @@ -162,60 +182,42 @@ int board_early_init_f(void) return 0; } -#ifdef CONFIG_BOARD_PRE_INIT -int board_pre_init (void) +int board_pre_init(void) { - return board_early_init_f (); + return board_early_init_f(); } -#endif - -enum { - /* HW_GENERATION_HCU1 is no longer supported */ - HW_GENERATION_HCU2 = 0x10, - HW_GENERATION_HCU3 = 0x10, - HW_GENERATION_HCU4 = 0x20, - HW_GENERATION_HCU5 = 0x30, - HW_GENERATION_MCU = 0x08, - HW_GENERATION_MCU20 = 0x0a, - HW_GENERATION_MCU25 = 0x09, -}; - -int checkboard (void) +int checkboard(void) { -#define SDR0_ECID0 0x0080 -#define SDR0_ECID1 0x0081 -#define SDR0_ECID2 0x0082 -#define SDR0_ECID3 0x0083 - unsigned j; - uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER; - uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER; - uint16_t generation = *boardVersReg & 0xf0; - uint16_t index = *boardVersReg & 0x0f; - ulong ecid0, ecid1, ecid2, ecid3; - printf ("Netstal Maschinen AG: "); + unsigned int j; + u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; + u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; + u16 generation = *boardVersReg & 0xf0; + u16 index = *boardVersReg & 0x0f; + u32 ecid0, ecid1, ecid2, ecid3; + + printf("Netstal Maschinen AG: "); if (generation == HW_GENERATION_HCU3) - printf ("HCU3: index %d", index); + printf("HCU3: index %d", index); else if (generation == HW_GENERATION_HCU4) - printf ("HCU4: index %d", index); + printf("HCU4: index %d", index); else if (generation == HW_GENERATION_HCU5) - printf ("HCU5: index %d", index); - printf (" HW 0x%02x\n", *hwVersReg & 0xff); + printf("HCU5: index %d", index); + printf(" HW 0x%02x\n", *hwVersReg & 0xff); mfsdr(SDR0_ECID0, ecid0); mfsdr(SDR0_ECID1, ecid1); mfsdr(SDR0_ECID2, ecid2); mfsdr(SDR0_ECID3, ecid3); - printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); - for (j=0; j < 6;j++) { + printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); + for (j = 0;j < 6; j++) { sysLedSet(1 << j); - udelay(200*1000); + udelay(200 * 1000); } + return 0; } -#define SYS_IO_ADDRESS 0xcce00000 - u32 sysLedGet(void) { return in16(SYS_IO_ADDRESS) & 0x3f; @@ -232,9 +234,10 @@ void sysLedSet(u32 value /* value to place in LEDs */) static u32 getSerialNr(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; - if (*serial == 0xffffffff) { + + if (*serial == 0xffffffff) return get_ticks(); - } + return *serial; } @@ -242,45 +245,44 @@ static u32 getSerialNr(void) /*---------------------------------------------------------------------------+ * misc_init_r. *---------------------------------------------------------------------------*/ - -#define DEFAULT_ETH_ADDR "ethaddr" -/* ethaddr for first or etha1ddr for second ethernet */ - int misc_init_r(void) { char *s = getenv(DEFAULT_ETH_ADDR); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = getSerialNr(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; for (i = 0; i < 6; ++i) { - gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; + gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; if (s) s = (*e) ? e + 1 : e; } + if (gd->bd->bi_enetaddr[3] == 0 && gd->bd->bi_enetaddr[4] == 0 && gd->bd->bi_enetaddr[5] == 0) { char ethaddr[22]; + /* Must be in sync with CONFIG_ETHADDR */ gd->bd->bi_enetaddr[0] = 0x00; gd->bd->bi_enetaddr[1] = 0x60; gd->bd->bi_enetaddr[2] = 0x13; - gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; - gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; + gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; + gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; /* byte[5].bit 0 must be zero */ - gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; - sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", - gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], - gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], - gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; + gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", + gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], + gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], + gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, ethaddr, serial); - setenv (DEFAULT_ETH_ADDR, ethaddr); + setenv(DEFAULT_ETH_ADDR, ethaddr); } + #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -334,9 +336,9 @@ int misc_init_r(void) mtsdr(SDR0_USB2H0CR, usb2h0cr); /*clear resets*/ - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); + udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); @@ -356,7 +358,7 @@ int misc_init_r(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -374,7 +376,7 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(sdr_amp1, addr); mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb3_acr); - // mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ /*-------------------------------------------------------------------+ @@ -383,7 +385,7 @@ int pci_pre_init(struct pci_controller *hose) mfsdr(sdr_amp0, addr); mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ -// mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */ + /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ mtdcr(plb4_acr, addr); /* Sequoia */ /*-------------------------------------------------------------------+ @@ -393,24 +395,23 @@ int pci_pre_init(struct pci_controller *hose) addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; -// addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */ + /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ - // mtdcr(plb0_acr, addr); /* Sequoia */ - mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF - + /* mtdcr(plb0_acr, addr); */ /* Sequoia */ + mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; addr = (addr & ~plb1_acr_wrp_mask) ; - // mtdcr(plb1_acr, addr); /* Sequoia */ - mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF + /* mtdcr(plb1_acr, addr); */ /* Sequoia */ + mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -476,7 +477,6 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_word(0, PCI_ERREN, 0); pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ @@ -523,4 +523,3 @@ int is_pci_host(struct pci_controller *hose) return 1; } #endif /* defined(CONFIG_PCI) */ - diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index 6da5f22..5ab6cd2 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -55,7 +55,7 @@ tlbtab: tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for EBC (CFG_CPLD) */ - // tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + /* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ /* CAN */ tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* IMC + CPLD */ @@ -77,5 +77,3 @@ tlbtab: /* TLB for SDRAM will be added by initdram (sdram.c) */ tlbtab_end - - diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index f7d6865..4039195 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -216,8 +216,9 @@ long int initdram (int board_type) { #define HCU_HW_SDRAM_CONFIG_MASK 0x7 #define INVALID_HW_CONFIG "Invalid HW-Config" - uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER; - unsigned int dram_size=0; + u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; + unsigned int dram_size = 0; + mtsdram(DDR0_02, 0x00000000); /* Values must be kept in sync with Excel-table <> ! */ @@ -229,15 +230,15 @@ long int initdram (int board_type) switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { case 0: dram_size = 128 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C80D); // 128MB RAM - mtsdram(DDR0_11, 0x000FC800); // 128MB RAM - mtsdram(DDR0_43, 0x030A0300); // 128MB RAM + mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ + mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ + mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ break; case 1: dram_size = 256 * 1024 * 1024 ; - mtsdram(DDR0_06, 0x0102C812); // 256MB RAM - mtsdram(DDR0_11, 0x0014C800); // 256MB RAM - mtsdram(DDR0_43, 0x030A0200); // 256MB RAM + mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ + mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ + mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ break; default: sdram_panic(INVALID_HW_CONFIG); @@ -245,8 +246,10 @@ long int initdram (int board_type) } dram_size -= 16 * 1024 * 1024; mtsdram(DDR0_07, 0x00090100); - // TCPD=200 cycles of clock input is required to lock the DLL. - // CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + /* + * TCPD=200 cycles of clock input is required to lock the DLL. + * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); + */ mtsdram(DDR0_08, 0x02C80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); -- cgit v1.1 From cf0b185e58ca0aec8ae2b2a8804ec0ef58ee21d4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 6 Aug 2007 17:39:44 -0500 Subject: 8641hpcn: Do correct sized pointer math. When I rebased Ed's patch and cleaned up a few compilation problems, I apparently rebased my brain on crack first. Fix that by doing (char *) sized pointer math as needed. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d2182ab..1bfbe88 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -268,8 +268,8 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) CFG_PCI1_MEM_BASE - + CFG_PCI1_MEM_SIZE - 0x1000000); + in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000))); } else { puts("PCI-EXPRESS 1: Disabled\n"); -- cgit v1.1 From c74b2108e31fe09bd1c5d291c3cf360510d4f13e Mon Sep 17 00:00:00 2001 From: Sergey Kubushyn Date: Fri, 10 Aug 2007 20:26:18 +0200 Subject: [ARM] TI DaVinci support, hopefully final Add support for the following DaVinci boards: - DV_EVM - SCHMOOGIE - SONATA Changes: - Split into separate board directories - Removed changes to MTD_DEBUG (or whatever it's called) - New CONFIG_CMD party line followed - Some cosmetic fixes, cleanup etc. - Patches against the latest U-Boot tree as of now. - Fixed CONFIG_CMD_NET in net files. - Fixed CONFIG_CMD_EEPROM for schmoogie. - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and DV_EVM. Can't check if it works on SONATA, don't have a board any more, but it at least compiles. Here is an excerpt from session log on SCHMOOGIE... U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) DRAM: 128 MB NAND: 128 MiB In: serial Out: serial Err: serial ARM Clock : 297MHz DDR Clock : 162MHz ETH PHY : DP83848 @ 0x01 U-Boot > iprobe Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F U-Boot > ping 192.168.253.10 host 192.168.253.10 is alive U-Boot > Signed-off-by: Sergey Kubushyn Acked-by: Dirk Behme Acked-by: Zach Sadecki Acked-by: Stefan Roese --- board/davinci/dv-evm/Makefile | 52 +++++++ board/davinci/dv-evm/board_init.S | 29 ++++ board/davinci/dv-evm/config.mk | 39 ++++++ board/davinci/dv-evm/dv_board.c | 211 +++++++++++++++++++++++++++++ board/davinci/dv-evm/u-boot.lds | 52 +++++++ board/davinci/schmoogie/Makefile | 52 +++++++ board/davinci/schmoogie/board_init.S | 29 ++++ board/davinci/schmoogie/config.mk | 39 ++++++ board/davinci/schmoogie/dv_board.c | 253 +++++++++++++++++++++++++++++++++++ board/davinci/schmoogie/u-boot.lds | 52 +++++++ board/davinci/sonata/Makefile | 52 +++++++ board/davinci/sonata/board_init.S | 100 ++++++++++++++ board/davinci/sonata/config.mk | 39 ++++++ board/davinci/sonata/dv_board.c | 208 ++++++++++++++++++++++++++++ board/davinci/sonata/u-boot.lds | 52 +++++++ 15 files changed, 1259 insertions(+) create mode 100644 board/davinci/dv-evm/Makefile create mode 100644 board/davinci/dv-evm/board_init.S create mode 100644 board/davinci/dv-evm/config.mk create mode 100644 board/davinci/dv-evm/dv_board.c create mode 100644 board/davinci/dv-evm/u-boot.lds create mode 100644 board/davinci/schmoogie/Makefile create mode 100644 board/davinci/schmoogie/board_init.S create mode 100644 board/davinci/schmoogie/config.mk create mode 100644 board/davinci/schmoogie/dv_board.c create mode 100644 board/davinci/schmoogie/u-boot.lds create mode 100644 board/davinci/sonata/Makefile create mode 100644 board/davinci/sonata/board_init.S create mode 100644 board/davinci/sonata/config.mk create mode 100644 board/davinci/sonata/dv_board.c create mode 100644 board/davinci/sonata/u-boot.lds (limited to 'board') diff --git a/board/davinci/dv-evm/Makefile b/board/davinci/dv-evm/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/dv-evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dv-evm/board_init.S b/board/davinci/dv-evm/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/davinci/dv-evm/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/dv-evm/config.mk b/board/davinci/dv-evm/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/dv-evm/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c new file mode 100644 index 0000000..94925ec --- /dev/null +++ b/board/davinci/dv-evm/dv_board.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_DAVINCI_EVM 901 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1); + + setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc")); + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/dv-evm/u-boot.lds b/board/davinci/dv-evm/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/davinci/dv-evm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/schmoogie/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/davinci/schmoogie/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/schmoogie/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c new file mode 100644 index 0000000..b15c5f7 --- /dev/null +++ b/board/davinci/schmoogie/dv_board.c @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_SCHMOOGIE 1255 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + /* Set serial number from UID chip */ + u_int8_t crc_tbl[256] = { + 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, + 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, + 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e, + 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, + 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0, + 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62, + 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, + 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff, + 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5, + 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, + 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58, + 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a, + 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, + 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24, + 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b, + 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, + 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f, + 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd, + 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, + 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50, + 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c, + 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, + 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1, + 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73, + 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, + 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b, + 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4, + 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, + 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a, + 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8, + 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, + 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35 + }; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set serial number from UID chip */ + if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + if (buf[0] != 0x70) { /* Device Family Code */ + printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } + } + /* Now check CRC */ + tmp[0] = 0; + for (i = 0; i < 8; i++) + tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; + + if (tmp[0] != 0) { + printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR); + forceenv("serial#", "FAILED"); + } else { + /* CRC OK, set "serial" env variable */ + sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", + buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); + forceenv("serial#", (char *)&tmp[0]); + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/schmoogie/u-boot.lds b/board/davinci/schmoogie/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/davinci/schmoogie/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/sonata/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S new file mode 100644 index 0000000..fbb9ea7 --- /dev/null +++ b/board/davinci/sonata/board_init.S @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer + * Sonata boards, AFAIK, don't use this so it's just return by default. Ask + * Visioneering if they reinvented the wheel once again to make sure :) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl dv_board_init +dv_board_init: +#ifdef SONATA_BOARD_GPIOWP + /* Set PINMUX0 to enable GPIO4 */ + ldr r0, _PINMUX0 + ldr r1, GPIO4_EN_MASK + ldr r2, [r0] + and r2, r2, r1 + str r2, [r0] + + /* Enable GPIO LPSC module */ + ldr r0, PTSTAT + +gpio_ptstat_loop1: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop1 + + ldr r1, MDCTL_GPIO + ldr r2, [r1] + and r2, r2, $0xfffffff8 + orr r2, r2, $0x00000003 + str r2, [r1] + + orr r2, r2, $0x00000200 + str r2, [r1] + + ldr r1, PTCMD + mov r2, $0x00000001 + str r2, [r1] + +gpio_ptstat_loop2: + ldr r2, [r0] + tst r2, $0x00000001 + bne gpio_ptstat_loop2 + + ldr r0, MDSTAT_GPIO +gpio_mdstat_loop: + ldr r2, [r0] + and r2, r2, $0x0000001f + teq r2, $0x00000003 + bne gpio_mdstat_loop + + /* GPIO4 -> output */ + ldr r0, GPIO_DIR01 + mov r1, $0x10 + ldr r2, [r0] + bic r2, r2, r0 + str r2, [r0] + + /* Set it to 0 (Write Protect) */ + ldr r0, GPIO_CLR_DATA01 + str r1, [r0] +#endif + + mov pc, lr + +#ifdef SONATA_BOARD_GPIOWP +.ltorg + +GPIO4_EN_MASK: + .word 0xf77fffff +MDCTL_GPIO: + .word 0x01c41a68 +MDSTAT_GPIO: + .word 0x01c41868 +GPIO_DIR01: + .word 0x01c67010 +GPIO_CLR_DATA01: + .word 0x01c6701c +#endif diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/sonata/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2003 +# Texas Instruments, +# Swaminathan +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c new file mode 100644 index 0000000..7b0a459 --- /dev/null +++ b/board/davinci/sonata/dv_board.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include + +#define MACH_TYPE_SONATA 1254 + +extern void i2c_init(int speed, int slaveaddr); +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ( (id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO) + ) + *mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SONATA; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r (void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); + printf ("DDR Clock : %dMHz\n", (clk / 2)); + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("ethernet init failed!\n"); + } else { + printf("ETH PHY : %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/sonata/u-boot.lds b/board/davinci/sonata/u-boot.lds new file mode 100644 index 0000000..710b2a2 --- /dev/null +++ b/board/davinci/sonata/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} -- cgit v1.1 From 8ac273271d57321f90505c7a51cdb1ef2113b628 Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Thu, 9 Aug 2007 15:10:53 -0500 Subject: Add support for SBC8641D. Board files. Add support for Wind River's SBC8641D reference board. Signed-off by: Joe Hamman Acked-by: Wolfgang Denk Acked-by: Jon Loeliger --- board/sbc8641d/Makefile | 52 ++++++++ board/sbc8641d/config.mk | 30 +++++ board/sbc8641d/init.S | 192 +++++++++++++++++++++++++++ board/sbc8641d/sbc8641d.c | 326 ++++++++++++++++++++++++++++++++++++++++++++++ board/sbc8641d/u-boot.lds | 135 +++++++++++++++++++ 5 files changed, 735 insertions(+) create mode 100644 board/sbc8641d/Makefile create mode 100644 board/sbc8641d/config.mk create mode 100644 board/sbc8641d/init.S create mode 100644 board/sbc8641d/sbc8641d.c create mode 100644 board/sbc8641d/u-boot.lds (limited to 'board') diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile new file mode 100644 index 0000000..a90b725 --- /dev/null +++ b/board/sbc8641d/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/sbc8641d/config.mk b/board/sbc8641d/config.mk new file mode 100644 index 0000000..dd1754d --- /dev/null +++ b/board/sbc8641d/config.mk @@ -0,0 +1,30 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Jeff Brown +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# sbc8641 board +# default CCSRBAR is at 0xff700000 +# +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/sbc8641d/init.S b/board/sbc8641d/init.S new file mode 100644 index 0000000..c151d7e --- /dev/null +++ b/board/sbc8641d/init.S @@ -0,0 +1,192 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman joe.hamman@embeddedspecialties.com + * + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x0fff_ffff DDR1 256M + * 0x1000_0000 0x1fff_ffff DDR2 256M + * 0xe000_0000 0xffff_ffff LBC 512M + * + * Notes: + * CCSRBAR doesn't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +# DDR Bank 1 +# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +# DDR Bank 2 +# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) +# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +# LBC +# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff) +# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +/* + * LAW (Local Access Window) configuration: + * + * 0x0000_0000 DDR 256M + * 0x1000_0000 DDR2 256M + * 0x8000_0000 PCI1 MEM 512M + * 0xa000_0000 PCI2 MEM 512M + * 0xc000_0000 RapidIO 512M + * 0xe200_0000 PCI1 IO 16M + * 0xe300_0000 PCI2 IO 16M + * 0xf800_0000 CCSRBAR 2M + * 0xfe00_0000 FLASH (boot bank) 32M + * + */ + +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) +#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) + +#define LAWBAR4 ((0xf8000000>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) +#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) + +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) + +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + + blr diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c new file mode 100644 index 0000000..e5dd550 --- /dev/null +++ b/board/sbc8641d/sbc8641d.c @@ -0,0 +1,326 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman joe.hamman@embeddedspecialties.com + * + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup (void *blob, bd_t * bd); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc (unsigned int dram_size); +#endif + +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif + +void sdram_init (void); +long int fixed_sdram (void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts ("Board: Wind River SBC8641D\n"); + +#ifdef CONFIG_PCI + + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug ("\n"); + } else { + puts ("PCI-EXPRESS 1: Disabled in hardware\n"); + } + +#else + puts ("PCI-EXPRESS1: Disabled in configuration\n"); +#endif + + return 0; +} + +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + puts (" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc (dram_size); +#endif + + puts (" DDR: "); + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + puts ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts ("SDRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int fixed_sdram (void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs1_bnds = CFG_DDR_CS1_BNDS; + ddr->cs2_bnds = CFG_DDR_CS2_BNDS; + ddr->cs3_bnds = CFG_DDR_CS3_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->cs1_config = CFG_DDR_CS1_CONFIG; + ddr->cs2_config = CFG_DDR_CS2_CONFIG; + ddr->cs3_config = CFG_DDR_CS3_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_cfg_1 = CFG_DDR_CFG_1A; + ddr->sdram_cfg_2 = CFG_DDR_CFG_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + + asm ("sync;isync"); + + udelay (500); + + ddr->sdram_cfg_1 = CFG_DDR_CFG_1B; + asm ("sync; isync"); + + udelay (500); + ddr = &immap->im_ddr2; + + ddr->cs0_bnds = CFG_DDR2_CS0_BNDS; + ddr->cs1_bnds = CFG_DDR2_CS1_BNDS; + ddr->cs2_bnds = CFG_DDR2_CS2_BNDS; + ddr->cs3_bnds = CFG_DDR2_CS3_BNDS; + ddr->cs0_config = CFG_DDR2_CS0_CONFIG; + ddr->cs1_config = CFG_DDR2_CS1_CONFIG; + ddr->cs2_config = CFG_DDR2_CS2_CONFIG; + ddr->cs3_config = CFG_DDR2_CS3_CONFIG; + ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; + ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A; + ddr->sdram_cfg_2 = CFG_DDR2_CFG_2; + ddr->sdram_mode_1 = CFG_DDR2_MODE_1; + ddr->sdram_mode_2 = CFG_DDR2_MODE_2; + ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL; + ddr->sdram_interval = CFG_DDR2_INTERVAL; + ddr->sdram_data_init = CFG_DDR2_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL; + + asm ("sync;isync"); + + udelay (500); + + ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B; + asm ("sync; isync"); + + udelay (500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc86xxcts_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc86xx_init (struct pci_controller *hose); + + pci_mpc86xx_init (&hose); +#endif /* CONFIG_PCI */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t * bd) +{ + u32 *p; + int len; + + ft_cpu_setup (blob, bd); + + p = ft_get_prop (blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); + } +} +#endif + +void sbc8641d_reset_board (void) +{ + puts ("Resetting board....\n"); +} + +/* + * get_board_sys_clk + * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk (ulong dummy) +{ + int i; + ulong val = 0; + + i = 5; + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds new file mode 100644 index 0000000..fd0f350 --- /dev/null +++ b/board/sbc8641d/u-boot.lds @@ -0,0 +1,135 @@ +/* + * Copyright 2006, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/sbc8641d/init.o (.bootpg) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From afaac86fe2948ac84cd9a12bbed883b3c683e7d9 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 12 Aug 2007 14:27:39 +0200 Subject: Clean up some remaining CFG_CMD_ -> CONFIG_CMD_ issues. Signed-off-by: Wolfgang Denk --- board/cm5200/cmd_cm5200.c | 4 ++-- board/pcs440ep/pcs440ep.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 5119a99..fd9b914 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -27,7 +27,7 @@ #include #include -#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#ifdef CONFIG_CMD_BSB int do_i2c(char *argv[]) { @@ -445,4 +445,4 @@ U_BOOT_CMD( "fkt usb\n" " - Test USB communication\n" ); -#endif /* CFG_CMD_BSP */ +#endif /* CONFIG_CMD_BSP */ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 696423e..e247fee 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -879,7 +879,7 @@ int ide_preinit (void) } #endif -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) void ide_set_reset (int idereset) { debug ("ide_reset(%d)\n", idereset); @@ -890,4 +890,4 @@ void ide_set_reset (int idereset) } udelay (10000); } -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ -- cgit v1.1 From a4d2636f2a859245ed3a401f26189da2dfda4ceb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 12 Aug 2007 15:11:38 +0200 Subject: Adapt board configuration and fix kernel crash on MCC200 board. The update procedure was modified to turn off the USB subsystem before exit for MCC200 and TRAB. This is necessary as otherwise the USB controller continues to write periodically to system memory! MCC200-specific notes: - the patch disables the magic key check for MCC200 - the patch contains the configuration changes made for the new revision of the board. Signed-off-by: Sergei Poselenov Signed-off-by: Wolfgang Denk --- board/mcc200/auto_update.c | 18 +++++++++++++----- board/trab/auto_update.c | 16 ++++++++++------ 2 files changed, 23 insertions(+), 11 deletions(-) (limited to 'board') diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 6044565..28e4c87 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -330,6 +330,8 @@ int do_auto_update(void) int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; char *env; long start, end; + +#if 0 /* disable key-press detection to speed up boot-up time */ uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; /* @@ -347,6 +349,7 @@ int do_auto_update(void) return 0; } +#endif au_usb_stor_curr_dev = -1; /* start USB */ if (usb_stop() < 0) { @@ -364,18 +367,21 @@ int do_auto_update(void) au_usb_stor_curr_dev = usb_stor_scan(0); if (au_usb_stor_curr_dev == -1) { debug ("No device found. Not initialized?\n"); - return -1; + res = -1; + goto xit; } /* check whether it has a partition table */ stor_dev = get_dev("usb", 0); if (stor_dev == NULL) { debug ("uknown device type\n"); - return -1; + res = -1; + goto xit; } if (fat_register_device(stor_dev, 1) != 0) { debug ("Unable to use USB %d:%d for fatls\n", au_usb_stor_curr_dev, 1); - return -1; + res = -1; + goto xit; } if (file_fat_detectfs() != 0) { debug ("file_fat_detectfs failed\n"); @@ -504,7 +510,7 @@ int do_auto_update(void) } while (res < 0); #endif } - usb_stop(); + /* restore the old state */ disable_ctrlc(old_ctrlc); #ifdef CONFIG_PROGRESSBAR @@ -517,6 +523,8 @@ int do_auto_update(void) lcd_enable(); } #endif - return 0; + xit: + usb_stop(); + return res; } #endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 92120b0..54d3645 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -450,7 +450,7 @@ do_auto_update(void) { block_dev_desc_t *stor_dev; long sz; - int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc; + int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; char *env; long start, end; @@ -477,18 +477,21 @@ do_auto_update(void) au_usb_stor_curr_dev = usb_stor_scan(0); if (au_usb_stor_curr_dev == -1) { debug ("No device found. Not initialized?\n"); - return -1; + res = -1; + goto xit; } /* check whether it has a partition table */ stor_dev = get_dev("usb", 0); if (stor_dev == NULL) { debug ("uknown device type\n"); - return -1; + res = -1; + goto xit; } if (fat_register_device(stor_dev, 1) != 0) { debug ("Unable to use USB %d:%d for fatls\n", au_usb_stor_curr_dev, 1); - return -1; + res = -1; + goto xit; } if (file_fat_detectfs() != 0) { debug ("file_fat_detectfs failed\n"); @@ -648,9 +651,10 @@ do_auto_update(void) /* enable the power switch */ *CPLD_VFD_BK &= ~POWER_OFF; } - usb_stop(); /* restore the old state */ disable_ctrlc(old_ctrlc); - return 0; +xit: + usb_stop(); + return res; } #endif /* CONFIG_AUTO_UPDATE */ -- cgit v1.1 From 6f6d7b9c8559e241e8d232621542b8b59699b07b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 12 Aug 2007 18:28:18 +0200 Subject: Cleanup output on ADS5121 board Signed-off-by: Wolfgang Denk --- board/ads5121/ads5121.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'board') diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index c8bfdb8..f275ce7 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -85,9 +85,7 @@ long int initdram (int board_type) { u32 msize = 0; - puts ("Initializing\n"); msize = fixed_sdram (); - puts (" DDR RAM: "); return msize; } -- cgit v1.1 From cca34967cbd13ff6bd352be29e3f1cc88ab24c05 Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Sat, 11 Aug 2007 06:54:58 -0500 Subject: Modify SBC8641D to use new Freescale PCI routines PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT adapter. Signed-off-by: Joe Hamman Signde-off-by: Jon Loeliger --- board/sbc8641d/sbc8641d.c | 156 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 118 insertions(+), 38 deletions(-) (limited to 'board') diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index e5dd550..7adc42f 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #if defined(CONFIG_OF_FLAT_TREE) @@ -60,36 +61,6 @@ int checkboard (void) { puts ("Board: Wind River SBC8641D\n"); -#ifdef CONFIG_PCI - - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } else { - puts ("PCI-EXPRESS 1: Disabled in hardware\n"); - } - -#else - puts ("PCI-EXPRESS1: Disabled in configuration\n"); -#endif - return 0; } @@ -244,21 +215,130 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { }; #endif -static struct pci_controller hose = { +static struct pci_controller pci1_hose = { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table #endif }; +#endif /* CONFIG_PCI */ -#endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ -void pci_init_board (void) +int first_free_busno = 0; + +void pci_init_board(void) { -#ifdef CONFIG_PCI - extern void pci_mpc86xx_init (struct pci_controller *hose); + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; +#ifdef DEBUG + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); +#endif + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + debug("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } +} +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif /* CONFIG_PCI1 */ + +#ifdef CONFIG_PCI2 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci2_hose; + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); +} +#else + puts("PCI-EXPRESS 2: Disabled\n"); +#endif /* CONFIG_PCI2 */ - pci_mpc86xx_init (&hose); -#endif /* CONFIG_PCI */ } #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -- cgit v1.1 From be5d72d10d47609326226225181e301fb9a33b58 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 13 Aug 2007 21:57:53 +0200 Subject: Minor coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- board/cm5200/cm5200.c | 6 +++--- board/cm5200/cm5200.h | 2 +- board/cm5200/cmd_cm5200.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 6804e33..b74ac08 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -122,7 +122,7 @@ long int initdram(int board_type) mem_conf_t *mem_conf; mem_conf = get_mem_config(board_type); - + /* configure SDRAM start/end for detection */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ @@ -303,7 +303,7 @@ int checkboard(void) hw_id_t hw_id_tmp; char module_name_tmp[MODULE_NAME_MAXLEN] = ""; - /* + /* * We need I2C to access HW ID data from EEPROM, so we call i2c_init() * here despite the fact that it will be called again later on. We * also use a little trick to silence I2C-related output. @@ -321,7 +321,7 @@ int checkboard(void) else printf("Board: unrecognized cm5200 module (%s)\n", module_name_tmp); - + return 0; } diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h index a6cbc88..b2ea5ce 100644 --- a/board/cm5200/cm5200.h +++ b/board/cm5200/cm5200.h @@ -138,7 +138,7 @@ static char **hw_id_list[] = { cmu1_qa_hw_id, }; -/* indices to the above list - keep in sync */ +/* indices to the above list - keep in sync */ enum { CM1_QA, CM11_QA, diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index fd9b914..513c365 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2007 Markus Kappeler * - * Adapted for U-Boot 1.2 by Piotr Kruszynski + * Adapted for U-Boot 1.2 by Piotr Kruszynski * * See file CREDITS for list of people who contributed to this * project. -- cgit v1.1 From 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:51 -0500 Subject: 8544ds PCIE support PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/freescale/mpc8544ds/init.S | 6 +- board/freescale/mpc8544ds/mpc8544ds.c | 350 ++++++++++++++++++++++++++++++++++ 2 files changed, 353 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 296fee5..ea7d54d 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -52,8 +52,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -214,7 +214,7 @@ law_entry: .long 0 .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4ff1da9..8ddbb01 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -22,8 +22,10 @@ #include #include +#include #include #include +#include #include #include @@ -51,12 +53,19 @@ int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %x\n",&gur->porpllsr); } printf ("Board: MPC8544DS\n"); + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + return 0; } @@ -118,6 +127,316 @@ testdram(void) } #endif +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno=0; + +void +pci_init_board(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (io_sel & 1) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + printf (" eTSEC1 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf (" eTSEC3 is in sgmii mode.\n"); + } + +#ifdef CONFIG_PCIE3 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie3_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE3 connected to ULI as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE3_MEM_BASE, + CFG_PCIE3_MEM_PHYS, + CFG_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE3_IO_BASE, + CFG_PCIE3_IO_PHYS, + CFG_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE3_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE3_MEM_BASE2, + CFG_PCIE3_MEM_PHYS2, + CFG_PCIE3_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCIE3 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE3: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 5); + int pcie_configured = io_sel & 6; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE1_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE1_MEM_BASE2, + CFG_PCIE1_MEM_PHYS2, + CFG_PCIE1_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE1: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = io_sel & 4; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE2_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE2_MEM_BASE2, + CFG_PCIE2_MEM_PHYS2, + CFG_PCIE2_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf (" PCIE2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE2: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + uint pci_agent = (host_agent == 6); + uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ + uint pci_32 = 1; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter", + (uint)pci + ); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 3; +#ifdef CFG_PCIE3_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE3_MEM_BASE2, + CFG_PCIE3_MEM_PHYS2, + CFG_PCIE3_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif +} + + int last_stage_init(void) { return 0; @@ -197,5 +516,36 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE3 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; + debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } } #endif -- cgit v1.1 From f2cff6b104f82b993bef6086ce0c97159bbe1add Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:52 -0500 Subject: 8548cds PCIE support. Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/cds/mpc8548cds/config.mk | 4 +- board/cds/mpc8548cds/init.S | 162 +++++++++++++------------- board/cds/mpc8548cds/mpc8548cds.c | 237 +++++++++++++++++++++++++++++++++----- board/cds/mpc8548cds/u-boot.lds | 3 +- 4 files changed, 291 insertions(+), 115 deletions(-) (limited to 'board') diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk index 242a676..b23bc87 100644 --- a/board/cds/mpc8548cds/config.mk +++ b/board/cds/mpc8548cds/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2004 Freescale Semiconductor. +# Copyright 2004, 2007 Freescale Semiconductor. # # See file CREDITS for list of people who contributed to this # project. @@ -23,7 +23,9 @@ # # mpc8548cds board # +ifndef TEXT_BASE TEXT_BASE = 0xfff80000 +endif PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index d468f5b..72940b0 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Copyright 2002,2003, Motorola Inc. * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,12 @@ #include #include +#define LAWAR_TRGT_PCI1 0x00000000 +#define LAWAR_TRGT_PCI2 0x00100000 +#define LAWAR_TRGT_PCIE 0x00200000 +#define LAWAR_TRGT_RIO 0x00c00000 +#define LAWAR_TRGT_LBC 0x00400000 +#define LAWAR_TRGT_DDR 0x00f00000 /* * TLB0 and TLB1 Entries @@ -47,8 +53,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -84,8 +90,8 @@ tlb1_entry: #endif /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization + * TLB0 16K Cacheable, guarded + * Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory @@ -97,28 +103,28 @@ tlb1_entry: .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,1,0,1,0,1) @@ -130,51 +136,44 @@ tlb1_entry: */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b */ .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1) +#ifdef CFG_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI2 MEM */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), - 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 3: 1GB Non-cacheable, guarded - * 0xa0000000 256M PEX MEM First half - * 0xb0000000 256M PEX MEM Second half - * 0xc0000000 256M Rapid IO MEM First half - * 0xd0000000 256M Rapid IO MEM Second half + * TLB 3: 256M Non-cacheable, guarded */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: Reserved for future usage - */ - + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) +#endif /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCI2 IO - * 0xe300_0000 16M PEX IO + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) @@ -187,17 +186,18 @@ tlb1_entry: */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers + * TLB 7: 64M Non-cacheable, guarded + * 0xf8000000 64M CADMUS registers, relocated L2SRAM */ .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1) + 2: entry_end @@ -205,14 +205,13 @@ tlb1_entry: * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M - * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M - * 0xa000_0000 0xbfff_ffff PEX MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe27f_ffff PCI1 IO 8M - * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M - * 0xe300_0000 0xe3ff_ffff PEX IO 16M + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M + * 0xe300_0000 0xe30f_ffff PCIe IO 1M * 0xf000_0000 0xf3ff_ffff SDRAM 64M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -222,47 +221,50 @@ tlb1_entry: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. + * LAW 0 is reserved for boot mapping */ -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + .long (4f-3f)/8 +3: + .long 0 + .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) +#ifdef CFG_PCI1_MEM_PHYS + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M)) + .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#ifdef CFG_PCI2_MEM_PHYS + .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) -#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif -#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#ifdef CFG_PCIE1_MEM_PHYS + .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) -#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif - .section .bootpg, "ax" - .globl law_entry + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) -law_entry: - entry_start - .long (4f-3f)/8 -3: - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7 - .long LAWBAR8,LAWAR8 +#ifdef CFG_RIO_MEM_PHYS + .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) +#endif 4: entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index b723641..242a68c 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt * @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -33,10 +34,15 @@ #include "../common/eeprom.h" #include "../common/via.h" +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif +DECLARE_GLOBAL_DATA_PTR; + extern long int spd_sdram(void); void local_bus_init(void); @@ -56,13 +62,6 @@ int checkboard (void) /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", @@ -71,20 +70,6 @@ int checkboard (void) printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - /* * Initialize local bus. */ @@ -102,6 +87,8 @@ int checkboard (void) */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; } @@ -176,6 +163,9 @@ local_bus_init(void) lbc->lcrr |= 0x00030000; asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ } /* @@ -301,7 +291,7 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -320,21 +310,175 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { {}, }; -static struct pci_controller hose[] = { - { config_table: pci_mpc85xxcds_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - +static struct pci_controller pci1_hose = { + config_table: pci_mpc85xxcds_config_table}; #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno=0; + void pci_init_board(void) { -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + struct pci_config_table *table; + + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + + /* outbound memory */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 2; + + /* relocate config table pointers */ + hose->config_table = \ + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); + for (table = hose->config_table; table && table->vendor; table++) + table->config_device += gd->reloc_off; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); + } #endif + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif + +#ifdef CONFIG_PCI2 +{ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + } int last_stage_init(void) @@ -367,3 +511,32 @@ int last_stage_init(void) return 0; } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +} +#endif diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds index c1f3495..530ba5a 100644 --- a/board/cds/mpc8548cds/u-boot.lds +++ b/board/cds/mpc8548cds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -71,7 +71,6 @@ SECTIONS cpu/mpc85xx/cpu.o (.text) drivers/tsec.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) -- cgit v1.1 From 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:38:06 -0500 Subject: Fix minor 85xx warnings Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming --- board/mpc8560ads/mpc8560ads.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 41acb97..eef524b 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -554,7 +554,6 @@ ft_soc_setup(void *blob, bd_t *bd) { u32 *p; int len; - ulong data; p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); -- cgit v1.1 From c59e4091ffe0148398b9e9ff14a019ea038b7432 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 19 Jun 2007 14:18:34 -0400 Subject: Add PCI support for MPC8568MDS board This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang Signed-off-by: Ebony Zhu --- board/mpc8568mds/init.S | 48 +++++++++++++--------------------- board/mpc8568mds/mpc8568mds.c | 60 ++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 74 insertions(+), 34 deletions(-) (limited to 'board') diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S index 0d87982..972a7d4 100644 --- a/board/mpc8568mds/init.S +++ b/board/mpc8568mds/init.S @@ -143,54 +143,42 @@ tlb1_entry: .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM + * TLBe 2: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCIe Mem - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLBe 4: Reserved for future usage - */ - - /* - * TLBe 5: 64M Non-cacheable, guarded + * TLBe 3: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS0(1, 3, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 6: 64M Cacheable, non-guarded + * TLBe 4: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS0(1, 4, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 7: 256K Non-cacheable, guarded + * TLBe 5: 256K Non-cacheable, guarded * 0xf8000000 32K BCSR * 0xf8008000 32K PIB (CS4) * 0xf8010000 32K PIB (CS5) */ - .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1) @@ -202,12 +190,12 @@ tlb1_entry: * LAW(Local Access Window) configuration: * *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB - *5) 0xc000_0000 0xdfff_ffff SRIO 256MB + *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB + *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB *-) 0xe000_0000 0xe00f_ffff CCSR 1M *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M + *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M + *5) 0xc000_0000 0xdfff_ffff SRIO 512MB *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB @@ -226,20 +214,20 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 9c7960d..23caaec 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "bcsr.h" @@ -50,6 +51,15 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#ifdef CFG_I2C2_OFFSET + /* Enable I2C2_SCL and I2C2_SDA */ + volatile struct par_io *port_c; + port_c = (struct par_io*)(CFG_IMMR + 0xe0140); + port_c->cpdir2 |= 0x0f000000; + port_c->cppar2 &= ~0x0f000000; + port_c->cppar2 |= 0x0a000000; +#endif + return 0; } @@ -269,20 +279,62 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = { #endif static struct pci_controller hose[] = { + { #ifndef CONFIG_PCI_PNP - { config_table: pci_mpc8568mds_config_table,}, -#endif -#ifdef CONFIG_MPC85XX_PCI2 - {}, + config_table: pci_mpc8568mds_config_table, #endif + } }; #endif /* CONFIG_PCI */ +/* + * pib_init() -- Initialize the PCA9555 IO expander on the PIB board + */ +void +pib_init(void) +{ + u8 val8, orig_i2c_bus; + /* + * Assign PIB PMC2/3 to PCI bus + */ + + /*switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0x00; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0x00; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); + val8 = 0xf9; + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0x00; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + asm("eieio"); +} + void pci_init_board(void) { #ifdef CONFIG_PCI + pib_init(); pci_mpc85xx_init(&hose); #endif } -- cgit v1.1 From da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 00:14:25 -0500 Subject: Add support for UEC to 8568 Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- board/mpc8568mds/bcsr.c | 7 +++++ board/mpc8568mds/bcsr.h | 1 + board/mpc8568mds/mpc8568mds.c | 61 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 68 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index 2e2e8cd..aae0f98 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -47,3 +47,10 @@ void disable_8568mds_flash_write() bcsr[9] &= ~(0x01); } + +void enable_8568mds_qe_mdio() +{ + u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[7] |= 0x01; +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index 8d4cb2f..aefd9bf 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -95,5 +95,6 @@ void enable_8568mds_duart(void); void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); +void enable_8568mds_qe_mdio(void); #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 23caaec..818ff13 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -28,9 +28,65 @@ #include #include #include +#include #include "bcsr.h" +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {4, 10, 1, 0, 2}, /* TxD0 */ + {4, 9, 1, 0, 2}, /* TxD1 */ + {4, 8, 1, 0, 2}, /* TxD2 */ + {4, 7, 1, 0, 2}, /* TxD3 */ + {4, 23, 1, 0, 2}, /* TxD4 */ + {4, 22, 1, 0, 2}, /* TxD5 */ + {4, 21, 1, 0, 2}, /* TxD6 */ + {4, 20, 1, 0, 2}, /* TxD7 */ + {4, 15, 2, 0, 2}, /* RxD0 */ + {4, 14, 2, 0, 2}, /* RxD1 */ + {4, 13, 2, 0, 2}, /* RxD2 */ + {4, 12, 2, 0, 2}, /* RxD3 */ + {4, 29, 2, 0, 2}, /* RxD4 */ + {4, 28, 2, 0, 2}, /* RxD5 */ + {4, 27, 2, 0, 2}, /* RxD6 */ + {4, 26, 2, 0, 2}, /* RxD7 */ + {4, 11, 1, 0, 2}, /* TX_EN */ + {4, 24, 1, 0, 2}, /* TX_ER */ + {4, 16, 2, 0, 2}, /* RX_DV */ + {4, 30, 2, 0, 2}, /* RX_ER */ + {4, 17, 2, 0, 2}, /* RX_CLK */ + {4, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + + /* GETH2 */ + {5, 10, 1, 0, 2}, /* TxD0 */ + {5, 9, 1, 0, 2}, /* TxD1 */ + {5, 8, 1, 0, 2}, /* TxD2 */ + {5, 7, 1, 0, 2}, /* TxD3 */ + {5, 23, 1, 0, 2}, /* TxD4 */ + {5, 22, 1, 0, 2}, /* TxD5 */ + {5, 21, 1, 0, 2}, /* TxD6 */ + {5, 20, 1, 0, 2}, /* TxD7 */ + {5, 15, 2, 0, 2}, /* RxD0 */ + {5, 14, 2, 0, 2}, /* RxD1 */ + {5, 13, 2, 0, 2}, /* RxD2 */ + {5, 12, 2, 0, 2}, /* RxD3 */ + {5, 29, 2, 0, 2}, /* RxD4 */ + {5, 28, 2, 0, 2}, /* RxD5 */ + {5, 27, 2, 0, 3}, /* RxD6 */ + {5, 26, 2, 0, 2}, /* RxD7 */ + {5, 11, 1, 0, 2}, /* TX_EN */ + {5, 24, 1, 0, 2}, /* TX_ER */ + {5, 16, 2, 0, 2}, /* RX_DV */ + {5, 30, 2, 0, 2}, /* RX_ER */ + {5, 17, 2, 0, 2}, /* RX_CLK */ + {5, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 6, 3, 0, 2}, /* MDIO */ + {4, 5, 1, 0, 2}, /* MDC */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -50,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) + enable_8568mds_qe_mdio(); +#endif #ifdef CFG_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ @@ -335,6 +394,6 @@ pci_init_board(void) { #ifdef CONFIG_PCI pib_init(); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } -- cgit v1.1 From e41094c7e38177c755fbd9b182018069614f080d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:50:09 -0500 Subject: 85xxCDS: Enable the VIA PCI-to-ISA bridge. Author: Randy Vinson Enable the PCI-to-ISA bridge in the VIA Southbridge located on the Arcadia main board. Signed-off-by: Randy Vinson Signed-off-by: York Sun --- board/cds/common/via.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/cds/common/via.c b/board/cds/common/via.c index e79bd02..ded214f 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -28,11 +28,16 @@ void mpc85xx_config_via(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) { pci_dev_t bridge; + unsigned int cmdstat; /* Enable USB and IDE functions */ pci_hose_write_config_byte(hose, dev, 0x48, 0x08); - pciauto_config_device(hose, dev); + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); /* * Force the backplane P2P bridge to have a window -- cgit v1.1 From 7f3f2bd2dc08e0b05e185662ca2e2d283757104a Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Tue, 27 Feb 2007 19:42:22 -0700 Subject: 85xxCDS: Add make targets for legacy systems. The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson --- board/cds/common/via.c | 2 +- board/cds/mpc8541cds/mpc8541cds.c | 15 +++++++++------ board/cds/mpc8548cds/mpc8548cds.c | 15 +++++++++------ board/cds/mpc8555cds/mpc8555cds.c | 15 +++++++++------ 4 files changed, 28 insertions(+), 19 deletions(-) (limited to 'board') diff --git a/board/cds/common/via.c b/board/cds/common/via.c index ded214f..4a63d77 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -45,7 +45,7 @@ void mpc85xx_config_via(struct pci_controller *hose, * This allows legacy I/O (i8259, etc) on the VIA * southbridge to be accessed. */ - bridge = PCI_BDF(0,17,0); + bridge = PCI_BDF(0,BRIDGE_ID,0); pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 4192324..558ba99 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -476,14 +476,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 242a68c..48753d7 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -299,14 +299,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 704bf03..8f16421 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -473,14 +473,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; -- cgit v1.1 From d4fc6012fd0a5c211b825691f44b06f8032c0551 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:10:52 +0100 Subject: Add MACH_TYPE records for several AT91 boards. Merge to two at45.c files into a common file, split to at45.c and spi.c Fix spelling error in DM9161 PHY Support. Initialize at91rm9200 board (and set LED). Add PIO control for at91rm9200dk LEDs and Mux. Change dataflash partition boundaries to be compatible with Linux 2.6. Signed-off-by: Peter Pearse Signed-off-by: Ulf Samuelsson --- board/at91rm9200dk/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile index 0fcafd9..7dfc27f 100644 --- a/board/at91rm9200dk/Makefile +++ b/board/at91rm9200dk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := at91rm9200dk.o at45.o flash.o +COBJS := at91rm9200dk.o at45.o flash.o led.o mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -- cgit v1.1 From dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:14:05 +0100 Subject: Add the files. --- board/at91rm9200dk/led.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++ board/at91rm9200dk/mux.c | 39 +++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 board/at91rm9200dk/led.c create mode 100644 board/at91rm9200dk/mux.c (limited to 'board') diff --git a/board/at91rm9200dk/led.c b/board/at91rm9200dk/led.c new file mode 100644 index 0000000..0518918 --- /dev/null +++ b/board/at91rm9200dk/led.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define GREEN_LED AT91C_PIO_PB0 +#define YELLOW_LED AT91C_PIO_PB1 +#define RED_LED AT91C_PIO_PB2 + +void green_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = GREEN_LED; +} + +void yellow_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = YELLOW_LED; +} + +void red_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_CODR = RED_LED; +} + +void green_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = GREEN_LED; +} + +void yellow_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = YELLOW_LED; +} + +void red_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = RED_LED; +} + + +void LED_init (void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + AT91PS_PMC PMC = AT91C_BASE_PMC; + PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */ + /* Disable peripherals on LEDs */ + PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + /* Enable pins as outputs */ + PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + /* Turn all LEDs OFF */ + PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; +} diff --git a/board/at91rm9200dk/mux.c b/board/at91rm9200dk/mux.c new file mode 100644 index 0000000..d573923 --- /dev/null +++ b/board/at91rm9200dk/mux.c @@ -0,0 +1,39 @@ +#include +#include +#include +#include + +int AT91F_GetMuxStatus(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + + + if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) { + return 1; + } else { + return 0; + } +#endif + return 0; +} + +void AT91F_SelectMMC(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + /* Set Output */ + AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; +#endif +} + +void AT91F_SelectSPI(void) { +#ifdef DATAFLASH_MMC_SELECT + AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; +#endif +} + + -- cgit v1.1 From 3454cece2db57cb9eb7087995f7e73066a163f71 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:21:06 +0100 Subject: Delete the merged files. --- board/at91rm9200dk/at45.c | 621 ---------------------------------------------- board/cmc_pu2/at45.c | 621 ---------------------------------------------- 2 files changed, 1242 deletions(-) delete mode 100644 board/at91rm9200dk/at45.c delete mode 100644 board/cmc_pu2/at45.c (limited to 'board') diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c deleted file mode 100644 index f886fe4..0000000 --- a/board/at91rm9200dk/at45.c +++ /dev/null @@ -1,621 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_HAS_DATAFLASH -#include - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -void AT91F_SpiInit(void) { - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - -} - -void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } else { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - - return status; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashWaitReady */ -/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return DATAFLASH_ERROR; - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashPagePgmBuf */ -/* Object : Main memory page program through buffer 1 or buffer 2 */ -/* Input Parameters : DataFlash Service */ -/* : <*src> = Source buffer */ -/* : = dataflash destination address */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) -{ - int cmdsize; - pDataFlash->pDataFlashDesc->tx_data_pt = src ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->rx_data_pt = src; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - - cmdsize = 4; - /* Send the command to the dataflash */ - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfert */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return DATAFLASH_BAD_ADDRESS; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } else { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Erase a page */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_BlockErase */ -/* Object : Erase a Block */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buffer1 or buffer2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partielly a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) { - AT91F_PageErase(pDataFlash, page); - /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - if (!status) - return DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -} - -#endif diff --git a/board/cmc_pu2/at45.c b/board/cmc_pu2/at45.c deleted file mode 100644 index 3c00132..0000000 --- a/board/cmc_pu2/at45.c +++ /dev/null @@ -1,621 +0,0 @@ -/* Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include - -#ifdef CONFIG_HAS_DATAFLASH -#include - -#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to -the Continuous Array Read function */ - -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ - -void AT91F_SpiInit(void) { - -/*-------------------------------------------------------------------*/ -/* SPI DataFlash Init */ -/*-------------------------------------------------------------------*/ - /* Configure PIOs */ - AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | - AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; - /* Enable CLock */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; - - /* Reset the SPI */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & - DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - -} - -void AT91F_SpiEnable(int cs) { - switch(cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); - break; - case 3: /* Configure SPI CS3 for Serial DataFlash Card */ - /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ - AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; - /* Configure PCS */ - AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; -} - -/*----------------------------------------------------------------------------*/ -/* \fn AT91F_SpiWrite */ -/* \brief Set the PDC registers for a transfert */ -/*----------------------------------------------------------------------------*/ -unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; - AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; - - if ( pDesc->tx_data_size != 0 ) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; - AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; - AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT){ - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashSendCommand */ -/* \brief Generic function to send a command to the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashSendCommand( - AT91PS_DataFlash pDataFlash, - unsigned char OpCode, - unsigned int CmdSize, - unsigned int DataflashAddress) -{ - unsigned int adr; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* process the address to obtain page address and byte address */ - adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); - - /* fill the command buffer */ - pDataFlash->pDataFlashDesc->command[0] = OpCode; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); - } else { - pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - } - pDataFlash->pDataFlashDesc->command[5] = 0; - pDataFlash->pDataFlashDesc->command[6] = 0; - pDataFlash->pDataFlashDesc->command[7] = 0; - - /* Initialize the SpiData structure for the spi write fuction */ - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; - - /* send the command and read the data */ - return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashGetStatus */ -/* \brief Read the status register of the dataflash */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) -{ - AT91S_DataFlashStatus status; - - /* if a transfert is in progress ==> return 0 */ - if( (pDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* first send the read status command (D7H) */ - pDesc->command[0] = DB_STATUS; - pDesc->command[1] = 0; - - pDesc->DataFlash_state = GET_STATUS; - pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ - pDesc->tx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_pt = pDesc->command ; - pDesc->rx_cmd_size = 2 ; - pDesc->tx_cmd_size = 2 ; - status = AT91F_SpiWrite (pDesc); - - pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); - - return status; -} - - -/*----------------------------------------------------------------------*/ -/* \fn AT91F_DataFlashWaitReady */ -/* \brief wait for dataflash ready (bit7 of the status register == 1) */ -/*----------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) -{ - pDataFlashDesc->DataFlash_state = IDLE; - - do { - AT91F_DataFlashGetStatus(pDataFlashDesc); - timeout--; - } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); - - if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) - return DATAFLASH_ERROR; - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashContinuousRead */ -/* Object : Continuous stream Read */ -/* Input Parameters : DataFlash Service */ -/* : = dataflash address */ -/* : <*dataBuffer> = data buffer pointer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( - AT91PS_DataFlash pDataFlash, - int src, - unsigned char *dataBuffer, - int sizeToRead ) -{ - AT91S_DataFlashStatus status; - /* Test the size to read in the device */ - if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; - pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; - - status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); - /* Send the command to the dataflash */ - return(status); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashPagePgmBuf */ -/* Object : Main memory page program through buffer 1 or buffer 2 */ -/* Input Parameters : DataFlash Service */ -/* : <*src> = Source buffer */ -/* : = dataflash destination address */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int SizeToWrite) -{ - int cmdsize; - pDataFlash->pDataFlashDesc->tx_data_pt = src ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->rx_data_pt = src; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; - - cmdsize = 4; - /* Send the command to the dataflash */ - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_MainMemoryToBufferTransfert */ -/* Object : Read a page in the SRAM Buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*----------------------------------------------------------------------------- */ -/* Function Name : AT91F_DataFlashWriteBuffer */ -/* Object : Write data to the internal sram buffer 1 or 2 */ -/* Input Parameters : DataFlash Service */ -/* : = command to write buffer1 or buffer2 */ -/* : <*dataBuffer> = data buffer to write */ -/* : = address in the internal buffer */ -/* : = data buffer size */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned char *dataBuffer, - unsigned int bufferAddress, - int SizeToWrite ) -{ - int cmdsize; - /* Test if the buffer command is legal */ - if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) - return DATAFLASH_BAD_COMMAND; - - /* buffer address must be lower than page size */ - if (bufferAddress > pDataFlash->pDevice->pages_size) - return DATAFLASH_BAD_ADDRESS; - - if ( (pDataFlash->pDataFlashDesc->state) != IDLE) - return DATAFLASH_BUSY; - - /* Send first Write Command */ - pDataFlash->pDataFlashDesc->command[0] = BufferCommand; - pDataFlash->pDataFlashDesc->command[1] = 0; - if (pDataFlash->pDevice->pages_number >= 16384) { - pDataFlash->pDataFlashDesc->command[2] = 0; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - cmdsize = 5; - } else { - pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; - pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; - pDataFlash->pDataFlashDesc->command[4] = 0; - cmdsize = 4; - } - - pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; - pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; - pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; - - pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; - pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; - pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; - - return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PageErase */ -/* Object : Erase a page */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PageErase( - AT91PS_DataFlash pDataFlash, - unsigned int page) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_BlockErase */ -/* Object : Erase a Block */ -/* Input Parameters : DataFlash Service */ -/* : Page concerned */ -/* : */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_BlockErase( - AT91PS_DataFlash pDataFlash, - unsigned int block) -{ - int cmdsize; - /* Test if the buffer command is legal */ - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); -} - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_WriteBufferToMain */ -/* Object : Write buffer to the main memory */ -/* Input Parameters : DataFlash Service */ -/* : = command to send to buffer1 or buffer2 */ -/* : = main memory address */ -/* Return value : State of the dataflash */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_WriteBufferToMain ( - AT91PS_DataFlash pDataFlash, - unsigned char BufferCommand, - unsigned int dest ) -{ - int cmdsize; - /* Test if the buffer command is correct */ - if ((BufferCommand != DB_BUF1_PAGE_PGM) && - (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && - (BufferCommand != DB_BUF2_PAGE_PGM) && - (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) - return DATAFLASH_BAD_COMMAND; - - /* no data to transmit or receive */ - pDataFlash->pDataFlashDesc->tx_data_size = 0; - - cmdsize = 4; - if (pDataFlash->pDevice->pages_number >= 16384) - cmdsize = 5; - /* Send the command to the dataflash */ - return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_PartialPageWrite */ -/* Object : Erase partielly a page */ -/* Input Parameters : = page number */ -/* : = adr to begin the fading */ -/* : = Number of bytes to erase */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_PartialPageWrite ( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - unsigned int dest, - unsigned int size) -{ - unsigned int page; - unsigned int AdrInPage; - - page = dest / (pDataFlash->pDevice->pages_size); - AdrInPage = dest % (pDataFlash->pDevice->pages_size); - - /* Read the contents of the page in the Sram Buffer */ - AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - /*Update the SRAM buffer */ - AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Erase page if a 128 Mbits device */ - if (pDataFlash->pDevice->pages_number >= 16384) { - AT91F_PageErase(pDataFlash, page); - /* Rewrite the modified Sram Buffer in the main memory */ - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - - /* Rewrite the modified Sram Buffer in the main memory */ - return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashWrite */ -/* Object : */ -/* Input Parameters : <*src> = Source buffer */ -/* : = dataflash adress */ -/* : = data buffer size */ -/*------------------------------------------------------------------------------*/ -AT91S_DataFlashStatus AT91F_DataFlashWrite( - AT91PS_DataFlash pDataFlash, - unsigned char *src, - int dest, - int size ) -{ - unsigned int length; - unsigned int page; - unsigned int status; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) - return DATAFLASH_MEMORY_OVERFLOW; - - /* If destination does not fit a page start address */ - if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { - length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); - - if (size < length) - length = size; - - if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= length; - dest += length; - src += length; - } - - while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { - /* program dataflash page */ - page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); - - status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - status = AT91F_PageErase(pDataFlash, page); - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - if (!status) - return DATAFLASH_ERROR; - - status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); - if(!status) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - - /* Update size, source and destination pointers */ - size -= pDataFlash->pDevice->pages_size ; - dest += pDataFlash->pDevice->pages_size ; - src += pDataFlash->pDevice->pages_size ; - } - - /* If still some bytes to read */ - if ( size > 0 ) { - /* program dataflash page */ - if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) - return DATAFLASH_ERROR; - - AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); - } - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataFlashRead */ -/* Object : Read a block in dataflash */ -/* Input Parameters : */ -/* Return value : */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataFlashRead( - AT91PS_DataFlash pDataFlash, - unsigned long addr, - unsigned long size, - char *buffer) -{ - unsigned long SizeToRead; - - AT91F_SpiEnable(pDataFlash->pDevice->cs); - - if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - while (size) { - SizeToRead = (size < 0x8000)? size:0x8000; - - if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) - return -1; - - if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) - return -1; - - size -= SizeToRead; - addr += SizeToRead; - buffer += SizeToRead; - } - - return DATAFLASH_OK; -} - - -/*------------------------------------------------------------------------------*/ -/* Function Name : AT91F_DataflashProbe */ -/* Object : */ -/* Input Parameters : */ -/* Return value : Dataflash status register */ -/*------------------------------------------------------------------------------*/ -int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) -{ - AT91F_SpiEnable(cs); - AT91F_DataFlashGetStatus(pDesc); - return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); -} - -#endif -- cgit v1.1 From 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Tue, 14 Aug 2007 10:30:06 +0100 Subject: Update Makefiles for merged and split at45.c. --- board/at91rm9200dk/Makefile | 2 +- board/cmc_pu2/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) mode change 100644 => 100755 board/at91rm9200dk/Makefile mode change 100644 => 100755 board/cmc_pu2/Makefile (limited to 'board') diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile old mode 100644 new mode 100755 index 7dfc27f..01f3bc3 --- a/board/at91rm9200dk/Makefile +++ b/board/at91rm9200dk/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := at91rm9200dk.o at45.o flash.o led.o mux.o +COBJS := at91rm9200dk.o flash.o led.o mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile old mode 100644 new mode 100755 index d445f28..f7a1360 --- a/board/cmc_pu2/Makefile +++ b/board/cmc_pu2/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o +COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -- cgit v1.1 From 779e975117a75e91fcebe226a63104dbfb924ab1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 14:44:41 +0200 Subject: ppc4xx: Add initial Zeus (PPC405EP) board support Signed-off-by: Stefan Roese --- board/amcc/bubinga/bubinga.c | 13 +- board/amcc/taihu/taihu.c | 6 + board/zeus/Makefile | 51 +++++ board/zeus/config.mk | 24 ++ board/zeus/u-boot.lds | 133 +++++++++++ board/zeus/update.c | 105 +++++++++ board/zeus/zeus.c | 511 +++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 842 insertions(+), 1 deletion(-) create mode 100644 board/zeus/Makefile create mode 100644 board/zeus/config.mk create mode 100644 board/zeus/u-boot.lds create mode 100644 board/zeus/update.c create mode 100644 board/zeus/zeus.c (limited to 'board') diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index fe6ce8a..66e7509 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -20,10 +20,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -long int spd_sdram(void); #include #include +#include + +long int spd_sdram(void); int board_early_init_f(void) { @@ -34,6 +36,15 @@ int board_early_init_f(void) mtdcr(uictr, 0x00000010); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + /* + * Configure CPC0_PCI to enable PerWE as output + * and enable the internal PCI arbiter if selected + */ + if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + else + mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN); + return 0; } diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index ee9d3b5..ea83671 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -50,6 +50,12 @@ int board_early_init_f(void) mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ mtebc(pb3cr, CFG_EBC_PB3CR); + /* + * Configure CPC0_PCI to enable PerWE as output + * and enable the internal PCI arbiter + */ + mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + return 0; } diff --git a/board/zeus/Makefile b/board/zeus/Makefile new file mode 100644 index 0000000..f0d4e9f --- /dev/null +++ b/board/zeus/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o update.o +SOBJS = + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/zeus/config.mk b/board/zeus/config.mk new file mode 100644 index 0000000..1bdf5e4 --- /dev/null +++ b/board/zeus/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/zeus/u-boot.lds b/board/zeus/u-boot.lds new file mode 100644 index 0000000..73b83eb --- /dev/null +++ b/board/zeus/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/zeus/update.c b/board/zeus/update.c new file mode 100644 index 0000000..c76519f --- /dev/null +++ b/board/zeus/update.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_ZEUS) + +u8 buf_zeus_ce[] = { +/*00 01 02 03 04 05 06 07 */ + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*08 09 0a 0b 0c 0d 0e 0f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*10 11 12 13 14 15 16 17 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*18 19 1a 1b 1c 1d 1e 1f */ + 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 }; + +u8 buf_zeus_pe[] = { + +/* CPU_CLOCK_DIV 1 = 00 + CPU_PLB_FREQ_DIV 3 = 10 + OPB_PLB_FREQ_DIV 2 = 01 + EBC_PLB_FREQ_DIV 2 = 00 + MAL_PLB_FREQ_DIV 1 = 00 + PCI_PLB_FRQ_DIV 3 = 10 + PLL_PLLOUTA = IS SET + PLL_OPERATING = IS NOT SET + PLL_FDB_MUL 10 = 1010 + PLL_FWD_DIV_A 3 = 101 + PLL_FWD_DIV_B 3 = 101 + TUNE = 0x2be */ +/*00 01 02 03 04 05 06 07 */ + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*08 09 0a 0b 0c 0d 0e 0f */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*10 11 12 13 14 15 16 17 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/*18 19 1a 1b 1c 1d 1e 1f */ + 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 }; + +static int update_boot_eeprom(void) +{ + u32 len = 0x20; + u8 chip = CFG_I2C_EEPROM_ADDR; + u8 *pbuf; + u8 base; + int i; + + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) { + pbuf = buf_zeus_pe; + base = 0x40; + } else { + pbuf = buf_zeus_ce; + base = 0x00; + } + + for (i = 0; i < len; i++, base++) { + if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) { + printf("i2c_write fail\n"); + return 1; + } + udelay(11000); + } + + return 0; +} + +int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) +{ + return update_boot_eeprom(); +} + +U_BOOT_CMD ( + update_boot_eeprom, 1, 1, do_update_boot_eeprom, + "update_boot_eeprom - update boot eeprom content\n", + NULL +); + +#endif diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c new file mode 100644 index 0000000..4ab853f --- /dev/null +++ b/board/zeus/zeus.c @@ -0,0 +1,511 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define REBOOT_MAGIC 0x07081967 +#define REBOOT_NOP 0x00000000 +#define REBOOT_DO_POST 0x00000001 + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern env_t *env_ptr; +extern uchar default_environment[]; + +ulong flash_get_size(ulong base, int banknum); +void env_crc_update(void); +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +static u32 start_time; + +int board_early_init_f(void) +{ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); + mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ + mtdcr(uictr, 0x00000000); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + + /* + * Configure CPC0_PCI to enable PerWE as output + */ + mtdcr(cpc0_pci, CPC0_PCI_SPE); + + return 0; +} + +int misc_init_r(void) +{ + u32 pbcr; + int size_val = 0; + u32 post_magic; + u32 post_val; + + post_magic = in_be32((void *)CFG_POST_MAGIC); + post_val = in_be32((void *)CFG_POST_VAL); + if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) { + /* + * Set special bootline bootparameter to pass this POST boot + * mode to Linux to reset the username/password + */ + setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes"); + + /* + * Normally don't run POST tests, only when enabled + * via the sw-reset button. So disable further tests + * upon next bootup here. + */ + out_be32((void *)CFG_POST_VAL, REBOOT_NOP); + } else { + /* + * Only run POST when initiated via the sw-reset button mechanism + */ + post_word_store(0); + } + + /* + * Get current time + */ + start_time = get_timer(0); + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + mfebc(pb0cr, pbcr); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Zeus-"); + + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) + puts("PE"); + else + puts("CE"); + + puts(" of BulletEndPoint"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + /* both LED's off */ + gpio_write_bit(CFG_GPIO_LED_RED, 0); + gpio_write_bit(CFG_GPIO_LED_GREEN, 0); + udelay(10000); + /* and on again */ + gpio_write_bit(CFG_GPIO_LED_RED, 1); + gpio_write_bit(CFG_GPIO_LED_GREEN, 1); + + return (0); +} + +static u32 detect_sdram_size(void) +{ + u32 val; + u32 size; + + mfsdram(mem_mb0cf, val); + size = (4 << 20) << ((val & 0x000e0000) >> 17); + + /* + * Check if 2nd bank is enabled too + */ + mfsdram(mem_mb1cf, val); + if (val & 1) + size += (4 << 20) << ((val & 0x000e0000) >> 17); + + return size; +} + +long int initdram (int board_type) +{ + return detect_sdram_size(); +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + unsigned long msr; + unsigned long total_kbytes; + + total_kbytes = detect_sdram_size(); + + msr = mfmsr(); + mtmsr(msr & ~(MSR_EE)); + + for (k = 0; k < total_kbytes ; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + mtmsr(msr); + + return 0; +} +#endif + +static int default_env_var(char *buf, char *var) +{ + char *ptr; + char *val; + + /* + * Find env variable + */ + ptr = strstr(buf + 4, var); + if (ptr == NULL) { + printf("ERROR: %s not found!\n", var); + return -1; + } + ptr += strlen(var) + 1; + + /* + * Now the ethaddr needs to be updated in the "normal" + * environment storage -> redundant flash. + */ + val = ptr; + setenv(var, val); + printf("Updated %s from eeprom to %s!\n", var, val); + + return 0; +} + +static int restore_default(void) +{ + char *buf; + char *buf_save; + u32 crc; + + /* + * Unprotect and erase environment area + */ + flash_protect(FLAG_PROTECT_CLEAR, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + flash_sect_erase(CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1); + + /* + * Now restore default environment from U-Boot image + * -> ipaddr, serverip... + */ + memset(env_ptr, 0, sizeof(env_t)); + memcpy(env_ptr->data, default_environment, ENV_SIZE); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update(); + gd->env_valid = 1; + + /* + * Read board specific values from I2C EEPROM + * and set env variables accordingly + * -> ethaddr, eth1addr, serial# + */ + buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); + if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, + (u8 *)buf, FACTORY_RESET_ENV_SIZE)) { + puts("\nError reading EEPROM!\n"); + } else { + crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4); + if (crc != *(u32 *)buf) { + printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf); + return -1; + } + + default_env_var(buf, "ethaddr"); + buf += 8 + 18; + default_env_var(buf, "eth1addr"); + buf += 9 + 18; + default_env_var(buf, "serial#"); + } + + /* + * Finally save updated env variables back to flash + */ + saveenv(); + + free(buf_save); + + return 0; +} + +int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *buf; + char *buf_save; + char str[32]; + u32 crc; + char var[32]; + + if (argc < 4) { + puts("ERROR!\n"); + return -1; + } + + buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); + memset(buf, 0, FACTORY_RESET_ENV_SIZE); + + strcpy(var, "ethaddr"); + printf("Setting %s to %s\n", var, argv[1]); + sprintf(str, "%s=%s", var, argv[1]); + strcpy(buf + 4, str); + buf += strlen(str) + 1; + + strcpy(var, "eth1addr"); + printf("Setting %s to %s\n", var, argv[2]); + sprintf(str, "%s=%s", var, argv[2]); + strcpy(buf + 4, str); + buf += strlen(str) + 1; + + strcpy(var, "serial#"); + printf("Setting %s to %s\n", var, argv[3]); + sprintf(str, "%s=%s", var, argv[3]); + strcpy(buf + 4, str); + + crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4); + *(u32 *)buf_save = crc; + + if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, + (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) { + puts("\nError writing EEPROM!\n"); + return -1; + } + + free(buf_save); + + return 0; +} + +U_BOOT_CMD( + setdef, 4, 1, do_set_default, + "setdef - write board-specific values to EEPROM (ethaddr...)\n", + "ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n" + ); + +static inline int sw_reset_pressed(void) +{ + return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET)); +} + +int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) +{ + int delta; + int count = 0; + int post = 0; + int factory_reset = 0; + + if (!sw_reset_pressed()) { + printf("SW-Reset already high (Button released)\n"); + printf("-> No action taken!\n"); + return 0; + } + + printf("Waiting for SW-Reset button to be released."); + + while (1) { + delta = get_timer(start_time); + if (!sw_reset_pressed()) + break; + + if ((delta > CFG_TIME_POST) && !post) { + printf("\nWhen released now, POST tests will be started."); + gpio_write_bit(CFG_GPIO_LED_GREEN, 0); + post = 1; + } + + if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) { + printf("\nWhen released now, factory default values" + " will be restored."); + gpio_write_bit(CFG_GPIO_LED_RED, 0); + factory_reset = 1; + } + + udelay(1000); + if (!(count++ % 1000)) + printf("."); + } + + + printf("\nSW-Reset Button released after %d milli-seconds!\n", delta); + + if (delta > CFG_TIME_FACTORY_RESET) { + printf("Starting factory reset value restoration...\n"); + + /* + * Restore default setting + */ + restore_default(); + + /* + * Reset the board for default to become valid + */ + do_reset(NULL, 0, 0, NULL); + + return 0; + } + + if (delta > CFG_TIME_POST) { + printf("Starting POST configuration...\n"); + + /* + * Enable POST upon next bootup + */ + out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC); + out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST); + post_bootmode_init(); + + /* + * Reset the logbuffer for a clean start + */ + logbuff_reset(); + + do_reset(NULL, 0, 0, NULL); + + return 0; + } + + return 0; +} + +U_BOOT_CMD ( + chkreset, 1, 1, do_chkreset, + "chkreset- Check for status of SW-reset button and act accordingly\n", + NULL +); + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + u32 post_magic; + u32 post_val; + + post_magic = in_be32((void *)CFG_POST_MAGIC); + post_val = in_be32((void *)CFG_POST_VAL); + + if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) + return 1; + else + return 0; +} +#endif /* CONFIG_POST */ -- cgit v1.1 From f01dbb5424a81453c81190dd30e945891466f621 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 14 Aug 2007 18:42:36 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- board/at91rm9200dk/mux.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/at91rm9200dk/mux.c b/board/at91rm9200dk/mux.c index d573923..767d280 100644 --- a/board/at91rm9200dk/mux.c +++ b/board/at91rm9200dk/mux.c @@ -23,8 +23,8 @@ void AT91F_SelectMMC(void) { AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ /* Set Output */ - AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; -#endif + AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT; +#endif } void AT91F_SelectSPI(void) { @@ -32,8 +32,6 @@ void AT91F_SelectSPI(void) { AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */ AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */ /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; -#endif + AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT; +#endif } - - -- cgit v1.1 From b361acd64fd2525c081b9b288b0804efe209c0e9 Mon Sep 17 00:00:00 2001 From: "ksi@koi8.net" Date: Tue, 14 Aug 2007 10:02:16 -0700 Subject: TI DaVinci - fix unsupported %hhx format Signed-off-by: Sergey Kubushyn --- board/davinci/dv-evm/dv_board.c | 2 +- board/davinci/schmoogie/dv_board.c | 2 +- board/davinci/sonata/dv_board.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c index 94925ec..604edb5 100644 --- a/board/davinci/dv-evm/dv_board.c +++ b/board/davinci/dv-evm/dv_board.c @@ -181,7 +181,7 @@ int misc_init_r (void) tmp[0] &= buf[i]; if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); setenv("ethaddr", (char *)&tmp[0]); } diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c index b15c5f7..9f271a1 100644 --- a/board/davinci/schmoogie/dv_board.c +++ b/board/davinci/schmoogie/dv_board.c @@ -228,7 +228,7 @@ int misc_init_r (void) forceenv("serial#", "FAILED"); } else { /* CRC OK, set "serial" env variable */ - sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", + sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x", buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]); forceenv("serial#", (char *)&tmp[0]); } diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c index 7b0a459..99857c4 100644 --- a/board/davinci/sonata/dv_board.c +++ b/board/davinci/sonata/dv_board.c @@ -182,7 +182,7 @@ int misc_init_r (void) tmp[0] &= buf[i]; if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { - sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); setenv("ethaddr", (char *)&tmp[0]); } -- cgit v1.1 From 0e19209767194a97cec6d93dba9e64d1da8d548e Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Wed, 15 Aug 2007 12:14:23 +0200 Subject: PPC4xx:HCU4/5-Board fix compile warning Signed-off-by: Niklaus Giger --- board/netstal/common/flash.c | 528 --------------------------------------- board/netstal/common/hcu_flash.c | 528 +++++++++++++++++++++++++++++++++++++++ board/netstal/hcu4/Makefile | 14 +- board/netstal/hcu5/Makefile | 14 +- 4 files changed, 546 insertions(+), 538 deletions(-) delete mode 100644 board/netstal/common/flash.c create mode 100644 board/netstal/common/hcu_flash.c (limited to 'board') diff --git a/board/netstal/common/flash.c b/board/netstal/common/flash.c deleted file mode 100644 index be2cb37..0000000 --- a/board/netstal/common/flash.c +++ /dev/null @@ -1,528 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - * - * Modified 6/6/2007 - * Added isync - * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com - * - */ - -#include -#include -#include - -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" -#endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*-----------------------------------------------------------------------*/ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - - /* Init: no FLASHes known */ - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, - &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + monitor_flash_len - 1, - &flash_info[0]); - flash_info[0].size = size_b0; - - return size_b0; -} - - -/*-----------------------------------------------------------------------*/ -/* - * This implementation assumes that the flash chips are uniform sector - * devices. This is true for all likely flash devices on a HCUx. - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - unsigned idx; - unsigned long sector_size = info->size / info->sector_count; - - for (idx = 0; idx < info->sector_count; idx += 1) { - info->start[idx] = base + (idx * sector_size); - } -} - -/*-----------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("ST Micro "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* (Reduced table of only parts expected in HCUx boards.) */ - switch (info->flash_id) { - case FLASH_MAN_AMD | FLASH_AM040: - printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_MAN_STM | FLASH_AM040: - printf ("MM29W040W (512 Kbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; -} - -/*-----------------------------------------------------------------------*/ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - asm("isync"); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - asm("isync"); - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - asm("isync"); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - asm("isync"); - - value = addr2[0]; - asm("isync"); - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - printf("Unknown flash manufacturer code: 0x%x at %p\n", - value, addr); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* Calculate the sector offsets (Use HCUx Optimized code). */ - flash_get_offsets(base, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, - *(A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors not erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == - FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - /* block erase */ - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; - for (i = 0; i < 50; i++) udelay (1000); - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - /* sector erase */ - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - -DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = - (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/netstal/common/hcu_flash.c b/board/netstal/common/hcu_flash.c new file mode 100644 index 0000000..be2cb37 --- /dev/null +++ b/board/netstal/common/hcu_flash.c @@ -0,0 +1,528 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + * + * Modified 6/6/2007 + * Added isync + * Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com + * + */ + +#include +#include +#include + +#if CFG_MAX_FLASH_BANKS != 1 +#error "CFG_MAX_FLASH_BANKS must be 1" +#endif +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static int write_word (flash_info_t * info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t * info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*-----------------------------------------------------------------------*/ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + + /* Init: no FLASHes known */ + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, + &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void) flash_protect (FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM + monitor_flash_len - 1, + &flash_info[0]); + flash_info[0].size = size_b0; + + return size_b0; +} + + +/*-----------------------------------------------------------------------*/ +/* + * This implementation assumes that the flash chips are uniform sector + * devices. This is true for all likely flash devices on a HCUx. + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + unsigned idx; + unsigned long sector_size = info->size / info->sector_count; + + for (idx = 0; idx < info->sector_count; idx += 1) { + info->start[idx] = base + (idx * sector_size); + } +} + +/*-----------------------------------------------------------------------*/ +void flash_print_info (flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + case FLASH_MAN_SST: + printf ("SST "); + break; + case FLASH_MAN_STM: + printf ("ST Micro "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + /* (Reduced table of only parts expected in HCUx boards.) */ + switch (info->flash_id) { + case FLASH_MAN_AMD | FLASH_AM040: + printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_MAN_STM | FLASH_AM040: + printf ("MM29W040W (512 Kbit, uniform sector size)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; +} + +/*-----------------------------------------------------------------------*/ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; + + /* Write auto select command: read Manufacturer ID */ + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + asm("isync"); + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + asm("isync"); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + asm("isync"); + + value = addr2[0]; + asm("isync"); + + switch (value) { + case (FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + printf("Unknown flash manufacturer code: 0x%x at %p\n", + value, addr); + addr2[ADDR0] = (FLASH_WORD_SIZE) 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* Calculate the sector offsets (Use HCUx Optimized code). */ + flash_get_offsets(base, info); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, + *(A7 .. A0) = 0x02 + * D0 = 1 if protected + */ + addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *) info->start[0]; + *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7 (flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = + (FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*-----------------------------------------------------------------------*/ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors not erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf ("Erasing sector %p\n", addr2); /* CLH */ + + if ((info->flash_id & FLASH_VENDMASK) == + FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* block erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00500050; + for (i = 0; i < 50; i++) udelay (1000); + } else { + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + /* sector erase */ + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7 (info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7 (info, l_sect); + +DONE: +#endif + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = + (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile index d9825a5..af90821 100644 --- a/board/netstal/hcu4/Makefile +++ b/board/netstal/hcu4/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile index eee310b..27398b9 100644 --- a/board/netstal/hcu5/Makefile +++ b/board/netstal/hcu5/Makefile @@ -22,16 +22,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -vpath flash.c ../common -COBJS = $(BOARD).o sdram.o flash.o +vpath hcu_flash.c ../common + +# NOBJS : Netstal common objects +NOBJS = hcu_flash.o +COBJS = $(BOARD).o sdram.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) +NOBJS := $(addprefix $(obj),$(NOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) $(NOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS) clean: rm -f $(SOBJS) $(OBJS) -- cgit v1.1 From 4ce917742b1e48faa9bf9a9757545e56fb4cfe44 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 15 Aug 2007 12:20:40 -0500 Subject: Move the MPC8641HPCN board under board/freescale. Minor path corrections needed to ensure buildability. Signed-off-by: Jon Loeliger --- board/freescale/common/sys_eeprom.c | 256 +++++++++++++++++++ board/freescale/mpc8641hpcn/Makefile | 59 +++++ board/freescale/mpc8641hpcn/config.mk | 31 +++ board/freescale/mpc8641hpcn/init.S | 179 +++++++++++++ board/freescale/mpc8641hpcn/mpc8641hpcn.c | 407 ++++++++++++++++++++++++++++++ board/freescale/mpc8641hpcn/u-boot.lds | 136 ++++++++++ board/mpc8641hpcn/Makefile | 58 ----- board/mpc8641hpcn/config.mk | 31 --- board/mpc8641hpcn/init.S | 179 ------------- board/mpc8641hpcn/mpc8641hpcn.c | 407 ------------------------------ board/mpc8641hpcn/sys_eeprom.c | 256 ------------------- board/mpc8641hpcn/u-boot.lds | 136 ---------- 12 files changed, 1068 insertions(+), 1067 deletions(-) create mode 100644 board/freescale/common/sys_eeprom.c create mode 100644 board/freescale/mpc8641hpcn/Makefile create mode 100644 board/freescale/mpc8641hpcn/config.mk create mode 100644 board/freescale/mpc8641hpcn/init.S create mode 100644 board/freescale/mpc8641hpcn/mpc8641hpcn.c create mode 100644 board/freescale/mpc8641hpcn/u-boot.lds delete mode 100644 board/mpc8641hpcn/Makefile delete mode 100644 board/mpc8641hpcn/config.mk delete mode 100644 board/mpc8641hpcn/init.S delete mode 100644 board/mpc8641hpcn/mpc8641hpcn.c delete mode 100644 board/mpc8641hpcn/sys_eeprom.c delete mode 100644 board/mpc8641hpcn/u-boot.lds (limited to 'board') diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c new file mode 100644 index 0000000..7bc663b --- /dev/null +++ b/board/freescale/common/sys_eeprom.c @@ -0,0 +1,256 @@ +/* + * Copyright 2006 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CFG_ID_EEPROM +typedef struct { + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5]; /* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37]; /* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6]; /* 0x0042 - 0x0071 */ + unsigned char res_2[126]; /* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ +} EEPROM_data; + +static EEPROM_data mac_data; + +int mac_show(void) +{ + int i; + unsigned char ethaddr[8][18]; + + printf("ID %c%c%c%c\n", + mac_data.id[0], + mac_data.id[1], + mac_data.id[2], + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", + mac_data.errata[0], + mac_data.errata[1], + mac_data.errata[2], + mac_data.errata[3], + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", + mac_data.date[0], + mac_data.date[1], + mac_data.date[2], + mac_data.date[3], + mac_data.date[4], + mac_data.date[5], + mac_data.date[6]); + for (i = 0; i < 8; i++) { + sprintf((char *)ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); + printf("MAC %d %s\n", i, ethaddr[i]); + } + + setenv("ethaddr", (char *)ethaddr[0]); + setenv("eth1addr", (char *)ethaddr[1]); + setenv("eth2addr", (char *)ethaddr[2]); + setenv("eth3addr", (char *)ethaddr[3]); + + return 0; +} + +int mac_read(void) +{ + int ret, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *data; + + length = sizeof(EEPROM_data); + ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length); + if (ret) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + printf("Check CRC on reading ..."); + crc = crc32(crc, data, length - 4); + if (crc != mac_data.crc) { + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n", + mac_data.crc, crc); + return -1; + } else { + printf("CRC OK\n"); + mac_show(); + } + return 0; +} + +int mac_prog(void) +{ + int ret, i, length; + unsigned int crc = 0; + unsigned char dev = ID_EEPROM_ADDR, *ptr; + unsigned char *eeprom_data = (unsigned char *)(&mac_data); + + for (i = 0; i < sizeof(mac_data.res_1); i++) + mac_data.res_1[i] = 0; + for (i = 0; i < sizeof(mac_data.res_2); i++) + mac_data.res_2[i] = 0; + length = sizeof(EEPROM_data); + crc = crc32(crc, eeprom_data, length - 4); + mac_data.crc = crc; + for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { + ret = + i2c_write(dev, i, 1, ptr, + (length - i) < 8 ? (length - i) : 8); + udelay(5000); /* 5ms write cycle timing */ + if (ret) + break; + } + if (ret) { + printf("Programming failed.\n"); + return -1; + } else { + printf("Programming %d bytes. Reading back ...\n", length); + mac_read(); + } + return 0; +} + +int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + char cmd = 's'; + unsigned long long mac_val; + + if (i2c_probe(ID_EEPROM_ADDR) != 0) + return -1; + + if (argc > 1) { + cmd = argv[1][0]; + switch (cmd) { + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i = 0; i < 4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i = 0; i < 12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i = 0; i < 5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i = 0; i < 7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = + (unsigned char)simple_strtoul(argv[2], NULL, 16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2], NULL, 16); + for (i = 0; i < 6; i++) { + mac_data.mac[cmd - '0'][i] = + *((unsigned char *) + (((unsigned int)(&mac_val)) + i + 2)); + } + break; + case 'h': /* help */ + default: + printf("Usage:\n%s\n", cmdtp->usage); + break; + } + } else { + mac_show(); + } + return 0; +} + +int mac_read_from_eeprom(void) +{ + int length, i; + unsigned char dev = ID_EEPROM_ADDR; + unsigned char *data; + unsigned char ethaddr[4][18]; + unsigned char enetvar[32]; + unsigned int crc = 0; + + length = sizeof(EEPROM_data); + if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) { + printf("Read failed.\n"); + return -1; + } + + data = (unsigned char *)(&mac_data); + crc = crc32(crc, data, length - 4); + if (crc != mac_data.crc) { + return -1; + } else { + for (i = 0; i < 4; i++) { + if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf((char *)ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); + sprintf((char *)enetvar, + i ? "eth%daddr" : "ethaddr", + i); + setenv((char *)enetvar, (char *)ethaddr[i]); + } + } + } + return 0; +} +#endif /* CFG_ID_EEPROM */ diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile new file mode 100644 index 0000000..93b015d --- /dev/null +++ b/board/freescale/mpc8641hpcn/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o \ + ../common/sys_eeprom.o \ + ../common/pixis.o + +SOBJS := init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/freescale/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk new file mode 100644 index 0000000..f778dcb --- /dev/null +++ b/board/freescale/mpc8641hpcn/config.mk @@ -0,0 +1,31 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Jeff Brown +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8641hpcn board +# default CCSRBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff00000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/freescale/mpc8641hpcn/init.S b/board/freescale/mpc8641hpcn/init.S new file mode 100644 index 0000000..cb21ba6 --- /dev/null +++ b/board/freescale/mpc8641hpcn/init.S @@ -0,0 +1,179 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR1 0 +#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) + +#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff) +#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) +#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) +#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR8 0 +#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff) +#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + .section .bootpg, "ax" + .globl law_entry +law_entry: + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + addi r4,r7,0 + addi r5,r7,0 + + /* Skip LAWAR0, start at LAWAR1 */ + lis r6,LAWBAR1@h + ori r6,r6,LAWBAR1@l + stwu r6, 0xc28(r4) + + lis r6,LAWAR1@h + ori r6,r6,LAWAR1@l + stwu r6, 0xc30(r5) + + /* LAWBAR2, LAWAR2 */ + lis r6,LAWBAR2@h + ori r6,r6,LAWBAR2@l + stwu r6, 0x20(r4) + + lis r6,LAWAR2@h + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) + + /* LAWBAR3, LAWAR3 */ + lis r6,LAWBAR3@h + ori r6,r6,LAWBAR3@l + stwu r6, 0x20(r4) + + lis r6,LAWAR3@h + ori r6,r6,LAWAR3@l + stwu r6, 0x20(r5) + + /* LAWBAR4, LAWAR4 */ + lis r6,LAWBAR4@h + ori r6,r6,LAWBAR4@l + stwu r6, 0x20(r4) + + lis r6,LAWAR4@h + ori r6,r6,LAWAR4@l + stwu r6, 0x20(r5) + /* LAWBAR5, LAWAR5 */ + lis r6,LAWBAR5@h + ori r6,r6,LAWBAR5@l + stwu r6, 0x20(r4) + + lis r6,LAWAR5@h + ori r6,r6,LAWAR5@l + stwu r6, 0x20(r5) + + /* LAWBAR6, LAWAR6 */ + lis r6,LAWBAR6@h + ori r6,r6,LAWBAR6@l + stwu r6, 0x20(r4) + + lis r6,LAWAR6@h + ori r6,r6,LAWAR6@l + stwu r6, 0x20(r5) + + /* LAWBAR7, LAWAR7 */ + lis r6,LAWBAR7@h + ori r6,r6,LAWBAR7@l + stwu r6, 0x20(r4) + + lis r6,LAWAR7@h + ori r6,r6,LAWAR7@l + stwu r6, 0x20(r5) + + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) + + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) + + /* LAWBAR9, LAWAR9 */ + lis r6,LAWBAR9@h + ori r6,r6,LAWBAR9@l + stwu r6, 0x20(r4) + + lis r6,LAWAR9@h + ori r6,r6,LAWAR9@l + stwu r6, 0x20(r5) + + blr diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c new file mode 100644 index 0000000..ffd11cb --- /dev/null +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -0,0 +1,407 @@ +/* + * Copyright 2006, 2007 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#include "../common/pixis.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif + +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + puts("Board: MPC8641HPCN\n"); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram(); +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CFG_RAMBOOT) + puts(" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + puts(" DDR: "); + return dram_size; +} + + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + puts("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + puts("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int +fixed_sdram(void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; + +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000008D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync"); + + udelay(500); + +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg_1 = CFG_DDR_CONTROL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; +#endif + asm("sync; isync"); + + udelay(500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} +}; +#endif + + +static struct pci_controller pci1_hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc86xxcts_config_table +#endif +}; +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +int first_free_busno = 0; + + +void pci_init_board(void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; +#ifdef DEBUG + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); +#endif + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + debug("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000))); + + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } +} +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif /* CONFIG_PCI1 */ + +#ifdef CONFIG_PCI2 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci2_hose; + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); +} +#else + puts("PCI-EXPRESS 2: Disabled\n"); +#endif /* CONFIG_PCI2 */ + +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif + + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long +get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds new file mode 100644 index 0000000..fd16362 --- /dev/null +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -0,0 +1,136 @@ +/* + * Copyright 2006, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc86xx/start.o (.text) + board/freescale/mpc8641hpcn/init.o (.bootpg) + cpu/mpc86xx/traps.o (.text) + cpu/mpc86xx/interrupts.o (.text) + cpu/mpc86xx/cpu_init.o (.text) + cpu/mpc86xx/cpu.o (.text) + cpu/mpc86xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + drivers/bios_emulator/atibios.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile deleted file mode 100644 index df56b31..0000000 --- a/board/mpc8641hpcn/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../freescale/common) -endif - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o sys_eeprom.o \ - ../freescale/common/pixis.o - -SOBJS := init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -.PHONY: distclean -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude ($obj).depend - -######################################################################### diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk deleted file mode 100644 index f778dcb..0000000 --- a/board/mpc8641hpcn/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright 2004 Freescale Semiconductor. -# Modified by Jeff Brown -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8641hpcn board -# default CCSRBAR is at 0xff700000 -# assume U-Boot is less than 0.5MB -# -TEXT_BASE = 0xfff00000 - -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S deleted file mode 100644 index cb21ba6..0000000 --- a/board/mpc8641hpcn/init.S +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf800_0000 0xf80f_ffff CCSRBAR 1M - * 0xf810_0000 0xf81f_ffff PIXIS 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M - * - * Notes: - * CCSRBAR don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR1 0 -#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) - -/* - * This is not so much the SDRAM map as it is the whole localbus map. - */ -#define LAWBAR4 ((0xf8100000>>12) & 0xffffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) - -#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) - -#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) - -#if !defined(CONFIG_SPD_EEPROM) -#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#else -#define LAWBAR8 0 -#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) -#endif - -#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff) -#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) - - .section .bootpg, "ax" - .globl law_entry -law_entry: - lis r7,CFG_CCSRBAR@h - ori r7,r7,CFG_CCSRBAR@l - - addi r4,r7,0 - addi r5,r7,0 - - /* Skip LAWAR0, start at LAWAR1 */ - lis r6,LAWBAR1@h - ori r6,r6,LAWBAR1@l - stwu r6, 0xc28(r4) - - lis r6,LAWAR1@h - ori r6,r6,LAWAR1@l - stwu r6, 0xc30(r5) - - /* LAWBAR2, LAWAR2 */ - lis r6,LAWBAR2@h - ori r6,r6,LAWBAR2@l - stwu r6, 0x20(r4) - - lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) - - /* LAWBAR3, LAWAR3 */ - lis r6,LAWBAR3@h - ori r6,r6,LAWBAR3@l - stwu r6, 0x20(r4) - - lis r6,LAWAR3@h - ori r6,r6,LAWAR3@l - stwu r6, 0x20(r5) - - /* LAWBAR4, LAWAR4 */ - lis r6,LAWBAR4@h - ori r6,r6,LAWBAR4@l - stwu r6, 0x20(r4) - - lis r6,LAWAR4@h - ori r6,r6,LAWAR4@l - stwu r6, 0x20(r5) - /* LAWBAR5, LAWAR5 */ - lis r6,LAWBAR5@h - ori r6,r6,LAWBAR5@l - stwu r6, 0x20(r4) - - lis r6,LAWAR5@h - ori r6,r6,LAWAR5@l - stwu r6, 0x20(r5) - - /* LAWBAR6, LAWAR6 */ - lis r6,LAWBAR6@h - ori r6,r6,LAWBAR6@l - stwu r6, 0x20(r4) - - lis r6,LAWAR6@h - ori r6,r6,LAWAR6@l - stwu r6, 0x20(r5) - - /* LAWBAR7, LAWAR7 */ - lis r6,LAWBAR7@h - ori r6,r6,LAWBAR7@l - stwu r6, 0x20(r4) - - lis r6,LAWAR7@h - ori r6,r6,LAWAR7@l - stwu r6, 0x20(r5) - - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) - - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) - - /* LAWBAR9, LAWAR9 */ - lis r6,LAWBAR9@h - ori r6,r6,LAWBAR9@l - stwu r6, 0x20(r4) - - lis r6,LAWAR9@h - ori r6,r6,LAWAR9@l - stwu r6, 0x20(r5) - - blr diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c deleted file mode 100644 index 1bfbe88..0000000 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright 2006, 2007 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -extern void ft_cpu_setup(void *blob, bd_t *bd); -#endif - -#include "../freescale/common/pixis.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -#if defined(CONFIG_SPD_EEPROM) -#include "spd_sdram.h" -#endif - -void sdram_init(void); -long int fixed_sdram(void); - - -int board_early_init_f(void) -{ - return 0; -} - -int checkboard(void) -{ - puts("Board: MPC8641HPCN\n"); - - return 0; -} - - -long int -initdram(int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(); -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CFG_RAMBOOT) - puts(" DDR: "); - return dram_size; -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - puts(" DDR: "); - return dram_size; -} - - -#if defined(CFG_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; - uint *p; - - puts("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - puts("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -long int -fixed_sdram(void) -{ -#if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode_1 = CFG_DDR_MODE_1; - ddr->sdram_mode_2 = CFG_DDR_MODE_2; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; - ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; - -#if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000008D; - ddr->err_sbe = 0x00ff0000; -#endif - asm("sync;isync"); - - udelay(500); - -#if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); -#else - ddr->sdram_cfg_1 = CFG_DDR_CONTROL; - ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; -#endif - asm("sync; isync"); - - udelay(500); -#endif - return CFG_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_fsl86xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller pci1_hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table -#endif -}; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ - -int first_free_busno = 0; - - -void pci_init_board(void) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); - struct pci_controller *hose = &pci1_hose; -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - debug("\n"); - - /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - */ - in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE - + CFG_PCI1_MEM_SIZE - 0x1000000))); - - } else { - puts("PCI-EXPRESS 1: Disabled\n"); - } -} -#else - puts("PCI-EXPRESS1: Disabled\n"); -#endif /* CONFIG_PCI1 */ - -#ifdef CONFIG_PCI2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); - struct pci_controller *hose = &pci2_hose; - - - /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); -} -#else - puts("PCI-EXPRESS 2: Disabled\n"); -#endif /* CONFIG_PCI2 */ - -} - -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - ft_cpu_setup(blob, bd); - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -} -#endif - - -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long -get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); - else - i = in8(PIXIS_BASE + PIXIS_SPD); - } else { - i = in8(PIXIS_BASE + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c deleted file mode 100644 index 7bc663b..0000000 --- a/board/mpc8641hpcn/sys_eeprom.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor - * York Sun (yorksun@freescale.com) - * Haiying Wang (haiying.wang@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifdef CFG_ID_EEPROM -typedef struct { - unsigned char id[4]; /* 0x0000 - 0x0003 */ - unsigned char sn[12]; /* 0x0004 - 0x000F */ - unsigned char errata[5]; /* 0x0010 - 0x0014 */ - unsigned char date[7]; /* 0x0015 - 0x001a */ - unsigned char res_1[37]; /* 0x001b - 0x003f */ - unsigned char tab_size; /* 0x0040 */ - unsigned char tab_flag; /* 0x0041 */ - unsigned char mac[8][6]; /* 0x0042 - 0x0071 */ - unsigned char res_2[126]; /* 0x0072 - 0x00ef */ - unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ -} EEPROM_data; - -static EEPROM_data mac_data; - -int mac_show(void) -{ - int i; - unsigned char ethaddr[8][18]; - - printf("ID %c%c%c%c\n", - mac_data.id[0], - mac_data.id[1], - mac_data.id[2], - mac_data.id[3]); - printf("Errata %c%c%c%c%c\n", - mac_data.errata[0], - mac_data.errata[1], - mac_data.errata[2], - mac_data.errata[3], - mac_data.errata[4]); - printf("Date %c%c%c%c%c%c%c\n", - mac_data.date[0], - mac_data.date[1], - mac_data.date[2], - mac_data.date[3], - mac_data.date[4], - mac_data.date[5], - mac_data.date[6]); - for (i = 0; i < 8; i++) { - sprintf((char *)ethaddr[i], - "%02x:%02x:%02x:%02x:%02x:%02x", - mac_data.mac[i][0], - mac_data.mac[i][1], - mac_data.mac[i][2], - mac_data.mac[i][3], - mac_data.mac[i][4], - mac_data.mac[i][5]); - printf("MAC %d %s\n", i, ethaddr[i]); - } - - setenv("ethaddr", (char *)ethaddr[0]); - setenv("eth1addr", (char *)ethaddr[1]); - setenv("eth2addr", (char *)ethaddr[2]); - setenv("eth3addr", (char *)ethaddr[3]); - - return 0; -} - -int mac_read(void) -{ - int ret, length; - unsigned int crc = 0; - unsigned char dev = ID_EEPROM_ADDR, *data; - - length = sizeof(EEPROM_data); - ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length); - if (ret) { - printf("Read failed.\n"); - return -1; - } - - data = (unsigned char *)(&mac_data); - printf("Check CRC on reading ..."); - crc = crc32(crc, data, length - 4); - if (crc != mac_data.crc) { - printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n", - mac_data.crc, crc); - return -1; - } else { - printf("CRC OK\n"); - mac_show(); - } - return 0; -} - -int mac_prog(void) -{ - int ret, i, length; - unsigned int crc = 0; - unsigned char dev = ID_EEPROM_ADDR, *ptr; - unsigned char *eeprom_data = (unsigned char *)(&mac_data); - - for (i = 0; i < sizeof(mac_data.res_1); i++) - mac_data.res_1[i] = 0; - for (i = 0; i < sizeof(mac_data.res_2); i++) - mac_data.res_2[i] = 0; - length = sizeof(EEPROM_data); - crc = crc32(crc, eeprom_data, length - 4); - mac_data.crc = crc; - for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { - ret = - i2c_write(dev, i, 1, ptr, - (length - i) < 8 ? (length - i) : 8); - udelay(5000); /* 5ms write cycle timing */ - if (ret) - break; - } - if (ret) { - printf("Programming failed.\n"); - return -1; - } else { - printf("Programming %d bytes. Reading back ...\n", length); - mac_read(); - } - return 0; -} - -int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - int i; - char cmd = 's'; - unsigned long long mac_val; - - if (i2c_probe(ID_EEPROM_ADDR) != 0) - return -1; - - if (argc > 1) { - cmd = argv[1][0]; - switch (cmd) { - case 'r': /* display */ - mac_read(); - break; - case 's': /* save */ - mac_prog(); - break; - case 'i': /* id */ - for (i = 0; i < 4; i++) { - mac_data.id[i] = argv[2][i]; - } - break; - case 'n': /* serial number */ - for (i = 0; i < 12; i++) { - mac_data.sn[i] = argv[2][i]; - } - break; - case 'e': /* errata */ - for (i = 0; i < 5; i++) { - mac_data.errata[i] = argv[2][i]; - } - break; - case 'd': /* date */ - for (i = 0; i < 7; i++) { - mac_data.date[i] = argv[2][i]; - } - break; - case 'p': /* number of ports */ - mac_data.tab_size = - (unsigned char)simple_strtoul(argv[2], NULL, 16); - break; - case '0': /* mac 0 */ - case '1': /* mac 1 */ - case '2': /* mac 2 */ - case '3': /* mac 3 */ - case '4': /* mac 4 */ - case '5': /* mac 5 */ - case '6': /* mac 6 */ - case '7': /* mac 7 */ - mac_val = simple_strtoull(argv[2], NULL, 16); - for (i = 0; i < 6; i++) { - mac_data.mac[cmd - '0'][i] = - *((unsigned char *) - (((unsigned int)(&mac_val)) + i + 2)); - } - break; - case 'h': /* help */ - default: - printf("Usage:\n%s\n", cmdtp->usage); - break; - } - } else { - mac_show(); - } - return 0; -} - -int mac_read_from_eeprom(void) -{ - int length, i; - unsigned char dev = ID_EEPROM_ADDR; - unsigned char *data; - unsigned char ethaddr[4][18]; - unsigned char enetvar[32]; - unsigned int crc = 0; - - length = sizeof(EEPROM_data); - if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) { - printf("Read failed.\n"); - return -1; - } - - data = (unsigned char *)(&mac_data); - crc = crc32(crc, data, length - 4); - if (crc != mac_data.crc) { - return -1; - } else { - for (i = 0; i < 4; i++) { - if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { - sprintf((char *)ethaddr[i], - "%02x:%02x:%02x:%02x:%02x:%02x", - mac_data.mac[i][0], - mac_data.mac[i][1], - mac_data.mac[i][2], - mac_data.mac[i][3], - mac_data.mac[i][4], - mac_data.mac[i][5]); - sprintf((char *)enetvar, - i ? "eth%daddr" : "ethaddr", - i); - setenv((char *)enetvar, (char *)ethaddr[i]); - } - } - } - return 0; -} -#endif /* CFG_ID_EEPROM */ diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds deleted file mode 100644 index 5864464..0000000 --- a/board/mpc8641hpcn/u-boot.lds +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright 2006, 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - - /* Read-only sections, merged into text segment: */ - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc86xx/start.o (.text) - board/mpc8641hpcn/init.o (.bootpg) - cpu/mpc86xx/traps.o (.text) - cpu/mpc86xx/interrupts.o (.text) - cpu/mpc86xx/cpu_init.o (.text) - cpu/mpc86xx/cpu.o (.text) - cpu/mpc86xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - drivers/bios_emulator/atibios.o (.text) - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -- cgit v1.1 From 8f9e0e9f339aee4ce31a338d5f27356eb5457f85 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:19 -0500 Subject: mpc83xx: remaining 8360 libfdt fixes PCI clocks and QE frequencies weren't being updated, and the core clock was being updated incorrectly. This patch also adds a /memory node if it doesn't already exist prior to update. plus some cosmetic trimming to single line comments. Signed-off-by: Kim Phillips --- board/mpc8360emds/mpc8360emds.c | 8 ++++++++ board/mpc8360emds/pci.c | 8 ++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 3fa093d..e37d2dc 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -305,7 +305,15 @@ ft_board_setup(void *blob, bd_t *bd) int tmp[2]; nodeoffset = fdt_find_node_by_path(blob, "/memory"); + if (nodeoffset < 0) { + nodeoffset = fdt_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + printf("WARNING: failed to add /memory node: %s\n", + fdt_strerror(nodeoffset)); + } if (nodeoffset >= 0) { + fdt_setprop(blob, nodeoffset, "device_type", + "memory", sizeof("memory")); tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 8f90471..7981285 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -22,7 +22,6 @@ #include #elif defined(CONFIG_OF_LIBFDT) #include -#include #endif #include @@ -314,7 +313,12 @@ ft_pci_setup(void *blob, bd_t *bd) if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(hose[0].first_busno); tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); } } #elif defined(CONFIG_OF_FLAT_TREE) -- cgit v1.1 From 6a16e0dfcc4119b46adb1dce2d6c8fb3c5d108e1 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:26 -0500 Subject: mpc83xx: move common /memory node update mechanism to cpu.c also adds common prototypes to include/common.h. Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/mpc8323erdb.c | 22 ---------------------- board/mpc8360emds/mpc8360emds.c | 31 +------------------------------ 2 files changed, 1 insertion(+), 52 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 1886f19..81b82b7 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -17,7 +17,6 @@ #include #include #include -#include #if defined(CONFIG_PCI) #include #endif @@ -185,31 +184,10 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - void ft_board_setup(void *blob, bd_t *bd) { - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } - ft_cpu_setup(blob, bd); - #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index e37d2dc..eec46fb 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -29,7 +29,6 @@ #include #elif defined(CONFIG_OF_LIBFDT) #include -#include #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -287,38 +286,10 @@ void sdram_init(void) #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ && defined(CONFIG_OF_BOARD_SETUP) - -/* - * Prototypes of functions that we use. - */ -void ft_cpu_setup(void *blob, bd_t *bd); - -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif - void ft_board_setup(void *blob, bd_t *bd) { -#if defined(CONFIG_OF_LIBFDT) - int nodeoffset; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/memory"); - if (nodeoffset < 0) { - nodeoffset = fdt_add_subnode(blob, 0, "memory"); - if (nodeoffset < 0) - printf("WARNING: failed to add /memory node: %s\n", - fdt_strerror(nodeoffset)); - } - if (nodeoffset >= 0) { - fdt_setprop(blob, nodeoffset, "device_type", - "memory", sizeof("memory")); - tmp[0] = cpu_to_be32(bd->bi_memstart); - tmp[1] = cpu_to_be32(bd->bi_memsize); - fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp)); - } -#else +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -- cgit v1.1 From 3fde9e8b22cfbd7af489214758f9839a206576cb Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 15 Aug 2007 22:30:33 -0500 Subject: mpc83xx: migrate remaining freescale boards to libfdt this adds libfdt support code for the freescale mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, and gp boards. Boards remain compatible with OF_FLAT_TREE. Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/mpc8323erdb.c | 15 ++++++++--- board/mpc8313erdb/mpc8313erdb.c | 19 ++++++++------ board/mpc832xemds/mpc832xemds.c | 18 ++++++++------ board/mpc832xemds/pci.c | 24 +++++++++++++++++- board/mpc8349emds/mpc8349emds.c | 18 ++++++++------ board/mpc8349emds/pci.c | 41 ++++++++++++++++++++++++++++++- board/mpc8349itx/mpc8349itx.c | 18 ++++++++------ board/mpc8349itx/pci.c | 39 +++++++++++++++++++++++++++-- board/mpc8360emds/mpc8360emds.c | 11 +++------ 9 files changed, 158 insertions(+), 45 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 81b82b7..850d1c3 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -184,12 +184,21 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } -#endif /* CONFIG_OF_BOARD_SETUP */ +#endif diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/mpc8313erdb/mpc8313erdb.c index 999fe9e..861c143 100644 --- a/board/mpc8313erdb/mpc8313erdb.c +++ b/board/mpc8313erdb/mpc8313erdb.c @@ -23,7 +23,11 @@ */ #include +#if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif #include #include @@ -96,21 +100,22 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p) { + if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c index 772da67..f70783e 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/mpc832xemds/mpc832xemds.c @@ -29,6 +29,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif const qe_iop_conf_t qe_iop_conf_tab[] = { @@ -155,22 +157,22 @@ int checkboard(void) return 0; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c index d0a407a..c2f61ea 100644 --- a/board/mpc832xemds/pci.c +++ b/board/mpc832xemds/pci.c @@ -20,6 +20,8 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif #include @@ -299,7 +301,27 @@ void pci_init_board(void) } #endif /* CONFIG_PCISLAVE */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 521d1bb..2ad25ec 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -34,6 +34,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif int fixed_sdram(void); @@ -257,22 +259,22 @@ void sdram_init(void) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c index d6a12b8..ae94a2f 100644 --- a/board/mpc8349emds/pci.c +++ b/board/mpc8349emds/pci.c @@ -25,6 +25,12 @@ #include #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -382,7 +388,40 @@ pci_init_board(void) } -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 178b1d3..125e6c0 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -39,6 +39,8 @@ #endif #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif #ifndef CONFIG_SPD_EEPROM @@ -385,22 +387,22 @@ int misc_init_r(void) return rc; } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_OF_FLAT_TREE) u32 *p; int len; -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif } #endif diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c index e81ad27..5ca094d 100644 --- a/board/mpc8349itx/pci.c +++ b/board/mpc8349itx/pci.c @@ -31,6 +31,8 @@ #include #if defined(CONFIG_OF_FLAT_TREE) #include +#elif defined(CONFIG_OF_LIBFDT) +#include #endif DECLARE_GLOBAL_DATA_PTR; @@ -332,8 +334,40 @@ void pci_init_board(void) #endif } -#endif /* CONFIG_PCI */ -#ifdef CONFIG_OF_FLAT_TREE +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) void ft_pci_setup(void *blob, bd_t *bd) { @@ -355,3 +389,4 @@ ft_pci_setup(void *blob, bd_t *bd) #endif } #endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index eec46fb..3861733 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -284,10 +284,8 @@ void sdram_init(void) } #endif -#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ - && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_OF_FLAT_TREE) u32 *p; @@ -299,10 +297,9 @@ ft_board_setup(void *blob, bd_t *bd) *p = cpu_to_be32(bd->bi_memsize); } #endif - + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif - ft_cpu_setup(blob, bd); } -#endif /* CONFIG_OF_x */ +#endif -- cgit v1.1 From 02ba7022f62bb75908296c58c63866e1d294b69a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2007 09:52:29 +0200 Subject: ppc4xx: Update Sequoia/Rainier bootstrap command As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese --- board/amcc/sequoia/cmd_sequoia.c | 205 ++++++++++++++++++++++++++++++--------- 1 file changed, 157 insertions(+), 48 deletions(-) (limited to 'board') diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index 6fc60ea..f3803c0 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -26,76 +26,185 @@ #include #include -static u8 boot_533_nor[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 -}; +/* + * There are 2 versions of production Sequoia & Rainier platforms. + * The primary difference is the reference clock. Those with + * 33333333 reference clocks will also have 667MHz rated + * processors. Not enough differences to have unique clock + * settings. + * + * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The + * values are independent of the rest of the clock settings. + * + * All Sequoias & Rainiers select from two possible EEPROMs in Boot + * Config F. One for 33MHz PCI, one for 66MHz PCI. The following + * values are for the 33MHz PCI configuration. Byte 5 (0 base) is + * the only value affected for a 66MHz PCI and simply needs a +0x10. + */ + +#define NAND_COMPATIBLE 0x01 +#define NOR_COMPATIBLE 0x02 + +/* check with Stefan on CFG_I2C_EEPROM_ADDR */ +#define I2C_EEPROM_ADDR 0x52 -static u8 boot_533_nand[] = { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +static char *config_labels[] = { + "CPU: 333 PLB: 133 OPB: 66 EBC: 66", + "CPU: 333 PLB: 166 OPB: 83 EBC: 55", + "CPU: 400 PLB: 133 OPB: 66 EBC: 66", + "CPU: 400 PLB: 160 OPB: 80 EBC: 53", + "CPU: 416 PLB: 166 OPB: 83 EBC: 55", + "CPU: 500 PLB: 166 OPB: 83 EBC: 55", + "CPU: 533 PLB: 133 OPB: 66 EBC: 66", + "CPU: 667 PLB: 166 OPB: 83 EBC: 55", + NULL }; -static u8 boot_667_nor[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 +static u8 boot_configs[][17] = { + { + (NOR_COMPATIBLE), + 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NOR_COMPATIBLE), + 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40, + 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + } }; -static u8 boot_667_nand[] = { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 +/* + * Bytes 6,8,9,11 change for NAND boot + */ +static u8 nand_boot[] = { + 0xd0, 0xa0, 0x68, 0x58 }; static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u8 chip; - u8 *buf; - int cpu_freq; + u8 *buf, bNAND; + int x, y, nbytes, selcfg; + extern char console_buffer[]; - if (argc < 3) { + if (argc < 2) { printf("Usage:\n%s\n", cmdtp->usage); return 1; } - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (!((cpu_freq == 533) || (cpu_freq == 667))) { - printf("Unsupported cpu-frequency - only 533 and 667 supported\n"); + if ((strcmp(argv[1], "nor") != 0) && + (strcmp(argv[1], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); return 1; } - /* use 0x52 as I2C EEPROM address for now */ - chip = 0x52; + /* set the nand flag based on provided input */ + if ((strcmp(argv[1], "nand") == 0)) + bNAND = 1; + else + bNAND = 0; - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { - printf("Unsupported boot-device - only nor|nand support\n"); - return 1; - } + printf("Available configurations: \n\n"); - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nand; - break; - case 667: - buf = boot_667_nand; - break; + if (bNAND) { + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nand compatible */ + if (boot_configs[x][0] & NAND_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } else { - switch (cpu_freq) { - default: - case 533: - buf = boot_533_nor; - break; - case 667: - buf = boot_667_nor; - break; + for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { + /* filter on nor compatible */ + if (boot_configs[x][0] & NOR_COMPATIBLE) { + printf(" %d - %s\n", (y+1), config_labels[x]); + y++; + } } } - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); + do { + nbytes = readline(" Selection [1-x / quit]: "); + + if (nbytes) { + if (strcmp(console_buffer, "quit") == 0) + return 0; + selcfg = simple_strtol(console_buffer, NULL, 10); + if ((selcfg < 1) || (selcfg > y)) + nbytes = 0; + } + } while (nbytes == 0); + + + y = (selcfg - 1); + + for (x = 0; boot_configs[x][0] != 0; x++) { + if (bNAND) { + if (boot_configs[x][0] & NAND_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } else { + if (boot_configs[x][0] & NOR_COMPATIBLE) { + if (y > 0) + y--; + else if (y < 1) + break; + } + } + } + + buf = &boot_configs[x][1]; + + if (bNAND) { + buf[6] = nand_boot[0]; + buf[8] = nand_boot[1]; + buf[9] = nand_boot[2]; + buf[11] = nand_boot[3]; + } + + /* check CPLD register +5 for PCI 66MHz flag */ + if (in8(CFG_BCSR_BASE + 5) & 0x01) + buf[5] += 0x10; + + if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); printf("Done\n"); @@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, + bootstrap, 2, 0, do_bootstrap, "bootstrap - program the I2C bootstrap EEPROM\n", - " - program the I2C bootstrap EEPROM\n" + " - strap to boot from NAND or NOR flash\n" ); -- cgit v1.1 From 2d78074d2e806edc380c1464eb9e5df335ece65e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 22 Jun 2007 17:32:28 +0200 Subject: ppc7xx: Update CPCI750 board This small CPCI750 update extends the board specific command "show_config" to display the Marvell strapping registers and extends the PCI IDE controller. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese --- board/esd/cpci750/cpci750.c | 89 +++++++++++++++++++++++++++++++++++++++++++-- board/esd/cpci750/ide.c | 2 + 2 files changed, 87 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 17e3568..298aa6a 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -55,6 +55,71 @@ #define DP(x) #endif +static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ + {"PCI0DLL_1 "}, /* 30 */ + {"PCI0DLL_0 "}, /* 29 */ + {"PCI1DLL_2 "}, /* 28 */ + {"PCI1DLL_1 "}, /* 27 */ + {"PCI1DLL_0 "}, /* 26 */ + {"BbEP2En "}, /* 25 */ + {"SDRAMRdDataDel"}, /* 24 */ + {"SDRAMRdDel "}, /* 23 */ + {"SDRAMSync "}, /* 22 */ + {"SDRAMPipeSel_1"}, /* 21 */ + {"SDRAMPipeSel_0"}, /* 20 */ + {"SDRAMAddDel "}, /* 19 */ + {"SDRAMClkSel "}, /* 18 */ + {"Reserved(1!) "}, /* 17 */ + {"PCIRty "}, /* 16 */ + {"BootCSWidth_1 "}, /* 15 */ + {"BootCSWidth_0 "}, /* 14 */ + {"PCI1PadsCal "}, /* 13 */ + {"PCI0PadsCal "}, /* 12 */ + {"MultiMVId_1 "}, /* 11 */ + {"MultiMVId_0 "}, /* 10 */ + {"MultiGTEn "}, /* 09 */ + {"Int60xArb "}, /* 08 */ + {"CPUBusConfig_1"}, /* 07 */ + {"CPUBusConfig_0"}, /* 06 */ + {"DefIntSpc "}, /* 05 */ + {0 }, /* 04 */ + {"SROMAdd_1 "}, /* 03 */ + {"SROMAdd_0 "}, /* 02 */ + {"DRAMPadCal "}, /* 01 */ + {"SInitEn "}, /* 00 */ + {0 }, /* 31 */ + {0 }, /* 30 */ + {0 }, /* 29 */ + {0 }, /* 28 */ + {0 }, /* 27 */ + {0 }, /* 26 */ + {0 }, /* 25 */ + {0 }, /* 24 */ + {0 }, /* 23 */ + {0 }, /* 22 */ + {"JTAGCalBy "}, /* 21 */ + {"GB2Sel "}, /* 20 */ + {"GB1Sel "}, /* 19 */ + {"DRAMPLL_MDiv_5"}, /* 18 */ + {"DRAMPLL_MDiv_4"}, /* 17 */ + {"DRAMPLL_MDiv_3"}, /* 16 */ + {"DRAMPLL_MDiv_2"}, /* 15 */ + {"DRAMPLL_MDiv_1"}, /* 14 */ + {"DRAMPLL_MDiv_0"}, /* 13 */ + {"GB0Sel "}, /* 12 */ + {"DRAMPLLPU "}, /* 11 */ + {"DRAMPLL_HIKVCO"}, /* 10 */ + {"DRAMPLLNP "}, /* 09 */ + {"DRAMPLL_NDiv_7"}, /* 08 */ + {"DRAMPLL_NDiv_6"}, /* 07 */ + {"CPUPadCal "}, /* 06 */ + {"DRAMPLL_NDiv_5"}, /* 05 */ + {"DRAMPLL_NDiv_4"}, /* 04 */ + {"DRAMPLL_NDiv_3"}, /* 03 */ + {"DRAMPLL_NDiv_2"}, /* 02 */ + {"DRAMPLL_NDiv_1"}, /* 01 */ + {"DRAMPLL_NDiv_0"}}; /* 00 */ + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern flash_info_t flash_info[]; @@ -901,21 +966,37 @@ void board_prebootm_init () dcache_disable (); } - -int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { unsigned int reset_sample_low; unsigned int reset_sample_high; + unsigned int l, l1, l2; GT_REG_READ(0x3c4, &reset_sample_low); GT_REG_READ(0x3d4, &reset_sample_high); printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); + l2 = 0; + for (l=0; l<63; l++) { + if (show_config_tab[l][0] != 0) { + printf("%14s:%1x ", show_config_tab[l], + ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); + l2++; + if ((l2 % 4) == 0) + printf("\n"); + } else { + l1++; + } + if (l == 32) + reset_sample_low = reset_sample_high; + } + printf("\n"); + return(0); } U_BOOT_CMD( - show_cfg, 1, 1, do_show_cfg, - "show_cfg- Show Marvell strapping register\n", + show_config, 1, 1, do_show_config, + "show_config - Show Marvell strapping register\n", "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" ); diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 01b90c6..0adafe2 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -43,6 +43,8 @@ int ide_preinit (void) ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); + if (devbusfn == -1) + devbusfn = pci_find_device (0x1095, 0x3114, 0); if (devbusfn != -1) { status = 0; -- cgit v1.1 From 8fb6e80c06849e3013ac5c9350d8ed9e52967991 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 16 Aug 2007 11:21:49 +0200 Subject: ppc4xx: Remove #warning in esd auto_update.c Signed-off-by: Stefan Roese --- board/esd/common/auto_update.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'board') diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 62f6c20..c4a0957 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -24,10 +24,6 @@ #include -#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) -#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! -#endif - #include #include #include -- cgit v1.1 From 78f9fef7f406078c8bf7191e665a73f795157746 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 15 Aug 2007 15:46:46 -0500 Subject: mpc885ads: Don't define CONFIG_BZIP2. bzip2 requires a significant chunk of malloc space, and there isn't enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area and a downloaded image at 0x400000. Signed-off-by: Scott Wood --- board/fads/fads.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/fads/fads.h b/board/fads/fads.h index c6f7ccd..a7fe2e9 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -71,7 +71,10 @@ #undef CONFIG_BOOTARGS #undef CONFIG_WATCHDOG /* watchdog disabled */ + +#if !defined(CONFIG_MPC885ADS) #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#endif /* * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: -- cgit v1.1 From 1e6b07c64967c1eb2cd84faa4c32bf2a769bc8eb Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Thu, 16 Aug 2007 15:16:02 +0200 Subject: PPC4xx:HCU4/5 cleanup ecc/sdram init Make ecc initialisation robust, as DDR2-ECC errors may be generated while zeroing the RAM. Return 16 bytes (a cacheline) less than the available memory, as the board and/or PPC440EPx might have problems accessing the last bytes. Signed-off-by: Niklaus Giger --- board/netstal/hcu5/sdram.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 4039195..5d457f7 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -36,7 +36,7 @@ #include #include -void sysLedSet(u32 value); +void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); @@ -138,7 +138,7 @@ static int wait_for_dlllock(void) void sdram_panic(const char *reason) { printf("\n%s: reason %s", __FUNCTION__, reason); - sysLedSet(0xff); + hcu_led_set(0xff); while (1) { } /* Never return */ @@ -197,6 +197,13 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes, mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); + /* + * Clear possible errors + * If not done, then we could get an interrupt later on when + * exceptions are enabled. + */ + mtspr(mcsr, mfspr(mcsr)); + /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | @@ -244,7 +251,6 @@ long int initdram (int board_type) sdram_panic(INVALID_HW_CONFIG); break; } - dram_size -= 16 * 1024 * 1024; mtsdram(DDR0_07, 0x00090100); /* * TCPD=200 cycles of clock input is required to lock the DLL. @@ -283,6 +289,7 @@ long int initdram (int board_type) /* * Program tlb entries for this size (dynamic) */ + remove_tlb(CFG_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); /* @@ -291,6 +298,8 @@ long int initdram (int board_type) */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + /* Diminish RAM to initialize */ + dram_size = dram_size - 32 ; #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. -- cgit v1.1 From 07bc20560cb9d3d186cca268c05c82762e8c55ad Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Thu, 16 Aug 2007 15:16:03 +0200 Subject: PPC4xx:HCU4/5 cleanup Minor cleanups to confirm to the u-boot coding style. Some german expressions -> english. HCU5 enforces a unique IP adress for a given slot in the rack. Signed-off-by: Niklaus Giger --- board/netstal/hcu4/hcu4.c | 20 +++++++------- board/netstal/hcu5/hcu5.c | 69 +++++++++++++++++++++++++++++++++-------------- 2 files changed, 60 insertions(+), 29 deletions(-) (limited to 'board') diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 2b95604..48a3f13 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -43,7 +43,7 @@ enum { HW_GENERATION_MCU25 = 0x09, }; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); long int spd_sdram(int(read_spd)(uint addr)); #ifdef CONFIG_SPD_EEPROM @@ -121,22 +121,24 @@ int checkboard (void) printf ("HCU3: index %d\n\n", index); else if (generation == HW_GENERATION_HCU4) printf ("HCU4: index %d\n\n", index); - /* GPIO here noch nicht richtig initialisert !!! */ - sysLedSet(0); + hcu_led_set(0); for (j = 0; j < 7; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(50 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { u32 tmp = ~value; u32 *ledReg; @@ -243,9 +245,9 @@ long int fixed_hcu4_sdram (int board_type) } /*---------------------------------------------------------------------------+ - * getSerialNr + * hcu_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 hcu_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; @@ -265,7 +267,7 @@ int misc_init_r(void) char *s = getenv("ethaddr"); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = hcu_serial_number(); for (i = 0; i < 6; ++i) { gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 23df081..b9b10fd 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,10 +22,11 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -void sysLedSet(u32 value); +void hcu_led_set(u32 value); extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; @@ -41,7 +42,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083 -#define SYS_IO_ADDRESS 0xcce00000 +#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) +#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) #define DEFAULT_ETH_ADDR "ethaddr" /* ethaddr for first or etha1ddr for second ethernet */ @@ -182,11 +184,14 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_BOARD_PRE_INIT int board_pre_init(void) { return board_early_init_f(); } +#endif + int checkboard(void) { unsigned int j; @@ -211,38 +216,51 @@ int checkboard(void) printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); for (j = 0;j < 6; j++) { - sysLedSet(1 << j); + hcu_led_set(1 << j); udelay(200 * 1000); } return 0; } -u32 sysLedGet(void) +u32 hcu_led_get(void) { return in16(SYS_IO_ADDRESS) & 0x3f; } -void sysLedSet(u32 value /* value to place in LEDs */) +/*---------------------------------------------------------------------------+ + * hcu_led_set value to be placed into the LEDs (max 6 bit) + *---------------------------------------------------------------------------*/ +void hcu_led_set(u32 value) { out16(SYS_IO_ADDRESS, value); } /*---------------------------------------------------------------------------+ - * getSerialNr + * get_serial_number *---------------------------------------------------------------------------*/ -static u32 getSerialNr(void) +static u32 get_serial_number(void) { u32 *serial = (u32 *)CFG_FLASH_BASE; if (*serial == 0xffffffff) - return get_ticks(); + return 0; return *serial; } /*---------------------------------------------------------------------------+ + * hcu_get_slot + *---------------------------------------------------------------------------*/ +u32 hcu_get_slot(void) +{ + u16 *slot = (u16 *)SYS_SLOT_ADDRESS; + return (*slot) & 0x7f; +} + + +/*---------------------------------------------------------------------------+ * misc_init_r. *---------------------------------------------------------------------------*/ int misc_init_r(void) @@ -250,7 +268,7 @@ int misc_init_r(void) char *s = getenv(DEFAULT_ETH_ADDR); char *e; int i; - u32 serial = getSerialNr(); + u32 serial = get_serial_number(); unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; @@ -272,8 +290,7 @@ int misc_init_r(void) gd->bd->bi_enetaddr[2] = 0x13; gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; - /* byte[5].bit 0 must be zero */ - gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; + gd->bd->bi_enetaddr[5] = hcu_get_slot(); sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], @@ -283,6 +300,25 @@ int misc_init_r(void) setenv(DEFAULT_ETH_ADDR, ethaddr); } + /* IP-Adress update */ + { + IPaddr_t ipaddr; + char *ipstring; + + ipstring = getenv("ipaddr"); + if (ipstring == 0) + ipaddr = string_to_ip("172.25.1.99"); + else + ipaddr = string_to_ip(ipstring); + if ((ipaddr & 0xff) != (32 + hcu_get_slot())) { + char tmp[22]; + + ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot(); + ip_to_string (ipaddr, tmp); + printf("%s: enforce %s\n", __FUNCTION__, tmp); + setenv("ipaddr", tmp); + } + } #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, @@ -346,6 +382,7 @@ int misc_init_r(void) return 0; } +#if defined(CONFIG_PCI) /************************************************************************* * pci_pre_init * @@ -358,7 +395,6 @@ int misc_init_r(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -411,7 +447,6 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init @@ -421,7 +456,6 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*-------------------------------------------------------------+ @@ -478,13 +512,11 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -499,8 +531,6 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif -/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -517,9 +547,8 @@ void pci_master_init(struct pci_controller *hose) * * ************************************************************************/ -#if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */ -- cgit v1.1 From ea5877e31ed63ade948fd1293895ec23fe01472e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Aug 2007 11:01:21 -0500 Subject: Fix up some fdt issues on 8544DS It looks like we had a merge issue that duplicated a bit of code in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get the MAC address properly set in the device tree on boot for TSEC1 Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/mpc8544ds.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 8ddbb01..80822be 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -540,12 +540,5 @@ ft_board_setup(void *blob, bd_t *bd) debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); } #endif - ft_cpu_setup(blob, bd); - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } } #endif -- cgit v1.1 From d64ee908a1b525e5bb2b4cbeb5c449ad6a469666 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Aug 2007 15:05:04 -0500 Subject: Update MPC8544 DS PCI memory map The PCIe bus that the ULI M1575 is connected to has no possible way of needing more than the fixed amount of IO & Memory space needed by the ULI. So make it use far less IO & memory space and have it use the shared LAW. This free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed by each bus. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/init.S | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index ea7d54d..900c368 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -218,7 +218,7 @@ law_entry: .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) @@ -226,18 +226,17 @@ law_entry: .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) - /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region */ + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) + /* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE3_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M) + .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M) 4: entry_end -- cgit v1.1 From ab77bc547ba561c25ea34457ed17aa0b2f7c2723 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 15:39:17 -0500 Subject: ColdFire: MCF5329 Update and cleanup Signed-off-by: TsiChungLiew --- board/freescale/m5329evb/mii.c | 8 ++++---- board/freescale/m5329evb/nand.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 68dc04f..31f1510 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) #undef MII_DEBUG #undef ET_DEBUG @@ -50,7 +50,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } -#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) #include /* Make MII read/write commands for the FEC. */ @@ -134,7 +134,7 @@ uint mii_send(uint mii_cmd) return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ #if defined(CFG_DISCOVER_PHY) int mii_discover_phy(struct eth_device *dev) @@ -303,4 +303,4 @@ int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, return 0; } -#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */ +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 2272a24..fefb42e 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #include #include -- cgit v1.1 From 6706424d0bb851fb52af00cd1c3301e91ee7f2b0 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:41:06 -0500 Subject: ColdFire: cobra5272 platform for MCF52x2 update Signed-off-by: TsiChungLiew --- board/cobra5272/Makefile | 2 +- board/cobra5272/cobra5272.c | 5 +- board/cobra5272/mii.c | 303 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 306 insertions(+), 4 deletions(-) create mode 100644 board/cobra5272/mii.c (limited to 'board') diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile index cf07cf4..be704b7 100644 --- a/board/cobra5272/Makefile +++ b/board/cobra5272/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 26adb4a..86c7ee1 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -22,8 +22,7 @@ */ #include -#include -#include +#include int checkboard (void) @@ -35,7 +34,7 @@ int checkboard (void) long int initdram (int board_type) { - volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR); + volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c new file mode 100644 index 0000000..fadcbb3 --- /dev/null +++ b/board/cobra5272/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From 6cfd3c7bc813fb317ab7c0781f0d1874b1c0877c Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:43:20 -0500 Subject: ColdFire: idmr platform MCF52x2 update Signed-off-by: TsiChungLiew --- board/idmr/Makefile | 2 +- board/idmr/idmr.c | 3 +- board/idmr/mii.c | 303 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 305 insertions(+), 3 deletions(-) create mode 100644 board/idmr/mii.c (limited to 'board') diff --git a/board/idmr/Makefile b/board/idmr/Makefile index cf07cf4..be704b7 100644 --- a/board/idmr/Makefile +++ b/board/idmr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 58cdba1..081c375 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -22,8 +22,7 @@ */ #include -#include -#include +#include int checkboard (void) { puts ("Board: iDMR\n"); diff --git a/board/idmr/mii.c b/board/idmr/mii.c new file mode 100644 index 0000000..f6c63c3 --- /dev/null +++ b/board/idmr/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From a9505510bf56a9b5558248dd8b73ec9d9a1556a2 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:45:51 -0500 Subject: ColdFire: update r5200 platform for MCF52x2 Signed-off-by: TsiChungLiew --- board/r5200/Makefile | 2 +- board/r5200/mii.c | 303 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 304 insertions(+), 1 deletion(-) create mode 100644 board/r5200/mii.c (limited to 'board') diff --git a/board/r5200/Makefile b/board/r5200/Makefile index 424ab1c..2ec71ee 100644 --- a/board/r5200/Makefile +++ b/board/r5200/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/r5200/mii.c b/board/r5200/mii.c new file mode 100644 index 0000000..706c90f --- /dev/null +++ b/board/r5200/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From 870470dbf6f4bb9864e0d97aeedbc17c167c6d1c Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 19:55:10 -0500 Subject: ColdFire: Update EB+MCF-EV123 platform Signed-off-by: TsiChungLiew --- board/BuS/EB+MCF-EV123/Makefile | 2 +- board/BuS/EB+MCF-EV123/mii.c | 304 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 305 insertions(+), 1 deletion(-) create mode 100644 board/BuS/EB+MCF-EV123/mii.c (limited to 'board') diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile index ed3ac07..ceeffa7 100644 --- a/board/BuS/EB+MCF-EV123/Makefile +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o +COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c new file mode 100644 index 0000000..ebd3ed9 --- /dev/null +++ b/board/BuS/EB+MCF-EV123/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From f28e1bd9daa6de5eb33ae4822bda6b008ccb4e9e Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Wed, 15 Aug 2007 20:32:06 -0500 Subject: ColdFire: Update Freescale MCF52x2 platforms Signed-off-by: TsiChungLiew --- board/m5271evb/Makefile | 2 +- board/m5271evb/m5271evb.c | 3 +- board/m5271evb/mii.c | 303 +++++++++++++++++++++++++++++++++++++ board/m5272c3/Makefile | 2 +- board/m5272c3/m5272c3.c | 7 +- board/m5272c3/mii.c | 303 +++++++++++++++++++++++++++++++++++++ board/m5282evb/Makefile | 2 +- board/m5282evb/config.mk | 2 +- board/m5282evb/flash.c | 378 ---------------------------------------------- board/m5282evb/m5282evb.c | 61 +++++++- board/m5282evb/mii.c | 304 +++++++++++++++++++++++++++++++++++++ 11 files changed, 977 insertions(+), 390 deletions(-) create mode 100644 board/m5271evb/mii.c create mode 100644 board/m5272c3/mii.c delete mode 100644 board/m5282evb/flash.c create mode 100644 board/m5282evb/mii.c (limited to 'board') diff --git a/board/m5271evb/Makefile b/board/m5271evb/Makefile index 424ab1c..2ec71ee 100644 --- a/board/m5271evb/Makefile +++ b/board/m5271evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c index c26c91d..9caad63 100644 --- a/board/m5271evb/m5271evb.c +++ b/board/m5271evb/m5271evb.c @@ -22,8 +22,7 @@ */ #include -#include -#include +#include int checkboard (void) { puts ("Board: Freescale M5271EVB\n"); diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c new file mode 100644 index 0000000..f6c63c3 --- /dev/null +++ b/board/m5271evb/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + } else { + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile index cf07cf4..be704b7 100644 --- a/board/m5272c3/Makefile +++ b/board/m5272c3/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o flash.o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c index 0dfeaf2..6dcda4f 100644 --- a/board/m5272c3/m5272c3.c +++ b/board/m5272c3/m5272c3.c @@ -22,18 +22,17 @@ */ #include -#include -#include +#include int checkboard (void) { puts ("Board: "); - puts("MOTOROLA MCF5272C3 EVB\n"); + puts ("Freescale MCF5272C3 EVB\n"); return 0; }; long int initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR); + volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c new file mode 100644 index 0000000..fadcbb3 --- /dev/null +++ b/board/m5272c3/mii.c @@ -0,0 +1,303 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + } else { + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile index cf07cf4..2ec71ee 100644 --- a/board/m5282evb/Makefile +++ b/board/m5282evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o +COBJS = $(BOARD).o mii.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk index 8484307..0aa2361 100644 --- a/board/m5282evb/config.mk +++ b/board/m5282evb/config.mk @@ -22,4 +22,4 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x20000 +TEXT_BASE = 0xFFE00000 diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c deleted file mode 100644 index 36a7c31..0000000 --- a/board/m5282evb/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 32 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 34)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x10000 + 0x10000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0xffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index a08af68..243d6a4 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -22,14 +22,71 @@ */ #include +#include + +DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { - puts ("MOTOROLA M5272EVB Evaluation Board\n"); + puts ("Board: Freescale M5282EVB Evaluation Board\n"); return 0; } long int initdram (int board_type) { - return 0x1000000; + u32 dramsize, i, dramclk; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) + { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + MCFSDRAMC_DCR = (0 + | MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + + /* Initialize DACR0 */ + MCFSDRAMC_DACR0 = (0 + | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_32); + + /* Initialize DMR0 */ + MCFSDRAMC_DMR0 = (0 + | ((dramsize - 1) & 0xFFFC0000) + | MCFSDRAMC_DMR_V); + + /* Set IP (bit 3) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm ("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) { + asm(" nop"); + } + + /* Finish the configuration by issuing the IMRS. */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } } diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c new file mode 100644 index 0000000..ebd3ed9 --- /dev/null +++ b/board/m5282evb/mii.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + if (setclear) { + MCFGPIO_PASPAR |= 0x0F00; + MCFGPIO_PEHLPAR = CFG_PEHLPAR; + } else { + MCFGPIO_PASPAR &= 0xF0FF; + MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_AMD79C874VC "AMD79C874VC" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + strcpy(info->phy_name, + STR_ID_AMD79C874VC); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_AMD79C874VC: + printf(STR_ID_AMD79C874VC); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -- cgit v1.1 From a605aacd8324094199402816cc6d9124aba57b8d Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 05:04:31 -0500 Subject: ColdFire: Add M5249EVB platform for MCF52x2 Signed-off-by: TsiChungLiew --- board/freescale/m5249evb/Makefile | 44 +++++++++++ board/freescale/m5249evb/config.mk | 25 ++++++ board/freescale/m5249evb/m5249evb.c | 114 ++++++++++++++++++++++++++++ board/freescale/m5249evb/u-boot.lds | 146 ++++++++++++++++++++++++++++++++++++ 4 files changed, 329 insertions(+) create mode 100644 board/freescale/m5249evb/Makefile create mode 100644 board/freescale/m5249evb/config.mk create mode 100644 board/freescale/m5249evb/m5249evb.c create mode 100644 board/freescale/m5249evb/u-boot.lds (limited to 'board') diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile new file mode 100644 index 0000000..424ab1c --- /dev/null +++ b/board/freescale/m5249evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5249evb/config.mk b/board/freescale/m5249evb/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/freescale/m5249evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c new file mode 100644 index 0000000..b0bf413 --- /dev/null +++ b/board/freescale/m5249evb/m5249evb.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + + +/* Prototypes */ +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +int checkboard (void) { + ulong val; + uchar val8; + + puts ("Board: "); + puts("Freescale M5249EVB"); + val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; + printf(" (Switch=%1X)\n", val8); + + /* + * Set LED on + */ + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; + mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ + + return 0; +}; + + +long int initdram (int board_type) { + unsigned long junk = 0xa5a59696; + + /* + * Note: + * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 + */ + +#ifdef CFG_FAST_CLK + /* + * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 + */ + mbar_writeShort(MCFSIM_DCR, 0x8239); +#elif CFG_PLL_BYPASS + /* + * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 + */ + mbar_writeShort(MCFSIM_DCR, 0x8202); +#else + /* + * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) + */ + mbar_writeShort(MCFSIM_DCR, 0x8222); +#endif + + /* + * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), + * PM=1 (continuous page mode) + */ + + /* RE=0 (keep auto-refresh disabled while setting up registers) */ + mbar_writeLong(MCFSIM_DACR0, 0x00003324); + + /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ + mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); + + /** Precharge sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ + *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ + udelay(0x10); /* Allow several Precharge cycles */ + + /** Refresh Sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ + udelay(0x7d0); /* Allow gobs of refresh cycles */ + + /** Mode Register initialization **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ + *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} + diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds new file mode 100644 index 0000000..a803b1c --- /dev/null +++ b/board/freescale/m5249evb/u-boot.lds @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From a1436a842654a8d3927d082a8ae9ee0a10da62d7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 13:20:50 -0500 Subject: ColdFire: Add M5253EVBE platform for MCF52x2 Signed-off-by: TsiChungLiew --- board/freescale/m5253evbe/Makefile | 44 +++++++++++ board/freescale/m5253evbe/config.mk | 25 ++++++ board/freescale/m5253evbe/m5253evbe.c | 133 +++++++++++++++++++++++++++++++ board/freescale/m5253evbe/u-boot.lds | 144 ++++++++++++++++++++++++++++++++++ 4 files changed, 346 insertions(+) create mode 100644 board/freescale/m5253evbe/Makefile create mode 100644 board/freescale/m5253evbe/config.mk create mode 100644 board/freescale/m5253evbe/m5253evbe.c create mode 100644 board/freescale/m5253evbe/u-boot.lds (limited to 'board') diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile new file mode 100644 index 0000000..424ab1c --- /dev/null +++ b/board/freescale/m5253evbe/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk new file mode 100644 index 0000000..ccb2cf7 --- /dev/null +++ b/board/freescale/m5253evbe/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c new file mode 100644 index 0000000..67fab5b --- /dev/null +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5253 EVBE\n"); + return 0; +}; + +long int initdram(int board_type) +{ + int i; + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { + u32 RC, dramsize; + + RC = (CFG_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); + + mbar_writeLong(MCFSIM_DACR0, 0x00003224); + + /* Initialize DMR0 */ + dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; + mbar_writeLong(MCFSIM_DMR0, dramsize | 1); + + mbar_writeLong(MCFSIM_DACR0, 0x0000322c); + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + + /* Set RE bit in DACR */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x8000); + + /* Wait for at least 8 auto refresh cycles to occur */ + udelay(500); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x0040); + + *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CONFIG_CMD_IDE +#include +int ide_preinit(void) +{ + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ + }; + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(100); + } else { + mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); + +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(2000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif /* CONFIG_CMD_IDE */ + diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds new file mode 100644 index 0000000..e2fd070 --- /dev/null +++ b/board/freescale/m5253evbe/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 15:05:11 -0500 Subject: ColdFire: Add M54455EVB for MCF5445x Signed-off-by: TsiChungLiew --- board/freescale/m54455evb/Makefile | 44 ++ board/freescale/m54455evb/config.mk | 25 + board/freescale/m54455evb/flash.c | 974 ++++++++++++++++++++++++++++++++++ board/freescale/m54455evb/m54455evb.c | 165 ++++++ board/freescale/m54455evb/mii.c | 320 +++++++++++ board/freescale/m54455evb/u-boot.lds | 144 +++++ 6 files changed, 1672 insertions(+) create mode 100644 board/freescale/m54455evb/Makefile create mode 100644 board/freescale/m54455evb/config.mk create mode 100644 board/freescale/m54455evb/flash.c create mode 100644 board/freescale/m54455evb/m54455evb.c create mode 100644 board/freescale/m54455evb/mii.c create mode 100644 board/freescale/m54455evb/u-boot.lds (limited to 'board') diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile new file mode 100644 index 0000000..ca9a772 --- /dev/null +++ b/board/freescale/m54455evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### \ No newline at end of file diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m54455evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m54455evb/flash.c b/board/freescale/m54455evb/flash.c new file mode 100644 index 0000000..de2cca8 --- /dev/null +++ b/board/freescale/m54455evb/flash.c @@ -0,0 +1,974 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#ifndef CFG_FLASH_CFI +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_WRSETUP 0x00400040 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CFIQRY 0x00980098 +#define INTEL_SUSERASE 0x00B000B0 +#define INTEL_PROTPROG 0x00C000C0 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_WRBLK 0x00e800e8 +#define INTEL_RESET 0x00FF00FF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 +#define INTEL_ERASESUS 0x00600060 +#define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS) + +/* 28F160C3B CFI Data offset - This could vary */ +#define INTEL_CFI_MFG 0x00 /* Manufacturer ID */ +#define INTEL_CFI_PART 0x01 /* Product ID */ +#define INTEL_CFI_LOCK 0x02 /* */ +#define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */ +#define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */ +#define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */ +#define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */ +#define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */ +#define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */ +#define INTEL_CFI_CAP 0x28 +#define INTEL_CFI_WRBUF 0x2A +#define INTEL_CFI_BANK 0x2C /* Number of Bank */ +#define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */ +#define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */ +#define INTEL_CFI_SZ1A 0x2F /* Block Region Size */ +#define INTEL_CFI_SZ1B 0x30 +#define INTEL_CFI_BLK2A 0x31 +#define INTEL_CFI_BLK2B 0x32 +#define INTEL_CFI_SZ2A 0x33 +#define INTEL_CFI_SZ2B 0x34 + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x0aaa + +#define WR_BLOCK 0x20 + +/* not in the flash.h yet */ +#define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */ +#define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */ +#define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */ +#define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */ +#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */ +#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */ + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int flash_cmd_rd(volatile u16 * addr, int index); +int write_data(flash_info_t * info, ulong dest, FPW data); +int write_data_block(flash_info_t * info, ulong src, ulong dest); +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data); +void inline spin_wheel(void); +void flash_sync_real_protect(flash_info_t * info); +uchar intel_sector_protected(flash_info_t * info, ushort sector); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + int i; + ulong size = 0; + ulong fbase = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset(&flash_info[i], 0, sizeof(flash_info_t)); + + switch (i) { + case 0: + fbase = (ulong) CFG_FLASH0_BASE; + break; + case 1: + fbase = (ulong) CFG_FLASH1_BASE; + break; + } + + flash_get_size((FPWV *) fbase, &flash_info[i]); + flash_get_offsets((ulong) fbase, &flash_info[i]); + fbase += flash_info[i].size; + size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); + } + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int i, j, k; + int sectors, bs, banks; + ulong start; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->start[0] = base; + for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + for (j = 0; j < sect[i]; j++, k++) { + info->start[k + 1] = info->start[k] + sectsz[i]; + info->protect[k] = 0; + } + } + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + volatile u16 *addr16 = (volatile u16 *)base; + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = 0; + info->start[0] = base; + + for (k = 0, i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors = + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + + for (j = 0; j < sectors; j++, k++) { + info->start[k + 1] = info->start[k] + bs; + } + } + + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + } + + return ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf("INTEL "); + break; + case FLASH_MAN_ATM: + printf("ATMEL "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AT040: + printf("AT49BV040A\n"); + break; + case FLASH_28F128J3A: + printf("Intel 28F128J3A\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + if (info->size > 0x100000) { + int remainder; + + printf(" Size: %ld", info->size >> 20); + + remainder = (info->size % 0x100000); + if (remainder) { + remainder >>= 10; + remainder = (int)((float) + (((float)remainder / (float)1024) * + 10000)); + printf(".%d ", remainder); + } + + printf("MB in %d Sectors\n", info->sector_count); + } else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + volatile u16 *addr16 = (volatile u16 *)addr; + int intel = 0, banks = 0; + u16 value; + int i; + + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ + + switch (addr[0] & 0xff) { + case (u8) ATM_MANUFACT: + info->flash_id = FLASH_MAN_ATM; + value = addr[1]; + break; + case (u8) INTEL_MANUFACT: + /* Terminate Atmel ID read */ + addr[0] = (FPWV) 0x00F000F0; + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + *addr16 = (FPW) INTEL_RESET; /* restore read mode */ + *addr16 = (FPW) INTEL_READID; + + info->flash_id = FLASH_MAN_INTEL; + value = (addr16[INTEL_CFI_MFG] << 8); + value |= addr16[INTEL_CFI_PART] & 0xff; + intel = 1; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0x00F000F0; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u8) ATM_ID_LV040: + info->flash_id += FLASH_AT040; + break; + case (u16) INTEL_ID_28F128J3: + info->flash_id += FLASH_28F128J3A; + break; + case (u16) INTEL_ID_28F64P30T: + info->flash_id += FLASH_28F64P30T; + break; + case (u16) INTEL_ID_28F64P30B: + info->flash_id += FLASH_28F64P30B; + break; + case (u16) INTEL_ID_28F128P30T: + info->flash_id += FLASH_28F128P30T; + break; + case (u16) INTEL_ID_28F128P30B: + info->flash_id += FLASH_28F128P30B; + break; + case (u16) INTEL_ID_28F256P30T: + info->flash_id += FLASH_28F256P30T; + break; + case (u16) INTEL_ID_28F256P30B: + info->flash_id += FLASH_28F256P30B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (intel) { + /* Intel spec. under CFI section */ + u32 sz; + int sectors, bs; + + banks = addr16[INTEL_CFI_BANK] & 0xff; + + sectors = sz = 0; + for (i = 0; i < banks; i++) { + /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec. + * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count + * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count + */ + bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8) + | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) * + 0x100); + sectors += + (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1; + sz += (bs * sectors); + } + + info->sector_count = sectors; + info->size = sz; + *addr = (FPW) INTEL_RESET; /* restore read mode */ + } else { + int sect[] = CFG_ATMEL_SECT; + int sectsz[] = CFG_ATMEL_SECTSZ; + + info->sector_count = 0; + info->size = 0; + for (i = 0; i < CFG_ATMEL_REGION; i++) { + info->sector_count += sect[i]; + info->size += sect[i] * sectsz[i]; + } + + /* reset ID mode */ + addr[0] = (FPWV) 0x00F000F0; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_cmd_rd(volatile u16 * addr, int index) +{ + return (int)addr[index]; +} + +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +void flash_sync_real_protect(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +uchar intel_sector_protected(flash_info_t * info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + /*udelay(1); */ + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer(0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector]; + ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0, intel = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + + if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) { + type = (info->flash_id & FLASH_VENDMASK); + printf + ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + } + + if (type == FLASH_MAN_INTEL) + intel = 1; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + start = get_timer(0); + last = start; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + FPWV *addr = (FPWV *) (info->start[sect]); + int min = 0; + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + if (intel) { + *addr = (FPW) INTEL_READID; + min = addr[INTEL_CFI_TERB] & 0xff; + min = 1 << min; /* ms */ + min = (min / info->sector_count) * 1000; + + /* start erase block */ + *addr = (FPW) INTEL_CLEAR; /* clear status register */ + *addr = (FPW) INTEL_ERASE; /* erase setup */ + *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ + + while ((*addr & (FPW) INTEL_FINISHED) != + (FPW) INTEL_FINISHED) { + + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *addr = (FPW) INTEL_SUSERASE; /* suspend erase */ + *addr = (FPW) INTEL_RESET; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = (FPW) INTEL_RESET; /* resest to read mode */ + } else { + FPWV *base; /* first address in bank */ + FPWV *atmeladdr; + + flag = disable_interrupts(); + + atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */ + base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */ + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + *atmeladdr = (u8) 0x00300030; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*atmeladdr & (u8) 0x00800080) != + (u8) 0x00800080) { + if (get_timer(start) > + CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */ + } /* Atmel or Intel */ + } + } + printf(" done\n"); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_ATM: + { + u16 data = 0; + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= + sizeof(data) - bytes) { + + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + data = (data >> 8) | (data << 8); + res = write_word_atm(info, (FPWV *) addr, data); + } + return res; + } /* case FLASH_MAN_ATM */ + + case FLASH_MAN_INTEL: + { + ulong cp, wp; + u16 data; + int count, i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = sizeof(FPW); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = write_data(info, wp, data)) != 0) + return (rc); + + wp += port_width; + } + + if (cnt > WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= WR_BLOCK) { + + if ((rc = + write_data_block(info, + (ulong) src, + wp)) != 0) + return (rc); + + wp += WR_BLOCK; + src += WR_BLOCK; + cnt -= WR_BLOCK; + + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + /* handle word aligned part */ + if (cnt < WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) + data = (data << 8) | *src++; + + if ((rc = + write_data(info, + (ulong) ((FPWV *) wp), + (FPW) (data))) != 0) + return (rc); + + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; + ++i, ++cp) { + data = (data << 8) | (*src++); + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return write_data(info, (ulong) ((FPWV *) wp), + (FPW) data); + + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data_block(flash_info_t * info, ulong src, ulong dest) +{ + FPWV *srcaddr = (FPWV *) src; + FPWV *dstaddr = (FPWV *) dest; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < WR_BLOCK; i++) + if ((*dstaddr++ & 0xff) != 0xff) { + printf("not erased at %08lx (%lx)\n", + (ulong) dstaddr, *dstaddr); + return (2); + } + + dstaddr = (FPWV *) dest; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */ + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */ + for (i = 0; i < WR_BLOCK; i++) + *dstaddr++ = *srcaddr++; + + dstaddr -= 1; + *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_data(flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("not erased at %08lx (%lx)\n", (ulong) addr, + (ulong) * addr); + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = (int)disable_interrupts(); + + *addr = (FPW) INTEL_CLEAR; + *addr = (FPW) INTEL_RESET; + + *addr = (FPW) INTEL_WRSETUP; /* write setup */ + *addr = data; + + if (flag) + enable_interrupts(); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + /* wait while polling the status register */ + while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) INTEL_SUSERASE; /* suspend mode */ + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* reset */ + return (1); + } + } + + *addr = (FPW) INTEL_CLEAR; /* clear status */ + *addr = (FPW) INTEL_RESET; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for ATMEL FLASH + * A word is 16 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data) +{ + ulong start; + int flag, i; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16 *)dest) & data) != data) { + return (2); + } + + base = (FPWV *) (CFG_ATMEL_BASE); + + for (i = 0; i < sizeof(u16); i++) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (u8) 0x00800080) != + (data & (u8) 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (u8) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + *dest++ = (u8) 0x00F000F0; /* reset bank */ + data >>= 8; + } + + return (res); +} + +void inline spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#ifdef CFG_FLASH_PROTECTION +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t * info, long sector, int prot) +{ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ + FPW value; + + addr = (FPWV *) (info->start[sector]); + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + *addr = (FPW) INTEL_RESET; /* make sure in read mode */ + *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */ + + if (prot) + *addr = (FPW) INTEL_PROTECT; /* lock sector */ + else + *addr = (FPW) INTEL_CONFIRM; /* unlock sector */ + + /* now see if it really is locked/unlocked as requested */ + *addr = (FPW) INTEL_READID; + + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but return failure. Mixed protected and + * unprotected devices within a sector should never happen. + */ + value = addr[2] & (FPW) INTEL_PROTECT; + if (value == 0) + info->protect[sector] = 0; + else if (value == (FPW) INTEL_PROTECT) + info->protect[sector] = 1; + else { + /* error, mixed protected and unprotected */ + rcode = 1; + info->protect[sector] = 1; + } + if (info->protect[sector] != prot) + rcode = 1; /* failed to protect/unprotect as requested */ + + /* reload all protection bits from hardware for now */ + flash_sync_real_protect(info); + break; + + default: + /* no hardware protect that we support */ + info->protect[sector] = prot; + break; + } + + return rcode; +} +#endif +#endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c new file mode 100644 index 0000000..1411a1a --- /dev/null +++ b/board/freescale/m54455evb/m54455evb.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M54455 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + gpio->mscr_sdram = 0xAA; + + sdram->sdcs0 = (CFG_SDRAM_BASE | i); + sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); + + sdram->sdcfg1 = CFG_SDRAM_CFG1; + sdram->sdcfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + sdram->sdmr = CFG_SDRAM_EMOD | 0x408; + sdram->sdmr = CFG_SDRAM_MODE | 0x300; + + udelay(500); + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Perform two refresh cycles */ + sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CFG_SDRAM_CTRL | 4; + + sdram->sdmr = CFG_SDRAM_MODE | 0x200; + + sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return (dramsize << 1); +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#if defined(CONFIG_CMD_IDE) +#include + +int ide_preinit(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_feci2c |= + (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | + GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); + gpio->par_ata |= + (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 + | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | + GPIO_PAR_ATA_IORDY_IORDY); + gpio->par_pci |= + (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); + + return (0); +} + +void ide_set_reset(int idereset) +{ + volatile atac_t *ata = (atac_t *) MMAP_ATA; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { + {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} + }; /* PIO 4 */ + + if (idereset) { + ata->cr = 0; /* control reset */ + udelay(10000); + } else { +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / gd->bus_clk; /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + ata->t1 = CALC_TIMING(piotms[2][0]); + ata->t2w = CALC_TIMING(piotms[2][1]); + ata->t2r = CALC_TIMING(piotms[2][1]); + ata->ta = CALC_TIMING(piotms[2][8]); + ata->trd = CALC_TIMING(piotms[2][7]); + ata->t4 = CALC_TIMING(piotms[2][3]); + ata->t9 = CALC_TIMING(piotms[2][6]); + + ata->cr = 0x40; /* IORDY enable */ + udelay(200000); + ata->cr |= 0x01; /* IORDY enable */ + } +} +#endif + +#if defined(CONFIG_PCI) +/* + * Initialize PCI devices, report devices found. + */ +static struct pci_controller hose; +extern void pci_mcf5445x_init(struct pci_controller *hose); + +void pci_init_board(void) +{ + pci_mcf5445x_init(&hose); +} +#endif /* CONFIG_PCI */ + diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c new file mode 100644 index 0000000..c067183 --- /dev/null +++ b/board/freescale/m54455evb/mii.c @@ -0,0 +1,320 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + struct fec_info_s *info = (struct fec_info_s *)dev->priv; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + else + gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + + if (info->iobase == CFG_FEC0_IOBASE) + gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; + else + gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; + } + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + struct eth_device *dev; + int i, miispd; + u16 rst = 0; + + dev = eth_get_dev(); + + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); + for (i = 0; i < FEC_RESET_DELAY; ++i) { + udelay(500); + miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); + if ((rst & PHY_BMCR_RESET) == 0) + break; + } + if (i == FEC_RESET_DELAY) + printf("Mii reset timeout %d\n", i); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + strcpy(info->phy_name, + STR_ID_DP83848VV); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_DP83848VV: + printf(STR_ID_DP83848VV); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds new file mode 100644 index 0000000..bda68e4 --- /dev/null +++ b/board/freescale/m54455evb/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5445x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From 14778585d1389d86d5846efec29e5fce892680ce Mon Sep 17 00:00:00 2001 From: Tony Li Date: Fri, 17 Aug 2007 10:35:59 +0800 Subject: mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board. Signed-off-by Tony Li --- board/freescale/common/pq-mds-pib.c | 101 ++++++++++++++++++++++++++++++++++++ board/freescale/common/pq-mds-pib.h | 9 ++++ board/mpc832xemds/Makefile | 2 +- board/mpc832xemds/mpc832xemds.c | 11 ++++ board/mpc832xemds/pci.c | 40 -------------- board/mpc8360emds/Makefile | 2 +- board/mpc8360emds/mpc8360emds.c | 11 ++++ board/mpc8360emds/pci.c | 40 -------------- 8 files changed, 134 insertions(+), 82 deletions(-) create mode 100644 board/freescale/common/pq-mds-pib.c create mode 100644 board/freescale/common/pq-mds-pib.h (limited to 'board') diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c new file mode 100644 index 0000000..9799117 --- /dev/null +++ b/board/freescale/common/pq-mds-pib.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * Tony Li + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +#include +#include +#include + +#include "pq-mds-pib.h" + +int pib_init(void) +{ + u8 val8; + u8 orig_i2c_bus; + + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); +#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) + /* Assign PIB PMC slot to desired PCI bus */ + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(CONFIG_MPC832XEMDS) + val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ +#else + val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + eieio(); + +#if defined(CONFIG_MPC832XEMDS) + printf("PCI 32bit bus on PMC2 &PMC3\n"); +#else + printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); +#endif +#endif + +#if defined(CONFIG_PQ_MDS_PIB_ATM) +#if defined(CONFIG_MPC8360EMDS) + val8 = 0; + i2c_write(0x20, 0x6, 1, &val8, 1); + i2c_write(0x20, 0x7, 1, &val8, 1); + + val8 = 0xdf; + i2c_write(0x20, 0x2, 1, &val8, 1); + val8 = 0xf7; + i2c_write(0x20, 0x3, 1, &val8, 1); + + eieio(); + + printf("QOC3 ATM card on PMC0\n"); +#elif defined(CONFIG_MPC832XEMDS) + val = 0; + i2c_write(0x26, 0x7, 1, &val, 1); + val = 0xf7; + i2c_write(0x26, 0x3, 1, &val, 1); + + val = 0; + i2c_write(0x21, 0x6, 1, &val, 1); + i2c_write(0x21, 0x7, 1, &val, 1); + + val = 0xdf; + i2c_write(0x21, 0x2, 1, &val, 1); + val = 0xef; + i2c_write(0x21, 0x3, 1, &val, 1); + + eieio(); + + printf("QOC3 ATM card on PMC1\n"); +#endif +#endif + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); + return 0; +} diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h new file mode 100644 index 0000000..67066fd --- /dev/null +++ b/board/freescale/common/pq-mds-pib.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +extern int pib_init(void); diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile index 5ec7a87..4da74b8 100644 --- a/board/mpc832xemds/Makefile +++ b/board/mpc832xemds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c index f70783e..207fcdf 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/mpc832xemds/mpc832xemds.c @@ -32,6 +32,9 @@ #elif defined(CONFIG_OF_LIBFDT) #include #endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../freescale/common/pq-mds-pib.h" +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* ETH3 */ @@ -88,6 +91,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + int fixed_sdram(void); long int initdram(int board_type) diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c index c2f61ea..6bc35c7 100644 --- a/board/mpc832xemds/pci.c +++ b/board/mpc832xemds/pci.c @@ -131,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -200,43 +199,6 @@ void pci_init_board(void) PIWAR_IWS_2G; /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - - /* * Release PCI RST Output signal */ udelay(2000); @@ -292,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC2 & PMC3\n"); - /* * Hose scan. */ diff --git a/board/mpc8360emds/Makefile b/board/mpc8360emds/Makefile index 5ec7a87..4da74b8 100644 --- a/board/mpc8360emds/Makefile +++ b/board/mpc8360emds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index 3861733..d6d0f4e 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -30,6 +30,9 @@ #elif defined(CONFIG_OF_LIBFDT) #include #endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../freescale/common/pq-mds-pib.h" +#endif const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ @@ -106,6 +109,14 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void ddr_enable_ecc(unsigned int dram_size); #endif diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 7981285..cf7ef90 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -131,7 +131,6 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - u8 val8, orig_i2c_bus; u16 reg16; u32 val32; u32 dev; @@ -200,43 +199,6 @@ void pci_init_board(void) PIWAR_IWS_2G; /* - * Assign PIB PMC slot to desired PCI bus - */ - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - - val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - - /* * Release PCI RST Output signal */ udelay(2000); @@ -292,8 +254,6 @@ void pci_init_board(void) pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); - /* * Hose scan. */ -- cgit v1.1 From bbea46f76f767b919070b4829bf34c86bd223248 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:52:48 -0500 Subject: mpc83xx: implement board_add_ram_info add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips --- board/freescale/mpc8323erdb/mpc8323erdb.c | 2 -- board/mpc8313erdb/sdram.c | 3 --- board/mpc832xemds/mpc832xemds.c | 2 -- board/mpc8349emds/mpc8349emds.c | 8 +------- board/mpc8349itx/mpc8349itx.c | 3 +-- board/mpc8360emds/mpc8360emds.c | 5 +---- board/sbc8349/sbc8349.c | 5 +---- board/tqm834x/tqm834x.c | 4 ++-- 8 files changed, 6 insertions(+), 26 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 850d1c3..e738613 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -91,8 +91,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c index 4b67788..e6e8410 100644 --- a/board/mpc8313erdb/sdram.c +++ b/board/mpc8313erdb/sdram.c @@ -112,8 +112,6 @@ long int initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ msize = fixed_sdram(); @@ -127,7 +125,6 @@ long int initdram(int board_type) resume_from_sleep(); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return msize; } diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c index 207fcdf..7a45ded 100644 --- a/board/mpc832xemds/mpc832xemds.c +++ b/board/mpc832xemds/mpc832xemds.c @@ -114,8 +114,6 @@ long int initdram(int board_type) msize = fixed_sdram(); - puts("\n DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 2ad25ec..39c0916 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -70,8 +70,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -90,7 +88,7 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -191,9 +189,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc= &immap->lbus; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -255,7 +250,6 @@ void sdram_init(void) #else void sdram_init(void) { - puts(" SDRAM on Local Bus is NOT available!\n"); } #endif diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 125e6c0..c82f784 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -76,7 +76,7 @@ int fixed_sdram(void) im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; im->ddr.sdram_mode = (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); im->ddr.sdram_interval = @@ -162,7 +162,6 @@ long int initdram(int board_type) ddr_enable_ecc(msize * 1048576); #endif - puts(" DDR RAM: "); /* return total bus RAM size(bytes) */ return msize * 1024 * 1024; } diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index d6d0f4e..0751c6f 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -149,7 +149,7 @@ long int initdram(int board_type) * Initialize SDRAM if it is on local bus. */ sdram_init(); - puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -234,8 +234,6 @@ void sdram_init(void) volatile lbus83xx_t *lbc = &immap->lbus; uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ @@ -291,7 +289,6 @@ void sdram_init(void) #else void sdram_init(void) { - puts("SDRAM on Local Bus is NOT available!\n"); } #endif diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 4cd447e..86166ea 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -64,8 +64,6 @@ long int initdram (int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - puts("Initializing\n"); - /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) @@ -84,7 +82,6 @@ long int initdram (int board_type) */ ddr_enable_ecc(msize * 1024 * 1024); #endif - puts(" DDR RAM: "); /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); } @@ -130,7 +127,7 @@ int fixed_sdram(void) #if defined(CONFIG_DDR_2T_TIMING) | SDRAM_CFG_2T_EN #endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + | SDRAM_CFG_SDRAM_TYPE_DDR1; #if defined (CONFIG_DDR_32BIT) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 9c35e22..7d0b055 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -114,7 +114,7 @@ long int initdram (int board_type) /* enable DDR controller */ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR); + SDRAM_CFG_SDRAM_TYPE_DDR1); SYNC; /* size detection */ @@ -388,7 +388,7 @@ static void set_ddr_config(void) { /* don't enable DDR controller yet */ im->ddr.sdram_cfg = SDRAM_CFG_SREN | - SDRAM_CFG_SDRAM_TYPE_DDR; + SDRAM_CFG_SDRAM_TYPE_DDR1; SYNC; /* Set SDRAM mode */ -- cgit v1.1 From 5aa4ad8d8e7e9468219990c7875d5fdc9e962f47 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:52:59 -0500 Subject: mpc83xx: suppress unused variable 'val8' warning Signed-off-by: Kim Phillips --- board/freescale/common/pq-mds-pib.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 9799117..8c013c7 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -22,9 +22,10 @@ int pib_init(void) /* Switch temporarily to I2C bus #2 */ orig_i2c_bus = i2c_get_bus_num(); i2c_set_bus_num(1); + + val8 = 0; #if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) /* Assign PIB PMC slot to desired PCI bus */ - val8 = 0; i2c_write(0x23, 0x6, 1, &val8, 1); i2c_write(0x23, 0x7, 1, &val8, 1); val8 = 0xff; -- cgit v1.1 From e58fe95784d2514fc9c21028dc59f2b319a35d80 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:53:09 -0500 Subject: mpc83xx: move freescale boards to boards/freescale includes build fixes. Signed-off-by: Kim Phillips --- board/freescale/mpc8313erdb/Makefile | 50 ++++ board/freescale/mpc8313erdb/config.mk | 1 + board/freescale/mpc8313erdb/mpc8313erdb.c | 121 ++++++++ board/freescale/mpc8313erdb/sdram.c | 130 +++++++++ board/freescale/mpc832xemds/Makefile | 50 ++++ board/freescale/mpc832xemds/config.mk | 28 ++ board/freescale/mpc832xemds/mpc832xemds.c | 187 +++++++++++++ board/freescale/mpc832xemds/pci.c | 298 ++++++++++++++++++++ board/freescale/mpc8349emds/Makefile | 50 ++++ board/freescale/mpc8349emds/config.mk | 28 ++ board/freescale/mpc8349emds/mpc8349emds.c | 274 ++++++++++++++++++ board/freescale/mpc8349emds/pci.c | 446 ++++++++++++++++++++++++++++++ board/freescale/mpc8349itx/Makefile | 48 ++++ board/freescale/mpc8349itx/config.mk | 31 +++ board/freescale/mpc8349itx/mpc8349itx.c | 407 +++++++++++++++++++++++++++ board/freescale/mpc8349itx/pci.c | 392 ++++++++++++++++++++++++++ board/freescale/mpc8360emds/Makefile | 50 ++++ board/freescale/mpc8360emds/config.mk | 28 ++ board/freescale/mpc8360emds/mpc8360emds.c | 313 +++++++++++++++++++++ board/freescale/mpc8360emds/pci.c | 298 ++++++++++++++++++++ board/mpc8313erdb/Makefile | 50 ---- board/mpc8313erdb/config.mk | 1 - board/mpc8313erdb/mpc8313erdb.c | 121 -------- board/mpc8313erdb/sdram.c | 130 --------- board/mpc832xemds/Makefile | 50 ---- board/mpc832xemds/config.mk | 28 -- board/mpc832xemds/mpc832xemds.c | 187 ------------- board/mpc832xemds/pci.c | 298 -------------------- board/mpc8349emds/Makefile | 50 ---- board/mpc8349emds/config.mk | 28 -- board/mpc8349emds/mpc8349emds.c | 274 ------------------ board/mpc8349emds/pci.c | 446 ------------------------------ board/mpc8349itx/Makefile | 48 ---- board/mpc8349itx/config.mk | 31 --- board/mpc8349itx/mpc8349itx.c | 407 --------------------------- board/mpc8349itx/pci.c | 392 -------------------------- board/mpc8360emds/Makefile | 50 ---- board/mpc8360emds/config.mk | 28 -- board/mpc8360emds/mpc8360emds.c | 313 --------------------- board/mpc8360emds/pci.c | 298 -------------------- 40 files changed, 3230 insertions(+), 3230 deletions(-) create mode 100644 board/freescale/mpc8313erdb/Makefile create mode 100644 board/freescale/mpc8313erdb/config.mk create mode 100644 board/freescale/mpc8313erdb/mpc8313erdb.c create mode 100644 board/freescale/mpc8313erdb/sdram.c create mode 100644 board/freescale/mpc832xemds/Makefile create mode 100644 board/freescale/mpc832xemds/config.mk create mode 100644 board/freescale/mpc832xemds/mpc832xemds.c create mode 100644 board/freescale/mpc832xemds/pci.c create mode 100644 board/freescale/mpc8349emds/Makefile create mode 100644 board/freescale/mpc8349emds/config.mk create mode 100644 board/freescale/mpc8349emds/mpc8349emds.c create mode 100644 board/freescale/mpc8349emds/pci.c create mode 100644 board/freescale/mpc8349itx/Makefile create mode 100644 board/freescale/mpc8349itx/config.mk create mode 100644 board/freescale/mpc8349itx/mpc8349itx.c create mode 100644 board/freescale/mpc8349itx/pci.c create mode 100644 board/freescale/mpc8360emds/Makefile create mode 100644 board/freescale/mpc8360emds/config.mk create mode 100644 board/freescale/mpc8360emds/mpc8360emds.c create mode 100644 board/freescale/mpc8360emds/pci.c delete mode 100644 board/mpc8313erdb/Makefile delete mode 100644 board/mpc8313erdb/config.mk delete mode 100644 board/mpc8313erdb/mpc8313erdb.c delete mode 100644 board/mpc8313erdb/sdram.c delete mode 100644 board/mpc832xemds/Makefile delete mode 100644 board/mpc832xemds/config.mk delete mode 100644 board/mpc832xemds/mpc832xemds.c delete mode 100644 board/mpc832xemds/pci.c delete mode 100644 board/mpc8349emds/Makefile delete mode 100644 board/mpc8349emds/config.mk delete mode 100644 board/mpc8349emds/mpc8349emds.c delete mode 100644 board/mpc8349emds/pci.c delete mode 100644 board/mpc8349itx/Makefile delete mode 100644 board/mpc8349itx/config.mk delete mode 100644 board/mpc8349itx/mpc8349itx.c delete mode 100644 board/mpc8349itx/pci.c delete mode 100644 board/mpc8360emds/Makefile delete mode 100644 board/mpc8360emds/config.mk delete mode 100644 board/mpc8360emds/mpc8360emds.c delete mode 100644 board/mpc8360emds/pci.c (limited to 'board') diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile new file mode 100644 index 0000000..a987e510 --- /dev/null +++ b/board/freescale/mpc8313erdb/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk new file mode 100644 index 0000000..f768264 --- /dev/null +++ b/board/freescale/mpc8313erdb/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c new file mode 100644 index 0000000..861c143 --- /dev/null +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * + * Author: Scott Wood + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ +#ifndef CFG_8313ERDB_BROKEN_PMC + volatile immap_t *im = (immap_t *)CFG_IMMR; + + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + gd->flags |= GD_FLG_SILENT; +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: Freescale MPC8313ERDB\n"); + return 0; +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; +#ifndef CFG_8313ERDB_BROKEN_PMC + warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; +#endif + + mpc83xx_pci_init(1, reg, warmboot); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c new file mode 100644 index 0000000..e6e8410 --- /dev/null +++ b/board/freescale/mpc8313erdb/sdram.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * + * Authors: Nick.Spence@freescale.com + * Wilson.Lo@freescale.com + * scottwood@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +#include + +#ifndef CFG_8313ERDB_BROKEN_PMC +static void resume_from_sleep(void) +{ + DECLARE_GLOBAL_DATA_PTR; + u32 magic = *(u32 *)0; + + typedef void (*func_t)(void); + func_t resume = *(func_t *)4; + + if (magic == 0xf5153ae5) + resume(); + + gd->flags &= ~GD_FLG_SILENT; + puts("\nResume from sleep failed: bad magic word\n"); +} +#endif + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + + /* Currently we use only one CS, so disable the other bank. */ + im->ddr.cs_config[1] = 0; + + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; + else +#endif + im->ddr.sdram_cfg = CFG_SDRAM_CFG; + + im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE_2; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + sync(); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +long int initdram(int board_type) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc = &im->lbus; + u32 msize; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + sync(); + +#ifndef CFG_8313ERDB_BROKEN_PMC + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + resume_from_sleep(); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile new file mode 100644 index 0000000..ea52484 --- /dev/null +++ b/board/freescale/mpc832xemds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc832xemds/config.mk b/board/freescale/mpc832xemds/config.mk new file mode 100644 index 0000000..6c3eca7 --- /dev/null +++ b/board/freescale/mpc832xemds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC832XEMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c new file mode 100644 index 0000000..6ba25d4 --- /dev/null +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#else +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* ETH3 */ + {1, 0, 1, 0, 1}, /* TxD0 */ + {1, 1, 1, 0, 1}, /* TxD1 */ + {1, 2, 1, 0, 1}, /* TxD2 */ + {1, 3, 1, 0, 1}, /* TxD3 */ + {1, 9, 1, 0, 1}, /* TxER */ + {1, 12, 1, 0, 1}, /* TxEN */ + {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1}, /* RxD0 */ + {1, 5, 2, 0, 1}, /* RxD1 */ + {1, 6, 2, 0, 1}, /* RxD2 */ + {1, 7, 2, 0, 1}, /* RxD3 */ + {1, 8, 2, 0, 1}, /* RxER */ + {1, 10, 2, 0, 1}, /* RxDV */ + {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1}, /* COL */ + {1, 13, 2, 0, 1}, /* CRS */ + + /* ETH4 */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 20, 1, 0, 1}, /* TxD2 */ + {1, 21, 1, 0, 1}, /* TxD3 */ + {1, 27, 1, 0, 1}, /* TxER */ + {1, 30, 1, 0, 1}, /* TxEN */ + {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 24, 2, 0, 1}, /* RxD2 */ + {1, 25, 2, 0, 1}, /* RxD3 */ + {1, 26, 1, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1}, /* COL */ + {1, 31, 2, 0, 1}, /* CRS */ + + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +int board_early_init_f(void) +{ + volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; + + /* Enable flash write */ + bcsr[9] &= ~0x08; + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 128) +#warning Currenly any ddr size other than 128 is not supported +#endif + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__ ("sync"); + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + __asm__ __volatile__ ("sync"); + return msize; +} + +int checkboard(void) +{ + puts("Board: Freescale MPC832XEMDS\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c new file mode 100644 index 0000000..6bc35c7 --- /dev/null +++ b/board/freescale/mpc832xemds/pci.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/* + * PCI Configuration space access support for MPC83xx PCI Bridge + */ +#include +#include +#include +#include +#include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +#define PCI_FUNCTION_CONFIG 0x44 +#define PCI_FUNCTION_CFG_LOCK 0x20 + +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxemds_config_table[] = { + { + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, + {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif +static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxemds_config_table, +#endif + }, +}; + +/********************************************************************** + * pci_init_board() + *********************************************************************/ +void pci_init_board(void) +#ifdef CONFIG_PCISLAVE +{ + u16 reg16; + volatile immap_t *immr; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + immr = (immap_t *) CFG_IMMR; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar0 = 0x0; + pci_ctrl[0].pibar0 = 0x0; + pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_4K; + + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 &= ~PIWAR_EN; + + pci_ctrl[0].pitar2 = 0x0; + pci_ctrl[0].pibar2 = 0x0; + pci_ctrl[0].piebar2 = 0x0; + pci_ctrl[0].piwar2 &= ~PIWAR_EN; + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + reg16 = 0xff; + + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), + PCI_LATENCY_TIMER, 0x80); + + /* + * Unlock configuration lock in PCI function configuration register. + */ + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, ®16); + reg16 &= ~(PCI_FUNCTION_CFG_LOCK); + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, reg16); + + printf("Enabled PCI 32bit Agent Mode\n"); +} +#else +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + u16 reg16; + u32 val32; + u32 dev; + + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + val32 = clk->occr; + udelay(2000); +#if defined(PCI_66M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#elif defined(PCI_33M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | + OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; + printf("PCI clock is 33MHz\n"); +#else + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#endif + udelay(2000); + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = + POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI mmio - non-prefetch mem space */ + pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI IO space */ + pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + PIWAR_IWS_2G; + + /* + * Release PCI RST Output signal + */ + udelay(2000); + pci_ctrl[0].gcr = 1; + udelay(2000); + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose[0].regions + 0, + CFG_PCI_MEM_BASE, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose[0].regions + 1, + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose[0].regions + 2, + CFG_PCI_IO_BASE, + CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose[0].regions + 3, + CFG_PCI_SLV_MEM_LOCAL, + CFG_PCI_SLV_MEM_BUS, + CFG_PCI_SLV_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose[0].region_count = 4; + + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write command register + */ + reg16 = 0xff; + dev = PCI_BDF(0, 0, 0); + pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCISLAVE */ + +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +} +#elif defined(CONFIG_OF_FLAT_TREE) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = hose[0].first_busno; + p[1] = hose[0].last_busno; + } +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile new file mode 100644 index 0000000..5ec7a87 --- /dev/null +++ b/board/freescale/mpc8349emds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8349emds/config.mk b/board/freescale/mpc8349emds/config.mk new file mode 100644 index 0000000..edf64d1 --- /dev/null +++ b/board/freescale/mpc8349emds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8349EMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c new file mode 100644 index 0000000..39c0916 --- /dev/null +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_SPD_EEPROM) +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + +int fixed_sdram(void); +void sdram_init(void); + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) +void ddr_enable_ecc(unsigned int dram_size); +#endif + +int board_early_init_f (void) +{ + volatile u8* bcsr = (volatile u8*)CFG_BCSR; + + /* Enable flash write */ + bcsr[1] &= ~0x01; + +#ifdef CFG_USE_MPC834XSYS_USB_PHY + /* Use USB PHY on SYS board */ + bcsr[5] |= 0x02; +#endif + + return 0; +} + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; + im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else + im->ddr.csbnds[2].csbnds = 0x0000000f; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + + /* currently we use only one CS, so disable the other banks */ + im->ddr.cs_config[0] = 0; + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[3] = 0; + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; +#if defined (CONFIG_DDR_32BIT) + /* for 32-bit mode burst length is 8 */ + im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +#endif + im->ddr.sdram_mode = CFG_DDR_MODE; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Freescale MPC8349EMDS\n"); + return 0; +} + +/* + * if MPC8349EMDS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /* setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733; mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void sdram_init(void) +{ +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c new file mode 100644 index 0000000..ae94a2f --- /dev/null +++ b/board/freescale/mpc8349emds/pci.c @@ -0,0 +1,446 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_PCI + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349emds_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + } +}; + +/************************************************************************** + * + * pib_init() -- initialize the PCA9555PW IO expander on the PIB board + * + */ +void +pib_init(void) +{ + u8 val8, orig_i2c_bus; + /* + * Assign PIB PMC slot to desired PCI bus + */ + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(PCI_64BIT) + val8 = 0xf4; /* PMC2:PCI1/64-bit */ +#elif defined(PCI_ALL_PCI1) + val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ +#elif defined(PCI_ONE_PCI1) + val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ +#else + val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + asm("eieio"); + +#if defined(PCI_64BIT) + printf("PCI1: 64-bit on PMC2\n"); +#elif defined(PCI_ALL_PCI1) + printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); +#elif defined(PCI_ONE_PCI1) + printf("PCI1: 32-bit on PMC1\n"); + printf("PCI2: 32-bit on PMC2, PMC3\n"); +#else + printf("PCI1: 32-bit on PMC1, PMC2\n"); + printf("PCI2: 32-bit on PMC3\n"); +#endif + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); +} + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not currently supported + * + */ +void +pci_init_board(void) +{ + volatile immap_t * immr; + volatile clk83xx_t * clk; + volatile law83xx_t * pci_law; + volatile pot83xx_t * pci_pot; + volatile pcictrl83xx_t * pci_ctrl; + volatile pciconf83xx_t * pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller * hose; + + immr = (immap_t *)CFG_IMMR; + clk = (clk83xx_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + pib_init(); + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + clk->occr = 0xff000000; + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; ++i) + udelay (1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, + CFG_PCI1_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR+0x8300), + (CFG_IMMR+0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, + CFG_PCI2_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR+0x8380), + (CFG_IMMR+0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif + +} + +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC83XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile new file mode 100644 index 0000000..31bcdb8 --- /dev/null +++ b/board/freescale/mpc8349itx/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8349itx/config.mk b/board/freescale/mpc8349itx/config.mk new file mode 100644 index 0000000..79f1765 --- /dev/null +++ b/board/freescale/mpc8349itx/config.mk @@ -0,0 +1,31 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8349E-mITX and MPC8349E-mITX-GP +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFEF00000 +endif diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c new file mode 100644 index 0000000..c82f784 --- /dev/null +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -0,0 +1,407 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PCI +#include +#include +#endif + +#ifdef CONFIG_SPD_EEPROM +#include +#else +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + +#ifndef CONFIG_SPD_EEPROM +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 ddr_size; /* The size of RAM, in bytes */ + u32 ddr_size_log2 = 0; + + for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { + if (ddr_size & 1) { + return -1; + } + ddr_size_log2++; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; + + /* Only one CS0 for DDR */ + im->ddr.csbnds[0].csbnds = 0x0000000f; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + + debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); + debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); + + debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); + debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; + im->ddr.sdram_mode = + (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); + im->ddr.sdram_interval = + (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << + SDRAM_INTERVAL_BSTOPRE_SHIFT); + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); + debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); + debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); + debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); + + return CFG_DDR_SIZE; +} +#endif + +#ifdef CONFIG_PCI +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxmitx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + 0x0f, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; +#ifdef CONFIG_DDR_ECC + volatile ddr83xx_t *ddr = &im->ddr; +#endif + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#ifdef CONFIG_SPD_EEPROM + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#ifdef CONFIG_DDR_ECC + if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) + /* Unlike every other board, on the 83xx spd_sdram() returns + megabytes instead of just bytes. That's why we need to + multiple by 1MB when calling ddr_enable_ecc(). */ + ddr_enable_ecc(msize * 1048576); +#endif + + /* return total bus RAM size(bytes) */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ +#ifdef CONFIG_MPC8349ITX + puts("Board: Freescale MPC8349E-mITX\n"); +#else + puts("Board: Freescale MPC8349E-mITX-GP\n"); +#endif + + return 0; +} + +/* + * Implement a work-around for a hardware problem with compact + * flash. + * + * Program the UPM if compact flash is enabled. + */ +int misc_init_f(void) +{ +#ifdef CONFIG_VSC7385 + volatile u32 *vsc7385_cpuctrl; + + /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up + default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That + means it is 0 when the IRQ is not active. This makes the wire-AND + logic always assert IRQ7 to CPU even if there is no request from the + switch. Since the compact flash and the switch share the same IRQ, + the Linux kernel will think that the compact flash is requesting irq + and get stuck when it tries to clear the IRQ. Thus we need to set + the L2_IRQ0 and L2_IRQ1 to active low. + + The following code sets the L1_IRQ and L2_IRQ polarity to active low. + Without this code, compact flash will not work in Linux because + unlike U-Boot, Linux uses the IRQ, so this code is necessary if we + don't enable compact flash for U-Boot. + */ + + vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); + *vsc7385_cpuctrl |= 0x0c; +#endif + +#ifdef CONFIG_COMPACT_FLASH + /* UPM Table Configuration Code */ + static uint UPMATable[] = { + 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, + 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, + 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 + }; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbus = &immap->lbus; + + lbus->bank[3].br = CFG_BR3_PRELIM; + lbus->bank[3].or = CFG_OR3_PRELIM; + + /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, + GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 + */ + lbus->mamr = 0x08404440; + + upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); + + puts("UPMA: Configured for compact flash\n"); +#endif + + return 0; +} + +/* + * Make sure the EEPROM has the HRCW correctly programmed. + * Make sure the RTC is correctly programmed. + * + * The MPC8349E-mITX can be configured to load the HRCW from + * EEPROM instead of flash. This is controlled via jumpers + * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all + * jumpered), but if they're set to 001 or 010, then the HRCW is + * read from the "I2C EEPROM". + * + * This function makes sure that the I2C EEPROM is programmed + * correctly. + */ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_HARD_I2C + + unsigned int orig_bus = i2c_get_bus_num(); + u8 i2c_data; + +#ifdef CFG_I2C_RTC_ADDR + u8 ds1339_data[17]; +#endif + +#ifdef CFG_I2C_EEPROM_ADDR + static u8 eeprom_data[] = /* HRCW data */ + { + 0xAA, 0x55, 0xAA, /* Preamble */ + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ + (CFG_HRCW_LOW >> 24) & 0xFF, + (CFG_HRCW_LOW >> 16) & 0xFF, + (CFG_HRCW_LOW >> 8) & 0xFF, + CFG_HRCW_LOW & 0xFF, + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ + (CFG_HRCW_HIGH >> 24) & 0xFF, + (CFG_HRCW_HIGH >> 16) & 0xFF, + (CFG_HRCW_HIGH >> 8) & 0xFF, + CFG_HRCW_HIGH & 0xFF + }; + + u8 data[sizeof(eeprom_data)]; +#endif + + printf("Board revision: "); + i2c_set_bus_num(1); + if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else { + printf("Unknown\n"); + rc = 1; + } + +#ifdef CFG_I2C_EEPROM_ADDR + i2c_set_bus_num(0); + + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { + if (memcmp(data, eeprom_data, sizeof(data)) != 0) { + if (i2c_write + (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, + sizeof(eeprom_data)) != 0) { + puts("Failure writing the HRCW to EEPROM via I2C.\n"); + rc = 1; + } + } + } else { + puts("Failure reading the HRCW from EEPROM via I2C.\n"); + rc = 1; + } +#endif + +#ifdef CFG_I2C_RTC_ADDR + i2c_set_bus_num(1); + + if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) + == 0) { + + /* Work-around for MPC8349E-mITX bug #13601. + If the RTC does not contain valid register values, the DS1339 + Linux driver will not work. + */ + + /* Make sure status register bits 6-2 are zero */ + ds1339_data[0x0f] &= ~0x7c; + + /* Check for a valid day register value */ + ds1339_data[0x03] &= ~0xf8; + if (ds1339_data[0x03] == 0) { + ds1339_data[0x03] = 1; + } + + /* Check for a valid date register value */ + ds1339_data[0x04] &= ~0xc0; + if ((ds1339_data[0x04] == 0) || + ((ds1339_data[0x04] & 0x0f) > 9) || + (ds1339_data[0x04] >= 0x32)) { + ds1339_data[0x04] = 1; + } + + /* Check for a valid month register value */ + ds1339_data[0x05] &= ~0x60; + + if ((ds1339_data[0x05] == 0) || + ((ds1339_data[0x05] & 0x0f) > 9) || + ((ds1339_data[0x05] >= 0x13) + && (ds1339_data[0x05] <= 0x19))) { + ds1339_data[0x05] = 1; + } + + /* Enable Oscillator and rate select */ + ds1339_data[0x0e] = 0x1c; + + /* Work-around for MPC8349E-mITX bug #13330. + Ensure that the RTC control register contains the value 0x1c. + This affects SATA performance. + */ + + if (i2c_write + (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, + sizeof(ds1339_data))) { + puts("Failure writing to the RTC via I2C.\n"); + rc = 1; + } + } else { + puts("Failure reading from the RTC via I2C.\n"); + rc = 1; + } +#endif + + i2c_set_bus_num(orig_bus); +#endif + + return rc; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c new file mode 100644 index 0000000..5ca094d --- /dev/null +++ b/board/freescale/mpc8349itx/pci.c @@ -0,0 +1,392 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include +#include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349itx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_IDSEL_NUMBER, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349itx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349itx_config_table, +#endif + } +}; + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not currently supported + * + */ +void pci_init_board(void) +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + u8 reg8; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller *hose; + + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + +#ifdef CONFIG_HARD_I2C + i2c_set_bus_num(1); + /* Read the PCI_M66EN jumper setting */ + if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || + (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { + if (reg8 & I2C_8574_PCI66) + clk->occr = 0xff000000; /* 66 MHz PCI */ + else + clk->occr = 0xff600001; /* 33 MHz PCI */ + } else { + clk->occr = 0xff600001; /* 33 MHz PCI */ + } +#else + clk->occr = 0xff000000; /* 66 MHz PCI */ +#endif + + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; i++) + udelay(1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif +} + +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#ifdef CONFIG_MPC83XX_PCI2 + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +#endif +} +#elif defined(CONFIG_OF_FLAT_TREE) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC83XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile new file mode 100644 index 0000000..ea52484 --- /dev/null +++ b/board/freescale/mpc8360emds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8360emds/config.mk b/board/freescale/mpc8360emds/config.mk new file mode 100644 index 0000000..9ace886 --- /dev/null +++ b/board/freescale/mpc8360emds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8360EMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c new file mode 100644 index 0000000..e050cd4 --- /dev/null +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -0,0 +1,313 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#else +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif +#if defined(CONFIG_PQ_MDS_PIB) +#include "../common/pq-mds-pib.h" +#endif + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {0, 3, 1, 0, 1}, /* TxD0 */ + {0, 4, 1, 0, 1}, /* TxD1 */ + {0, 5, 1, 0, 1}, /* TxD2 */ + {0, 6, 1, 0, 1}, /* TxD3 */ + {1, 6, 1, 0, 3}, /* TxD4 */ + {1, 7, 1, 0, 1}, /* TxD5 */ + {1, 9, 1, 0, 2}, /* TxD6 */ + {1, 10, 1, 0, 2}, /* TxD7 */ + {0, 9, 2, 0, 1}, /* RxD0 */ + {0, 10, 2, 0, 1}, /* RxD1 */ + {0, 11, 2, 0, 1}, /* RxD2 */ + {0, 12, 2, 0, 1}, /* RxD3 */ + {0, 13, 2, 0, 1}, /* RxD4 */ + {1, 1, 2, 0, 2}, /* RxD5 */ + {1, 0, 2, 0, 2}, /* RxD6 */ + {1, 4, 2, 0, 2}, /* RxD7 */ + {0, 7, 1, 0, 1}, /* TX_EN */ + {0, 8, 1, 0, 1}, /* TX_ER */ + {0, 15, 2, 0, 1}, /* RX_DV */ + {0, 16, 2, 0, 1}, /* RX_ER */ + {0, 0, 2, 0, 1}, /* RX_CLK */ + {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + /* GETH2 */ + {0, 17, 1, 0, 1}, /* TxD0 */ + {0, 18, 1, 0, 1}, /* TxD1 */ + {0, 19, 1, 0, 1}, /* TxD2 */ + {0, 20, 1, 0, 1}, /* TxD3 */ + {1, 2, 1, 0, 1}, /* TxD4 */ + {1, 3, 1, 0, 2}, /* TxD5 */ + {1, 5, 1, 0, 3}, /* TxD6 */ + {1, 8, 1, 0, 3}, /* TxD7 */ + {0, 23, 2, 0, 1}, /* RxD0 */ + {0, 24, 2, 0, 1}, /* RxD1 */ + {0, 25, 2, 0, 1}, /* RxD2 */ + {0, 26, 2, 0, 1}, /* RxD3 */ + {0, 27, 2, 0, 1}, /* RxD4 */ + {1, 12, 2, 0, 2}, /* RxD5 */ + {1, 13, 2, 0, 3}, /* RxD6 */ + {1, 11, 2, 0, 2}, /* RxD7 */ + {0, 21, 1, 0, 1}, /* TX_EN */ + {0, 22, 1, 0, 1}, /* TX_ER */ + {0, 29, 2, 0, 1}, /* RX_DV */ + {0, 30, 2, 0, 1}, /* RX_ER */ + {0, 31, 2, 0, 1}, /* RX_CLK */ + {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ + {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ + + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +int board_early_init_f(void) +{ + + u8 *bcsr = (u8 *)CFG_BCSR; + const immap_t *immr = (immap_t *)CFG_IMMR; + + /* Enable flash write */ + bcsr[0xa] &= ~0x04; + + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ + if (immr->sysconf.spridr == SPR_8360_REV20 || + immr->sysconf.spridr == SPR_8360E_REV20 || + immr->sysconf.spridr == SPR_8360_REV21 || + immr->sysconf.spridr == SPR_8360E_REV21) + bcsr[0xe] = 0x30; + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_PQ_MDS_PIB + pib_init(); +#endif + return 0; +} + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif +int fixed_sdram(void); +void sdram_init(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* + * Initialize DDR ECC byte + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else + im->ddr.csbnds[0].csbnds = 0x00000007; + im->ddr.csbnds[1].csbnds = 0x0008000f; + + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[1] = CFG_DDR_CONFIG; + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.sdram_cfg = CFG_DDR_CONTROL; + + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif + udelay(200); + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} +#endif /*!CFG_SPD_EEPROM */ + +int checkboard(void) +{ + puts("Board: Freescale MPC8360EMDS\n"); + return 0; +} + +/* + * if MPC8360EMDS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc = &immap->lbus; + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + /*setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ + lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + /* + * We need do 8 times auto refresh operation. + */ + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + *sdram_addr = 0xff; /* 1 times */ + udelay(100); + *sdram_addr = 0xff; /* 2 times */ + udelay(100); + *sdram_addr = 0xff; /* 3 times */ + udelay(100); + *sdram_addr = 0xff; /* 4 times */ + udelay(100); + *sdram_addr = 0xff; /* 5 times */ + udelay(100); + *sdram_addr = 0xff; /* 6 times */ + udelay(100); + *sdram_addr = 0xff; /* 7 times */ + udelay(100); + *sdram_addr = 0xff; /* 8 times */ + udelay(100); + + /* Mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *(sdram_addr + 0xcc) = 0xff; + udelay(100); + + /* Normal operation */ + lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void sdram_init(void) +{ +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_OF_FLAT_TREE) + u32 *p; + int len; + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +#endif + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c new file mode 100644 index 0000000..cf7ef90 --- /dev/null +++ b/board/freescale/mpc8360emds/pci.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/* + * PCI Configuration space access support for MPC83xx PCI Bridge + */ +#include +#include +#include +#include +#include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#elif defined(CONFIG_OF_LIBFDT) +#include +#endif + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +#define PCI_FUNCTION_CONFIG 0x44 +#define PCI_FUNCTION_CFG_LOCK 0x20 + +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxemds_config_table[] = { + { + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, + {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif +static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxemds_config_table, +#endif + }, +}; + +/********************************************************************** + * pci_init_board() + *********************************************************************/ +void pci_init_board(void) +#ifdef CONFIG_PCISLAVE +{ + u16 reg16; + volatile immap_t *immr; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + immr = (immap_t *) CFG_IMMR; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar0 = 0x0; + pci_ctrl[0].pibar0 = 0x0; + pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_4K; + + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 &= ~PIWAR_EN; + + pci_ctrl[0].pitar2 = 0x0; + pci_ctrl[0].pibar2 = 0x0; + pci_ctrl[0].piebar2 = 0x0; + pci_ctrl[0].piwar2 &= ~PIWAR_EN; + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + reg16 = 0xff; + + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), + PCI_LATENCY_TIMER, 0x80); + + /* + * Unlock configuration lock in PCI function configuration register. + */ + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, ®16); + reg16 &= ~(PCI_FUNCTION_CFG_LOCK); + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, reg16); + + printf("Enabled PCI 32bit Agent Mode\n"); +} +#else +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + u16 reg16; + u32 val32; + u32 dev; + + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + val32 = clk->occr; + udelay(2000); +#if defined(PCI_66M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#elif defined(PCI_33M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | + OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; + printf("PCI clock is 33MHz\n"); +#else + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#endif + udelay(2000); + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = + POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI mmio - non-prefetch mem space */ + pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI IO space */ + pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + PIWAR_IWS_2G; + + /* + * Release PCI RST Output signal + */ + udelay(2000); + pci_ctrl[0].gcr = 1; + udelay(2000); + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose[0].regions + 0, + CFG_PCI_MEM_BASE, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose[0].regions + 1, + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose[0].regions + 2, + CFG_PCI_IO_BASE, + CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose[0].regions + 3, + CFG_PCI_SLV_MEM_LOCAL, + CFG_PCI_SLV_MEM_BUS, + CFG_PCI_SLV_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose[0].region_count = 4; + + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write command register + */ + reg16 = 0xff; + dev = PCI_BDF(0, 0, 0); + pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCISLAVE */ + +#if defined(CONFIG_OF_LIBFDT) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int nodeoffset; + int err; + int tmp[2]; + + nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); + if (nodeoffset >= 0) { + tmp[0] = cpu_to_be32(hose[0].first_busno); + tmp[1] = cpu_to_be32(hose[0].last_busno); + err = fdt_setprop(blob, nodeoffset, "bus-range", + tmp, sizeof(tmp)); + + tmp[0] = cpu_to_be32(gd->pci_clk); + err = fdt_setprop(blob, nodeoffset, "clock-frequency", + tmp, sizeof(tmp[0])); + } +} +#elif defined(CONFIG_OF_FLAT_TREE) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = hose[0].first_busno; + p[1] = hose[0].last_busno; + } +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc8313erdb/Makefile b/board/mpc8313erdb/Makefile deleted file mode 100644 index a987e510..0000000 --- a/board/mpc8313erdb/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o sdram.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpc8313erdb/config.mk b/board/mpc8313erdb/config.mk deleted file mode 100644 index f768264..0000000 --- a/board/mpc8313erdb/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0xFE000000 diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/mpc8313erdb/mpc8313erdb.c deleted file mode 100644 index 861c143..0000000 --- a/board/mpc8313erdb/mpc8313erdb.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * - * Author: Scott Wood - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ -#ifndef CFG_8313ERDB_BROKEN_PMC - volatile immap_t *im = (immap_t *)CFG_IMMR; - - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - gd->flags |= GD_FLG_SILENT; -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: Freescale MPC8313ERDB\n"); - return 0; -} - -static struct pci_region pci_regions[] = { - { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - struct pci_region *reg[] = { pci_regions }; - int warmboot; - - /* Enable all 3 PCI_CLK_OUTPUTs. */ - clk->occr |= 0xe0000000; - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; -#ifndef CFG_8313ERDB_BROKEN_PMC - warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; -#endif - - mpc83xx_pci_init(1, reg, warmboot); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/mpc8313erdb/sdram.c b/board/mpc8313erdb/sdram.c deleted file mode 100644 index e6e8410..0000000 --- a/board/mpc8313erdb/sdram.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 - * - * Authors: Nick.Spence@freescale.com - * Wilson.Lo@freescale.com - * scottwood@freescale.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include -#include - -#include - -#ifndef CFG_8313ERDB_BROKEN_PMC -static void resume_from_sleep(void) -{ - DECLARE_GLOBAL_DATA_PTR; - u32 magic = *(u32 *)0; - - typedef void (*func_t)(void); - func_t resume = *(func_t *)4; - - if (magic == 0xf5153ae5) - resume(); - - gd->flags &= ~GD_FLG_SILENT; - puts("\nResume from sleep failed: bad magic word\n"); -} -#endif - -/* Fixed sdram init -- doesn't use serial presence detect. - * - * This is useful for faster booting in configs where the RAM is unlikely - * to be changed, or for things like NAND booting where space is tight. - */ -static long fixed_sdram(void) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; - - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - udelay(50000); - - im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - - /* Currently we use only one CS, so disable the other bank. */ - im->ddr.cs_config[1] = 0; - - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - -#ifndef CFG_8313ERDB_BROKEN_PMC - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; - else -#endif - im->ddr.sdram_cfg = CFG_SDRAM_CFG; - - im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE_2; - - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - sync(); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} - -long int initdram(int board_type) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc = &im->lbus; - u32 msize; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - msize = fixed_sdram(); - - /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - sync(); - -#ifndef CFG_8313ERDB_BROKEN_PMC - if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - resume_from_sleep(); -#endif - - /* return total bus SDRAM size(bytes) -- DDR */ - return msize; -} diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile deleted file mode 100644 index 4da74b8..0000000 --- a/board/mpc832xemds/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpc832xemds/config.mk b/board/mpc832xemds/config.mk deleted file mode 100644 index 6c3eca7..0000000 --- a/board/mpc832xemds/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC832XEMDS -# - -TEXT_BASE = 0xFE000000 diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c deleted file mode 100644 index 7a45ded..0000000 --- a/board/mpc832xemds/mpc832xemds.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * Dave Liu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_PCI) -#include -#endif -#if defined(CONFIG_SPD_EEPROM) -#include -#else -#include -#endif -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif -#if defined(CONFIG_PQ_MDS_PIB) -#include "../freescale/common/pq-mds-pib.h" -#endif - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* ETH3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ - - /* ETH4 */ - {1, 18, 1, 0, 1}, /* TxD0 */ - {1, 19, 1, 0, 1}, /* TxD1 */ - {1, 20, 1, 0, 1}, /* TxD2 */ - {1, 21, 1, 0, 1}, /* TxD3 */ - {1, 27, 1, 0, 1}, /* TxER */ - {1, 30, 1, 0, 1}, /* TxEN */ - {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ - - {1, 22, 2, 0, 1}, /* RxD0 */ - {1, 23, 2, 0, 1}, /* RxD1 */ - {1, 24, 2, 0, 1}, /* RxD2 */ - {1, 25, 2, 0, 1}, /* RxD3 */ - {1, 26, 1, 0, 1}, /* RxER */ - {1, 28, 2, 0, 1}, /* Rx_DV */ - {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ - {1, 29, 2, 0, 1}, /* COL */ - {1, 31, 2, 0, 1}, /* CRS */ - - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -int board_early_init_f(void) -{ - volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; - - /* Enable flash write */ - bcsr[9] &= ~0x08; - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - return 0; -} - -int fixed_sdram(void); - -long int initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; - - msize = fixed_sdram(); - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 128) -#warning Currenly any ddr size other than 128 is not supported -#endif - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - __asm__ __volatile__ ("sync"); - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - __asm__ __volatile__ ("sync"); - return msize; -} - -int checkboard(void) -{ - puts("Board: Freescale MPC832XEMDS\n"); - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c deleted file mode 100644 index 6bc35c7..0000000 --- a/board/mpc832xemds/pci.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/* - * PCI Configuration space access support for MPC83xx PCI Bridge - */ -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_PCI) -#define PCI_FUNCTION_CONFIG 0x44 -#define PCI_FUNCTION_CFG_LOCK 0x20 - -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxemds_config_table[] = { - { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif -static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxemds_config_table, -#endif - }, -}; - -/********************************************************************** - * pci_init_board() - *********************************************************************/ -void pci_init_board(void) -#ifdef CONFIG_PCISLAVE -{ - u16 reg16; - volatile immap_t *immr; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; - - immr = (immap_t *) CFG_IMMR; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar0 = 0x0; - pci_ctrl[0].pibar0 = 0x0; - pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_4K; - - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 &= ~PIWAR_EN; - - pci_ctrl[0].pitar2 = 0x0; - pci_ctrl[0].pibar2 = 0x0; - pci_ctrl[0].piebar2 = 0x0; - pci_ctrl[0].piwar2 &= ~PIWAR_EN; - - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); - reg16 = 0xff; - - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), - PCI_LATENCY_TIMER, 0x80); - - /* - * Unlock configuration lock in PCI function configuration register. - */ - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, ®16); - reg16 &= ~(PCI_FUNCTION_CFG_LOCK); - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, reg16); - - printf("Enabled PCI 32bit Agent Mode\n"); -} -#else -{ - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; - - u16 reg16; - u32 val32; - u32 dev; - - immr = (immap_t *) CFG_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); -#if defined(PCI_66M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#elif defined(PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - udelay(2000); - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI IO space */ - pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - PIWAR_IWS_2G; - - /* - * Release PCI RST Output signal - */ - udelay(2000); - pci_ctrl[0].gcr = 1; - udelay(2000); - - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose[0].regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose[0].regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose[0].regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose[0].regions + 3, - CFG_PCI_SLV_MEM_LOCAL, - CFG_PCI_SLV_MEM_BUS, - CFG_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose[0].region_count = 4; - - pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write command register - */ - reg16 = 0xff; - dev = PCI_BDF(0, 0, 0); - pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCISLAVE */ - -#if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int err; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = hose[0].first_busno; - p[1] = hose[0].last_busno; - } -} -#endif /* CONFIG_OF_FLAT_TREE */ -#endif /* CONFIG_PCI */ diff --git a/board/mpc8349emds/Makefile b/board/mpc8349emds/Makefile deleted file mode 100644 index 5ec7a87..0000000 --- a/board/mpc8349emds/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o pci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpc8349emds/config.mk b/board/mpc8349emds/config.mk deleted file mode 100644 index edf64d1..0000000 --- a/board/mpc8349emds/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC8349EMDS -# - -TEXT_BASE = 0xFE000000 diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c deleted file mode 100644 index 39c0916..0000000 --- a/board/mpc8349emds/mpc8349emds.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_SPD_EEPROM) -#include -#endif -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif - -int fixed_sdram(void); -void sdram_init(void); - -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) -void ddr_enable_ecc(unsigned int dram_size); -#endif - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CFG_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - -#ifdef CFG_USE_MPC834XSYS_USB_PHY - /* Use USB PHY on SYS board */ - bcsr[5] |= 0x02; -#endif - - return 0; -} - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) - -long int initdram (int board_type) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - -#if (CFG_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#ifdef CONFIG_DDR_II - im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; - im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; -#else - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.cs_config[0] = 0; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - - im->ddr.sdram_cfg = - SDRAM_CFG_SREN -#if defined(CONFIG_DDR_2T_TIMING) - | SDRAM_CFG_2T_EN -#endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; -#if defined (CONFIG_DDR_32BIT) - /* for 32-bit mode burst length is 8 */ - im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); -#endif - im->ddr.sdram_mode = CFG_DDR_MODE; - - im->ddr.sdram_interval = CFG_DDR_INTERVAL; -#endif - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return msize; -} -#endif/*!CFG_SPD_EEPROM*/ - - -int checkboard (void) -{ - puts("Board: Freescale MPC8349EMDS\n"); - return 0; -} - -/* - * if MPC8349EMDS is soldered with SDRAM - */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733; mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void sdram_init(void) -{ -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c deleted file mode 100644 index ae94a2f..0000000 --- a/board/mpc8349emds/pci.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif - - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_PCI - -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349emds_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } - }, - {} -}; -#endif - -static struct pci_controller pci_hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - } -}; - -/************************************************************************** - * - * pib_init() -- initialize the PCA9555PW IO expander on the PIB board - * - */ -void -pib_init(void) -{ - u8 val8, orig_i2c_bus; - /* - * Assign PIB PMC slot to desired PCI bus - */ - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(PCI_64BIT) - val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(PCI_ALL_PCI1) - val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(PCI_ONE_PCI1) - val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ -#else - val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ -#endif - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - -#if defined(PCI_64BIT) - printf("PCI1: 64-bit on PMC2\n"); -#elif defined(PCI_ALL_PCI1) - printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(PCI_ONE_PCI1) - printf("PCI1: 32-bit on PMC1\n"); - printf("PCI2: 32-bit on PMC2, PMC3\n"); -#else - printf("PCI1: 32-bit on PMC1, PMC2\n"); - printf("PCI2: 32-bit on PMC3\n"); -#endif - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); -} - -/************************************************************************** - * pci_init_board() - * - * NOTICE: PCI2 is not currently supported - * - */ -void -pci_init_board(void) -{ - volatile immap_t * immr; - volatile clk83xx_t * clk; - volatile law83xx_t * pci_law; - volatile pot83xx_t * pci_pot; - volatile pcictrl83xx_t * pci_ctrl; - volatile pciconf83xx_t * pci_conf; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller * hose; - - immr = (immap_t *)CFG_IMMR; - clk = (clk83xx_t *)&immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; - - pib_init(); - - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); - clk->occr = 0xff000000; - udelay(2000); - - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; - udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - - for (i = 0; i < 1000; ++i) - udelay (1000); - } - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, - CFG_PCI1_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, - CFG_PCI2_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8380), - (CFG_IMMR+0x8384)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -#endif - -} - -#if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int err; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -#ifdef CONFIG_MPC83XX_PCI2 - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[1].first_busno); - tmp[1] = cpu_to_be32(pci_hose[1].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -#endif -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - -#ifdef CONFIG_MPC83XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; - } -#endif -} -#endif /* CONFIG_OF_FLAT_TREE */ -#endif /* CONFIG_PCI */ diff --git a/board/mpc8349itx/Makefile b/board/mpc8349itx/Makefile deleted file mode 100644 index 31bcdb8..0000000 --- a/board/mpc8349itx/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o pci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk deleted file mode 100644 index 79f1765..0000000 --- a/board/mpc8349itx/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC8349E-mITX and MPC8349E-mITX-GP -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -TEXT_BASE = 0xFEF00000 -endif diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c deleted file mode 100644 index c82f784..0000000 --- a/board/mpc8349itx/mpc8349itx.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_PCI -#include -#include -#endif - -#ifdef CONFIG_SPD_EEPROM -#include -#else -#include -#endif -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif - -#ifndef CONFIG_SPD_EEPROM -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 ddr_size; /* The size of RAM, in bytes */ - u32 ddr_size_log2 = 0; - - for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { - if (ddr_size & 1) { - return -1; - } - ddr_size_log2++; - } - - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; - - /* Only one CS0 for DDR */ - im->ddr.csbnds[0].csbnds = 0x0000000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - - debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); - debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); - - debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); - debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); - - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ - im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; - im->ddr.sdram_mode = - (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); - im->ddr.sdram_interval = - (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << - SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; - - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); - debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); - debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); - debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); - debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); - - return CFG_DDR_SIZE; -} -#endif - -#ifdef CONFIG_PCI -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxmitx_config_table[] = { - { - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - 0x0f, - PCI_ANY_ID, - pci_cfgfunc_config_device, - { - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif - -volatile static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxmitx_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxmitx_config_table, -#endif - } -}; -#endif /* CONFIG_PCI */ - -long int initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; -#ifdef CONFIG_DDR_ECC - volatile ddr83xx_t *ddr = &im->ddr; -#endif - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; -#ifdef CONFIG_SPD_EEPROM - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#ifdef CONFIG_DDR_ECC - if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) - /* Unlike every other board, on the 83xx spd_sdram() returns - megabytes instead of just bytes. That's why we need to - multiple by 1MB when calling ddr_enable_ecc(). */ - ddr_enable_ecc(msize * 1048576); -#endif - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ -#ifdef CONFIG_MPC8349ITX - puts("Board: Freescale MPC8349E-mITX\n"); -#else - puts("Board: Freescale MPC8349E-mITX-GP\n"); -#endif - - return 0; -} - -/* - * Implement a work-around for a hardware problem with compact - * flash. - * - * Program the UPM if compact flash is enabled. - */ -int misc_init_f(void) -{ -#ifdef CONFIG_VSC7385 - volatile u32 *vsc7385_cpuctrl; - - /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up - default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That - means it is 0 when the IRQ is not active. This makes the wire-AND - logic always assert IRQ7 to CPU even if there is no request from the - switch. Since the compact flash and the switch share the same IRQ, - the Linux kernel will think that the compact flash is requesting irq - and get stuck when it tries to clear the IRQ. Thus we need to set - the L2_IRQ0 and L2_IRQ1 to active low. - - The following code sets the L1_IRQ and L2_IRQ polarity to active low. - Without this code, compact flash will not work in Linux because - unlike U-Boot, Linux uses the IRQ, so this code is necessary if we - don't enable compact flash for U-Boot. - */ - - vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); - *vsc7385_cpuctrl |= 0x0c; -#endif - -#ifdef CONFIG_COMPACT_FLASH - /* UPM Table Configuration Code */ - static uint UPMATable[] = { - 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, - 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, - 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 - }; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbus = &immap->lbus; - - lbus->bank[3].br = CFG_BR3_PRELIM; - lbus->bank[3].or = CFG_OR3_PRELIM; - - /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, - GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 - */ - lbus->mamr = 0x08404440; - - upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); - - puts("UPMA: Configured for compact flash\n"); -#endif - - return 0; -} - -/* - * Make sure the EEPROM has the HRCW correctly programmed. - * Make sure the RTC is correctly programmed. - * - * The MPC8349E-mITX can be configured to load the HRCW from - * EEPROM instead of flash. This is controlled via jumpers - * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all - * jumpered), but if they're set to 001 or 010, then the HRCW is - * read from the "I2C EEPROM". - * - * This function makes sure that the I2C EEPROM is programmed - * correctly. - */ -int misc_init_r(void) -{ - int rc = 0; - -#ifdef CONFIG_HARD_I2C - - unsigned int orig_bus = i2c_get_bus_num(); - u8 i2c_data; - -#ifdef CFG_I2C_RTC_ADDR - u8 ds1339_data[17]; -#endif - -#ifdef CFG_I2C_EEPROM_ADDR - static u8 eeprom_data[] = /* HRCW data */ - { - 0xAA, 0x55, 0xAA, /* Preamble */ - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ - 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ - (CFG_HRCW_LOW >> 24) & 0xFF, - (CFG_HRCW_LOW >> 16) & 0xFF, - (CFG_HRCW_LOW >> 8) & 0xFF, - CFG_HRCW_LOW & 0xFF, - 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ - 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ - (CFG_HRCW_HIGH >> 24) & 0xFF, - (CFG_HRCW_HIGH >> 16) & 0xFF, - (CFG_HRCW_HIGH >> 8) & 0xFF, - CFG_HRCW_HIGH & 0xFF - }; - - u8 data[sizeof(eeprom_data)]; -#endif - - printf("Board revision: "); - i2c_set_bus_num(1); - if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) - printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) - printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else { - printf("Unknown\n"); - rc = 1; - } - -#ifdef CFG_I2C_EEPROM_ADDR - i2c_set_bus_num(0); - - if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { - if (memcmp(data, eeprom_data, sizeof(data)) != 0) { - if (i2c_write - (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, - sizeof(eeprom_data)) != 0) { - puts("Failure writing the HRCW to EEPROM via I2C.\n"); - rc = 1; - } - } - } else { - puts("Failure reading the HRCW from EEPROM via I2C.\n"); - rc = 1; - } -#endif - -#ifdef CFG_I2C_RTC_ADDR - i2c_set_bus_num(1); - - if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) - == 0) { - - /* Work-around for MPC8349E-mITX bug #13601. - If the RTC does not contain valid register values, the DS1339 - Linux driver will not work. - */ - - /* Make sure status register bits 6-2 are zero */ - ds1339_data[0x0f] &= ~0x7c; - - /* Check for a valid day register value */ - ds1339_data[0x03] &= ~0xf8; - if (ds1339_data[0x03] == 0) { - ds1339_data[0x03] = 1; - } - - /* Check for a valid date register value */ - ds1339_data[0x04] &= ~0xc0; - if ((ds1339_data[0x04] == 0) || - ((ds1339_data[0x04] & 0x0f) > 9) || - (ds1339_data[0x04] >= 0x32)) { - ds1339_data[0x04] = 1; - } - - /* Check for a valid month register value */ - ds1339_data[0x05] &= ~0x60; - - if ((ds1339_data[0x05] == 0) || - ((ds1339_data[0x05] & 0x0f) > 9) || - ((ds1339_data[0x05] >= 0x13) - && (ds1339_data[0x05] <= 0x19))) { - ds1339_data[0x05] = 1; - } - - /* Enable Oscillator and rate select */ - ds1339_data[0x0e] = 0x1c; - - /* Work-around for MPC8349E-mITX bug #13330. - Ensure that the RTC control register contains the value 0x1c. - This affects SATA performance. - */ - - if (i2c_write - (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, - sizeof(ds1339_data))) { - puts("Failure writing to the RTC via I2C.\n"); - rc = 1; - } - } else { - puts("Failure reading from the RTC via I2C.\n"); - rc = 1; - } -#endif - - i2c_set_bus_num(orig_bus); -#endif - - return rc; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c deleted file mode 100644 index 5ca094d..0000000 --- a/board/mpc8349itx/pci.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349itx_config_table[] = { - { - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_IDSEL_NUMBER, - PCI_ANY_ID, - pci_cfgfunc_config_device, - { - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} - }, - {} -}; -#endif - -static struct pci_controller pci_hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349itx_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349itx_config_table, -#endif - } -}; - -/************************************************************************** - * pci_init_board() - * - * NOTICE: PCI2 is not currently supported - * - */ -void pci_init_board(void) -{ - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; - u8 reg8; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller *hose; - - immr = (immap_t *) CFG_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; - - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); - -#ifdef CONFIG_HARD_I2C - i2c_set_bus_num(1); - /* Read the PCI_M66EN jumper setting */ - if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || - (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { - if (reg8 & I2C_8574_PCI66) - clk->occr = 0xff000000; /* 66 MHz PCI */ - else - clk->occr = 0xff600001; /* 33 MHz PCI */ - } else { - clk->occr = 0xff600001; /* 33 MHz PCI */ - } -#else - clk->occr = 0xff000000; /* 66 MHz PCI */ -#endif - - udelay(2000); - - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; - udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - - for (i = 0; i < 1000; i++) - udelay(1000); - } - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; - - /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; - - /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -#endif -} - -#if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int err; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -#ifdef CONFIG_MPC83XX_PCI2 - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[1].first_busno); - tmp[1] = cpu_to_be32(pci_hose[1].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -#endif -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - -#ifdef CONFIG_MPC83XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; - } -#endif -} -#endif /* CONFIG_OF_FLAT_TREE */ -#endif /* CONFIG_PCI */ diff --git a/board/mpc8360emds/Makefile b/board/mpc8360emds/Makefile deleted file mode 100644 index 4da74b8..0000000 --- a/board/mpc8360emds/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o pci.o ../freescale/common/pq-mds-pib.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpc8360emds/config.mk b/board/mpc8360emds/config.mk deleted file mode 100644 index 9ace886..0000000 --- a/board/mpc8360emds/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC8360EMDS -# - -TEXT_BASE = 0xFE000000 diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c deleted file mode 100644 index 0751c6f..0000000 --- a/board/mpc8360emds/mpc8360emds.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_PCI) -#include -#endif -#if defined(CONFIG_SPD_EEPROM) -#include -#else -#include -#endif -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif -#if defined(CONFIG_PQ_MDS_PIB) -#include "../freescale/common/pq-mds-pib.h" -#endif - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* GETH1 */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {1, 6, 1, 0, 3}, /* TxD4 */ - {1, 7, 1, 0, 1}, /* TxD5 */ - {1, 9, 1, 0, 2}, /* TxD6 */ - {1, 10, 1, 0, 2}, /* TxD7 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 13, 2, 0, 1}, /* RxD4 */ - {1, 1, 2, 0, 2}, /* RxD5 */ - {1, 0, 2, 0, 2}, /* RxD6 */ - {1, 4, 2, 0, 2}, /* RxD7 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 16, 2, 0, 1}, /* RX_ER */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ - /* GETH2 */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {1, 2, 1, 0, 1}, /* TxD4 */ - {1, 3, 1, 0, 2}, /* TxD5 */ - {1, 5, 1, 0, 3}, /* TxD6 */ - {1, 8, 1, 0, 3}, /* TxD7 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 27, 2, 0, 1}, /* RxD4 */ - {1, 12, 2, 0, 2}, /* RxD5 */ - {1, 13, 2, 0, 3}, /* RxD6 */ - {1, 11, 2, 0, 2}, /* RxD7 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 30, 2, 0, 1}, /* RX_ER */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ -}; - -int board_early_init_f(void) -{ - - u8 *bcsr = (u8 *)CFG_BCSR; - const immap_t *immr = (immap_t *)CFG_IMMR; - - /* Enable flash write */ - bcsr[0xa] &= ~0x04; - - /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ - if (immr->sysconf.spridr == SPR_8360_REV20 || - immr->sysconf.spridr == SPR_8360E_REV20 || - immr->sysconf.spridr == SPR_8360_REV21 || - immr->sysconf.spridr == SPR_8360E_REV21) - bcsr[0xe] = 0x30; - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - return 0; -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); -void sdram_init(void); - -long int initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) - /* - * Initialize DDR ECC byte - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#ifdef CONFIG_DDR_II - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; -#else - im->ddr.csbnds[0].csbnds = 0x00000007; - im->ddr.csbnds[1].csbnds = 0x0008000f; - - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; - - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.sdram_cfg = CFG_DDR_CONTROL; - - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; -#endif - udelay(200); - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} -#endif /*!CFG_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC8360EMDS\n"); - return 0; -} - -/* - * if MPC8360EMDS is soldered with SDRAM - */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbc = &immap->lbus; - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* - * We need do 8 times auto refresh operation. - */ - lbc->lsdmr = CFG_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; /* 1 times */ - udelay(100); - *sdram_addr = 0xff; /* 2 times */ - udelay(100); - *sdram_addr = 0xff; /* 3 times */ - udelay(100); - *sdram_addr = 0xff; /* 4 times */ - udelay(100); - *sdram_addr = 0xff; /* 5 times */ - udelay(100); - *sdram_addr = 0xff; /* 6 times */ - udelay(100); - *sdram_addr = 0xff; /* 7 times */ - udelay(100); - *sdram_addr = 0xff; /* 8 times */ - udelay(100); - - /* Mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *(sdram_addr + 0xcc) = 0xff; - udelay(100); - - /* Normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void sdram_init(void) -{ -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#if defined(CONFIG_OF_FLAT_TREE) - u32 *p; - int len; - - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } -#endif - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} -#endif diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c deleted file mode 100644 index cf7ef90..0000000 --- a/board/mpc8360emds/pci.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/* - * PCI Configuration space access support for MPC83xx PCI Bridge - */ -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#elif defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_PCI) -#define PCI_FUNCTION_CONFIG 0x44 -#define PCI_FUNCTION_CFG_LOCK 0x20 - -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxemds_config_table[] = { - { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif -static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxemds_config_table, -#endif - }, -}; - -/********************************************************************** - * pci_init_board() - *********************************************************************/ -void pci_init_board(void) -#ifdef CONFIG_PCISLAVE -{ - u16 reg16; - volatile immap_t *immr; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; - - immr = (immap_t *) CFG_IMMR; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar0 = 0x0; - pci_ctrl[0].pibar0 = 0x0; - pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_4K; - - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 &= ~PIWAR_EN; - - pci_ctrl[0].pitar2 = 0x0; - pci_ctrl[0].pibar2 = 0x0; - pci_ctrl[0].piebar2 = 0x0; - pci_ctrl[0].piwar2 &= ~PIWAR_EN; - - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); - reg16 = 0xff; - - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), - PCI_LATENCY_TIMER, 0x80); - - /* - * Unlock configuration lock in PCI function configuration register. - */ - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, ®16); - reg16 &= ~(PCI_FUNCTION_CFG_LOCK); - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, reg16); - - printf("Enabled PCI 32bit Agent Mode\n"); -} -#else -{ - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; - - u16 reg16; - u32 val32; - u32 dev; - - immr = (immap_t *) CFG_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); -#if defined(PCI_66M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#elif defined(PCI_33M) - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | - OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; - printf("PCI clock is 33MHz\n"); -#else - clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; - printf("PCI clock is 66MHz\n"); -#endif - udelay(2000); - - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI IO space */ - pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - PIWAR_IWS_2G; - - /* - * Release PCI RST Output signal - */ - udelay(2000); - pci_ctrl[0].gcr = 1; - udelay(2000); - - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose[0].regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose[0].regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose[0].regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose[0].regions + 3, - CFG_PCI_SLV_MEM_LOCAL, - CFG_PCI_SLV_MEM_BUS, - CFG_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose[0].region_count = 4; - - pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write command register - */ - reg16 = 0xff; - dev = PCI_BDF(0, 0, 0); - pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCISLAVE */ - -#if defined(CONFIG_OF_LIBFDT) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int err; - int tmp[2]; - - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", - tmp, sizeof(tmp)); - - tmp[0] = cpu_to_be32(gd->pci_clk); - err = fdt_setprop(blob, nodeoffset, "clock-frequency", - tmp, sizeof(tmp[0])); - } -} -#elif defined(CONFIG_OF_FLAT_TREE) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = hose[0].first_busno; - p[1] = hose[0].last_busno; - } -} -#endif /* CONFIG_OF_FLAT_TREE */ -#endif /* CONFIG_PCI */ -- cgit v1.1 From 4a442d3186b31893b4f77c6e82f63c4517a5224b Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Thu, 16 Aug 2007 19:23:50 -0500 Subject: ColdFire: Add M5235EVB Platform for MCF523x Signed-off-by: TsiChungLiew --- board/freescale/m5235evb/Makefile | 44 ++++++ board/freescale/m5235evb/config.mk | 28 ++++ board/freescale/m5235evb/m5235evb.c | 117 ++++++++++++++ board/freescale/m5235evb/mii.c | 307 ++++++++++++++++++++++++++++++++++++ board/freescale/m5235evb/u-boot.16 | 145 +++++++++++++++++ board/freescale/m5235evb/u-boot.32 | 153 ++++++++++++++++++ board/freescale/m5235evb/u-boot.lds | 145 +++++++++++++++++ 7 files changed, 939 insertions(+) create mode 100644 board/freescale/m5235evb/Makefile create mode 100644 board/freescale/m5235evb/config.mk create mode 100644 board/freescale/m5235evb/m5235evb.c create mode 100644 board/freescale/m5235evb/mii.c create mode 100644 board/freescale/m5235evb/u-boot.16 create mode 100644 board/freescale/m5235evb/u-boot.32 create mode 100644 board/freescale/m5235evb/u-boot.lds (limited to 'board') diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile new file mode 100644 index 0000000..74c2528 --- /dev/null +++ b/board/freescale/m5235evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o mii.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk new file mode 100644 index 0000000..ada38dd --- /dev/null +++ b/board/freescale/m5235evb/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +/*TEXT_BASE = 0xFFC00000*/ +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) \ No newline at end of file diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c new file mode 100644 index 0000000..585854c --- /dev/null +++ b/board/freescale/m5235evb/m5235evb.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M5235 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 dramsize, i, dramclk; + + /* + * When booting from external Flash, the port-size is less than + * the port-size of SDRAM. In this case it is necessary to enable + * Data[15:0] on Port Address/Data. + */ + gpio->par_ad = + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | + GPIO_PAR_AD_DATAL; + + /* Initialize PAR to enable SDRAM signals */ + gpio->par_sdram = + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | + GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); + + dramsize = CFG_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { + dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + + /* Initialize DRAM Control Register: DCR */ + sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | + SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4); + + /* Initialize DACR0 */ + sdram->dacr0 = + SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | + SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; + + /* Initialize DMR0 */ + sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V; + + /* Set IP (bit 3) in DACR */ + sdram->dacr0 |= SDRAMC_DARCn_IP; + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + sdram->dacr0 |= SDRAMC_DARCn_RE; + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 0x2000; i++) { + asm("nop"); + } + + /* Finish the configuration by issuing the MRS. */ + sdram->dacr0 |= SDRAMC_DARCn_IMRS; + + /* Write to the SDRAM Mode Register */ + *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + } + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c new file mode 100644 index 0000000..58fabdf --- /dev/null +++ b/board/freescale/m5235evb/mii.c @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +int fecpin_setclear(struct eth_device *dev, int setclear) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if (setclear) { + gpio->par_feci2c |= + (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + } else { + gpio->par_feci2c &= + ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + } + + return 0; +} + +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) +#include + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) + +/* PHY identification */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ +#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ +#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ +#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ + +#define STR_ID_LXT970 "LXT970" +#define STR_ID_LXT971 "LXT971" +#define STR_ID_82555 "Intel82555" +#define STR_ID_QS6612 "QS6612" +#define STR_ID_AMD79C784 "AMD79C784" +#define STR_ID_LSI80225 "LSI80225" +#define STR_ID_LSI80225B "LSI80225/B" +#define STR_ID_DP83848VV "N83848" +#define STR_ID_DP83849 "N83849" +#define STR_ID_KS8721BL "KS8721BL" + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_reset(struct fec_info_s *info) +{ + volatile fec_t *fecp = (fec_t *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) { + printf("FEC_RESET_DELAY timeout\n"); + } +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + struct fec_info_s *info; + struct eth_device *dev; + volatile fec_t *ep; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (fec_t *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CFG_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + struct fec_info_s *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + strcpy(info->phy_name, + STR_ID_KS8721BL); + info->phyname_init = 1; + break; + default: + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d type ", phyno, pass); + switch (phytype & 0xffffffff) { + case PHY_ID_KS8721BL: + printf(STR_ID_KS8721BL); + break; + default: + printf("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CFG_DISCOVER_PHY */ + +int mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + volatile fec_t *fecp; + struct fec_info_s *info; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (fec_t *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5235evb/u-boot.16 b/board/freescale/m5235evb/u-boot.16 new file mode 100644 index 0000000..8ffd326 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.16 @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu_init.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/u-boot.32 b/board/freescale/m5235evb/u-boot.32 new file mode 100644 index 0000000..9b72f66 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.32 @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu.o (.text) + cpu/mcf523x/cpu_init.o (.text) + cpu/mcf523x/interrupts.o (.text) + cpu/mcf523x/speed.o (.text) + lib_m68k/libm68k.a (.text) + common/dlmalloc.o (.text) + common/cmd_bootm.o (.text) + common/cmd_flash.o (.text) + common/cmd_elf.o (.text) + common/cmd_mem.o (.text) + common/console.o (.text) + common/main.o (.text) + lib_generic/libgeneric.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds new file mode 100644 index 0000000..8ffd326 --- /dev/null +++ b/board/freescale/m5235evb/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf523x/start.o (.text) + cpu/mcf523x/cpu_init.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From 8280f6a1c43247616b68224675188e5ccd124650 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 18 Aug 2007 14:33:02 +0200 Subject: Coding style cleanup Signed-off-by: Stefan Roese --- board/freescale/m5249evb/m5249evb.c | 1 - board/freescale/m5253evbe/m5253evbe.c | 1 - board/freescale/m54455evb/m54455evb.c | 1 - 3 files changed, 3 deletions(-) (limited to 'board') diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index b0bf413..e8f621b 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -111,4 +111,3 @@ int testdram (void) { return (0); } - diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index 67fab5b..43aa84d 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -130,4 +130,3 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_CMD_IDE */ - diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 1411a1a..6a02782 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -162,4 +162,3 @@ void pci_init_board(void) pci_mcf5445x_init(&hose); } #endif /* CONFIG_PCI */ - -- cgit v1.1 From 79f240f7ecc0506b43ac50d1ea405ff6540d4d57 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 16 Aug 2007 22:52:39 -0500 Subject: lib_ppc: make board_add_ram_info weak platforms wishing to display RAM diagnostics in addition to size, can do so, on one line, in their own board_add_ram_info() implementation. this consequently eliminates CONFIG_ADD_RAM_INFO. Thanks to Stefan for the hint. Signed-off-by: Kim Phillips --- board/lwmon5/sdram.c | 2 -- board/netstal/hcu5/sdram.c | 2 -- 2 files changed, 4 deletions(-) (limited to 'board') diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index f906b85..d4547e2 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -57,7 +57,6 @@ void dcbz_area(u32 start_address, u32 num_bytes); void dflush(void); -#ifdef CONFIG_ADD_RAM_INFO static u32 is_ecc_enabled(void) { u32 val; @@ -87,7 +86,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif static int wait_for_dlllock(void) { diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 4039195..c5be8b9 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -70,7 +70,6 @@ void dflush(void); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -#ifdef CONFIG_ADD_RAM_INFO void board_add_ram_info(int use_default) { PPC440_SYS_INFO board_cfg; @@ -99,7 +98,6 @@ void board_add_ram_info(int use_default) val = DDR0_03_CASLAT_DECODE(val); printf(", CL%d)", val); } -#endif /*-------------------------------------------------------------------- * wait_for_dlllock. -- cgit v1.1 From 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 21 Aug 2007 16:27:57 +0200 Subject: ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based) This patch adds support for the matrix keyboard on the lwmon5 board. Since the implementation in the dsPCI is kind of compatible with the "old" lwmon board, most of the code is copied from the lwmon board directory. Signed-off-by: Stefan Roese --- board/lwmon5/Makefile | 2 +- board/lwmon5/kbd.c | 458 ++++++++++++++++++++++++++++++++++++++++++++++++++ board/lwmon5/lwmon5.c | 19 +-- 3 files changed, 466 insertions(+), 13 deletions(-) create mode 100644 board/lwmon5/kbd.c (limited to 'board') diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile index 06ef7f9..2a93571 100644 --- a/board/lwmon5/Makefile +++ b/board/lwmon5/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o sdram.o +COBJS = $(BOARD).o kbd.o sdram.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c new file mode 100644 index 0000000..1e5349a --- /dev/null +++ b/board/lwmon5/kbd.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2001, 2002 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include +#include + +#include +#include /* for strdup */ + +DECLARE_GLOBAL_DATA_PTR; + +static void kbd_init (void); +static int compare_magic (uchar *kbd_data, uchar *str); + +/*--------------------- Local macros and constants --------------------*/ +#define _NOT_USED_ 0xFFFFFFFF + +/*------------------------- Keyboard controller -----------------------*/ +/* command codes */ +#define KEYBD_CMD_READ_KEYS 0x01 +#define KEYBD_CMD_READ_VERSION 0x02 +#define KEYBD_CMD_READ_STATUS 0x03 +#define KEYBD_CMD_RESET_ERRORS 0x10 + +/* status codes */ +#define KEYBD_STATUS_MASK 0x3F +#define KEYBD_STATUS_H_RESET 0x20 +#define KEYBD_STATUS_BROWNOUT 0x10 +#define KEYBD_STATUS_WD_RESET 0x08 +#define KEYBD_STATUS_OVERLOAD 0x04 +#define KEYBD_STATUS_ILLEGAL_WR 0x02 +#define KEYBD_STATUS_ILLEGAL_RD 0x01 + +/* Number of bytes returned from Keyboard Controller */ +#define KEYBD_VERSIONLEN 2 /* version information */ + +/* + * This is different from the "old" lwmon dsPIC kbd controller + * implementation. Now the controller still answers with 9 bytes, + * but the last 3 bytes are always "0x06 0x07 0x08". So we just + * set the length to compare to 6 instead of 9. + */ +#define KEYBD_DATALEN 6 /* normal key scan data */ + +/* maximum number of "magic" key codes that can be assigned */ + +static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; + +static uchar *key_match (uchar *); + +#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ + +/*********************************************************************** +F* Function: int board_postclk_init (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: This function is the board_postclk_init() method implementation +Z* for the lwmon board. + * + ***********************************************************************/ +int board_postclk_init (void) +{ + kbd_init(); + + return (0); +} + +static void kbd_init (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar tmp_data[KEYBD_DATALEN]; + uchar val, errcd; + int i; + + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + gd->kbd_status = 0; + + /* Forced by PIC. Delays <= 175us loose */ + udelay(1000); + + /* Read initial keyboard error code */ + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &errcd, 1); + /* clear unused bits */ + errcd &= KEYBD_STATUS_MASK; + /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ + errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); + if (errcd) { + gd->kbd_status |= errcd << 8; + } + /* Reset error code and verify */ + val = KEYBD_CMD_RESET_ERRORS; + i2c_write (kbd_addr, 0, 0, &val, 1); + udelay(1000); /* delay NEEDED by keyboard PIC !!! */ + + val = KEYBD_CMD_READ_STATUS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, &val, 1); + + val &= KEYBD_STATUS_MASK; /* clear unused bits */ + if (val) { /* permanent error, report it */ + gd->kbd_status |= val; + return; + } + + /* + * Read current keyboard state. + * + * After the error reset it may take some time before the + * keyboard PIC picks up a valid keyboard scan - the total + * scan time is approx. 1.6 ms (information by Martin Rajek, + * 28 Sep 2002). We read a couple of times for the keyboard + * to stabilize, using a big enough delay. + * 10 times should be enough. If the data is still changing, + * we use what we get :-( + */ + + memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ + for (i=0; i<10; ++i) { + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { + /* consistent state, done */ + break; + } + /* remeber last state, delay, and retry */ + memcpy (tmp_data, kbd_data, KEYBD_DATALEN); + udelay (5000); + } +} + +/*********************************************************************** +F* Function: int misc_init_r (void) P*A*Z* + * +P* Parameters: none +P* +P* Returnvalue: int +P* - 0 is always returned, even in the case of a keyboard +P* error. + * +Z* Intention: This function is the misc_init_r() method implementation +Z* for the lwmon board. +Z* The keyboard controller is initialized and the result +Z* of a read copied to the environment variable "keybd". +Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for +Z* this key, and if found display to the LCD will be enabled. +Z* The keys in "keybd" are checked against the magic +Z* keycommands defined in the environment. +Z* See also key_match(). + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int misc_init_r_kbd (void) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar kbd_init_status = gd->kbd_status >> 8; + uchar kbd_status = gd->kbd_status; + uchar val; + char *str; + int i; + + if (kbd_init_status) { + printf ("KEYBD: Error %02X\n", kbd_init_status); + } + if (kbd_status) { /* permanent error, report it */ + printf ("*** Keyboard error code %02X ***\n", kbd_status); + sprintf (keybd_env, "%02X", kbd_status); + setenv ("keybd", keybd_env); + return 0; + } + + /* + * Now we know that we have a working keyboard, so disable + * all output to the LCD except when a key press is detected. + */ + + if ((console_assign (stdout, "serial") < 0) || + (console_assign (stderr, "serial") < 0)) { + printf ("Can't assign serial port as output device\n"); + } + + /* Read Version */ + val = KEYBD_CMD_READ_VERSION; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); + printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); + + /* Read current keyboard state */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + } + setenv ("keybd", keybd_env); + + str = strdup ((char *)key_match (kbd_data)); /* decode keys */ +#ifdef KEYBD_SET_DEBUGMODE + if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ + if ((console_assign (stdout, "lcd") < 0) || + (console_assign (stderr, "lcd") < 0)) { + printf ("Can't assign LCD display as output device\n"); + } + } +#endif /* KEYBD_SET_DEBUGMODE */ +#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ + setenv ("preboot", str); /* set or delete definition */ +#endif /* CONFIG_PREBOOT */ + if (str != NULL) { + free (str); + } + return (0); +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +static int compare_magic (uchar *kbd_data, uchar *str) +{ + uchar compare[KEYBD_DATALEN-1]; + char *nxt; + int i; + + /* Don't include modifier byte */ + memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); + + for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { + uchar c; + int k; + + c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); + + if (str == (uchar *)nxt) { /* invalid character */ + break; + } + + /* + * Check if this key matches the input. + * Set matches to zero, so they match only once + * and we can find duplicates or extra keys + */ + for (k = 0; k < sizeof(compare); ++k) { + if (compare[k] == '\0') /* only non-zero entries */ + continue; + if (c == compare[k]) { /* found matching key */ + compare[k] = '\0'; + break; + } + } + if (k == sizeof(compare)) { + return -1; /* unmatched key */ + } + } + + /* + * A full match leaves no keys in the `compare' array, + */ + for (i = 0; i < sizeof(compare); ++i) { + if (compare[i]) + { + return -1; + } + } + + return 0; +} + +/*********************************************************************** +F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* + * +P* Parameters: uchar *kbd_data +P* - The keys to match against our magic definitions +P* +P* Returnvalue: uchar * +P* - != NULL: Pointer to the corresponding command(s) +P* NULL: No magic is about to happen + * +Z* Intention: Check if pressed key(s) match magic sequence, +Z* and return the command string associated with that key(s). +Z* +Z* If no key press was decoded, NULL is returned. +Z* +Z* Note: the first character of the argument will be +Z* overwritten with the "magic charcter code" of the +Z* decoded key(s), or '\0'. +Z* +Z* Note: the string points to static environment data +Z* and must be saved before you call any function that +Z* modifies the environment. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +static uchar *key_match (uchar *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can pe appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + debug ("### Check magic \"%s\"\n", magic); + if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + + cmd = getenv (cmd_name); + debug ("### Set PREBOOT to $(%s): \"%s\"\n", + cmd_name, cmd ? cmd : "<>"); + *kbd_data = *suffix; + return ((uchar *)cmd); + } + } + debug ("### Delete PREBOOT\n"); + *kbd_data = '\0'; + return (NULL); +} +#endif /* CONFIG_PREBOOT */ + +/*********************************************************************** +F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, +F* int argc, char *argv[]) P*A*Z* + * +P* Parameters: cmd_tbl_t *cmdtp +P* - Pointer to our command table entry +P* int flag +P* - If the CMD_FLAG_REPEAT bit is set, then this call is +P* a repetition +P* int argc +P* - Argument count +P* char *argv[] +P* - Array of the actual arguments +P* +P* Returnvalue: int +P* - 0 is always returned. + * +Z* Intention: Implement the "kbd" command. +Z* The keyboard status is read. The result is printed on +Z* the console and written into the "keybd" environment +Z* variable. + * +D* Design: wd@denx.de +C* Coding: wd@denx.de +V* Verification: dzu@denx.de + ***********************************************************************/ +int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar kbd_data[KEYBD_DATALEN]; + char keybd_env[2 * KEYBD_DATALEN + 1]; + uchar val; + int i; + +#if 0 /* Done in kbd_init */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + puts ("Keys:"); + for (i = 0; i < KEYBD_DATALEN; ++i) { + sprintf (keybd_env + i + i, "%02X", kbd_data[i]); + printf (" %02x", kbd_data[i]); + } + putc ('\n'); + setenv ("keybd", keybd_env); + return 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL +); + +/*----------------------------- Utilities -----------------------------*/ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + uchar kbd_data[KEYBD_DATALEN]; + uchar val; + + /* Read keys */ + val = KEYBD_CMD_READ_KEYS; + i2c_write (kbd_addr, 0, 0, &val, 1); + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + + return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); +} +#endif diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 830ec19..0958194 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -28,7 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -ulong flash_get_size (ulong base, int banknum); +ulong flash_get_size(ulong base, int banknum); +int misc_init_r_kbd(void); int board_early_init_f(void) { @@ -295,6 +296,11 @@ int misc_init_r(void) out_be32((void *)0xc4000024, 0x64); out_be32((void *)0xc4000020, 0x701); + /* + * Init matrix keyboard + */ + misc_init_r_kbd(); + return 0; } @@ -521,14 +527,3 @@ void hw_watchdog_reset(void) val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; gpio_write_bit(CFG_GPIO_WATCHDOG, val); } - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return (ctrlc()); -} -#endif -- cgit v1.1 From c25dd8fc25e9ca3695db996a257d9ba4dab414db Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 23 Aug 2007 11:02:37 +0200 Subject: ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5 board. Now the "eeprom" command can be used to read/write from/to this device. Additionally a new command was added "eepromwp" to en-/disable the write-protect of this 2nd EEPROM. The 1st EEPROM is not affected by this write-protect command. Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'board') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 0958194..77f9989 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -19,6 +19,7 @@ */ #include +#include #include #include #include @@ -527,3 +528,29 @@ void hw_watchdog_reset(void) val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; gpio_write_bit(CFG_GPIO_WATCHDOG, val); } + +int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if ((strcmp(argv[1], "on") == 0)) { + gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1); + } else if ((strcmp(argv[1], "off") == 0)) { + gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0); + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + + return 0; +} + +U_BOOT_CMD( + eepromwp, 2, 0, do_eeprom_wp, + "eepromwp- eeprom write protect off/on\n", + " - enable (on) or disable (off) I2C EEPROM write protect\n" +); -- cgit v1.1 From f98984cb194bb34dbe1db9429d3b51133af30d07 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 28 Aug 2007 17:39:14 +0200 Subject: IDE: - make ide_inb () and ide_outb () "weak", so boards can define there own I/O functions. (Needed for the pcs440ep board). - The default I/O Functions are again 8 Bit accesses. - Added CONFIG_CMD_IDE for the pcs440ep Board. Signed-off-by: Heiko Schocher --- board/pcs440ep/pcs440ep.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'board') diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index e247fee..90e99d3 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -30,6 +30,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -867,6 +868,29 @@ U_BOOT_CMD( ); #endif +#if defined (CONFIG_CMD_IDE) +/* These addresses need to be shifted one place to the left + * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) + * These values are shifted + */ +extern ulong *ide_bus_offset; +void inline ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+port)); + + out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val); +} +unsigned char inline ide_inb(int dev, int port) +{ + uchar val; + val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1))); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+port), val); + return (val); +} +#endif + #ifdef CONFIG_IDE_PREINIT int ide_preinit (void) { -- cgit v1.1 From 9bb8b209ed2058a5756ecbeb544c067e44a42aea Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 20 Aug 2007 07:09:05 +0200 Subject: Fix compilation error for omap2420h4_config. omap2420h4 switched to cfi, so remove old (already disabled) flash.c and flash_probe() calls in env_flash.c. Signed-off-by: Dirk Behme --- board/omap2420h4/flash.c | 537 ----------------------------------------------- 1 file changed, 537 deletions(-) delete mode 100644 board/omap2420h4/flash.c (limited to 'board') diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c deleted file mode 100644 index d5e106a..0000000 --- a/board/omap2420h4/flash.c +++ /dev/null @@ -1,537 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define PHYS_FLASH_SECT_SIZE SZ_128K -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -# define FLASH_PORT_WIDTH ushort -# define FLASH_PORT_WIDTHV vu_short -# define SWAP(x) __swab16(x) -#else -# define FLASH_PORT_WIDTH ulong -# define FLASH_PORT_WIDTHV vu_long -# define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, SZ_32K}, /* 4 * 32kBytes sectors */ - {255, SZ_128K}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info, int bank); -int flash_probe(void); - -/*----------------------------------------------------------------------- - */ - -/* see if flash is ok */ -int flash_probe(void) -{ - return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0])); -} - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i],i); - break; - - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - -#ifdef CFG_ENV_IS_IN_FLASH - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info, int bank) -{ - int j; - if (!bank) - j=2; /* leave 0,1 locked for boot bank */ - else - j=0; /* get the whole bank for #2 */ - - for (;jstart[j]); - if (addr == NULL) { - printf("Warning Flash probe failed\n"); - break; - } - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/ - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 254) { /* 255,256,257,258 */ - r=i; - info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE)); - info->protect[i] = 0; - } else { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */ - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/ - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return(0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): /* 880D */ - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; /*0-258*/ - info->size = SZ_32M; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CFG_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return(info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start, last; - int rcode = 0; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - -#ifdef CONFIG_USE_IRQ - /* Disable interrupts which might cause a timeout here */ - iflag = disable_interrupts (); -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return(rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return(0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return(write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; -#ifdef CONFIG_USE_IRQ - int iflag; -#endif - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return(2); - } - /* Disable interrupts which might cause a timeout here */ -#ifdef CONFIG_USE_IRQ - iflag = disable_interrupts (); -#endif - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return(1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - -#ifdef CONFIG_USE_IRQ - if (iflag) - enable_interrupts(); -#endif - - return(0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} -- cgit v1.1 From 7608d75f9c87c9eb5b3a43219d0506d3e979a13f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 21 Aug 2007 17:00:17 -0500 Subject: support board vendor-common makefiles if a board/$(VENDOR)/common/Makefile exists, build it. also add the first such case, board/freescale/common/Makefile, to handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as dictated by board configuration. thusly get rid of alternate build dir errors such as: FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory by putting the common/ mkdir command in its proper place (the common Makefile). Common bits from existing individual board Makefiles have been removed. Signed-off-by: Kim Phillips --- board/freescale/common/Makefile | 56 ++++++++++++++++++++++++++++++++++++ board/freescale/common/pixis.c | 3 ++ board/freescale/common/pq-mds-pib.c | 3 ++ board/freescale/mpc832xemds/Makefile | 2 +- board/freescale/mpc8360emds/Makefile | 2 +- board/freescale/mpc8544ds/Makefile | 7 +---- board/freescale/mpc8641hpcn/Makefile | 8 +----- 7 files changed, 66 insertions(+), 15 deletions(-) create mode 100644 board/freescale/common/Makefile (limited to 'board') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile new file mode 100644 index 0000000..44f613e --- /dev/null +++ b/board/freescale/common/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS := sys_eeprom.o \ + pixis.o \ + pq-mds-pib.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 99cc2ee..ae4bef1 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -27,6 +27,8 @@ #include #include +#ifdef CONFIG_FSL_PIXIS + #include "pixis.h" @@ -470,3 +472,4 @@ U_BOOT_CMD( " pixis_reset altbank cf \n" " pixis_reset cf \n" ); +#endif /* CONFIG_FSL_PIXIS */ diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 8c013c7..d79f2eb 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -12,6 +12,8 @@ #include #include +#ifdef CONFIG_PQ_MDS_PIB + #include "pq-mds-pib.h" int pib_init(void) @@ -100,3 +102,4 @@ int pib_init(void) i2c_set_bus_num(orig_i2c_bus); return 0; } +#endif /* CONFIG_PQ_MDS_PIB */ diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index ea52484..5ec7a87 100644 --- a/board/freescale/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o +COBJS := $(BOARD).o pci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index ea52484..5ec7a87 100644 --- a/board/freescale/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o +COBJS := $(BOARD).o pci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 308f707..006fdc9 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -24,14 +24,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ - ../common/pixis.o +COBJS := $(BOARD).o SOBJS := init.o diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 93b015d..201da3e 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -23,15 +23,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o \ - ../common/sys_eeprom.o \ - ../common/pixis.o +COBJS := $(BOARD).o SOBJS := init.o -- cgit v1.1 From 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Wed, 22 Aug 2007 17:54:49 +0800 Subject: Remove the bios emulator binary files from MAI board Signed-off-by: Jason Jin --- board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake | Bin 70812 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp | Bin 37612 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo | Bin 11924 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm | Bin 38300 -> 0 bytes .../MAI/bios_emulator/scitech/bin-linux/glibc/makedep | Bin 58623 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm | Bin 263498 -> 0 bytes .../MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm | Bin 100192 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/glibc/trans | Bin 9244 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/libc/dmake | Bin 71264 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/libc/nasm | Bin 168228 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm | Bin 66888 -> 0 bytes board/MAI/bios_emulator/scitech/bin-linux/libc/trans | Bin 8984 -> 0 bytes board/MAI/bios_emulator/scitech/makedefs/makedefs.prj | Bin 9025 -> 0 bytes board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj | Bin 59 -> 0 bytes 14 files changed, 0 insertions(+), 0 deletions(-) delete mode 100755 board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake delete mode 100755 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b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans deleted file mode 100755 index e536c04..0000000 Binary files a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj deleted file mode 100644 index edd8809..0000000 Binary files a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj and /dev/null differ diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj deleted file mode 100644 index 5533346..0000000 Binary files a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj and /dev/null differ -- cgit v1.1 From 4bf4abb8a4e9955556b120a1aafa30c03e74032a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 21 Aug 2007 09:38:59 -0500 Subject: 8548cds fixes Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the correct consoledev needed for linux boot. Standardize on fdt{file,addr} var to hold dtb file name. Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}. Signed-off-by: Ed Swarthout --- board/cds/mpc8548cds/mpc8548cds.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 48753d7..796ae22 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -362,20 +362,28 @@ pci_init_board(void) ); - /* outbound memory */ + /* inbound */ pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region(hose->regions + 1, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 1, + pci_set_region(hose->regions + 2, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 2; + hose->region_count = 3; /* relocate config table pointers */ hose->config_table = \ -- cgit v1.1 From 81b73dec16fd1227369a191e725e10044a9d56b8 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 15:21:46 +0200 Subject: ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- board/amcc/sequoia/init.S | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 45bcd4b..5fe3af9 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -126,6 +126,9 @@ tlbtab: /* TLB-entry for peripherals */ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbtab_end #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -- cgit v1.1 From f75e89e9b5714db2b0e80074071dfbdd6f59488a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 30 Aug 2007 01:58:48 -0500 Subject: ft_board_setup update 85xx/86xx of pci/pcie bus-range property. pcie is now differentiated from pci. Add 8641 bus-range updates. Signed-off-by: Ed Swarthout --- board/cds/mpc8548cds/mpc8548cds.c | 2 +- board/freescale/mpc8544ds/mpc8544ds.c | 14 +++++++++++--- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 16 ++++++++++++++++ 3 files changed, 28 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 796ae22..36d7e1e 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -542,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd) #endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 80822be..4c3b27f 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -516,8 +516,16 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; @@ -525,7 +533,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; @@ -533,7 +541,7 @@ ft_board_setup(void *blob, bd_t *bd) } #endif #ifdef CONFIG_PCIE3 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len); + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len); if (p != NULL) { p[0] = 0; p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index ffd11cb..931be9f 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -338,6 +338,22 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci2_hose.last_busno - pci2_hose.first_busno; + debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif } #endif -- cgit v1.1 From 56a9270521baaa00e12639a978302a67f61ef060 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Aug 2007 16:18:18 -0500 Subject: Fix ULI RTC support on MPC8544 DS The RTC on the M1575 ULI chipset requires a dummy read before we are able to talk to the RTC. We accomplish this by adding a second memory region to the PHB the ULI is on and read from it. The second region is added to maintain compatiabilty with Linux's view of the PCI memory map. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/init.S | 2 +- board/freescale/mpc8544ds/mpc8544ds.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 900c368..68ccba7 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -237,6 +237,6 @@ law_entry: /* contains both PCIE3 MEM & IO space */ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M) + .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) 4: entry_end diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4c3b27f..76d9091 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -222,6 +223,11 @@ pci_init_board(void) printf (" PCIE3 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32(CFG_PCIE3_MEM_BASE); } else { printf (" PCIE3: disabled\n"); } -- cgit v1.1 From cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Thu, 6 Sep 2007 09:46:23 -0600 Subject: Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200 Tested on: lite5200b Note: the fixup functions have not been moved to a common place. This patch is targeted for immediate merging as in solves a build issue, but the final name/location of the fixups is still subject to debate. I propose to merge this now, and move the fixups in the next merge window to be usable by all targets. Signed-off-by: Grant Likely --- board/icecube/icecube.c | 7 ++----- board/jupiter/jupiter.c | 8 ++------ board/motionpro/motionpro.c | 8 +++----- board/tqm5200/tqm5200.c | 9 +++------ 4 files changed, 10 insertions(+), 22 deletions(-) (limited to 'board') diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index c027f6f..07ba245 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -28,10 +28,7 @@ #include #include #include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif +#include #if defined(CONFIG_LITE5200B) #include "mt46v32m16.h" @@ -386,7 +383,7 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index b227487..efdc333 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -28,11 +28,7 @@ #include #include #include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif - +#include #define SDRAM_DDR 0 #if 1 @@ -308,7 +304,7 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 6eb5fe9..f83998e 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -29,9 +29,7 @@ #include #include #include -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif +#include #if defined(CONFIG_STATUS_LED) #include @@ -196,12 +194,12 @@ int checkboard(void) } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ #if defined(CONFIG_STATUS_LED) diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 51f4aeb..21f67aa 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -31,10 +31,7 @@ #include #include #include - -#if defined(CONFIG_OF_FLAT_TREE) -#include -#endif +#include #ifdef CONFIG_VIDEO_SM501 #include @@ -780,9 +777,9 @@ int board_get_height (void) #endif /* CONFIG_VIDEO_SM501 */ -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); } -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -- cgit v1.1 From 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 Mon Sep 17 00:00:00 2001 From: stefano babic Date: Thu, 30 Aug 2007 23:01:49 +0200 Subject: PXA270: Added support for TrizepsIV board. This patch add support for the Trizeps IV module (520Mhz). Signed-off-by: Stefano Babic --- board/trizepsiv/Makefile | 51 ++++ board/trizepsiv/config.mk | 3 + board/trizepsiv/conxs.c | 146 ++++++++++++ board/trizepsiv/eeprom.c | 85 +++++++ board/trizepsiv/lowlevel_init.S | 503 ++++++++++++++++++++++++++++++++++++++++ board/trizepsiv/pxavoltage.S | 31 +++ board/trizepsiv/u-boot.lds | 56 +++++ 7 files changed, 875 insertions(+) create mode 100644 board/trizepsiv/Makefile create mode 100644 board/trizepsiv/config.mk create mode 100644 board/trizepsiv/conxs.c create mode 100644 board/trizepsiv/eeprom.c create mode 100644 board/trizepsiv/lowlevel_init.S create mode 100644 board/trizepsiv/pxavoltage.S create mode 100644 board/trizepsiv/u-boot.lds (limited to 'board') diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile new file mode 100644 index 0000000..115e17d --- /dev/null +++ b/board/trizepsiv/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := conxs.o eeprom.o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk new file mode 100644 index 0000000..4486f6b --- /dev/null +++ b/board/trizepsiv/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c new file mode 100644 index 0000000..7c6c855 --- /dev/null +++ b/board/trizepsiv/conxs.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ + +extern struct serial_device serial_ffuart_device; +extern struct serial_device serial_btuart_device; +extern struct serial_device serial_stuart_device; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +void usb_board_init(void) +{ + UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + UHCHR |= UHCHR_FSBIR; + + while (UHCHR & UHCHR_FSBIR); + + UHCHR &= ~UHCHR_SSE; + UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + + /* Clear any OTG Pin Hold */ + if (PSSR & PSSR_OTGPH) + PSSR |= PSSR_OTGPH; + + UHCRHDA &= ~(RH_A_NPS); + UHCRHDA |= RH_A_PSM; + + /* Set port power control mask bits, only 3 ports. */ + UHCRHDB |= (0x7<<17); +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + UHCHR |= UHCHR_FHR; + udelay(11); + UHCHR &= ~UHCHR_FHR; + + UHCCOMS |= 1; + udelay(10); + + CKEN &= ~CKEN10_USBHOST; + + puts("Called USB STOP\n"); + return; +} + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ConXS Board */ + gd->bd->bi_arch_number = 776; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ +#if defined(CONFIG_SERIAL_MULTI) + char *console=getenv("boot_console"); + + if ((strcmp(console,"serial_btuart") == 0) || + (strcmp(console,"serial_stuart") == 0) || + (strcmp(console,"serial_ffuart") == 0)) { + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); + } else { + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + } +#endif + return 0; +} + +struct serial_device *default_serial_console (void) +{ + return &serial_ffuart_device; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c new file mode 100644 index 0000000..3d3bc00 --- /dev/null +++ b/board/trizepsiv/eeprom.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static unsigned char srom[128]; +extern u16 read_srom_word(int); +extern void write_srom_word(int offset, u16 val); + +static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int i; + + for (i=0; i < 0x40; i++) { + if (!(i % 0x10)) + printf("\n%08lx:", i); + printf(" %04x", read_srom_word(i)); + } + printf ("\n"); + return (0); +} + +static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + int offset,value; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + offset=simple_strtoul(argv[2],NULL,16); + value=simple_strtoul(argv[3],NULL,16); + if (offset > 0x40) { + printf("Wrong offset : 0x%x\n",offset); + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + write_srom_word(offset, value); + return (0); +} + +int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp (argv[1],"read") == 0) { + return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else if (strcmp (argv[1],"write") == 0) { + return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + dm9000ee,4,1,do_dm9000_eeprom, + "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "\ndm9000ee write \n" + "\tdm9000ee read \n" + "\tword:\t\t00-02 : MAC Address\n" + "\t\t\t03-07 : DM9000 Configuration\n" + "\t\t\t08-63 : User data\n"); diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S new file mode 100644 index 0000000..d886938 --- /dev/null +++ b/board/trizepsiv/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CFG_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CFG_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CFG_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CFG_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CFG_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CFG_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CFG_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CFG_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S new file mode 100644 index 0000000..5e41132 --- /dev/null +++ b/board/trizepsiv/pxavoltage.S @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr + diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds new file mode 100644 index 0000000..f010239 --- /dev/null +++ b/board/trizepsiv/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} -- cgit v1.1 From a89cbbd27a60e6740772000fd0688ffba1c2576a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 7 Sep 2007 01:21:25 +0200 Subject: Update CHANGELOG, minor coding style cleanup. --- board/trizepsiv/pxavoltage.S | 2 -- 1 file changed, 2 deletions(-) (limited to 'board') diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S index 5e41132..9659c2b 100644 --- a/board/trizepsiv/pxavoltage.S +++ b/board/trizepsiv/pxavoltage.S @@ -23,9 +23,7 @@ #include - .global initPXAvoltage initPXAvoltage: mov pc, lr - -- cgit v1.1 From 8d17979d0359492a822a0a409d26e3a3549b4cd4 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 7 Sep 2007 17:05:36 +0200 Subject: [MPC512x] Correct fixup relocation Signed-off-by: Rafal Jaworowski --- board/ads5121/u-boot.lds | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds index 038d849..34ceb0f 100644 --- a/board/ads5121/u-boot.lds +++ b/board/ads5121/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS { cpu/mpc512x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) -- cgit v1.1 From 7f1913938984ef6c6a46cb53e003719196d9c5de Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:20:23 +0200 Subject: [PPC440SPe] Improve PCIe configuration space access - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki --- board/amcc/katmai/init.S | 12 ++++++------ board/amcc/katmai/katmai.c | 9 +++++---- board/amcc/yucca/init.S | 12 ++++++------ board/amcc/yucca/yucca.c | 9 +++++---- 4 files changed, 22 insertions(+), 20 deletions(-) (limited to 'board') diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 5202ae6..e3f3da6 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -67,9 +67,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -109,9 +109,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index b804d55..a9ae4a3 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -392,7 +392,7 @@ int katmai_pcie_card_present(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -401,7 +401,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for katmai card presence */ if (!katmai_pcie_card_present(i)) @@ -418,8 +418,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -443,6 +443,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index c92dcf7..67e8f8f 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -70,9 +70,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -112,9 +112,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d08fcf3..252e4fe 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -846,7 +846,7 @@ void yucca_setup_pcie_fpga_endpoint(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -855,7 +855,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) @@ -874,8 +874,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -899,6 +899,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } -- cgit v1.1 From 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:35:37 +0200 Subject: [PPC440SPe] PCIe environment settings for Katmai and Yucca - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki --- board/amcc/katmai/katmai.c | 12 ++++++++++++ board/amcc/yucca/yucca.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) (limited to 'board') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index a9ae4a3..afd60ec 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -396,6 +396,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -439,6 +441,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 252e4fe..397b018 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -850,6 +850,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -895,6 +897,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ -- cgit v1.1 From 38ad82da0c1180ecdeb212a8f4245e945bcc546e Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Tue, 11 Sep 2007 15:42:11 +0200 Subject: [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to scan on second pci bus. Signed-off-by: Grzegorz Bernacki --- board/stxssa/stxssa.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 5882124..9a2bfbe 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -378,9 +378,12 @@ static struct pci_config_table pci_stxgp3_config_table[] = { #endif -static struct pci_controller hose = { +static struct pci_controller hose[] = { #ifndef CONFIG_PCI_PNP - config_table: pci_stxgp3_config_table, + { config_table: pci_stxgp3_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, +#endif #endif }; @@ -393,6 +396,6 @@ pci_init_board(void) #ifdef CONFIG_PCI extern void pci_mpc85xx_init(struct pci_controller *hose); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif /* CONFIG_PCI */ } -- cgit v1.1 From f34024d4a328e6edd906456da98d2c537155c4f7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 12 Sep 2007 00:48:57 +0200 Subject: Fix memory corruption problem on STX GP3 SSA Board. Signed-off-by: Wolfgang Denk --- board/stxssa/stxssa.c | 4 +++- board/stxssa/u-boot.lds | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 9a2bfbe..9bacb98 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -381,9 +381,11 @@ static struct pci_config_table pci_stxgp3_config_table[] = { static struct pci_controller hose[] = { #ifndef CONFIG_PCI_PNP { config_table: pci_stxgp3_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 +#else {}, #endif +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif }; diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds index 95ecf66..65e1bcf 100644 --- a/board/stxssa/u-boot.lds +++ b/board/stxssa/u-boot.lds @@ -145,6 +145,7 @@ SECTIONS . = ALIGN(256); __init_end = .; + . = .; __bss_start = .; .bss : { -- cgit v1.1 From 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Thu, 13 Sep 2007 18:21:48 +0200 Subject: cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9 Signed-off-by: Marian Balakowicz --- board/cm5200/cmd_cm5200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 513c365..354f2bf 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -27,7 +27,7 @@ #include #include -#ifdef CONFIG_CMD_BSB +#ifdef CONFIG_CMD_BSP int do_i2c(char *argv[]) { -- cgit v1.1 From 66b3f24d665be678a9dbb125b1e84185400f63b5 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Sat, 15 Sep 2007 11:55:42 +0200 Subject: Make DECLARE_GLOBAL_DATA_PTR global for DaVinci As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not function local. Signed-off-by: Dirk Behme [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805 --- board/davinci/dv-evm/dv_board.c | 6 ++---- board/davinci/schmoogie/dv_board.c | 6 ++---- board/davinci/sonata/dv_board.c | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) (limited to 'board') diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c index 604edb5..dce821b 100644 --- a/board/davinci/dv-evm/dv_board.c +++ b/board/davinci/dv-evm/dv_board.c @@ -31,6 +31,8 @@ #define MACH_TYPE_DAVINCI_EVM 901 +DECLARE_GLOBAL_DATA_PTR; + extern void i2c_init(int speed, int slaveaddr); extern void timer_init(void); extern int eth_hw_init(void); @@ -115,8 +117,6 @@ void dsp_on(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM; @@ -202,8 +202,6 @@ int misc_init_r (void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c index 9f271a1..0a07523 100644 --- a/board/davinci/schmoogie/dv_board.c +++ b/board/davinci/schmoogie/dv_board.c @@ -31,6 +31,8 @@ #define MACH_TYPE_SCHMOOGIE 1255 +DECLARE_GLOBAL_DATA_PTR; + extern void i2c_init(int speed, int slaveaddr); extern void timer_init(void); extern int eth_hw_init(void); @@ -115,8 +117,6 @@ void dsp_on(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; @@ -244,8 +244,6 @@ int misc_init_r (void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c index 99857c4..cd2dac6 100644 --- a/board/davinci/sonata/dv_board.c +++ b/board/davinci/sonata/dv_board.c @@ -31,6 +31,8 @@ #define MACH_TYPE_SONATA 1254 +DECLARE_GLOBAL_DATA_PTR; + extern void i2c_init(int speed, int slaveaddr); extern void timer_init(void); extern int eth_hw_init(void); @@ -115,8 +117,6 @@ void dsp_on(void) int board_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number of the board */ gd->bd->bi_arch_number = MACH_TYPE_SONATA; @@ -199,8 +199,6 @@ int misc_init_r (void) int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -- cgit v1.1 From 1218abf1b5817a39a82399b4b928b00750575bda Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 15 Sep 2007 20:48:41 +0200 Subject: Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global Signed-off-by: Wolfgang Denk --- board/amcc/katmai/katmai.c | 4 ++-- board/amcc/taishan/taishan.c | 4 ++-- board/amcc/yucca/yucca.c | 4 ++-- board/bf533-ezkit/bf533-ezkit.c | 3 ++- board/bf533-stamp/bf533-stamp.c | 3 ++- board/bf537-stamp/bf537-stamp.c | 3 ++- board/bf561-ezkit/bf561-ezkit.c | 3 ++- board/freescale/mpc8313erdb/sdram.c | 3 ++- board/lpc2292sodimm/lpc2292sodimm.c | 7 +------ board/mpc7448hpc2/mpc7448hpc2.c | 4 ++-- board/mpc7448hpc2/tsi108_init.c | 4 ++-- board/mpl/vcma9/cmd_vcma9.c | 4 ++-- board/sbc2410x/sbc2410x.c | 5 +---- board/siemens/SMN42/smn42.c | 7 +------ board/tqm5200/tqm5200.c | 4 ++-- 15 files changed, 27 insertions(+), 35 deletions(-) (limited to 'board') diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index afd60ec..a49066f 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -34,6 +34,8 @@ #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ +DECLARE_GLOBAL_DATA_PTR; + int ppc440spe_init_pcie_rootport(int port); void ppc440spe_setup_pcie(struct pci_controller *hose, int port); @@ -322,8 +324,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index bc976c7..f00397e 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -32,6 +32,8 @@ void show_reset_reg(void); #endif +DECLARE_GLOBAL_DATA_PTR; + int lcd_init(void); int board_early_init_f (void) @@ -266,8 +268,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 397b018..d7cc384 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -34,6 +34,8 @@ #include "yucca.h" #include "../cpu/ppc4xx/440spe_pcie.h" +DECLARE_GLOBAL_DATA_PTR; + #undef PCIE_ENDPOINT /* #define PCIE_ENDPOINT 1 */ @@ -668,8 +670,6 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { - DECLARE_GLOBAL_DATA_PTR; - /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 1dd4a3f..98ed6f8 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -30,6 +30,8 @@ #include "psd4256.h" #endif +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { #if (BFIN_CPU == ADSP_BF531) @@ -46,7 +48,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index b9dff99..69e425b 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -30,6 +30,8 @@ #include #include "bf533-stamp.h" +DECLARE_GLOBAL_DATA_PTR; + #define STATUS_LED_OFF 0 #define STATUS_LED_ON 1 @@ -55,7 +57,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG printf("SDRAM attributes:\n"); printf diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 919cef6..b3d8bda 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,8 @@ #include #include "ether_bf537.h" +DECLARE_GLOBAL_DATA_PTR; + #define POST_WORD_ADDR 0xFF903FFC /* @@ -132,7 +134,6 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 989b019..2ff44a7 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -29,6 +29,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int checkboard(void) { printf("CPU: ADSP BF561\n"); @@ -39,7 +41,6 @@ int checkboard(void) long int initdram(int board_type) { - DECLARE_GLOBAL_DATA_PTR; #ifdef DEBUG int brate; char *tmp = getenv("baudrate"); diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index e6e8410..16ec4bb 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -33,10 +33,11 @@ #include +DECLARE_GLOBAL_DATA_PTR; + #ifndef CFG_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { - DECLARE_GLOBAL_DATA_PTR; u32 magic = *(u32 *)0; typedef void (*func_t)(void); diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c index d212c63..9c2d1af 100644 --- a/board/lpc2292sodimm/lpc2292sodimm.c +++ b/board/lpc2292sodimm/lpc2292sodimm.c @@ -28,8 +28,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations @@ -37,8 +36,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* Activate LED flasher */ IO_LEDFLSH = 0x40; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index 63c99de..81846eb 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -38,6 +38,8 @@ extern void ft_cpu_setup (void *blob, bd_t *bd); #undef DEBUG +DECLARE_GLOBAL_DATA_PTR; + extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern void tsi108_init_f (void); @@ -46,8 +48,6 @@ int display_mem_map (void); void after_reloc (ulong dest_addr) { - DECLARE_GLOBAL_DATA_PTR; - /* * Jump to the main U-Boot board init code */ diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index 8a7efef..30ae17d 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -33,6 +33,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void mpicInit (int verbose); /* @@ -141,7 +143,6 @@ unsigned long get_board_bus_clk (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; ulong i; gd->mem_clk = 0; @@ -583,7 +584,6 @@ unsigned long get_l2cr (void) int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 44b4112..227c492 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -40,6 +40,8 @@ static uchar cs8900_chksum(ushort data) #endif +DECLARE_GLOBAL_DATA_PTR; + extern void print_vcma9_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); @@ -53,8 +55,6 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - DECLARE_GLOBAL_DATA_PTR; - if (strcmp(argv[1], "info") == 0) { print_vcma9_info(); diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index b4865e1..6c894a3 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -35,7 +35,7 @@ #include #endif -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; #define FCLK_SPEED 1 @@ -74,7 +74,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -128,8 +127,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/siemens/SMN42/smn42.c b/board/siemens/SMN42/smn42.c index cbfc76c..52d1d7e 100644 --- a/board/siemens/SMN42/smn42.c +++ b/board/siemens/SMN42/smn42.c @@ -31,8 +31,7 @@ #include #include -/* ------------------------------------------------------------------------- */ - +DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initialisations @@ -40,8 +39,6 @@ int board_init (void) { - DECLARE_GLOBAL_DATA_PTR; - /* arch number MACH_TYPE_ARMADILLO - not official*/ gd->bd->bi_arch_number = 83; @@ -53,8 +50,6 @@ int board_init (void) int dram_init (void) { - DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 21f67aa..29d6f00 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -43,6 +43,8 @@ #include "mt48lc16m16a2-75.h" #endif +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_PS2MULT void ps2mult_early_init(void); #endif @@ -477,8 +479,6 @@ int silent_boot (void) int board_early_init_f (void) { - DECLARE_GLOBAL_DATA_PTR; - if (silent_boot()) gd->flags |= GD_FLG_SILENT; -- cgit v1.1 From 314d5b6ce52a4ed19dd295d1364e246c5e605017 Mon Sep 17 00:00:00 2001 From: Liew Tsi Chung-r5aahp Date: Thu, 13 Sep 2007 16:04:05 -0700 Subject: ColdFire: Fix build error caused by pixis.c Moved the #include inside the #ifdef CONFIG_FSL_PIXIS. Signed-off-by: TsiChungLiew --- board/freescale/common/pixis.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index ae4bef1..fd99a93 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -25,10 +25,9 @@ #include #include #include -#include #ifdef CONFIG_FSL_PIXIS - +#include #include "pixis.h" -- cgit v1.1 From dcb88630290d2bcd803386dd4c2be73142994c4f Mon Sep 17 00:00:00 2001 From: Liew Tsi Chung-r5aahp Date: Thu, 13 Sep 2007 16:06:05 -0700 Subject: ColdFire: fix build error becasue of bad type of mii_init() Signed-off-by: TsiChungLiew --- board/freescale/m5235evb/mii.c | 2 +- board/freescale/m5329evb/mii.c | 2 +- board/freescale/m54455evb/mii.c | 2 +- board/m5271evb/mii.c | 2 +- board/m5272c3/mii.c | 2 +- board/m5282evb/mii.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c index 58fabdf..1fd4d99 100644 --- a/board/freescale/m5235evb/mii.c +++ b/board/freescale/m5235evb/mii.c @@ -204,7 +204,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c index 31f1510..8f6abf3 100644 --- a/board/freescale/m5329evb/mii.c +++ b/board/freescale/m5329evb/mii.c @@ -203,7 +203,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c index c067183..7a59aa0 100644 --- a/board/freescale/m54455evb/mii.c +++ b/board/freescale/m54455evb/mii.c @@ -221,7 +221,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5271evb/mii.c b/board/m5271evb/mii.c index f6c63c3..3830ce7 100644 --- a/board/m5271evb/mii.c +++ b/board/m5271evb/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5272c3/mii.c b/board/m5272c3/mii.c index fadcbb3..0ecc44a 100644 --- a/board/m5272c3/mii.c +++ b/board/m5272c3/mii.c @@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { diff --git a/board/m5282evb/mii.c b/board/m5282evb/mii.c index ebd3ed9..d7c6d1f 100644 --- a/board/m5282evb/mii.c +++ b/board/m5282evb/mii.c @@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -int mii_init(void) __attribute__((weak,alias("__mii_init"))); +void mii_init(void) __attribute__((weak,alias("__mii_init"))); void __mii_init(void) { -- cgit v1.1 From 67c31036acaaaa992fc346cc89db0909a7e733c4 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 16 Sep 2007 17:10:04 +0200 Subject: TQM8xx[LM]: Fix broken environment alignment. With recent toolchains, the environment sectors were no longer aligned to sector boundaries. The reason was a combination of two bugs: 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined for all TQM8xxL and TQM8xxM boards. But "include/common.h", where this gets defined, is not included here (and cannot be included without causing lots of problems). Added a new #define CFG_USE_PPCENV for all boards which really want to put the environment is a ".ppcenv" section. 2) The linker scripts just include environment.o, silently assuming that the objects in that file are really in the order in which they are coded in the C file, i. e. "environment" first, then "redundand_environment", and "env_size" last. However, current toolchains (GCC-4.x) reorder the objects, causing the environment data not to start on a flash sector boundary: Instead of: we got: 40008000 T environment 40008000 T env_size 4000c000 T redundand_environment 40008004 T redundand_environment 40010000 T env_size 4000c004 T environment Note: this patch fixes just the first part, and cures the alignment problem by making sure that "env_size" gets placed correctly. However, we still have a potential issue because primary and redundant environment sectors are actually swapped, i. e. we have now: 40008000 T redundand_environment 4000c000 T environment 40010000 T env_size This shall be fixed in the next version. Signed-off-by: Wolfgang Denk --- board/fads/fads.h | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/fads/fads.h b/board/fads/fads.h index a7fe2e9..dea8a0d 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -229,6 +229,7 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #define CFG_DIRECT_FLASH_TFTP -- cgit v1.1