From 9660c5de74aae900077c3769d7d18b39a124d9d5 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 22 Oct 2010 00:20:22 -0500 Subject: xes: Use common PCI initialization code Common Freescale code for PCI initialization now exists, so migrate X-ES boards to use it. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/xes/common/fsl_8xxx_pci.c | 328 ++++++---------------------------------- 1 file changed, 49 insertions(+), 279 deletions(-) (limited to 'board') diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index ece7882..f425cee 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -25,10 +25,10 @@ #include #include #include +#include #include #include -int first_free_busno = 0; #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; @@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -#ifdef CONFIG_MPC8572 -/* Correlate host/agent POR bits to usable info. Table 4-14 */ -struct host_agent_cfg_t { - uchar pcie_root[3]; - uchar rio_host; -} host_agent_cfg[8] = { - {{0, 0, 0}, 0}, - {{0, 1, 1}, 1}, - {{1, 0, 1}, 0}, - {{1, 1, 0}, 1}, - {{0, 0, 1}, 0}, - {{0, 1, 0}, 1}, - {{1, 0, 0}, 0}, - {{1, 1, 1}, 1} -}; - -/* Correlate port width POR bits to usable info. Table 4-15 */ -struct io_port_cfg_t { - uchar pcie_width[3]; - uchar rio_width; -} io_port_cfg[16] = { - {{0, 0, 0}, 0}, - {{0, 0, 0}, 0}, - {{4, 0, 0}, 0}, - {{4, 4, 0}, 0}, - {{0, 0, 0}, 0}, - {{0, 0, 0}, 0}, - {{0, 0, 0}, 4}, - {{4, 2, 2}, 0}, - {{0, 0, 0}, 0}, - {{0, 0, 0}, 0}, - {{0, 0, 0}, 0}, - {{4, 0, 0}, 4}, - {{4, 0, 0}, 4}, - {{0, 0, 0}, 4}, - {{0, 0, 0}, 4}, - {{8, 0, 0}, 0}, -}; -#elif defined CONFIG_MPC8548 -/* Correlate host/agent POR bits to usable info. Table 4-12 */ -struct host_agent_cfg_t { - uchar pci_host[2]; - uchar pcie_root[1]; - uchar rio_host; -} host_agent_cfg[8] = { - {{1, 1}, {0}, 0}, - {{1, 1}, {1}, 0}, - {{1, 1}, {0}, 1}, - {{0, 0}, {0}, 0}, /* reserved */ - {{0, 1}, {1}, 0}, - {{1, 1}, {1}, 0}, - {{0, 1}, {1}, 1}, - {{1, 1}, {1}, 1} -}; - -/* Correlate port width POR bits to usable info. Table 4-13 */ -struct io_port_cfg_t { - uchar pcie_width[1]; - uchar rio_width; -} io_port_cfg[8] = { - {{0}, 0}, - {{0}, 0}, - {{0}, 0}, - {{4}, 4}, - {{4}, 4}, - {{0}, 4}, - {{0}, 4}, - {{8}, 0}, -}; -#elif defined CONFIG_MPC86xx -/* Correlate host/agent POR bits to usable info. Table 4-17 */ -struct host_agent_cfg_t { - uchar pcie_root[2]; - uchar rio_host; -} host_agent_cfg[8] = { - {{0, 0}, 0}, - {{1, 0}, 1}, - {{0, 1}, 0}, - {{1, 1}, 1} -}; - -/* Correlate port width POR bits to usable info. Table 4-16 */ -struct io_port_cfg_t { - uchar pcie_width[2]; - uchar rio_width; -} io_port_cfg[16] = { - {{0, 0}, 0}, - {{0, 0}, 0}, - {{8, 0}, 0}, - {{8, 8}, 0}, - {{0, 0}, 0}, - {{8, 0}, 4}, - {{8, 0}, 4}, - {{8, 0}, 4}, - {{0, 0}, 0}, - {{0, 0}, 4}, - {{0, 0}, 4}, - {{0, 0}, 4}, - {{0, 0}, 0}, - {{0, 0}, 0}, - {{0, 8}, 0}, - {{8, 8}, 0}, -}; -#endif - /* * 85xx and 86xx share naming conventions, but different layout. * Correlate names to CPU-specific values to share common @@ -173,22 +68,22 @@ struct io_port_cfg_t { void pci_init_board(void) { - struct pci_controller *hose; - volatile ccsr_fsl_pci_t *pci; - int width; - int host; + struct fsl_pci_info pci_info[3]; + int first_free_busno = 0; + int num = 0; + int pcie_ep; + __maybe_unused int pcie_configured; + #if defined(CONFIG_MPC85xx) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #elif defined(CONFIG_MPC86xx) immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; #endif - uint devdisr = in_be32(&gur->devdisr); - uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >> + u32 devdisr = in_be32(&gur->devdisr); + u32 pordevsr = in_be32(&gur->pordevsr); + __maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >> MPC8xxx_PORDEVSR_IO_SEL_SHIFT; - uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >> - MPC8xxx_PORBMSR_HA_SHIFT; - struct pci_region *r; #ifdef CONFIG_PCI1 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; @@ -197,49 +92,19 @@ void pci_init_board(void) uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; - width = 0; /* Silence compiler warning... */ - io_sel &= 0xf; /* Silence compiler warning... */ - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - hose = &pci1_hose; - host = host_agent_cfg[host_agent].pci_host[0]; - r = hose->regions; - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", pci_32 ? 32 : 64, pcix ? "PCIX" : "PCI", pci_spd_norm ? ">=" : "<=", pcix ? freq * 2 : freq, - host ? "host" : "agent", + pcie_ep ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - /* Unlock inbound PCI configuration cycles */ - if (!host) - fsl_pci_config_unlock(hose); - - first_free_busno = hose->last_busno + 1; - printf(" PCI1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf(" PCI1: disabled\n"); } @@ -247,148 +112,53 @@ void pci_init_board(void) /* PCI1 not present on MPC8572 */ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); #endif -#ifdef CONFIG_PCIE1 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - hose = &pcie1_hose; - host = host_agent_cfg[host_agent].pcie_root[0]; - width = io_port_cfg[io_sel].pcie_width[0]; - r = hose->regions; - - if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { - printf("\n PCIE1 connected as %s (x%d)", - host ? "Root Complex" : "Endpoint", width); - if (in_be32(&pci->pme_msg_det)) { - out_be32(&pci->pme_msg_det, 0xffffffff); - debug(" with errors. Clearing. Now 0x%08x", - in_be32(&pci->pme_msg_det)); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - /* Unlock inbound PCI configuration cycles */ - if (!host) - fsl_pci_config_unlock(hose); - - first_free_busno = hose->last_busno + 1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); +#ifdef CONFIG_PCIE1 + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected as %s\n", + pcie_ep ? "Endpoint" : "Root Complex"); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf(" PCIE1: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1); #endif /* CONFIG_PCIE1 */ #ifdef CONFIG_PCIE2 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - hose = &pcie2_hose; - host = host_agent_cfg[host_agent].pcie_root[1]; - width = io_port_cfg[io_sel].pcie_width[1]; - r = hose->regions; - - if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { - printf("\n PCIE2 connected as %s (x%d)", - host ? "Root Complex" : "Endpoint", width); - if (in_be32(&pci->pme_msg_det)) { - out_be32(&pci->pme_msg_det, 0xffffffff); - debug(" with errors. Clearing. Now 0x%08x", - in_be32(&pci->pme_msg_det)); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - /* Unlock inbound PCI configuration cycles */ - if (!host) - fsl_pci_config_unlock(hose); - - first_free_busno = hose->last_busno + 1; - printf(" PCIE2 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected as %s\n", + pcie_ep ? "Endpoint" : "Root Complex"); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf(" PCIE2: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2); #endif /* CONFIG_PCIE2 */ #ifdef CONFIG_PCIE3 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - hose = &pcie3_hose; - host = host_agent_cfg[host_agent].pcie_root[2]; - width = io_port_cfg[io_sel].pcie_width[2]; - r = hose->regions; - - if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { - printf("\n PCIE3 connected as %s (x%d)", - host ? "Root Complex" : "Endpoint", width); - if (in_be32(&pci->pme_msg_det)) { - out_be32(&pci->pme_msg_det, 0xffffffff); - debug(" with errors. Clearing. Now 0x%08x", - in_be32(&pci->pme_msg_det)); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BASE, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - /* Unlock inbound PCI configuration cycles */ - if (!host) - fsl_pci_config_unlock(hose); - - first_free_busno = hose->last_busno + 1; - printf(" PCIE3 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + + if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf(" PCIE3 connected as %s\n", + pcie_ep ? "Endpoint" : "Root Complex"); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); + } else { + printf(" PCIE3: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3); -- cgit v1.1 From 92af6549b8c52e9c973e4e197aa4d1edf4df5803 Mon Sep 17 00:00:00 2001 From: John Schmoller Date: Fri, 22 Oct 2010 00:20:24 -0500 Subject: xes: Consolidate checkboard() Create a common checkboard() function to support all X-ES's Freescale boards. Also, add a get_board_derivative() function which reads hardware strapping resistors to determine what model a board is. This allows one U-Boot image to support multiple boards. Signed-off-by: John Schmoller Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/xes/common/Makefile | 2 ++ board/xes/common/board.c | 64 +++++++++++++++++++++++++++++++++++++ board/xes/common/fsl_8xxx_misc.c | 47 +++++++++++++++++++++++++++ board/xes/common/fsl_8xxx_misc.h | 28 ++++++++++++++++ board/xes/xpedite5170/xpedite5170.c | 20 +----------- board/xes/xpedite5200/xpedite5200.c | 27 ---------------- board/xes/xpedite5370/xpedite5370.c | 20 ------------ 7 files changed, 142 insertions(+), 66 deletions(-) create mode 100644 board/xes/common/board.c create mode 100644 board/xes/common/fsl_8xxx_misc.c create mode 100644 board/xes/common/fsl_8xxx_misc.h (limited to 'board') diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index d022831..bfade31 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,6 +33,8 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o +COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o +COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/xes/common/board.c b/board/xes/common/board.c new file mode 100644 index 0000000..738f0a6 --- /dev/null +++ b/board/xes/common/board.c @@ -0,0 +1,64 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include "fsl_8xxx_misc.h" + +int checkboard(void) +{ + char name[] = CONFIG_SYS_BOARD_NAME; + char *s; + +#ifdef CONFIG_SYS_FORM_CUSTOM + s = "Custom"; +#elif CONFIG_SYS_FORM_6U_CPCI + s = "6U CompactPCI"; +#elif CONFIG_SYS_FORM_ATCA_PMC + s = "ATCA w/PMC"; +#elif CONFIG_SYS_FORM_ATCA_AMC + s = "ATCA w/AMC"; +#elif CONFIG_SYS_FORM_VME + s = "VME"; +#elif CONFIG_SYS_FORM_6U_VPX + s = "6U VPX"; +#elif CONFIG_SYS_FORM_PMC + s = "PMC"; +#elif CONFIG_SYS_FORM_PCI + s = "PCI"; +#elif CONFIG_SYS_FORM_3U_CPCI + s = "3U CompactPCI"; +#elif CONFIG_SYS_FORM_AMC + s = "AdvancedMC"; +#elif CONFIG_SYS_FORM_XMC + s = "XMC"; +#elif CONFIG_SYS_FORM_PMC_XMC + s = "PMC/XMC"; +#elif CONFIG_SYS_FORM_PCI_EXPRESS + s = "PCI Express"; +#elif CONFIG_SYS_FORM_3U_VPX + s = "3U VPX"; +#else +#error "Form factor not defined" +#endif + + name[strlen(name) - 1] += get_board_derivative(); + printf("Board: X-ES %s %s SBC\n", name, s); + + /* Display board specific information */ + puts(" "); + if ((s = getenv("board_rev"))) + printf("Rev %s, ", s); + if ((s = getenv("serial#"))) + printf("Serial# %s, ", s); + if ((s = getenv("board_cfg"))) + printf("Cfg %s", s); + puts("\n"); + + return 0; +} diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c new file mode 100644 index 0000000..e37a3c1 --- /dev/null +++ b/board/xes/common/fsl_8xxx_misc.c @@ -0,0 +1,47 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * Return a board's derivative model number. For example: + * return 2 for the XPedite5372 and return 1 for the XPedite5201. + */ +uint get_board_derivative(void) +{ +#if defined(CONFIG_MPC85xx) + volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#elif defined(CONFIG_MPC86xx) + volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; +#endif + + /* + * The top 4 lines of the local bus address are pulled low/high and + * can be read to determine the least significant digit of a board's + * model number. + */ + return gur->gpporcr >> 28; +} + + diff --git a/board/xes/common/fsl_8xxx_misc.h b/board/xes/common/fsl_8xxx_misc.h new file mode 100644 index 0000000..ecc70da --- /dev/null +++ b/board/xes/common/fsl_8xxx_misc.h @@ -0,0 +1,28 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_8XXX_MISC_H___ +#define __FSL_8XXX_MISC_H___ + +uint get_board_derivative(void); + +#endif /* __FSL_8XXX_MISC_H__ */ diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c index 5822941..0f7fa6c 100644 --- a/board/xes/xpedite5170/xpedite5170.c +++ b/board/xes/xpedite5170/xpedite5170.c @@ -26,30 +26,12 @@ #include #include #include +#include "../common/fsl_8xxx_misc.h" #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI) extern void ft_board_pci_setup(void *blob, bd_t *bd); #endif -int checkboard(void) -{ - char *s; - - printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); - printf(" "); - s = getenv("board_rev"); - if (s) - printf("Rev %s, ", s); - s = getenv("serial#"); - if (s) - printf("Serial# %s, ", s); - s = getenv("board_cfg"); - if (s) - printf("Cfg %s", s); - printf("\n"); - - return 0; -} /* * Print out which flash was booted from and if booting from the 2nd flash, * swap flash chip selects to maintain consistent flash numbering/addresses. diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c index a2627f8..dc5c965 100644 --- a/board/xes/xpedite5200/xpedite5200.c +++ b/board/xes/xpedite5200/xpedite5200.c @@ -36,33 +36,6 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd); -int checkboard(void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - char *s; - - printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME); - printf(" "); - s = getenv("board_rev"); - if (s) - printf("Rev %s, ", s); - s = getenv("serial#"); - if (s) - printf("Serial# %s, ", s); - s = getenv("board_cfg"); - if (s) - printf("Cfg %s", s); - printf("\n"); - - out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ - out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ - out_be32(&ecm->eedr, 0xffffffff); /* Clear ecm errors */ - out_be32(&ecm->eeer, 0xffffffff); /* Enable ecm errors */ - - return 0; -} - static void flash_cs_fixup(void) { int flash_sel; diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c index 2a060c2..89fa6c7 100644 --- a/board/xes/xpedite5370/xpedite5370.c +++ b/board/xes/xpedite5370/xpedite5370.c @@ -36,26 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_board_pci_setup(void *blob, bd_t *bd); -int checkboard(void) -{ - char *s; - - printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); - printf(" "); - s = getenv("board_rev"); - if (s) - printf("Rev %s, ", s); - s = getenv("serial#"); - if (s) - printf("Serial# %s, ", s); - s = getenv("board_cfg"); - if (s) - printf("Cfg %s", s); - printf("\n"); - - return 0; -} - static void flash_cs_fixup(void) { int flash_sel; -- cgit v1.1 From 72fb68d53cfbe505319cbb4aa92a1fe7ecf3d4fb Mon Sep 17 00:00:00 2001 From: John Schmoller Date: Fri, 22 Oct 2010 00:20:25 -0500 Subject: xes: Add board_flash_wp_on() Add board_flash_wp_on() to check a pca9557 gpio pin to see if non-volatile memory write protection is enabled. Previously, write protected NOR flashes would fail initialization which resulted in a bootup error such as: ... DTT: 53 C local / 64 C remote (adt7461@4c) DTT: 54 C local (ds1621@48) FLASH: Executed from FLASH1 POST memory PASSED FLASH: ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB ## Unknown FLASH on Bank 2 - Size = 0x00000000 = 0 MB *** failed *** ### ERROR ### Please RESET the board ### With this patch, NOR flash initialization is skipped: ... DTT: 53 C local / 64 C remote (adt7461@4c) DTT: 54 C local (ds1621@48) FLASH: Executed from FLASH1 POST memory PASSED FLASH: Uninitialized - Write Protect On L2: 1024 KB enabled NAND: 1024 MiB ... Note that flash related commands such as flinfo and saveenv will error out when flash write protection is enabled. Signed-off-by: John Schmoller Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/xes/common/fsl_8xxx_misc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'board') diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index e37a3c1..b7fa695 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -22,6 +22,21 @@ #include #include +#ifdef CONFIG_PCA953X +#include + +/* + * Determine if a board's flashes are write protected + */ +int board_flash_wp_on(void) +{ + if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_NVM_WP) + return 1; + + return 0; +} +#endif /* * Return a board's derivative model number. For example: -- cgit v1.1 From c00ac259f60112bb263a73f211ce3bb8f529c2c0 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 22 Oct 2010 00:20:26 -0500 Subject: xes: Make X-ES board names more generic Some U-Boot images for X-ES boards support multiple products in the same family. For example, the XPedite5370, XPedite5371, and XPedite5372 are similar enough that one U-Boot image can work on all 3 cards. To make it clear that a U-Boot image can work on boards of the same family, rename the boards with the least significant digit of 'x'. While we're at it, change the board config file and make targets to be lowercase. Also change the default uImage and fdt filenames to "board.uImage" and "board.dtb" to be more generic. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/xes/xpedite5170/Makefile | 52 ------- board/xes/xpedite5170/ddr.c | 168 ---------------------- board/xes/xpedite5170/law.c | 52 ------- board/xes/xpedite5170/xpedite5170.c | 91 ------------ board/xes/xpedite517x/Makefile | 52 +++++++ board/xes/xpedite517x/ddr.c | 168 ++++++++++++++++++++++ board/xes/xpedite517x/law.c | 52 +++++++ board/xes/xpedite517x/xpedite517x.c | 91 ++++++++++++ board/xes/xpedite5200/Makefile | 55 -------- board/xes/xpedite5200/ddr.c | 91 ------------ board/xes/xpedite5200/law.c | 51 ------- board/xes/xpedite5200/tlb.c | 85 ------------ board/xes/xpedite5200/xpedite5200.c | 96 ------------- board/xes/xpedite520x/Makefile | 55 ++++++++ board/xes/xpedite520x/ddr.c | 91 ++++++++++++ board/xes/xpedite520x/law.c | 51 +++++++ board/xes/xpedite520x/tlb.c | 85 ++++++++++++ board/xes/xpedite520x/xpedite520x.c | 96 +++++++++++++ board/xes/xpedite5370/Makefile | 45 ------ board/xes/xpedite5370/ddr.c | 270 ------------------------------------ board/xes/xpedite5370/law.c | 54 -------- board/xes/xpedite5370/tlb.c | 99 ------------- board/xes/xpedite5370/xpedite5370.c | 107 -------------- board/xes/xpedite537x/Makefile | 45 ++++++ board/xes/xpedite537x/ddr.c | 270 ++++++++++++++++++++++++++++++++++++ board/xes/xpedite537x/law.c | 54 ++++++++ board/xes/xpedite537x/tlb.c | 99 +++++++++++++ board/xes/xpedite537x/xpedite537x.c | 107 ++++++++++++++ 28 files changed, 1316 insertions(+), 1316 deletions(-) delete mode 100644 board/xes/xpedite5170/Makefile delete mode 100644 board/xes/xpedite5170/ddr.c delete mode 100644 board/xes/xpedite5170/law.c delete mode 100644 board/xes/xpedite5170/xpedite5170.c create mode 100644 board/xes/xpedite517x/Makefile create mode 100644 board/xes/xpedite517x/ddr.c create mode 100644 board/xes/xpedite517x/law.c create mode 100644 board/xes/xpedite517x/xpedite517x.c delete mode 100644 board/xes/xpedite5200/Makefile delete mode 100644 board/xes/xpedite5200/ddr.c delete mode 100644 board/xes/xpedite5200/law.c delete mode 100644 board/xes/xpedite5200/tlb.c delete mode 100644 board/xes/xpedite5200/xpedite5200.c create mode 100644 board/xes/xpedite520x/Makefile create mode 100644 board/xes/xpedite520x/ddr.c create mode 100644 board/xes/xpedite520x/law.c create mode 100644 board/xes/xpedite520x/tlb.c create mode 100644 board/xes/xpedite520x/xpedite520x.c delete mode 100644 board/xes/xpedite5370/Makefile delete mode 100644 board/xes/xpedite5370/ddr.c delete mode 100644 board/xes/xpedite5370/law.c delete mode 100644 board/xes/xpedite5370/tlb.c delete mode 100644 board/xes/xpedite5370/xpedite5370.c create mode 100644 board/xes/xpedite537x/Makefile create mode 100644 board/xes/xpedite537x/ddr.c create mode 100644 board/xes/xpedite537x/law.c create mode 100644 board/xes/xpedite537x/tlb.c create mode 100644 board/xes/xpedite537x/xpedite537x.c (limited to 'board') diff --git a/board/xes/xpedite5170/Makefile b/board/xes/xpedite5170/Makefile deleted file mode 100644 index fea6686..0000000 --- a/board/xes/xpedite5170/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude ($obj).depend - -######################################################################### diff --git a/board/xes/xpedite5170/ddr.c b/board/xes/xpedite5170/ddr.c deleted file mode 100644 index 1d57d09..0000000 --- a/board/xes/xpedite5170/ddr.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright 2009 Extreme Engineering Solutions, Inc. - * Copyright 2007-2008 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, - sizeof(ddr2_spd_eeprom_t)); -} - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; -#ifdef SPD_EEPROM_ADDRESS2 - } else if (ctrl_num == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; -#endif - } else { - /* An inalid ctrl number was give, use default SPD */ - printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num); - i2c_address = SPD_EEPROM_ADDRESS1; - } - - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -/* - * There are four board-specific SDRAM timing parameters which must be - * calculated based on the particular PCB artwork. These are: - * 1.) CPO (Read Capture Delay) - * - TIMING_CFG_2 register - * Source: Calculation based on board trace lengths and - * chip-specific internal delays. - * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) - * - TIMING_CFG_2 register - * Source: Calculation based on board trace lengths. - * Unless clock and DQ lanes are very different - * lengths (>2"), this should be set to the nominal value - * of 1/2 clock delay. - * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) - * - DDR_SDRAM_CLK_CNTL register - * Source: Signal Integrity Simulations - * 4.) 2T Timing on Addr/Ctl - * - TIMING_CFG_2 register - * Source: Signal Integrity Simulations - * Usually only needed with heavy load/very high speed (>DDR2-800) - * - * PCB routing on the XPedite5170 is nearly identical to the XPedite5370 - * so we use the XPedite5370 settings as a basis for the XPedite5170. - */ - -typedef struct board_memctl_options { - uint16_t datarate_mhz_low; - uint16_t datarate_mhz_high; - uint8_t clk_adjust; - uint8_t cpo_override; - uint8_t write_data_delay; -} board_memctl_options_t; - -static struct board_memctl_options bopts_ctrl[][2] = { - { - /* Controller 0 */ - { - /* DDR2 600/667 */ - .datarate_mhz_low = 500, - .datarate_mhz_high = 750, - .clk_adjust = 5, - .cpo_override = 8, - .write_data_delay = 2, - }, - { - /* DDR2 800 */ - .datarate_mhz_low = 750, - .datarate_mhz_high = 850, - .clk_adjust = 5, - .cpo_override = 9, - .write_data_delay = 2, - }, - }, - { - /* Controller 1 */ - { - /* DDR2 600/667 */ - .datarate_mhz_low = 500, - .datarate_mhz_high = 750, - .clk_adjust = 5, - .cpo_override = 7, - .write_data_delay = 2, - }, - { - /* DDR2 800 */ - .datarate_mhz_low = 750, - .datarate_mhz_high = 850, - .clk_adjust = 5, - .cpo_override = 8, - .write_data_delay = 2, - }, - }, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; - sys_info_t sysinfo; - int i; - unsigned int datarate; - - get_sys_info(&sysinfo); - datarate = fsl_ddr_get_mem_data_rate() / 1000000; - - for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { - if ((bopts[i].datarate_mhz_low <= datarate) && - (bopts[i].datarate_mhz_high >= datarate)) { - debug("controller %d:\n", ctrl_num); - debug(" clk_adjust = %d\n", bopts[i].clk_adjust); - debug(" cpo = %d\n", bopts[i].cpo_override); - debug(" write_data_delay = %d\n", - bopts[i].write_data_delay); - popts->clk_adjust = bopts[i].clk_adjust; - popts->cpo_override = bopts[i].cpo_override; - popts->write_data_delay = bopts[i].write_data_delay; - } - } - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/xes/xpedite5170/law.c b/board/xes/xpedite5170/law.c deleted file mode 100644 index 0b7d9ef..0000000 --- a/board/xes/xpedite5170/law.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Notes: - * CCSRBAR don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE - /* NAND LAW covers 2 NAND flashes */ - SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC), -#endif -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), -#endif -#ifdef CONFIG_SYS_PCIE2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5170/xpedite5170.c b/board/xes/xpedite5170/xpedite5170.c deleted file mode 100644 index 0f7fa6c..0000000 --- a/board/xes/xpedite5170/xpedite5170.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2009 Extreme Engineering Solutions, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include "../common/fsl_8xxx_misc.h" - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI) -extern void ft_board_pci_setup(void *blob, bd_t *bd); -#endif - -/* - * Print out which flash was booted from and if booting from the 2nd flash, - * swap flash chip selects to maintain consistent flash numbering/addresses. - */ -static void flash_cs_fixup(void) -{ - int flash_sel; - - /* - * Print boot dev and swap flash flash chip selects if booted from 2nd - * flash. Swapping chip selects presents user with a common memory - * map regardless of which flash was booted from. - */ - flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & - CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); - printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); - - if (flash_sel) { - set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); - set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - - set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); - set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); - } -} - -int board_early_init_r(void) -{ - /* Initialize PCA9557 devices */ - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); - - flash_cs_fixup(); - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_PCI - ft_board_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); -} -#endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile new file mode 100644 index 0000000..fea6686 --- /dev/null +++ b/board/xes/xpedite517x/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c new file mode 100644 index 0000000..1d57d09 --- /dev/null +++ b/board/xes/xpedite517x/ddr.c @@ -0,0 +1,168 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_bus_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) { + i2c_address = SPD_EEPROM_ADDRESS1; +#ifdef SPD_EEPROM_ADDRESS2 + } else if (ctrl_num == 1) { + i2c_address = SPD_EEPROM_ADDRESS2; +#endif + } else { + /* An inalid ctrl number was give, use default SPD */ + printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num); + i2c_address = SPD_EEPROM_ADDRESS1; + } + + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * PCB routing on the XPedite5170 is nearly identical to the XPedite5370 + * so we use the XPedite5370 settings as a basis for the XPedite5170. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = fsl_ddr_get_mem_data_rate() / 1000000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c new file mode 100644 index 0000000..0b7d9ef --- /dev/null +++ b/board/xes/xpedite517x/law.c @@ -0,0 +1,52 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE + /* NAND LAW covers 2 NAND flashes */ + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c new file mode 100644 index 0000000..0f7fa6c --- /dev/null +++ b/board/xes/xpedite517x/xpedite517x.c @@ -0,0 +1,91 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "../common/fsl_8xxx_misc.h" + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI) +extern void ft_board_pci_setup(void *blob, bd_t *bd); +#endif + +/* + * Print out which flash was booted from and if booting from the 2nd flash, + * swap flash chip selects to maintain consistent flash numbering/addresses. + */ +static void flash_cs_fixup(void) +{ + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); + + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite5200/Makefile deleted file mode 100644 index 02fe8fc..0000000 --- a/board/xes/xpedite5200/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# Copyright 2008 Extreme Engineering Solutions, Inc. -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite5200/ddr.c deleted file mode 100644 index c5616d5..0000000 --- a/board/xes/xpedite5200/ddr.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); - - /* We use soldered memory, but use an SPD EEPROM to describe it. - * The SPD has an unspecified dimm type, but the DDR2 initialization - * code requires a specific type to be specified. This sets the type - * as a standard unregistered SO-DIMM. */ - if (spd->dimm_type == 0) { - spd->dimm_type = 0x4; - ((uchar *)spd)[63] += 0x4; - } -} - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 9; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c deleted file mode 100644 index bbfcb9d..0000000 --- a/board/xes/xpedite5200/law.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#if CONFIG_SYS_PCI1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1), -#endif -#if CONFIG_SYS_PCI2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite5200/tlb.c deleted file mode 100644 index bd7bff8..0000000 --- a/board/xes/xpedite5200/tlb.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* W**G* - NOR flashes */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* *I*G* - NAND flash */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1M, 1), - -#if CONFIG_PCI1 - /* *I*G* - PCI MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), -#endif - -#if CONFIG_PCI2 - /* *I*G* - PCI MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), -#endif - -#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) - /* *I*G* - PCI IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_16M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c deleted file mode 100644 index dc5c965..0000000 --- a/board/xes/xpedite5200/xpedite5200.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2004, 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void ft_board_pci_setup(void *blob, bd_t *bd); - -static void flash_cs_fixup(void) -{ - int flash_sel; - - /* - * Print boot dev and swap flash flash chip selects if booted from 2nd - * flash. Swapping chip selects presents user with a common memory - * map regardless of which flash was booted from. - */ - flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & - CONFIG_SYS_PCA953X_FLASH_PASS_CS)); - printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); - - if (flash_sel) { - set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); - set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - - set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); - set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); - } -} - -int board_early_init_r(void) -{ - /* Initialize PCA9557 devices */ - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); - - /* - * Remap NOR flash region to caching-inhibited - * so that flash can be erased/programmed properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* Invalidate existing TLB entry for NOR flash */ - disable_tlb(0); - set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), - (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256M, 1); - - flash_cs_fixup(); - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_PCI - ft_board_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); -} -#endif diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile new file mode 100644 index 0000000..02fe8fc --- /dev/null +++ b/board/xes/xpedite520x/Makefile @@ -0,0 +1,55 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c new file mode 100644 index 0000000..c5616d5 --- /dev/null +++ b/board/xes/xpedite520x/ddr.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); + + /* We use soldered memory, but use an SPD EEPROM to describe it. + * The SPD has an unspecified dimm type, but the DDR2 initialization + * code requires a specific type to be specified. This sets the type + * as a standard unregistered SO-DIMM. */ + if (spd->dimm_type == 0) { + spd->dimm_type = 0x4; + ((uchar *)spd)[63] += 0x4; + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 9; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c new file mode 100644 index 0000000..bbfcb9d --- /dev/null +++ b/board/xes/xpedite520x/law.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#if CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1), +#endif +#if CONFIG_SYS_PCI2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite520x/tlb.c b/board/xes/xpedite520x/tlb.c new file mode 100644 index 0000000..bd7bff8 --- /dev/null +++ b/board/xes/xpedite520x/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#if CONFIG_PCI1 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#if CONFIG_PCI2 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) + /* *I*G* - PCI IO */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_16M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c new file mode 100644 index 0000000..dc5c965 --- /dev/null +++ b/board/xes/xpedite520x/xpedite520x.c @@ -0,0 +1,96 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +static void flash_cs_fixup(void) +{ + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); + + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite5370/Makefile deleted file mode 100644 index 919397c..0000000 --- a/board/xes/xpedite5370/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright 2008 Extreme Engineering Solutions, Inc. -# Copyright 2007 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += law.o -COBJS-y += tlb.o - -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS-y)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite5370/ddr.c deleted file mode 100644 index 4d3f255..0000000 --- a/board/xes/xpedite5370/ddr.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2008 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include -#include - -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, - sizeof(ddr2_spd_eeprom_t)); -} - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - if (ctrl_num == 1) - i2c_address = SPD_EEPROM_ADDRESS2; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -/* - * There are four board-specific SDRAM timing parameters which must be - * calculated based on the particular PCB artwork. These are: - * 1.) CPO (Read Capture Delay) - * - TIMING_CFG_2 register - * Source: Calculation based on board trace lengths and - * chip-specific internal delays. - * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) - * - TIMING_CFG_2 register - * Source: Calculation based on board trace lengths. - * Unless clock and DQ lanes are very different - * lengths (>2"), this should be set to the nominal value - * of 1/2 clock delay. - * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) - * - DDR_SDRAM_CLK_CNTL register - * Source: Signal Integrity Simulations - * 4.) 2T Timing on Addr/Ctl - * - TIMING_CFG_2 register - * Source: Signal Integrity Simulations - * Usually only needed with heavy load/very high speed (>DDR2-800) - * - * ====== XPedite5370 DDR2-600 read delay calculations ====== - * - * See Freescale's App Note AN2583 as refrence. This document also - * contains the chip-specific delays for 8548E, 8572, etc. - * - * For MPC8572E - * Minimum chip delay (Ch 0): 1.372ns - * Maximum chip delay (Ch 0): 2.914ns - * Minimum chip delay (Ch 1): 1.220ns - * Maximum chip delay (Ch 1): 2.595ns - * - * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps - * - * Minimum delay calc (Ch 0): - * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly - * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps - * = 3808ps - * = 3.808ns - * - * Maximum delay calc (Ch 0): - * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly - * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps - * = 6240ps - * = 6.240ns - * - * Minimum delay calc (Ch 1): - * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly - * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps - * = 3288ps - * = 3.288ns - * - * Maximum delay calc (Ch 1): - * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly - * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps - * = 5536ps - * = 5.536ns - * - * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) - * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) - * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) - * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) - * - * - * ====== XPedite5370 DDR2-800 read delay calculations ====== - * - * See Freescale's App Note AN2583 as refrence. This document also - * contains the chip-specific delays for 8548E, 8572, etc. - * - * For MPC8572E - * Minimum chip delay (Ch 0): 1.372ns - * Maximum chip delay (Ch 0): 2.914ns - * Minimum chip delay (Ch 1): 1.220ns - * Maximum chip delay (Ch 1): 2.595ns - * - * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps - * - * Minimum delay calc (Ch 0): - * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly - * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps - * = 3341ps - * = 3.341ns - * - * Maximum delay calc (Ch 0): - * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly - * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps - * = 5673ps - * = 5.673ns - * - * Minimum delay calc (Ch 1): - * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly - * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps - * = 2822ps - * = 2.822ns - * - * Maximum delay calc (Ch 1): - * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly - * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps - * = 4968ps - * = 4.968ns - * - * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) - * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) - * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) - * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) - * - * Write latency (WR_DATA_DELAY) is calculated by doing the following: - * - * The DDR SDRAM specification requires DQS be received no sooner than - * 75% of an SDRAM clock period—and no later than 125% of a clock - * period—from the capturing clock edge of the command/address at the - * SDRAM. - * - * Based on the above tracelengths, the following are calculated: - * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns - * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns - * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns - * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns - * - * Difference in arrival time CLK vs. DQS: - * Ch. 0 0.072ns - * Ch. 1 0.138ns - * - * Both of these values are much less than 25% of the clock - * period at DDR2-600 or DDR2-800, so no additional delay is needed over - * the 1/2 cycle which normally aligns the first DQS transition - * exactly WL (CAS latency minus one cycle) after the CAS strobe. - * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's - * terminology corresponds to exactly one clock period delay after - * the CAS strobe. (due to the fact that the "delay" is referenced - * from the *falling* edge of the CLK, just after the rising edge - * which the CAS strobe is latched on. - */ - -typedef struct board_memctl_options { - uint16_t datarate_mhz_low; - uint16_t datarate_mhz_high; - uint8_t clk_adjust; - uint8_t cpo_override; - uint8_t write_data_delay; -} board_memctl_options_t; - -static struct board_memctl_options bopts_ctrl[][2] = { - { - /* Controller 0 */ - { - /* DDR2 600/667 */ - .datarate_mhz_low = 500, - .datarate_mhz_high = 750, - .clk_adjust = 5, - .cpo_override = 8, - .write_data_delay = 2, - }, - { - /* DDR2 800 */ - .datarate_mhz_low = 750, - .datarate_mhz_high = 850, - .clk_adjust = 5, - .cpo_override = 9, - .write_data_delay = 2, - }, - }, - { - /* Controller 1 */ - { - /* DDR2 600/667 */ - .datarate_mhz_low = 500, - .datarate_mhz_high = 750, - .clk_adjust = 5, - .cpo_override = 7, - .write_data_delay = 2, - }, - { - /* DDR2 800 */ - .datarate_mhz_low = 750, - .datarate_mhz_high = 850, - .clk_adjust = 5, - .cpo_override = 8, - .write_data_delay = 2, - }, - }, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; - sys_info_t sysinfo; - int i; - unsigned int datarate; - - get_sys_info(&sysinfo); - datarate = sysinfo.freqDDRBus / 1000 / 1000; - - for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { - if ((bopts[i].datarate_mhz_low <= datarate) && - (bopts[i].datarate_mhz_high >= datarate)) { - debug("controller %d:\n", ctrl_num); - debug(" clk_adjust = %d\n", bopts[i].clk_adjust); - debug(" cpo = %d\n", bopts[i].cpo_override); - debug(" write_data_delay = %d\n", - bopts[i].write_data_delay); - popts->clk_adjust = bopts[i].clk_adjust; - popts->cpo_override = bopts[i].cpo_override; - popts->write_data_delay = bopts[i].write_data_delay; - } - } - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite5370/law.c deleted file mode 100644 index daee676..0000000 --- a/board/xes/xpedite5370/law.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), -#endif -#ifdef CONFIG_SYS_PCIE2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), -#endif -#ifdef CONFIG_SYS_PCIE3_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c deleted file mode 100644 index a465ce3..0000000 --- a/board/xes/xpedite5370/tlb.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* W**G* - NOR flashes */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* *I*G* - NAND flash */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1M, 1), - - /* **M** - Boot page for secondary processors */ - SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 3, BOOKE_PAGESZ_4K, 1), - -#ifdef CONFIG_PCIE1 - /* *I*G* - PCIe */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CONFIG_PCIE2 - /* *I*G* - PCIe */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), -#endif - -#ifdef CONFIG_PCIE3 - /* *I*G* - PCIe */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), -#endif - -#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) - /* *I*G* - PCIe */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_64M, 1), -#endif - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c deleted file mode 100644 index 89fa6c7..0000000 --- a/board/xes/xpedite5370/xpedite5370.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -extern void ft_board_pci_setup(void *blob, bd_t *bd); - -static void flash_cs_fixup(void) -{ - int flash_sel; - - /* - * Print boot dev and swap flash flash chip selects if booted from 2nd - * flash. Swapping chip selects presents user with a common memory - * map regardless of which flash was booted from. - */ - flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & - CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); - printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); - - if (flash_sel) { - set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); - set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); - - set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); - set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); - } -} - -int board_early_init_r(void) -{ - /* Initialize PCA9557 devices */ - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); - pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); - - /* - * Remap NOR flash region to caching-inhibited - * so that flash can be erased/programmed properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* Invalidate existing TLB entry for NOR flash */ - disable_tlb(0); - set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), - (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256M, 1); - - flash_cs_fixup(); - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_PCI - ft_board_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); -} -#endif - -#ifdef CONFIG_MP -extern void cpu_mp_lmb_reserve(struct lmb *lmb); - -void board_lmb_reserve(struct lmb *lmb) -{ - cpu_mp_lmb_reserve(lmb); -} -#endif diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile new file mode 100644 index 0000000..919397c --- /dev/null +++ b/board/xes/xpedite537x/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c new file mode 100644 index 0000000..4d3f255 --- /dev/null +++ b/board/xes/xpedite537x/ddr.c @@ -0,0 +1,270 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + if (ctrl_num == 1) + i2c_address = SPD_EEPROM_ADDRESS2; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * ====== XPedite5370 DDR2-600 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps + * = 3808ps + * = 3.808ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps + * = 6240ps + * = 6.240ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps + * = 3288ps + * = 3.288ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps + * = 5536ps + * = 5.536ns + * + * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) + * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) + * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) + * + * + * ====== XPedite5370 DDR2-800 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps + * = 3341ps + * = 3.341ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps + * = 5673ps + * = 5.673ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps + * = 2822ps + * = 2.822ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps + * = 4968ps + * = 4.968ns + * + * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) + * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) + * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) + * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * + * Write latency (WR_DATA_DELAY) is calculated by doing the following: + * + * The DDR SDRAM specification requires DQS be received no sooner than + * 75% of an SDRAM clock period—and no later than 125% of a clock + * period—from the capturing clock edge of the command/address at the + * SDRAM. + * + * Based on the above tracelengths, the following are calculated: + * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns + * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns + * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns + * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns + * + * Difference in arrival time CLK vs. DQS: + * Ch. 0 0.072ns + * Ch. 1 0.138ns + * + * Both of these values are much less than 25% of the clock + * period at DDR2-600 or DDR2-800, so no additional delay is needed over + * the 1/2 cycle which normally aligns the first DQS transition + * exactly WL (CAS latency minus one cycle) after the CAS strobe. + * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's + * terminology corresponds to exactly one clock period delay after + * the CAS strobe. (due to the fact that the "delay" is referenced + * from the *falling* edge of the CLK, just after the rising edge + * which the CAS strobe is latched on. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = sysinfo.freqDDRBus / 1000 / 1000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c new file mode 100644 index 0000000..daee676 --- /dev/null +++ b/board/xes/xpedite537x/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite537x/tlb.c b/board/xes/xpedite537x/tlb.c new file mode 100644 index 0000000..a465ce3 --- /dev/null +++ b/board/xes/xpedite537x/tlb.c @@ -0,0 +1,99 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + + /* **M** - Boot page for secondary processors */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 3, BOOKE_PAGESZ_4K, 1), + +#ifdef CONFIG_PCIE1 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCIE2 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_PCIE3 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c new file mode 100644 index 0000000..89fa6c7 --- /dev/null +++ b/board/xes/xpedite537x/xpedite537x.c @@ -0,0 +1,107 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +static void flash_cs_fixup(void) +{ + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); + + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif -- cgit v1.1 From bfe18815e8123f4456be8b5858b2b255d7881698 Mon Sep 17 00:00:00 2001 From: John Schmoller Date: Fri, 22 Oct 2010 00:20:34 -0500 Subject: XPedite5500 board support Initial support for Extreme Engineering Solutions XPedite5500 - a P2020-based PMC/XMC single board computer. Signed-off-by: John Schmoller Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/xes/common/Makefile | 2 + board/xes/common/fsl_8xxx_clk.c | 11 +++ board/xes/xpedite550x/Makefile | 39 +++++++++ board/xes/xpedite550x/ddr.c | 165 ++++++++++++++++++++++++++++++++++++ board/xes/xpedite550x/law.c | 54 ++++++++++++ board/xes/xpedite550x/tlb.c | 98 +++++++++++++++++++++ board/xes/xpedite550x/xpedite550x.c | 107 +++++++++++++++++++++++ 7 files changed, 476 insertions(+) create mode 100644 board/xes/xpedite550x/Makefile create mode 100644 board/xes/xpedite550x/ddr.c create mode 100644 board/xes/xpedite550x/law.c create mode 100644 board/xes/xpedite550x/tlb.c create mode 100644 board/xes/xpedite550x/xpedite550x.c (limited to 'board') diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index bfade31..16e0b66 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -32,7 +32,9 @@ LIB = $(obj)lib$(VENDOR).a COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o +COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o +COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c index f4a17b7..20d0a30 100644 --- a/board/xes/common/fsl_8xxx_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy) if (in_be32(&gur->gpporcr) & 0x10000) return 66666666; else +#ifdef CONFIG_P2020 + return 100000000; +#else return 50000000; +#endif } #ifdef CONFIG_MPC85xx @@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy) if (ddr_ratio == 0x7) return get_board_sys_clk(dummy); +#ifdef CONFIG_P2020 + if (in_be32(&gur->gpporcr) & 0x20000) + return 66666666; + else + return 100000000; +#else return 66666666; +#endif } #endif diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile new file mode 100644 index 0000000..8980a4b --- /dev/null +++ b/board/xes/xpedite550x/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c new file mode 100644 index 0000000..718cd98 --- /dev/null +++ b/board/xes/xpedite550x/ddr.c @@ -0,0 +1,165 @@ +/* + * Copyright 2010 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr3_spd_eeprom_t)); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +/* + * There are traditionally three board-specific SDRAM timing parameters + * which must be calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 3.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * ====== XPedite550x DDR3-800 read delay calculations ====== + * + * The P2020 processor provides an autoleveling option. Setting CPO to + * 0x1f enables this auto configuration. + */ + +typedef struct { + unsigned short datarate_mhz_low; + unsigned short datarate_mhz_high; + unsigned char clk_adjust; + unsigned char cpo; +} board_specific_parameters_t; + +const board_specific_parameters_t board_specific_parameters[][20] = { + { + /* Controller 0 */ + { + /* DDR3-600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo = 31, + }, + { + /* DDR3-800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo = 31, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + ulong ddr_freq; + + /* + * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 0; + } else { /* even CS */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 4; + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } + } + } + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->twoT_en = 0; + } + pbsp++; + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + + /* + * Enable on-die termination. + * From the Micron Technical Node TN-41-04, RTT_Nom should typically + * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR + * is handled in the Freescale DDR3 driver. Set RTT_Nom here. + */ + popts->rtt_override = 1; + popts->rtt_override_value = 3; +} + diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c new file mode 100644 index 0000000..4d4445d --- /dev/null +++ b/board/xes/xpedite550x/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2010 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c new file mode 100644 index 0000000..cf3ff4d --- /dev/null +++ b/board/xes/xpedite550x/tlb.c @@ -0,0 +1,98 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + + /* **M** - Boot page for secondary processors */ + SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 3, BOOKE_PAGESZ_4K, 1), + +#ifdef CONFIG_PCIE1 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCIE2 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_PCIE3 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c new file mode 100644 index 0000000..2ad30a3 --- /dev/null +++ b/board/xes/xpedite550x/xpedite550x.c @@ -0,0 +1,107 @@ +/* + * Copyright 2010 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +static void flash_cs_fixup(void) +{ + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); + + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM); + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM); + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif -- cgit v1.1