From f013dacf0a90667fbefe35580f8031a84caeb65e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 4 Dec 2005 00:40:34 +0100 Subject: Code cleanup, especially MIPS for GCC 4.x --- board/Marvell/db64360/mv_eth.c | 2 +- board/Marvell/db64460/mv_eth.c | 4 ++-- board/esd/cpci2dp/cpci2dp.c | 44 +++++++++++++++++++----------------------- board/esd/cpci750/mv_eth.c | 2 +- board/evb64260/eth_addrtbl.c | 2 +- board/incaip/flash.c | 2 +- board/incaip/incaip.c | 2 +- board/incaip/lowlevel_init.S | 9 ++++++--- board/mpc8260ads/mpc8260ads.c | 2 +- board/prodrive/p3p440/p3p440.c | 2 +- board/tqm834x/config.mk | 1 - board/tqm834x/pci.c | 36 +++++++++++++++++----------------- board/tqm834x/tqm834x.c | 16 +++++++-------- 13 files changed, 61 insertions(+), 63 deletions(-) (limited to 'board') diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index 2dd47bf..3c5dee7 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -283,7 +283,7 @@ void mv6436x_eth_initialize (bd_t * bis) /* set pointer to memory for stats data structure etc... */ port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; + ethernet_private->port_private = (void *)port_private; if (!port_private) { printf ("%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index a50f174..ec5d581 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -268,7 +268,7 @@ void mv6446x_eth_initialize (bd_t * bis) dev->recv = (void *) db64460_eth_poll; ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *)ethernet_private; + dev->priv = (void *)ethernet_private; if (!ethernet_private) { printf ("%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, @@ -282,7 +282,7 @@ void mv6446x_eth_initialize (bd_t * bis) /* set pointer to memory for stats data structure etc... */ port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; + ethernet_private->port_private = (void *)port_private; if (!port_private) { printf ("%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index b463f0e..df10c0e 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -36,11 +36,11 @@ int board_early_init_f (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00900000); - /* set output pins to high */ - out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); - /* INTA# is open drain */ + /* set output pins to high */ + out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED); + /* INTA# is open drain */ out32(GPIO0_ODR, CFG_INTA_FAKE); - /* setup for output */ + /* setup for output */ out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* @@ -55,14 +55,14 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) unused */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } @@ -142,18 +142,17 @@ int testdram (void) #if defined(CFG_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write + * -1: deliver current state + * 0: disable write * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done + * Returns: -1: wrong device address + * 0: dis-/en- able done * 0/1: current state if was -1. */ int eeprom_write_enable (unsigned dev_addr, int state) { if (CFG_I2C_EEPROM_ADDR != dev_addr) { return -1; - } - else { + } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ @@ -186,19 +185,16 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); - } - else { + } else { printf ("Write access for device 0x%0x is %sabled.\n", CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } - } - else { + } else { if ('0' == argv[1][0]) { /* Disable write access. */ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } - else { + } else { /* Enable write access. */ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); } diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c index 880528f..be176dc 100644 --- a/board/esd/cpci750/mv_eth.c +++ b/board/esd/cpci750/mv_eth.c @@ -284,7 +284,7 @@ void mv6436x_eth_initialize (bd_t * bis) /* set pointer to memory for stats data structure etc... */ port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; + ethernet_private->port_private = (void *)port_private; if (!port_private) { printf ("%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c index 69882f5..e8ef0e3 100644 --- a/board/evb64260/eth_addrtbl.c +++ b/board/evb64260/eth_addrtbl.c @@ -57,7 +57,7 @@ unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector) realAddrTableBase[port] = malloc (bytes + 64); - tableBase = (unsigned int)realAddrTableBase; + tableBase = (unsigned int)realAddrTableBase; if (!tableBase) { printf ("%s: alloc memory failed \n", __FUNCTION__); diff --git a/board/incaip/flash.c b/board/incaip/flash.c index 686f2e9..520514d 100644 --- a/board/incaip/flash.c +++ b/board/incaip/flash.c @@ -190,7 +190,7 @@ void flash_print_info (flash_info_t *info) int i; uchar *boottype; uchar *bootletter; - uchar *fmt; + char *fmt; uchar botbootletter[] = "B"; uchar topbootletter[] = "T"; uchar botboottype[] = "bottom boot sector"; diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index eb6eaea..b5d9e00 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -68,7 +68,7 @@ long int initdram(int board_type) { *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | (rows << 4) | cols; - size = get_ram_size((ulong *)CFG_SDRAM_BASE, + size = get_ram_size((long *)CFG_SDRAM_BASE, max_sdram_size()); if (size > max_size) diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index fb64ef4..14d738a 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -66,6 +66,7 @@ .globl ebu_init .ent ebu_init ebu_init: +__ebu_init: li t1, EBU_MODUL_BASE li t2, 0xA0000041 @@ -118,6 +119,7 @@ ebu_init: .globl cgu_init .ent cgu_init cgu_init: +__cgu_init: li t1, CGU_MODUL_BASE @@ -182,6 +184,7 @@ cgu_init: .globl sdram_init .ent sdram_init sdram_init: +__sdram_init: li t1, MC_MODUL_BASE @@ -281,11 +284,11 @@ lowlevel_init: /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init() * modify t0 and a0. */ - bal cgu_init + bal __cgu_init nop - bal ebu_init + bal __ebu_init nop - bal sdram_init + bal __sdram_init nop move ra, t0 diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c index 374e979..93550e2 100644 --- a/board/mpc8260ads/mpc8260ads.c +++ b/board/mpc8260ads/mpc8260ads.c @@ -251,7 +251,7 @@ void reset_phy (void) /* Advertise all capabilities */ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1); - + /* Do not bypass Rx/Tx (de)scrambler */ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000); diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 8ba66bf..d42a643 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -72,7 +72,7 @@ static void wait_for_pci_ready(void) for (;;) { if (in32(GPIO0_IR) & CFG_EREADY_IO) return; - } + } } diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk index 9295e77..f172c4e 100644 --- a/board/tqm834x/config.mk +++ b/board/tqm834x/config.mk @@ -21,4 +21,3 @@ # TEXT_BASE = 0x80000000 - diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c index 590987c..5a23e6c 100644 --- a/board/tqm834x/pci.c +++ b/board/tqm834x/pci.c @@ -86,29 +86,29 @@ pci_init_board(void) pci_conf = immr->pci_conf; hose = &pci1_hose; - + /* - * Configure PCI controller and PCI_CLK_OUTPUT + * Configure PCI controller and PCI_CLK_OUTPUT */ /* * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one * line actually used for clocking all external PCI devices in TQM83xx. - * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for + * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 - * are known to hang the board; this issue is under investigation + * are known to hang the board; this issue is under investigation * (13 oct 05) */ reg32 = OCCR_PCICOE1; -#if 0 +#if 0 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ reg32 = 0xff000000; -#endif +#endif if (clk->spmr & SPMR_CKID) { /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR * fields accordingly */ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); - + reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ | OCCR_PCICD6 | OCCR_PCICD7); @@ -138,7 +138,7 @@ pci_init_board(void) * Configure PCI Outbound Translation Windows */ - /* PCI1 mem space */ + /* PCI1 mem space */ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); @@ -152,8 +152,8 @@ pci_init_board(void) * Configure PCI Inbound Translation Windows */ - /* we need RAM mapped to PCI space for the devices to - * access main memory */ + /* we need RAM mapped to PCI space for the devices to + * access main memory */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; @@ -179,10 +179,10 @@ pci_init_board(void) /* System memory space */ pci_set_region(hose->regions + 2, CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + hose->region_count = 3; pci_setup_indirect(hose, @@ -195,18 +195,18 @@ pci_init_board(void) * Write to Command register */ reg16 = 0xff; - pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, + pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ - pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, + pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); #ifdef CONFIG_PCI_SCAN_SHOW diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index f681dc8..dada673 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -77,7 +77,7 @@ int board_early_init_r (void) { /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return 0; - + /* detect the number of Flash banks */ return detect_num_flash_banks(); } @@ -108,7 +108,7 @@ long int initdram (int board_type) set_ddr_config(); udelay(200); - + /* enable DDR controller */ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | @@ -154,7 +154,7 @@ int checkboard (void) /* get bus width */ w = 32; - if (immr->reset.rcwh & RCWH_PCI64) + if (immr->reset.rcwh & RCWH_PCI64) w = 64; /* get clock */ @@ -192,7 +192,7 @@ static int detect_num_flash_banks(void) ulong total_size; tqm834x_num_flash_banks = 2; /* assume two banks */ - + /* Get bank 1 and 2 information */ bank1_size = flash_get_size(CFG_FLASH_BASE, 0); debug("Bank1 size: %lu\n", bank1_size); @@ -318,10 +318,10 @@ static long int get_ddr_bank_size(short cs, volatile long *base) set_cs_config(cs, 0); return 0; } - + debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); - + /* configure cs ro detected params */ set_cs_config(cs, CSCONFIG_EN | conf[detected].row | conf[detected].col); @@ -367,7 +367,7 @@ static void set_ddr_config(void) { im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; SYNC; - + /* timing configuration */ im->ddr.timing_cfg_1 = (4 << TIMING_CFG1_PRETOACT_SHIFT) | @@ -389,7 +389,7 @@ static void set_ddr_config(void) { SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; SYNC; - + /* Set SDRAM mode */ im->ddr.sdram_mode = ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << -- cgit v1.1