From ee4dc2590f00d0109bcdb282ad86fd3dce567e50 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Wed, 3 Jun 2015 16:57:47 +0530 Subject: ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL register When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla --- board/ti/beagle_x15/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index 124a1d3..f25e75e 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -52,7 +52,7 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, @@ -120,7 +120,7 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, .emif_ddr_phy_ctlr_1_init = 0x0024400b, -- cgit v1.1