From 0f832b9cdcbe8a024b53c585622d70129652d20b Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 26 May 2016 14:49:36 +0100 Subject: malta: Allow MIPS64 builds Both real Malta boards & emulators that mimic Malta (eg. QEMU) can support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards, which enables the user to make use of the whole 64 bit address space. Signed-off-by: Paul Burton --- board/imgtec/malta/Kconfig | 3 ++- board/imgtec/malta/lowlevel_init.S | 13 +++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig index 2bb8e8b..98eb4d1 100644 --- a/board/imgtec/malta/Kconfig +++ b/board/imgtec/malta/Kconfig @@ -10,6 +10,7 @@ config SYS_CONFIG_NAME default "malta" config SYS_TEXT_BASE - default 0xbe000000 + default 0xbe000000 if 32BIT + default 0xffffffffbe000000 if 64BIT endif diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index 534db1d..3d48cdc 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -34,7 +35,7 @@ lowlevel_init: mtc0 t0, CP0_CONFIG, 2 /* detect the core card */ - li t0, KSEG1ADDR(MALTA_REVISION) + PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) lw t0, 0(t0) srl t0, t0, MALTA_REVISION_CORID_SHF andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ @@ -68,12 +69,12 @@ lowlevel_init: */ _gt64120: /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) + PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) li t0, CPU_TO_GT32(0xdf000000) sw t0, GT_ISD_OFS(t1) /* setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MALTA_GT_BASE) + PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) /* setup PCI0 io window to 0x18000000-0x181fffff */ li t0, CPU_TO_GT32(0xc0000000) @@ -100,7 +101,7 @@ _gt64120: */ _msc01: /* setup peripheral bus controller clock divide */ - li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) li t1, 0x1 << MSC01_PBC_CLKCFG_SHF sw t1, MSC01_PBC_CLKCFG_OFS(t0) @@ -122,7 +123,7 @@ _msc01: sw t1, MSC01_PBC_CS0CFG_OFS(t0) /* setup basic address decode */ - li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) li t1, 0x0 li t2, -CONFIG_SYS_MEM_SIZE sw t1, MSC01_BIU_MCBAS1L_OFS(t0) @@ -157,7 +158,7 @@ _msc01: sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) /* setup PCI memory */ - li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) + PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE) li t1, MALTA_MSC01_PCIMEM_BASE li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK li t3, MALTA_MSC01_PCIMEM_MAP -- cgit v1.1 From ace3be4f15875d74344336b9754c14274f940969 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:04 +0100 Subject: MIPS: Move cache sizes to Kconfig Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton --- board/dbau1x00/Kconfig | 9 +++++++++ board/micronas/vct/Kconfig | 9 +++++++++ board/pb1x00/Kconfig | 9 +++++++++ board/qca/ap121/Kconfig | 9 +++++++++ board/qca/ap143/Kconfig | 9 +++++++++ board/qemu-mips/Kconfig | 9 +++++++++ board/tplink/wdr4300/Kconfig | 9 +++++++++ 7 files changed, 63 insertions(+) (limited to 'board') diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index 342ec59..1715a28 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -12,6 +12,15 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0xbfc00000 +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + menu "dbau1x00 board options" choice diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 535a77b..5bb6f03 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -12,6 +12,15 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x87000000 +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + menu "vct board options" choice diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index 236a410..27b2ef0 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x83800000 +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig index c3ecc8f..f28ea1c 100644 --- a/board/qca/ap121/Kconfig +++ b/board/qca/ap121/Kconfig @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x9f000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig index 5ea5d6f..ff02236 100644 --- a/board/qca/ap143/Kconfig +++ b/board/qca/ap143/Kconfig @@ -12,4 +12,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x9f000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index 3de1f44..66957e7 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -11,4 +11,13 @@ config SYS_TEXT_BASE default 0xbfc00000 if 32BIT default 0xffffffffbfc00000 if 64BIT +config SYS_DCACHE_SIZE + default 16384 + +config SYS_ICACHE_SIZE + default 16384 + +config SYS_CACHELINE_SIZE + default 32 + endif diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index 65785bd..ded7f9b 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -15,4 +15,13 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0xa1000000 +config SYS_DCACHE_SIZE + default 32768 + +config SYS_ICACHE_SIZE + default 65536 + +config SYS_CACHELINE_SIZE + default 32 + endif -- cgit v1.1 From 372286217f050bfd57695001d59f618c52822f40 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:05 +0100 Subject: MIPS: Split I & D cache line size config Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck --- board/dbau1x00/Kconfig | 5 ++++- board/micronas/vct/Kconfig | 5 ++++- board/pb1x00/Kconfig | 5 ++++- board/qca/ap121/Kconfig | 5 ++++- board/qca/ap143/Kconfig | 5 ++++- board/qemu-mips/Kconfig | 5 ++++- board/tplink/wdr4300/Kconfig | 5 ++++- 7 files changed, 28 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index 1715a28..448176d 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 menu "dbau1x00 board options" diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 5bb6f03..df7c029 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 menu "vct board options" diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index 27b2ef0..ef8905d 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig index f28ea1c..4fd6a71 100644 --- a/board/qca/ap121/Kconfig +++ b/board/qca/ap121/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig index ff02236..74c632a 100644 --- a/board/qca/ap143/Kconfig +++ b/board/qca/ap143/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index 66957e7..e696a12 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -14,10 +14,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig index ded7f9b..67a0228 100644 --- a/board/tplink/wdr4300/Kconfig +++ b/board/tplink/wdr4300/Kconfig @@ -18,10 +18,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 32768 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 65536 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 endif -- cgit v1.1 From 04583c686e61e6883158549603d60741ebf249fe Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Mon, 30 May 2016 22:54:51 +0800 Subject: mips: ath79: ap121: Enable ethernet This patch enable network function for ap121 board. Signed-off-by: Wills Wang Acked-by: Marek Vasut --- board/qca/ap121/ap121.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c index d6c60fe..e245faa 100644 --- a/board/qca/ap121/ap121.c +++ b/board/qca/ap121/ap121.c @@ -10,6 +10,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -46,5 +47,6 @@ int board_early_init_f(void) debug_uart_init(); #endif ddr_init(); + ath79_eth_reset(); return 0; } -- cgit v1.1 From f1b65c98b0a134ce92c38141b917fd3a210ee535 Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Mon, 30 May 2016 22:54:55 +0800 Subject: mips: ath79: ap143: Reset ethernet on boot This patch reset the ethernet controller for ap143 board Signed-off-by: Wills Wang --- board/qca/ap143/ap143.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c index 1572472..e921ea5 100644 --- a/board/qca/ap143/ap143.c +++ b/board/qca/ap143/ap143.c @@ -10,6 +10,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -62,5 +63,6 @@ int board_early_init_f(void) debug_uart_init(); #endif ddr_init(); + ath79_eth_reset(); return 0; } -- cgit v1.1