From 9d1d6a34d26c5933bc097ce73c9348f95573cdd4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 21 Apr 2007 20:53:31 +0200 Subject: Change ML401 parameters - Xilinx BSP --- board/xilinx/ml401/config.mk | 2 +- board/xilinx/ml401/xparameters.h | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) (limited to 'board') diff --git a/board/xilinx/ml401/config.mk b/board/xilinx/ml401/config.mk index 807f169..c75daaf 100644 --- a/board/xilinx/ml401/config.mk +++ b/board/xilinx/ml401/config.mk @@ -25,7 +25,7 @@ # Version: Xilinx EDK 6.3 EDK_Gmm.12.3 # -TEXT_BASE = 0x12000000 +TEXT_BASE = 0x29000000 PLATFORM_CPPFLAGS += -mno-xl-soft-mul PLATFORM_CPPFLAGS += -mno-xl-soft-div diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h index 18d24f9..4fe36f8 100644 --- a/board/xilinx/ml401/xparameters.h +++ b/board/xilinx/ml401/xparameters.h @@ -27,41 +27,41 @@ */ /* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 66666667 +#define XILINX_CLOCK_FREQ 100000000 /* Interrupt controller is intc_0 */ -#define XILINX_INTC_BASEADDR 0xd1000fc0 -#define XILINX_INTC_NUM_INTR_INPUTS 12 +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 4 /* Timer pheriphery is opb_timer_0 */ -#define XILINX_TIMER_BASEADDR 0xa2000000 +#define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 /* Uart pheriphery is console_uart */ -#define XILINX_UART_BASEADDR 0xa0000000 +#define XILINX_UART_BASEADDR 0x40600000 #define XILINX_UART_BAUDRATE 115200 /* GPIO is opb_gpio_0*/ #define XILINX_GPIO_BASEADDR 0x90000000 /* Flash Memory is opb_emc_0 */ -#define XILINX_FLASH_START 0x28000000 +#define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 /* Main Memory is plb_ddr_0 */ -#define XILINX_RAM_START 0x10000000 -#define XILINX_RAM_SIZE 0x10000000 +#define XILINX_RAM_START 0x28000000 +#define XILINX_RAM_SIZE 0x04000000 /* Sysace Controller is opb_sysace_0 */ -#define XILINX_SYSACE_BASEADDR 0xCF000000 -#define XILINX_SYSACE_HIGHADDR 0xCF0001FF +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180FFFF #define XILINX_SYSACE_MEM_WIDTH 16 /* Ethernet controller is opb_ethernet_0 */ #define XPAR_XEMAC_NUM_INSTANCES 1 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF +#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0fFFF #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1 -- cgit v1.1 From ffc50f9bb194343c6303517a517708457a5eb6b8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 5 May 2007 18:54:42 +0200 Subject: new: FSL and MSR support #2 --- board/xilinx/ml401/xparameters.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h index 4fe36f8..f63ffed 100644 --- a/board/xilinx/ml401/xparameters.h +++ b/board/xilinx/ml401/xparameters.h @@ -29,6 +29,9 @@ /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 +/* Microblaze is microblaze_0 */ +#define XILINX_FSL_NUMBER 2 + /* Interrupt controller is intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 #define XILINX_INTC_NUM_INTR_INPUTS 4 -- cgit v1.1 From 48fbd3a4cdabbebc1debd7eed73c00c2caf914f6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 17:11:09 +0200 Subject: new: add writing to msr register --- board/xilinx/ml401/xparameters.h | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) mode change 100644 => 100755 board/xilinx/ml401/xparameters.h (limited to 'board') diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h old mode 100644 new mode 100755 index f63ffed..2b0c045 --- a/board/xilinx/ml401/xparameters.h +++ b/board/xilinx/ml401/xparameters.h @@ -21,50 +21,54 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 6.3 EDK_Gmm.12.3 + * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 */ /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 /* Microblaze is microblaze_0 */ -#define XILINX_FSL_NUMBER 2 +#define XILINX_FSL_NUMBER 3 -/* Interrupt controller is intc_0 */ +/* Interrupt controller is opb_intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 4 +#define XILINX_INTC_NUM_INTR_INPUTS 5 -/* Timer pheriphery is opb_timer_0 */ +/* Timer pheriphery is opb_timer_1 */ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* Uart pheriphery is console_uart */ +/* Uart pheriphery is RS232_Uart */ #define XILINX_UART_BASEADDR 0x40600000 #define XILINX_UART_BAUDRATE 115200 -/* GPIO is opb_gpio_0*/ -#define XILINX_GPIO_BASEADDR 0x90000000 +/* IIC pheriphery is IIC_EEPROM */ +#define XILINX_IIC_0_BASEADDR 0x40800000 +#define XILINX_IIC_0_FREQ 100000 +#define XILINX_IIC_0_BIT 0 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 -/* Flash Memory is opb_emc_0 */ +/* Flash Memory is FLASH_2Mx32 */ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is plb_ddr_0 */ +/* Main Memory is DDR_SDRAM_64Mx32 */ #define XILINX_RAM_START 0x28000000 #define XILINX_RAM_SIZE 0x04000000 -/* Sysace Controller is opb_sysace_0 */ +/* Sysace Controller is SysACE_CompactFlash */ #define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180FFFF +#define XILINX_SYSACE_HIGHADDR 0x4180ffff #define XILINX_SYSACE_MEM_WIDTH 16 -/* Ethernet controller is opb_ethernet_0 */ +/* Ethernet controller is Ethernet_MAC */ #define XPAR_XEMAC_NUM_INSTANCES 1 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0fFFF +#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1 -- cgit v1.1 From 19bf1fbad7f19d5a120be9b1daf136e052fcab39 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 19:33:51 +0200 Subject: new: fsl interrupt support FSL_Has_data is connected to INTC. --- board/xilinx/ml401/ml401.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c index b48103f..955936d 100644 --- a/board/xilinx/ml401/ml401.c +++ b/board/xilinx/ml401/ml401.c @@ -27,6 +27,8 @@ #include #include +#include +#include void do_reset (void) { @@ -43,7 +45,25 @@ void do_reset (void) int gpio_init (void) { #ifdef CFG_GPIO_0 - *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0; + *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0xFFFFFFFF; #endif return 0; } + +#ifdef CFG_FSL_2 +void fsl_isr2 (void *arg) { + volatile int num; + *((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)) = + ++(*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4))); + GET (num, 2); + NGET (num, 2); + puts("*"); +} + +void fsl_init2 (void) { + puts("fsl_init2\n"); + install_interrupt_handler (FSL_INTR_2,\ + fsl_isr2,\ + NULL); +} +#endif -- cgit v1.1 From fb05f6da35ea1c15c553abe6f23f656bf18dc5db Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 23:58:31 +0200 Subject: new: USE_MSR_INTR support --- board/xilinx/ml401/xparameters.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h index 2b0c045..1a116ea 100755 --- a/board/xilinx/ml401/xparameters.h +++ b/board/xilinx/ml401/xparameters.h @@ -29,11 +29,12 @@ #define XILINX_CLOCK_FREQ 100000000 /* Microblaze is microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 #define XILINX_FSL_NUMBER 3 /* Interrupt controller is opb_intc_0 */ #define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 5 +#define XILINX_INTC_NUM_INTR_INPUTS 6 /* Timer pheriphery is opb_timer_1 */ #define XILINX_TIMER_BASEADDR 0x41c00000 -- cgit v1.1