From 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:51 -0500 Subject: 8544ds PCIE support PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/freescale/mpc8544ds/init.S | 6 +- board/freescale/mpc8544ds/mpc8544ds.c | 350 ++++++++++++++++++++++++++++++++++ 2 files changed, 353 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 296fee5..ea7d54d 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -52,8 +52,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -214,7 +214,7 @@ law_entry: .long 0 .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4ff1da9..8ddbb01 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -22,8 +22,10 @@ #include #include +#include #include #include +#include #include #include @@ -51,12 +53,19 @@ int checkboard (void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %x\n",&gur->porpllsr); } printf ("Board: MPC8544DS\n"); + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + return 0; } @@ -118,6 +127,316 @@ testdram(void) } #endif +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno=0; + +void +pci_init_board(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (io_sel & 1) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + printf (" eTSEC1 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf (" eTSEC3 is in sgmii mode.\n"); + } + +#ifdef CONFIG_PCIE3 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie3_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE3 connected to ULI as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE3_MEM_BASE, + CFG_PCIE3_MEM_PHYS, + CFG_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE3_IO_BASE, + CFG_PCIE3_IO_PHYS, + CFG_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE3_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE3_MEM_BASE2, + CFG_PCIE3_MEM_PHYS2, + CFG_PCIE3_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCIE3 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE3: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 5); + int pcie_configured = io_sel & 6; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE1_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE1_MEM_BASE2, + CFG_PCIE1_MEM_PHYS2, + CFG_PCIE1_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE1: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = io_sel & 4; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE2_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE2_MEM_BASE2, + CFG_PCIE2_MEM_PHYS2, + CFG_PCIE2_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf (" PCIE2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE2: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + uint pci_agent = (host_agent == 6); + uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ + uint pci_32 = 1; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter", + (uint)pci + ); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 3; +#ifdef CFG_PCIE3_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE3_MEM_BASE2, + CFG_PCIE3_MEM_PHYS2, + CFG_PCIE3_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif +} + + int last_stage_init(void) { return 0; @@ -197,5 +516,36 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +#ifdef CONFIG_PCIE3 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;; + debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } } #endif -- cgit v1.1 From f2cff6b104f82b993bef6086ce0c97159bbe1add Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Fri, 27 Jul 2007 01:50:52 -0500 Subject: 8548cds PCIE support. Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- board/cds/mpc8548cds/config.mk | 4 +- board/cds/mpc8548cds/init.S | 162 +++++++++++++------------- board/cds/mpc8548cds/mpc8548cds.c | 237 +++++++++++++++++++++++++++++++++----- board/cds/mpc8548cds/u-boot.lds | 3 +- 4 files changed, 291 insertions(+), 115 deletions(-) (limited to 'board') diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk index 242a676..b23bc87 100644 --- a/board/cds/mpc8548cds/config.mk +++ b/board/cds/mpc8548cds/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2004 Freescale Semiconductor. +# Copyright 2004, 2007 Freescale Semiconductor. # # See file CREDITS for list of people who contributed to this # project. @@ -23,7 +23,9 @@ # # mpc8548cds board # +ifndef TEXT_BASE TEXT_BASE = 0xfff80000 +endif PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index d468f5b..72940b0 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * Copyright 2002,2003, Motorola Inc. * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,12 @@ #include #include +#define LAWAR_TRGT_PCI1 0x00000000 +#define LAWAR_TRGT_PCI2 0x00100000 +#define LAWAR_TRGT_PCIE 0x00200000 +#define LAWAR_TRGT_RIO 0x00c00000 +#define LAWAR_TRGT_LBC 0x00400000 +#define LAWAR_TRGT_DDR 0x00f00000 /* * TLB0 and TLB1 Entries @@ -47,8 +53,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -84,8 +90,8 @@ tlb1_entry: #endif /* - * TLB0 16K Cacheable, non-guarded - * 0xd001_0000 16K Temporary Global data for initialization + * TLB0 16K Cacheable, guarded + * Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory @@ -97,28 +103,28 @@ tlb1_entry: .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) + 0,0,0,0,0,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,1,0,1,0,1) @@ -130,51 +136,44 @@ tlb1_entry: */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 1G PCI1/PCIE 8,9,a,b */ .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1) +#ifdef CFG_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI2 MEM */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), - 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 3: 1GB Non-cacheable, guarded - * 0xa0000000 256M PEX MEM First half - * 0xb0000000 256M PEX MEM Second half - * 0xc0000000 256M Rapid IO MEM First half - * 0xd0000000 256M Rapid IO MEM Second half + * TLB 3: 256M Non-cacheable, guarded */ .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLB 4: Reserved for future usage - */ - + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) +#endif /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 8M PCI1 IO - * 0xe280_0000 8M PCI2 IO - * 0xe300_0000 16M PEX IO + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) @@ -187,17 +186,18 @@ tlb1_entry: */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLB 7: 1M Non-cacheable, guarded - * 0xf8000000 1M CADMUS registers + * TLB 7: 64M Non-cacheable, guarded + * 0xf8000000 64M CADMUS registers, relocated L2SRAM */ .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1) + 2: entry_end @@ -205,14 +205,13 @@ tlb1_entry: * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M - * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M - * 0xa000_0000 0xbfff_ffff PEX MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe27f_ffff PCI1 IO 8M - * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M - * 0xe300_0000 0xe3ff_ffff PEX IO 16M + * 0xe200_0000 0xe10f_ffff PCI1 IO 1M + * 0xe280_0000 0xe20f_ffff PCI2 IO 1M + * 0xe300_0000 0xe30f_ffff PCIe IO 1M * 0xf000_0000 0xf3ff_ffff SDRAM 64M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -222,47 +221,50 @@ tlb1_entry: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. * - * The defines below are 1-off of the actual LAWAR0 usage. - * So LAWAR3 define uses the LAWAR4 register in the ECM. + * LAW 0 is reserved for boot mapping */ -#define LAWBAR0 0 -#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) - -#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start -#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) + .long (4f-3f)/8 +3: + .long 0 + .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN -#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) +#ifdef CFG_PCI1_MEM_PHYS + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) -#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M)) + .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif -/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ -#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#ifdef CFG_PCI2_MEM_PHYS + .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) -#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif -#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#ifdef CFG_PCIE1_MEM_PHYS + .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) -#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) +#endif - .section .bootpg, "ax" - .globl law_entry + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) -law_entry: - entry_start - .long (4f-3f)/8 -3: - .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 - .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7 - .long LAWBAR8,LAWAR8 +#ifdef CFG_RIO_MEM_PHYS + .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff + .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) +#endif 4: entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index b723641..242a68c 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt * @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -33,10 +34,15 @@ #include "../common/eeprom.h" #include "../common/via.h" +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif +DECLARE_GLOBAL_DATA_PTR; + extern long int spd_sdram(void); void local_bus_init(void); @@ -56,13 +62,6 @@ int checkboard (void) /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ - uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - - uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - uint cpu_board_rev = get_cpu_board_revision (); printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", @@ -71,20 +70,6 @@ int checkboard (void) printf ("CPU Board Revision %d.%d (0x%04x)\n", MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - - printf (" PCI1: %d bit, %s MHz, %s\n", - (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", - pci1_clk_sel ? "sync" : "async"); - - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } - /* * Initialize local bus. */ @@ -102,6 +87,8 @@ int checkboard (void) */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; } @@ -176,6 +163,9 @@ local_bus_init(void) lbc->lcrr |= 0x00030000; asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ } /* @@ -301,7 +291,7 @@ testdram(void) } #endif -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -320,21 +310,175 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { {}, }; -static struct pci_controller hose[] = { - { config_table: pci_mpc85xxcds_config_table,}, -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - +static struct pci_controller pci1_hose = { + config_table: pci_mpc85xxcds_config_table}; #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno=0; + void pci_init_board(void) { -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + struct pci_config_table *table; + + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + + /* outbound memory */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 2; + + /* relocate config table pointers */ + hose->config_table = \ + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); + for (table = hose->config_table; table && table->vendor; table++) + table->config_device += gd->reloc_off; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); + } #endif + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif + +#ifdef CONFIG_PCI2 +{ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + } int last_stage_init(void) @@ -367,3 +511,32 @@ int last_stage_init(void) return 0; } + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + +#ifdef CONFIG_PCI1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pci1_hose.last_busno - pci1_hose.first_busno; + debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif + +#ifdef CONFIG_PCIE1 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len); + if (p != NULL) { + p[0] = 0; + p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]); + } +#endif +} +#endif diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds index c1f3495..530ba5a 100644 --- a/board/cds/mpc8548cds/u-boot.lds +++ b/board/cds/mpc8548cds/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -71,7 +71,6 @@ SECTIONS cpu/mpc85xx/cpu.o (.text) drivers/tsec.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) -- cgit v1.1 From 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 13 Aug 2007 14:38:06 -0500 Subject: Fix minor 85xx warnings Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming --- board/mpc8560ads/mpc8560ads.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 41acb97..eef524b 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -554,7 +554,6 @@ ft_soc_setup(void *blob, bd_t *bd) { u32 *p; int len; - ulong data; p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); -- cgit v1.1 From c59e4091ffe0148398b9e9ff14a019ea038b7432 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 19 Jun 2007 14:18:34 -0400 Subject: Add PCI support for MPC8568MDS board This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang Signed-off-by: Ebony Zhu --- board/mpc8568mds/init.S | 48 +++++++++++++--------------------- board/mpc8568mds/mpc8568mds.c | 60 ++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 74 insertions(+), 34 deletions(-) (limited to 'board') diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S index 0d87982..972a7d4 100644 --- a/board/mpc8568mds/init.S +++ b/board/mpc8568mds/init.S @@ -143,54 +143,42 @@ tlb1_entry: .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 2: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM + * TLBe 2: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCIe Mem - */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) - - /* - * TLBe 4: Reserved for future usage - */ - - /* - * TLBe 5: 64M Non-cacheable, guarded + * TLBe 3: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS0(1, 3, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 6: 64M Cacheable, non-guarded + * TLBe 4: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS0(1, 4, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) /* - * TLBe 7: 256K Non-cacheable, guarded + * TLBe 5: 256K Non-cacheable, guarded * 0xf8000000 32K BCSR * 0xf8008000 32K PIB (CS4) * 0xf8010000 32K PIB (CS5) */ - .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1) @@ -202,12 +190,12 @@ tlb1_entry: * LAW(Local Access Window) configuration: * *0) 0x0000_0000 0x7fff_ffff DDR 2G - *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB - *2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB - *5) 0xc000_0000 0xdfff_ffff SRIO 256MB + *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB + *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB *-) 0xe000_0000 0xe00f_ffff CCSR 1M *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M - *4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M + *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M + *5) 0xc000_0000 0xdfff_ffff SRIO 512MB *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB @@ -226,20 +214,20 @@ tlb1_entry: #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) -#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff) -#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) -#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 9c7960d..23caaec 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "bcsr.h" @@ -50,6 +51,15 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#ifdef CFG_I2C2_OFFSET + /* Enable I2C2_SCL and I2C2_SDA */ + volatile struct par_io *port_c; + port_c = (struct par_io*)(CFG_IMMR + 0xe0140); + port_c->cpdir2 |= 0x0f000000; + port_c->cppar2 &= ~0x0f000000; + port_c->cppar2 |= 0x0a000000; +#endif + return 0; } @@ -269,20 +279,62 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = { #endif static struct pci_controller hose[] = { + { #ifndef CONFIG_PCI_PNP - { config_table: pci_mpc8568mds_config_table,}, -#endif -#ifdef CONFIG_MPC85XX_PCI2 - {}, + config_table: pci_mpc8568mds_config_table, #endif + } }; #endif /* CONFIG_PCI */ +/* + * pib_init() -- Initialize the PCA9555 IO expander on the PIB board + */ +void +pib_init(void) +{ + u8 val8, orig_i2c_bus; + /* + * Assign PIB PMC2/3 to PCI bus + */ + + /*switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0x00; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0x00; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); + val8 = 0xf9; + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0x00; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + + asm("eieio"); +} + void pci_init_board(void) { #ifdef CONFIG_PCI + pib_init(); pci_mpc85xx_init(&hose); #endif } -- cgit v1.1 From da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 00:14:25 -0500 Subject: Add support for UEC to 8568 Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- board/mpc8568mds/bcsr.c | 7 +++++ board/mpc8568mds/bcsr.h | 1 + board/mpc8568mds/mpc8568mds.c | 61 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 68 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index 2e2e8cd..aae0f98 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -47,3 +47,10 @@ void disable_8568mds_flash_write() bcsr[9] &= ~(0x01); } + +void enable_8568mds_qe_mdio() +{ + u8 *bcsr = (u8 *)(CFG_BCSR); + + bcsr[7] |= 0x01; +} diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index 8d4cb2f..aefd9bf 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -95,5 +95,6 @@ void enable_8568mds_duart(void); void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); +void enable_8568mds_qe_mdio(void); #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 23caaec..818ff13 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -28,9 +28,65 @@ #include #include #include +#include #include "bcsr.h" +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GETH1 */ + {4, 10, 1, 0, 2}, /* TxD0 */ + {4, 9, 1, 0, 2}, /* TxD1 */ + {4, 8, 1, 0, 2}, /* TxD2 */ + {4, 7, 1, 0, 2}, /* TxD3 */ + {4, 23, 1, 0, 2}, /* TxD4 */ + {4, 22, 1, 0, 2}, /* TxD5 */ + {4, 21, 1, 0, 2}, /* TxD6 */ + {4, 20, 1, 0, 2}, /* TxD7 */ + {4, 15, 2, 0, 2}, /* RxD0 */ + {4, 14, 2, 0, 2}, /* RxD1 */ + {4, 13, 2, 0, 2}, /* RxD2 */ + {4, 12, 2, 0, 2}, /* RxD3 */ + {4, 29, 2, 0, 2}, /* RxD4 */ + {4, 28, 2, 0, 2}, /* RxD5 */ + {4, 27, 2, 0, 2}, /* RxD6 */ + {4, 26, 2, 0, 2}, /* RxD7 */ + {4, 11, 1, 0, 2}, /* TX_EN */ + {4, 24, 1, 0, 2}, /* TX_ER */ + {4, 16, 2, 0, 2}, /* RX_DV */ + {4, 30, 2, 0, 2}, /* RX_ER */ + {4, 17, 2, 0, 2}, /* RX_CLK */ + {4, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + + /* GETH2 */ + {5, 10, 1, 0, 2}, /* TxD0 */ + {5, 9, 1, 0, 2}, /* TxD1 */ + {5, 8, 1, 0, 2}, /* TxD2 */ + {5, 7, 1, 0, 2}, /* TxD3 */ + {5, 23, 1, 0, 2}, /* TxD4 */ + {5, 22, 1, 0, 2}, /* TxD5 */ + {5, 21, 1, 0, 2}, /* TxD6 */ + {5, 20, 1, 0, 2}, /* TxD7 */ + {5, 15, 2, 0, 2}, /* RxD0 */ + {5, 14, 2, 0, 2}, /* RxD1 */ + {5, 13, 2, 0, 2}, /* RxD2 */ + {5, 12, 2, 0, 2}, /* RxD3 */ + {5, 29, 2, 0, 2}, /* RxD4 */ + {5, 28, 2, 0, 2}, /* RxD5 */ + {5, 27, 2, 0, 3}, /* RxD6 */ + {5, 26, 2, 0, 2}, /* RxD7 */ + {5, 11, 1, 0, 2}, /* TX_EN */ + {5, 24, 1, 0, 2}, /* TX_ER */ + {5, 16, 2, 0, 2}, /* RX_DV */ + {5, 30, 2, 0, 2}, /* RX_ER */ + {5, 17, 2, 0, 2}, /* RX_CLK */ + {5, 19, 1, 0, 2}, /* GTX_CLK */ + {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 6, 3, 0, 2}, /* MDIO */ + {4, 5, 1, 0, 2}, /* MDC */ + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -50,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) + enable_8568mds_qe_mdio(); +#endif #ifdef CFG_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ @@ -335,6 +394,6 @@ pci_init_board(void) { #ifdef CONFIG_PCI pib_init(); - pci_mpc85xx_init(&hose); + pci_mpc85xx_init(hose); #endif } -- cgit v1.1 From e41094c7e38177c755fbd9b182018069614f080d Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:50:09 -0500 Subject: 85xxCDS: Enable the VIA PCI-to-ISA bridge. Author: Randy Vinson Enable the PCI-to-ISA bridge in the VIA Southbridge located on the Arcadia main board. Signed-off-by: Randy Vinson Signed-off-by: York Sun --- board/cds/common/via.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/cds/common/via.c b/board/cds/common/via.c index e79bd02..ded214f 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -28,11 +28,16 @@ void mpc85xx_config_via(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *tab) { pci_dev_t bridge; + unsigned int cmdstat; /* Enable USB and IDE functions */ pci_hose_write_config_byte(hose, dev, 0x48, 0x08); - pciauto_config_device(hose, dev); + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); /* * Force the backplane P2P bridge to have a window -- cgit v1.1 From 7f3f2bd2dc08e0b05e185662ca2e2d283757104a Mon Sep 17 00:00:00 2001 From: Randy Vinson Date: Tue, 27 Feb 2007 19:42:22 -0700 Subject: 85xxCDS: Add make targets for legacy systems. The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson --- board/cds/common/via.c | 2 +- board/cds/mpc8541cds/mpc8541cds.c | 15 +++++++++------ board/cds/mpc8548cds/mpc8548cds.c | 15 +++++++++------ board/cds/mpc8555cds/mpc8555cds.c | 15 +++++++++------ 4 files changed, 28 insertions(+), 19 deletions(-) (limited to 'board') diff --git a/board/cds/common/via.c b/board/cds/common/via.c index ded214f..4a63d77 100644 --- a/board/cds/common/via.c +++ b/board/cds/common/via.c @@ -45,7 +45,7 @@ void mpc85xx_config_via(struct pci_controller *hose, * This allows legacy I/O (i8259, etc) on the VIA * southbridge to be accessed. */ - bridge = PCI_BDF(0,17,0); + bridge = PCI_BDF(0,BRIDGE_ID,0); pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 4192324..558ba99 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -476,14 +476,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 242a68c..48753d7 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -299,14 +299,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 704bf03..8f16421 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -473,14 +473,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta static struct pci_config_table pci_mpc85xxcds_config_table[] = { {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, {}, }; -- cgit v1.1