From e5ff845bff6dfc6e4d1d8b75fb817a8bc7635b2f Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 22 May 2014 14:37:11 +0530 Subject: ARM: DRA7xx: Add cpsw second port pinmux Add cpsw second slave port pinmux to use it as primary ethernet port Signed-off-by: Mugunthan V N --- board/ti/dra7xx/mux_data.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'board') diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 38de9d5..56cda07 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -51,6 +51,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {RGMII0_RXD2, (IEN | M0) }, {RGMII0_RXD1, (IEN | M0) }, {RGMII0_RXD0, (IEN | M0) }, + {VIN2A_D12, (M3) }, + {VIN2A_D13, (M3) }, + {VIN2A_D14, (M3) }, + {VIN2A_D15, (M3) }, + {VIN2A_D16, (M3) }, + {VIN2A_D17, (M3) }, + {VIN2A_D18, (IEN | M3)}, + {VIN2A_D19, (IEN | M3)}, + {VIN2A_D20, (IEN | M3)}, + {VIN2A_D21, (IEN | M3)}, + {VIN2A_D22, (IEN | M3)}, + {VIN2A_D23, (IEN | M3)}, {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ -- cgit v1.1 From 4c8014b9429b593c28fbf0384a6c7ded8587806a Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 22 May 2014 14:37:12 +0530 Subject: ARM: dra7_evm: Add Ethernet support for dra72x platform Set the active_slave to 1 as slave 1 is pinned out in dra72x base board Signed-off-by: Mugunthan V N --- board/ti/dra7xx/evm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 073d151..955c16f 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -157,6 +157,8 @@ int spl_start_uboot(void) #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) +extern u32 *const omap_si_rev; + static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -183,7 +185,7 @@ static struct cpsw_platform_data cpsw_data = { .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, - .slaves = 1, + .slaves = 2, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, @@ -254,6 +256,9 @@ int board_eth_init(bd_t *bis) ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); + if (*omap_si_rev == DRA722_ES1_0) + cpsw_data.active_slave = 1; + ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); -- cgit v1.1 From 7aa5598aac3faf9188559f7a50940df11c30b656 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Jun 2014 16:06:29 -0400 Subject: tps65218/am43xx_evm: Add power framework support to TPS65218 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add in an init function for the drivers/power framework so we can dump and read the registers via i2c. Cc: Łukasz Majewski Signed-off-by: Tom Rini --- board/ti/am43xx/board.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'board') diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 054a452..f657776 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,6 +19,7 @@ #include #include #include "board.h" +#include #include #include #include @@ -484,6 +485,19 @@ void sdram_init(void) } #endif +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + + return 0; +} + int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -- cgit v1.1 From c6ac7e3bdc195a7dd39b5bf699deceedb9444c0c Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 4 Jul 2014 15:03:27 +0300 Subject: k2hk_evm: add script to automate NAND flash process Add script to automate NAND flash process. As for now the board has two burn scripts - burn to boot from SPI NOR flash and burn to boot from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi. Also update README to contain NAND burn U-boot process description. Signed-off-by: Ivan Khoronzhuk Acked-by: Murali Karicheri --- board/ti/k2hk_evm/README | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README index bfeb05b..7426b8d 100644 --- a/board/ti/k2hk_evm/README +++ b/board/ti/k2hk_evm/README @@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h Supported boot modes: - SPI NOR boot + - AEMIF NAND boot Supported image formats:- - u-boot.bin: for loading and running u-boot.bin through Texas instruments code composure studio (CCS) - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot Build instructions: =================== @@ -55,6 +57,10 @@ To build u-boot-spi.gph >make k2hk_evm_config >make u-boot-spi.gph +To build u-boot-nand.gph + >make k2hk_evm_config + >make u-boot-nand.gph + Load and Run U-Boot on K2HK EVM using CCS ========================================= @@ -115,8 +121,28 @@ instructions:- 5. At the U-Boot console type following to setup u-boot environment variables. setenv addr_uboot 0x87000000 setenv filesize - run burn_uboot + run burn_uboot_spi Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch to "SPI Little Endian Boot mode" as per instruction at http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. 6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. -- cgit v1.1 From c4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 7 Jul 2014 21:40:16 -0400 Subject: am335x_evm / gumstix pepper: Correct DDR settings As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee Cc: Ash Charles Signed-off-by: Tom Rini Tested-By: Ash Charles --- board/gumstix/pepper/board.c | 30 +++--------------------------- board/ti/am335x/board.c | 30 +++--------------------------- 2 files changed, 6 insertions(+), 54 deletions(-) (limited to 'board') diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index 75aac49..f644f81 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index da780ed..d81eec9 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header) #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { -- cgit v1.1 From 0b868589563ab96384b9a817bc5b82d93c573ea5 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 19:48:40 +0300 Subject: keystone: ddr3: add ddr3.h to hold ddr3 API It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/board.c | 3 ++- board/ti/k2hk_evm/ddr3.c | 27 ++++++++++++++++----------- 2 files changed, 18 insertions(+), 12 deletions(-) (limited to 'board') diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index ef90f9d..f910ebe 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -63,7 +64,7 @@ static struct pll_init_data pll_config[] = { int dram_init(void) { - init_ddr3(); + ddr3_init(); gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index 6092eb8..0085f29 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -228,7 +229,7 @@ struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); -void init_ddr3(void) +void ddr3_init(void) { char dimm_name[32]; @@ -239,22 +240,26 @@ void init_ddr3(void) if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { init_pll(&ddr3a_400); if (cpu_revision() > 0) { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_32); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { init_pll(&ddr3a_333); if (cpu_revision() > 0) { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_64); } else { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_32); } } else { printf("Unknown SO-DIMM. Cannot configure DDR3\n"); @@ -263,6 +268,6 @@ void init_ddr3(void) } init_pll(&ddr3b_333); - init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); - init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } -- cgit v1.1 From 101eec50f021a354487a511dc1f72691404b2b48 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:41 +0300 Subject: keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/ddr3.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 78 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index 0085f29..b604266 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -188,6 +188,61 @@ static struct ddr3_phy_config ddr3phy_1333_64 = { .pir_v2 = 0x0000FF81ul, }; /******************************************************/ + +/* DDR PHY Configs Updated for PG 2.0 + * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ +static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + int get_dimm_params(char *dimm_name) { u8 spd_params[256]; @@ -240,7 +295,18 @@ void ddr3_init(void) if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { init_pll(&ddr3a_400); if (cpu_revision() > 0) { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1600_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1600_64A); + } + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); @@ -253,7 +319,17 @@ void ddr3_init(void) } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { init_pll(&ddr3a_333); if (cpu_revision() > 0) { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1333_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1333_64A); + } ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); } else { -- cgit v1.1 From 4984bce41fe78da160ccdad573b09b40e277ec7a Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:43 +0300 Subject: keystone2: move cpu_to_bus() to keystone.c The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/board.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'board') diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index f910ebe..3333eb0 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -23,8 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 device_big_endian; - unsigned int external_clk[ext_clk_count] = { [sys_clk] = 122880000, [alt_core_clk] = 125000000, @@ -136,18 +134,6 @@ int board_eth_init(bd_t *bis) } #endif -/* Byte swap the 32-bit data if the device is BE */ -int cpu_to_bus(u32 *ptr, u32 length) -{ - u32 i; - - if (device_big_endian) - for (i = 0; i < length; i++, ptr++) - *ptr = __swab32(*ptr); - - return 0; -} - #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { -- cgit v1.1 From 3d315386255f6d944c0ccb4c7c8819ce604429ab Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 23:44:44 +0300 Subject: k2hk: use common KS2_ prefix for all hardware definitions Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/ddr3.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'board') diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index b604266..31e9c31 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -299,20 +299,20 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_64A_pg2); } else { /* PG 1.1 */ - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_64A); } - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } @@ -323,18 +323,18 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_64A_pg2); } else { /* PG 1.1 */ - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_64A); } - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); } else { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32); } } else { @@ -344,6 +344,6 @@ void ddr3_init(void) } init_pll(&ddr3b_333); - ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } -- cgit v1.1 From 0bedbb81351193f1507ad127b6b26e19a93c2c42 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Wed, 9 Jul 2014 23:44:45 +0300 Subject: keystone2: add env option to do unitrd dt fixup With latest v3.13 kernel, unitrd dt fixup is not needed. However for older kernel versions such as v3.8/v3.10, it is needed. So to work with both, add a u-boot env variable that can be set to do dt fixup for older kernels. Signed-off-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/board.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index 3333eb0..646ecb3 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -157,11 +157,14 @@ void ft_board_setup(void *blob, bd_t *bd) u64 size[2]; char name[32], *env, *endp; int lpae, nodeoffset; + int unitrd_fixup = 0; u32 ddr3a_size; int nbanks; env = getenv("mem_lpae"); lpae = env && simple_strtol(env, NULL, 0); + env = getenv("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); ddr3a_size = 0; if (lpae) { @@ -204,10 +207,11 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, start, size, nbanks); /* Fix up the initrd */ - if (lpae) { + if (lpae && unitrd_fixup) { u64 initrd_start, initrd_end; u32 *prop1, *prop2; int err; + nodeoffset = fdt_path_offset(blob, "/chosen"); if (nodeoffset >= 0) { prop1 = (u32 *)fdt_getprop(blob, nodeoffset, -- cgit v1.1 From e595107ebbdeb3e50351e703cce08eb07f70c614 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 23:44:46 +0300 Subject: ARM: keystone2: move K2HK board files to common KS2 board directory This patch moves K2HK board directory to a common Keystone II board directory. The Board related common functions are moved to a common keystone board file. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/Makefile | 9 -- board/ti/k2hk_evm/README | 148 ------------------ board/ti/k2hk_evm/board.c | 292 ----------------------------------- board/ti/k2hk_evm/ddr3.c | 349 ------------------------------------------ board/ti/ks2_evm/Makefile | 10 ++ board/ti/ks2_evm/README_K2HK | 148 ++++++++++++++++++ board/ti/ks2_evm/board.c | 229 +++++++++++++++++++++++++++ board/ti/ks2_evm/board.h | 19 +++ board/ti/ks2_evm/board_k2hk.c | 81 ++++++++++ board/ti/ks2_evm/ddr3_k2hk.c | 349 ++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 836 insertions(+), 798 deletions(-) delete mode 100644 board/ti/k2hk_evm/Makefile delete mode 100644 board/ti/k2hk_evm/README delete mode 100644 board/ti/k2hk_evm/board.c delete mode 100644 board/ti/k2hk_evm/ddr3.c create mode 100644 board/ti/ks2_evm/Makefile create mode 100644 board/ti/ks2_evm/README_K2HK create mode 100644 board/ti/ks2_evm/board.c create mode 100644 board/ti/ks2_evm/board.h create mode 100644 board/ti/ks2_evm/board_k2hk.c create mode 100644 board/ti/ks2_evm/ddr3_k2hk.c (limited to 'board') diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile deleted file mode 100644 index 3645f2f..0000000 --- a/board/ti/k2hk_evm/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# K2HK-EVM: board Makefile -# (C) Copyright 2012-2014 -# Texas Instruments Incorporated, -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += board.o -obj-y += ddr3.o diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README deleted file mode 100644 index 7426b8d..0000000 --- a/board/ti/k2hk_evm/README +++ /dev/null @@ -1,148 +0,0 @@ -U-Boot port for Texas Instruments XTCIEVMK2X -============================================ - -Author: Murali Karicheri - -This README has information on the u-boot port for XTCIEVMK2X EVM board. -Documentation for this board can be found at - http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx - -The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. -More details on these SoCs are available at company websites - K2K: http://www.ti.com/product/tci6638k2k - K2H: http://www.ti.com/product/tci6638k2h - -Board configuration: -==================== - -Some of the peripherals that are configured by u-boot are:- - -1. 2GB DDR3 (can support 8GB SO DIMM as well) -2. 512M NAND (over ti emif16 bus) -3. 6MB MSM SRAM (part of the SoC) -4. two 1GBit Ethernet ports (SoC supports upto 4) -5. two UART ports -6. three i2c interfaces -7. three spi interfaces (only 1 interface supported in driver) - -There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. -To bring up SMP Linux on this board, there is a boot monitor -code that will be installed in MSMC SRAM. There is command available -to install this image from u-boot. - -The port related files can be found at following folders - keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ - K2HK evm board files: board/ti/k2hk_evm/ - -board configuration file: include/configs/k2hk_evm.h - -Supported boot modes: - - SPI NOR boot - - AEMIF NAND boot - -Supported image formats:- - - u-boot.bin: for loading and running u-boot.bin through Texas instruments - code composure studio (CCS) - - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot - - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot - -Build instructions: -=================== - -To build u-boot.bin - >make k2hk_evm_config - >make u-boot-spi.gph - -To build u-boot-spi.gph - >make k2hk_evm_config - >make u-boot-spi.gph - -To build u-boot-nand.gph - >make k2hk_evm_config - >make u-boot-nand.gph - -Load and Run U-Boot on K2HK EVM using CCS -========================================= - -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin -on EVM. See instructions at below link for installing CCS on a Windows PC. -http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# -Installing_Code_Composer_Studio -Use u-boot.bin from the build folder for loading annd running u-boot binary -on EVM. Follow instructions at -http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup -to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" -and Power ON the EVM. Follow instructions to connect serial port of EVM to -PC and start TeraTerm or Hyper Terminal. - -Start CCS on a Windows machine and Launch Target -configuration as instructed at http://processors.wiki.ti.com/index.php/ -MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. -The instructions provided in the above link uses a script for -loading the u-boot binary on the target EVM. Instead do the following:- - -1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D - isconnected: Unknown)" at the debug window (This is created once Target - configuration is launched) and select "Connect Target". -2. Once target connect is successful, choose Tools->Load Memory option from the - top level menu. At the Load Memory window, choose the file u-boot.bin - through "Browse" button and click "next >" button. In the next window, enter - Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" - button. -3. Click View -> Registers from the top level menu to view registers window. -4. From Registers, window expand "Core Registers" to view PC. Edit PC value - to be 0xc001000. From the "Run" top level menu, select "Free Run" -5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as - below and type any key to stop autoboot as instructed := - -U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) - -I2C: ready -Detected SO-DIMM [SQR-SD3T-2G1333SED] -DRAM: 1.1 GiB -NAND: 512 MiB -Net: K2HK_EMAC -Warning: K2HK_EMAC using MAC address from net device -, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 -Hit any key to stop autoboot: 0 - -SPI NOR Flash programming instructions -====================================== -U-Boot image can be flashed to first 512KB of the NOR flash using following -instructions:- - -1. Start CCS and run U-boot as described above. -2. Suspend Target. Select Run -> Suspend from top level menu - CortexA15_1 (Free Running)" -3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM - using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. - setenv addr_uboot 0x87000000 - setenv filesize - run burn_uboot_spi - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch - to "SPI Little Endian Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. - -AEMIF NAND Flash programming instructions -====================================== -U-Boot image can be flashed to first 1024KB of the NAND flash using following -instructions:- - -1. Start CCS and run U-boot as described above. -2. Suspend Target. Select Run -> Suspend from top level menu - CortexA15_1 (Free Running)" -3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM - using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. - setenv filesize - run burn_uboot_nand - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch - to "ARM NAND Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c deleted file mode 100644 index 646ecb3..0000000 --- a/board/ti/k2hk_evm/board.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * K2HK EVM : Board initialization - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 122880000, - [alt_core_clk] = 125000000, - [pa_clk] = 122880000, - [tetris_clk] = 125000000, - [ddr3a_clk] = 100000000, - [ddr3b_clk] = 100000000, - [mcm_clk] = 312500000, - [pcie_clk] = 100000000, - [sgmii_srio_clk] = 156250000, - [xgmii_clk] = 156250000, - [usb_clk] = 100000000, - [rp1_clk] = 123456789 /* TODO: cannot find - what is that */ -}; - -static struct aemif_config aemif_configs[] = { - { /* CS0 */ - .mode = AEMIF_MODE_NAND, - .wr_setup = 0xf, - .wr_strobe = 0x3f, - .wr_hold = 7, - .rd_setup = 0xf, - .rd_strobe = 0x3f, - .rd_hold = 7, - .turn_around = 3, - .width = AEMIF_WIDTH_8, - }, - -}; - -static struct pll_init_data pll_config[] = { - CORE_PLL_1228, - PASS_PLL_983, - TETRIS_PLL_1200, -}; - -int dram_init(void) -{ - ddr3_init(); - - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - return 0; -} - -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2HK_EMAC", - .rx_flow = 22, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - }, - { - .int_name = "K2HK_EMAC1", - .rx_flow = 23, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - }, - { - .int_name = "K2HK_EMAC2", - .rx_flow = 24, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - }, - { - .int_name = "K2HK_EMAC3", - .rx_flow = 25, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - }, -}; - -int get_eth_env_param(char *env_name) -{ - char *env; - int res = -1; - - env = getenv(env_name); - if (env) - res = simple_strtol(env, NULL, 0); - - return res; -} - -int board_eth_init(bd_t *bis) -{ - int j; - int res; - char link_type_name[32]; - - for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t)); - j++) { - sprintf(link_type_name, "sgmii%d_link_type", j); - res = get_eth_env_param(link_type_name); - if (res >= 0) - eth_priv_cfg[j].sgmii_link_type = res; - - keystone2_emac_initialize(ð_priv_cfg[j]); - } - - return 0; -} -#endif - -#if defined(CONFIG_BOARD_EARLY_INIT_F) -int board_early_init_f(void) -{ - init_plls(ARRAY_SIZE(pll_config), pll_config); - return 0; -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -#define K2_DDR3_START_ADDR 0x80000000 -void ft_board_setup(void *blob, bd_t *bd) -{ - u64 start[2]; - u64 size[2]; - char name[32], *env, *endp; - int lpae, nodeoffset; - int unitrd_fixup = 0; - u32 ddr3a_size; - int nbanks; - - env = getenv("mem_lpae"); - lpae = env && simple_strtol(env, NULL, 0); - env = getenv("uinitrd_fixup"); - unitrd_fixup = env && simple_strtol(env, NULL, 0); - - ddr3a_size = 0; - if (lpae) { - env = getenv("ddr3a_size"); - if (env) - ddr3a_size = simple_strtol(env, NULL, 10); - if ((ddr3a_size != 8) && (ddr3a_size != 4)) - ddr3a_size = 0; - } - - nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; - - /* adjust memory start address for LPAE */ - if (lpae) { - start[0] -= K2_DDR3_START_ADDR; - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; - } - - if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { - size[1] = ((u64)ddr3a_size - 2) << 30; - start[1] = 0x880000000; - nbanks++; - } - - /* reserve memory at start of bank */ - sprintf(name, "mem_reserve_head"); - env = getenv(name); - if (env) { - start[0] += ustrtoul(env, &endp, 0); - size[0] -= ustrtoul(env, &endp, 0); - } - - sprintf(name, "mem_reserve"); - env = getenv(name); - if (env) - size[0] -= ustrtoul(env, &endp, 0); - - fdt_fixup_memory_banks(blob, start, size, nbanks); - - /* Fix up the initrd */ - if (lpae && unitrd_fixup) { - u64 initrd_start, initrd_end; - u32 *prop1, *prop2; - int err; - - nodeoffset = fdt_path_offset(blob, "/chosen"); - if (nodeoffset >= 0) { - prop1 = (u32 *)fdt_getprop(blob, nodeoffset, - "linux,initrd-start", NULL); - prop2 = (u32 *)fdt_getprop(blob, nodeoffset, - "linux,initrd-end", NULL); - if (prop1 && prop2) { - initrd_start = __be32_to_cpu(*prop1); - initrd_start -= K2_DDR3_START_ADDR; - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; - initrd_start = __cpu_to_be64(initrd_start); - initrd_end = __be32_to_cpu(*prop2); - initrd_end -= K2_DDR3_START_ADDR; - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; - initrd_end = __cpu_to_be64(initrd_end); - - err = fdt_delprop(blob, nodeoffset, - "linux,initrd-start"); - if (err < 0) - puts("error deleting initrd-start\n"); - - err = fdt_delprop(blob, nodeoffset, - "linux,initrd-end"); - if (err < 0) - puts("error deleting initrd-end\n"); - - err = fdt_setprop(blob, nodeoffset, - "linux,initrd-start", - &initrd_start, - sizeof(initrd_start)); - if (err < 0) - puts("error adding initrd-start\n"); - - err = fdt_setprop(blob, nodeoffset, - "linux,initrd-end", - &initrd_end, - sizeof(initrd_end)); - if (err < 0) - puts("error adding linux,initrd-end\n"); - } - } - } -} - -void ft_board_setup_ex(void *blob, bd_t *bd) -{ - int lpae; - char *env; - u64 *reserve_start, size; - - env = getenv("mem_lpae"); - lpae = env && simple_strtol(env, NULL, 0); - - if (lpae) { - /* - * the initrd and other reserved memory areas are - * embedded in in the DTB itslef. fix up these addresses - * to 36 bit format - */ - reserve_start = (u64 *)((char *)blob + - fdt_off_mem_rsvmap(blob)); - while (1) { - *reserve_start = __cpu_to_be64(*reserve_start); - size = __cpu_to_be64(*(reserve_start + 1)); - if (size) { - *reserve_start -= K2_DDR3_START_ADDR; - *reserve_start += - CONFIG_SYS_LPAE_SDRAM_BASE; - *reserve_start = - __cpu_to_be64(*reserve_start); - } else { - break; - } - reserve_start += 2; - } - } -} -#endif diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c deleted file mode 100644 index 31e9c31..0000000 --- a/board/ti/k2hk_evm/ddr3.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Keystone2: DDR3 initialization - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1600_64A = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_64 = { - .sdcfg = 0x6200CE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001869ul, -}; - -static struct ddr3_phy_config ddr3phy_1600_32 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_32 = { - .sdcfg = 0x6200DE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001869ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64A = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_64 = { - .sdcfg = 0x62008C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001457ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_32 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_32 = { - .sdcfg = 0x62009C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xf0073200ul, - .sdrfc = 0x00001457ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; -/******************************************************/ - -/* DDR PHY Configs Updated for PG 2.0 - * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ -static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x32868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x32857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -int get_dimm_params(char *dimm_name) -{ - u8 spd_params[256]; - int ret; - int old_bus; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, spd_params, 256); - - i2c_set_bus_num(old_bus); - - dimm_name[0] = '\0'; - - if (ret) { - puts("Cannot read DIMM params\n"); - return 1; - } - - /* - * We need to convert spd data to dimm parameters - * and to DDR3 EMIF and PHY regirsters values. - * For now we just return DIMM type string value. - * Caller may use this value to choose appropriate - * a pre-set DDR3 configuration - */ - - strncpy(dimm_name, (char *)&spd_params[0x80], 18); - dimm_name[18] = '\0'; - - return 0; -} - -struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); -struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); -struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); -struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); - -void ddr3_init(void) -{ - char dimm_name[32]; - - get_dimm_params(dimm_name); - - printf("Detected SO-DIMM [%s]\n", dimm_name); - - if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { - init_pll(&ddr3a_400); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A_pg2); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A); - } - - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_64); - printf("DRAM: Capacity 8 GiB (includes reported below)\n"); - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_32); - printf("DRAM: Capacity 4 GiB (includes reported below)\n"); - } - } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { - init_pll(&ddr3a_333); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A_pg2); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A); - } - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_64); - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_32); - } - } else { - printf("Unknown SO-DIMM. Cannot configure DDR3\n"); - while (1) - ; - } - - init_pll(&ddr3b_333); - ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); -} diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile new file mode 100644 index 0000000..58d77dc --- /dev/null +++ b/board/ti/ks2_evm/Makefile @@ -0,0 +1,10 @@ +# +# KS2-EVM: board Makefile +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o +obj-$(CONFIG_K2HK_EVM) += board_k2hk.o +obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o diff --git a/board/ti/ks2_evm/README_K2HK b/board/ti/ks2_evm/README_K2HK new file mode 100644 index 0000000..7426b8d --- /dev/null +++ b/board/ti/ks2_evm/README_K2HK @@ -0,0 +1,148 @@ +U-Boot port for Texas Instruments XTCIEVMK2X +============================================ + +Author: Murali Karicheri + +This README has information on the u-boot port for XTCIEVMK2X EVM board. +Documentation for this board can be found at + http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx + +The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. +More details on these SoCs are available at company websites + K2K: http://www.ti.com/product/tci6638k2k + K2H: http://www.ti.com/product/tci6638k2h + +Board configuration: +==================== + +Some of the peripherals that are configured by u-boot are:- + +1. 2GB DDR3 (can support 8GB SO DIMM as well) +2. 512M NAND (over ti emif16 bus) +3. 6MB MSM SRAM (part of the SoC) +4. two 1GBit Ethernet ports (SoC supports upto 4) +5. two UART ports +6. three i2c interfaces +7. three spi interfaces (only 1 interface supported in driver) + +There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. +To bring up SMP Linux on this board, there is a boot monitor +code that will be installed in MSMC SRAM. There is command available +to install this image from u-boot. + +The port related files can be found at following folders + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ + K2HK evm board files: board/ti/k2hk_evm/ + +board configuration file: include/configs/k2hk_evm.h + +Supported boot modes: + - SPI NOR boot + - AEMIF NAND boot + +Supported image formats:- + - u-boot.bin: for loading and running u-boot.bin through Texas instruments + code composure studio (CCS) + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot + +Build instructions: +=================== + +To build u-boot.bin + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-spi.gph + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-nand.gph + >make k2hk_evm_config + >make u-boot-nand.gph + +Load and Run U-Boot on K2HK EVM using CCS +========================================= + +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +on EVM. See instructions at below link for installing CCS on a Windows PC. +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# +Installing_Code_Composer_Studio +Use u-boot.bin from the build folder for loading annd running u-boot binary +on EVM. Follow instructions at +http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" +and Power ON the EVM. Follow instructions to connect serial port of EVM to +PC and start TeraTerm or Hyper Terminal. + +Start CCS on a Windows machine and Launch Target +configuration as instructed at http://processors.wiki.ti.com/index.php/ +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. +The instructions provided in the above link uses a script for +loading the u-boot binary on the target EVM. Instead do the following:- + +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D + isconnected: Unknown)" at the debug window (This is created once Target + configuration is launched) and select "Connect Target". +2. Once target connect is successful, choose Tools->Load Memory option from the + top level menu. At the Load Memory window, choose the file u-boot.bin + through "Browse" button and click "next >" button. In the next window, enter + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + button. +3. Click View -> Registers from the top level menu to view registers window. +4. From Registers, window expand "Core Registers" to view PC. Edit PC value + to be 0xc001000. From the "Run" top level menu, select "Free Run" +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as + below and type any key to stop autoboot as instructed := + +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) + +I2C: ready +Detected SO-DIMM [SQR-SD3T-2G1333SED] +DRAM: 1.1 GiB +NAND: 512 MiB +Net: K2HK_EMAC +Warning: K2HK_EMAC using MAC address from net device +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 +Hit any key to stop autoboot: 0 + +SPI NOR Flash programming instructions +====================================== +U-Boot image can be flashed to first 512KB of the NOR flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv addr_uboot 0x87000000 + setenv filesize + run burn_uboot_spi + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "SPI Little Endian Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c new file mode 100644 index 0000000..dfe7be6 --- /dev/null +++ b/board/ti/ks2_evm/board.c @@ -0,0 +1,229 @@ +/* + * Keystone : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "board.h" +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct aemif_config aemif_configs[] = { + { /* CS0 */ + .mode = AEMIF_MODE_NAND, + .wr_setup = 0xf, + .wr_strobe = 0x3f, + .wr_hold = 7, + .rd_setup = 0xf, + .rd_strobe = 0x3f, + .rd_hold = 7, + .turn_around = 3, + .width = AEMIF_WIDTH_8, + }, +}; + +int dram_init(void) +{ + ddr3_init(); + + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +int get_eth_env_param(char *env_name) +{ + char *env; + int res = -1; + + env = getenv(env_name); + if (env) + res = simple_strtol(env, NULL, 0); + + return res; +} + +int board_eth_init(bd_t *bis) +{ + int j; + int res; + int port_num; + char link_type_name[32]; + + port_num = get_num_eth_ports(); + + for (j = 0; j < port_num; j++) { + sprintf(link_type_name, "sgmii%d_link_type", j); + res = get_eth_env_param(link_type_name); + if (res >= 0) + eth_priv_cfg[j].sgmii_link_type = res; + + keystone2_emac_initialize(ð_priv_cfg[j]); + } + + return 0; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int lpae; + char *env; + char *endp; + int nbanks; + u64 size[2]; + u64 start[2]; + char name[32]; + int nodeoffset; + u32 ddr3a_size; + int unitrd_fixup = 0; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + env = getenv("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); + + ddr3a_size = 0; + if (lpae) { + env = getenv("ddr3a_size"); + if (env) + ddr3a_size = simple_strtol(env, NULL, 10); + if ((ddr3a_size != 8) && (ddr3a_size != 4)) + ddr3a_size = 0; + } + + nbanks = 1; + start[0] = bd->bi_dram[0].start; + size[0] = bd->bi_dram[0].size; + + /* adjust memory start address for LPAE */ + if (lpae) { + start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + } + + if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { + size[1] = ((u64)ddr3a_size - 2) << 30; + start[1] = 0x880000000; + nbanks++; + } + + /* reserve memory at start of bank */ + sprintf(name, "mem_reserve_head"); + env = getenv(name); + if (env) { + start[0] += ustrtoul(env, &endp, 0); + size[0] -= ustrtoul(env, &endp, 0); + } + + sprintf(name, "mem_reserve"); + env = getenv(name); + if (env) + size[0] -= ustrtoul(env, &endp, 0); + + fdt_fixup_memory_banks(blob, start, size, nbanks); + + /* Fix up the initrd */ + if (lpae && unitrd_fixup) { + int err; + u32 *prop1, *prop2; + u64 initrd_start, initrd_end; + + nodeoffset = fdt_path_offset(blob, "/chosen"); + if (nodeoffset >= 0) { + prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-start", NULL); + prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-end", NULL); + if (prop1 && prop2) { + initrd_start = __be32_to_cpu(*prop1); + initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start = __cpu_to_be64(initrd_start); + initrd_end = __be32_to_cpu(*prop2); + initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end = __cpu_to_be64(initrd_end); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-start"); + if (err < 0) + puts("error deleting initrd-start\n"); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-end"); + if (err < 0) + puts("error deleting initrd-end\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-start", + &initrd_start, + sizeof(initrd_start)); + if (err < 0) + puts("error adding initrd-start\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-end", + &initrd_end, + sizeof(initrd_end)); + if (err < 0) + puts("error adding linux,initrd-end\n"); + } + } + } +} + +void ft_board_setup_ex(void *blob, bd_t *bd) +{ + int lpae; + u64 size; + char *env; + u64 *reserve_start; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + + if (lpae) { + /* + * the initrd and other reserved memory areas are + * embedded in in the DTB itslef. fix up these addresses + * to 36 bit format + */ + reserve_start = (u64 *)((char *)blob + + fdt_off_mem_rsvmap(blob)); + while (1) { + *reserve_start = __cpu_to_be64(*reserve_start); + size = __cpu_to_be64(*(reserve_start + 1)); + if (size) { + *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start += + CONFIG_SYS_LPAE_SDRAM_BASE; + *reserve_start = + __cpu_to_be64(*reserve_start); + } else { + break; + } + reserve_start += 2; + } + } +} +#endif diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h new file mode 100644 index 0000000..d91ef73 --- /dev/null +++ b/board/ti/ks2_evm/board.h @@ -0,0 +1,19 @@ +/* + * K2HK EVM : Board common header + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KS2_BOARD +#define _KS2_BOARD + +#include + +extern struct eth_priv_t eth_priv_cfg[]; + +int get_num_eth_ports(void); + +#endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c new file mode 100644 index 0000000..a369d6b --- /dev/null +++ b/board/ti/ks2_evm/board_k2hk.c @@ -0,0 +1,81 @@ +/* + * K2HK EVM : Board initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 125000000, + [pa_clk] = 122880000, + [tetris_clk] = 125000000, + [ddr3a_clk] = 100000000, + [ddr3b_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_srio_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, + [rp1_clk] = 123456789 +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1228, + PASS_PLL_983, + TETRIS_PLL_1200, +}; + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2HK_EMAC", + .rx_flow = 22, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC1", + .rx_flow = 23, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC2", + .rx_flow = 24, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2HK_EMAC3", + .rx_flow = 25, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c new file mode 100644 index 0000000..31e9c31 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -0,0 +1,349 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1600_64A = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1600_64 = { + .sdcfg = 0x6200CE6aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +static struct ddr3_phy_config ddr3phy_1600_32 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1600_32 = { + .sdcfg = 0x6200DE6aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1333_64A = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | + NOSRA_MASK | UDIMM_MASK), + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1333_64 = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001457ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_32 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | + NOSRA_MASK | UDIMM_MASK), + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1333_32 = { + .sdcfg = 0x62009C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0xf0073200ul, + .sdrfc = 0x00001457ul, +}; + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1333_64 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; +/******************************************************/ + +/* DDR PHY Configs Updated for PG 2.0 + * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ +static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +int get_dimm_params(char *dimm_name) +{ + u8 spd_params[256]; + int ret; + int old_bus; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} + +struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); +struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); +struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); +struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); + +void ddr3_init(void) +{ + char dimm_name[32]; + + get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + init_pll(&ddr3a_400); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_64A); + } + + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_64); + printf("DRAM: Capacity 8 GiB (includes reported below)\n"); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_32); + printf("DRAM: Capacity 4 GiB (includes reported below)\n"); + } + } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { + init_pll(&ddr3a_333); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_64A); + } + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_64); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_32); + } + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; + } + + init_pll(&ddr3b_333); + ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); +} -- cgit v1.1 From b1babef856f936278d24bd0bf84f9cf702df2392 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 23:44:49 +0300 Subject: keystone: ddr3: move K2HK DDR3 configuration to a common file It's convenient to hold configurations for DDR3 PHY and EMIF in separate common place. This patch moves K2HK DDR3 PHY and EMIF configuration data with different rates and memory size to a common ddr3_cfg.c file. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/ks2_evm/Makefile | 1 + board/ti/ks2_evm/ddr3_cfg.c | 130 ++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.h | 21 +++ board/ti/ks2_evm/ddr3_k2hk.c | 305 +++---------------------------------------- 4 files changed, 172 insertions(+), 285 deletions(-) create mode 100644 board/ti/ks2_evm/ddr3_cfg.c create mode 100644 board/ti/ks2_evm/ddr3_cfg.h (limited to 'board') diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 58d77dc..774a7d5 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -6,5 +6,6 @@ # obj-y += board.o +obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c new file mode 100644 index 0000000..6e55af9 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -0,0 +1,130 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* DDR3 PHY configuration data with 1600M rate, 8GB size */ +struct ddr3_phy_config ddr3phy_1600_8g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ +struct ddr3_emif_config ddr3_1600_8g = { + .sdcfg = 0x6200CE6Aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +#ifdef CONFIG_K2HK_EVM +/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ +struct ddr3_phy_config ddr3phy_1333_2g = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ +struct ddr3_emif_config ddr3_1333_2g = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001457ul, +}; +#endif + +int ddr3_get_dimm_params(char *dimm_name) +{ + int ret; + int old_bus; + u8 spd_params[256]; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h new file mode 100644 index 0000000..d14bac3 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -0,0 +1,21 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR3_CFG_H +#define __DDR3_CFG_H + +extern struct ddr3_phy_config ddr3phy_1600_8g; +extern struct ddr3_emif_config ddr3_1600_8g; + +extern struct ddr3_phy_config ddr3phy_1333_2g; +extern struct ddr3_emif_config ddr3_1333_2g; + +int ddr3_get_dimm_params(char *dimm_name); + +#endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index 31e9c31..21a5a0a 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -8,287 +8,18 @@ */ #include +#include "ddr3_cfg.h" #include #include -#include -#include - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1600_64A = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_64 = { - .sdcfg = 0x6200CE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001869ul, -}; - -static struct ddr3_phy_config ddr3phy_1600_32 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_32 = { - .sdcfg = 0x6200DE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001869ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64A = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_64 = { - .sdcfg = 0x62008C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001457ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_32 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_32 = { - .sdcfg = 0x62009C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xf0073200ul, - .sdrfc = 0x00001457ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; -/******************************************************/ - -/* DDR PHY Configs Updated for PG 2.0 - * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ -static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x32868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x32857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -int get_dimm_params(char *dimm_name) -{ - u8 spd_params[256]; - int ret; - int old_bus; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, spd_params, 256); - - i2c_set_bus_num(old_bus); - - dimm_name[0] = '\0'; - - if (ret) { - puts("Cannot read DIMM params\n"); - return 1; - } - - /* - * We need to convert spd data to dimm parameters - * and to DDR3 EMIF and PHY regirsters values. - * For now we just return DIMM type string value. - * Caller may use this value to choose appropriate - * a pre-set DDR3 configuration - */ - - strncpy(dimm_name, (char *)&spd_params[0x80], 18); - dimm_name[18] = '\0'; - - return 0; -} struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); -struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); -struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); void ddr3_init(void) { char dimm_name[32]; - get_dimm_params(dimm_name); + ddr3_get_dimm_params(dimm_name); printf("Detected SO-DIMM [%s]\n", dimm_name); @@ -299,21 +30,25 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A_pg2); + &ddr3phy_1600_8g); } else { /* PG 1.1 */ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A); + &ddr3phy_1600_8g); } ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_64); + &ddr3_1600_8g); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_1600_8g.sdcfg |= 0x1000; ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_32); + &ddr3_1600_8g); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { @@ -323,27 +58,27 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); + ddr3phy_1333_2g.zq0cr1 |= 0x10000; + ddr3phy_1333_2g.zq1cr1 |= 0x10000; + ddr3phy_1333_2g.zq2cr1 |= 0x10000; ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A_pg2); + &ddr3phy_1333_2g); } else { /* PG 1.1 */ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A); + &ddr3phy_1333_2g); } ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_64); + &ddr3_1333_2g); } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); + ddr3_1333_2g.sdcfg |= 0x1000; ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_32); + &ddr3_1333_2g); } } else { printf("Unknown SO-DIMM. Cannot configure DDR3\n"); while (1) ; } - - init_pll(&ddr3b_333); - ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } -- cgit v1.1 From a906847966fd097835712b2ad3b5bac340793d43 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 16 Jul 2014 00:59:27 +0300 Subject: board: k2e-evm: add board support This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/ks2_evm/Makefile | 2 ++ board/ti/ks2_evm/board_k2e.c | 39 +++++++++++++++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.c | 40 ++++++++++++++++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.h | 3 +++ board/ti/ks2_evm/ddr3_k2e.c | 55 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 139 insertions(+) create mode 100644 board/ti/ks2_evm/board_k2e.c create mode 100644 board/ti/ks2_evm/ddr3_k2e.c (limited to 'board') diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 774a7d5..00f1164 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -9,3 +9,5 @@ obj-y += board.o obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o +obj-$(CONFIG_K2E_EVM) += board_k2e.o +obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c new file mode 100644 index 0000000..d2499b7 --- /dev/null +++ b/board/ti/ks2_evm/board_k2e.c @@ -0,0 +1,39 @@ +/* + * K2E EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 100000000, + [alt_core_clk] = 100000000, + [pa_clk] = 100000000, + [ddr3_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1200, + PASS_PLL_1000, +}; + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index 6e55af9..f7da9f2 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -93,6 +93,46 @@ struct ddr3_emif_config ddr3_1333_2g = { }; #endif +#ifdef CONFIG_K2E_EVM +/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ +struct ddr3_phy_config ddr3phy_1600_4g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x08861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D9CBB66ul, + .dtpr1 = 0x12840300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ +struct ddr3_emif_config ddr3_1600_4g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x421DFF53ul, + .sdtim4 = 0x543F07FFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; +#endif + int ddr3_get_dimm_params(char *dimm_name) { int ret; diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index d14bac3..15fcf52 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -16,6 +16,9 @@ extern struct ddr3_emif_config ddr3_1600_8g; extern struct ddr3_phy_config ddr3phy_1333_2g; extern struct ddr3_emif_config ddr3_1333_2g; +extern struct ddr3_phy_config ddr3phy_1600_4g; +extern struct ddr3_emif_config ddr3_1600_4g; + int ddr3_get_dimm_params(char *dimm_name); #endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c new file mode 100644 index 0000000..40fd966 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -0,0 +1,55 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + char dimm_name[32]; + + if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) + init_pll(&ddr3_400); + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + /* 8G SO-DIMM */ + ddr3_size = 8; + printf("DRAM: 8 GiB\n"); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); + } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { + /* 4G SO-DIMM */ + ddr3_size = 4; + printf("DRAM: 4 GiB\n"); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} -- cgit v1.1