From 4b97bcbe20d185f116b70613c42649e8a0a5146b Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Sat, 19 Apr 2014 22:12:18 +0200 Subject: am33xx: add SSC enable macro Signed-off-by: Yegor Yefremov --- board/siemens/rut/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index e0ada3f..1752df2 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -400,7 +400,7 @@ static int conf_disp_pll(int m, int n) #if defined(DISPL_PLL_SPREAD_SPECTRUM) writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ - writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12), + writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK, &cmwkup->clkmoddplldisp); /* 0x98 */ #endif return 0; -- cgit v1.1 From 9fc2ed40cd32cbb488e7a765e393e6b7ff21c1bc Mon Sep 17 00:00:00 2001 From: "Egli, Samuel" Date: Thu, 24 Apr 2014 17:57:52 +0200 Subject: siemens: cosmetic: remove unused and rename defines For dxr2 board DXR2_IOCTRL_VAL is set by data in EEPROM. In pxm2 board it does not make sense to have dxr2 as prefix. Replace it with more meaningful DDR prefix. Signed-off-by: Samuel Egli Cc: Pascal Bach Cc: Roger Meier Cc: Heiko Schocher Cc: Wolfgang Denk --- board/siemens/pxm2/board.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 98083d5..64e69dc 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -70,11 +70,11 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = { }; const struct ctrl_ioregs ioregs = { - .cm0ioctl = DXR2_IOCTRL_VAL, - .cm1ioctl = DXR2_IOCTRL_VAL, - .cm2ioctl = DXR2_IOCTRL_VAL, - .dt0ioctl = DXR2_IOCTRL_VAL, - .dt1ioctl = DXR2_IOCTRL_VAL, + .cm0ioctl = DDR_IOCTRL_VAL, + .cm1ioctl = DDR_IOCTRL_VAL, + .cm2ioctl = DDR_IOCTRL_VAL, + .dt0ioctl = DDR_IOCTRL_VAL, + .dt1ioctl = DDR_IOCTRL_VAL, }; config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data, -- cgit v1.1 From 823b2c4ce4b54b658b45055bbc4c79f15789d48c Mon Sep 17 00:00:00 2001 From: "Egli, Samuel" Date: Thu, 24 Apr 2014 17:57:53 +0200 Subject: siemens: update DDR3 parameters for dxr2 * add parameters for factory and print them at start up to facilitate control of right DDR3 settings in EEPROM. * cosmetic changes in a couple of printfs Signed-off-by: Samuel Egli Cc: Roger Meier Cc: Heiko Schocher Cc: Wolfgang Denk --- board/siemens/dxr2/board.c | 41 +++++++++++++++++++++++++++++------------ board/siemens/dxr2/board.h | 24 +++++++++++++----------- 2 files changed, 42 insertions(+), 23 deletions(-) (limited to 'board') diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 38ac93d..e9f157a 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -38,12 +38,26 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD static struct dxr2_baseboard_id __attribute__((section(".data"))) settings; -/* @303MHz-i0 */ + +#if DDR_PLL_FREQ == 303 +/* Default@303MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, + 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x0000093B, 0x0000014A, + "default name @303MHz \0", + "default marking \0", +}; +#elif DDR_PLL_FREQ == 400 +/* Default@400MHz-i0 */ const struct ddr3_data ddr3_default = { - 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4, - 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, + 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, 0x00000618, 0x0000014A, + "default name @400MHz \0", + "default marking \0", }; +#endif static void set_default_ddr3_timings(void) { @@ -53,8 +67,12 @@ static void set_default_ddr3_timings(void) static void print_ddr3_timings(void) { - printf("\n\nDDR3 Timing parameters:\n"); - printf("Diff Eeprom Default\n"); + printf("\nDDR3\n"); + printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); + printf("device:\t\t%s\n", settings.ddr3.manu_name); + printf("marking:\t%s\n", settings.ddr3.manu_marking); + printf("timing parameters\n"); + printf("diff\teeprom\tdefault\n"); PRINTARGS(magic); PRINTARGS(version); PRINTARGS(ddr3_sratio); @@ -78,9 +96,9 @@ static void print_ddr3_timings(void) static void print_chip_data(void) { - printf("\n"); - printf("Device: '%s'\n", settings.chip.sdevname); - printf("HW version: '%s'\n", settings.chip.shwver); + printf("\nCPU BOARD\n"); + printf("device: \t'%s'\n", settings.chip.sdevname); + printf("hw version: \t'%s'\n", settings.chip.shwver); } #endif /* CONFIG_SPL_BUILD */ @@ -112,19 +130,18 @@ static int read_eeprom(void) printf("Using DDR3 settings from EEPROM\n"); } else { if (ddr3_default.magic != settings.ddr3.magic) - printf("Error: No valid DDR3 data in eeprom.\n"); + printf("Warning: No valid DDR3 data in eeprom.\n"); if (ddr3_default.version != settings.ddr3.version) - printf("Error: DDR3 data version does not match.\n"); + printf("Warning: DDR3 data version does not match.\n"); printf("Using default settings\n"); set_default_ddr3_timings(); } if (MAGIC_CHIP == settings.chip.magic) { - printf("Valid chip data in eeprom\n"); print_chip_data(); } else { - printf("Error: No chip data in eeprom\n"); + printf("Warning: No chip data in eeprom\n"); } print_ddr3_timings(); diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h index abf5432..a59ffb0 100644 --- a/board/siemens/dxr2/board.h +++ b/board/siemens/dxr2/board.h @@ -22,24 +22,26 @@ #define MAGIC_CHIP 0x50494843 /* Automatic generated definition */ -/* Wed, 18 Sep 2013 18:58:27 +0200 */ -/* From file: draco/ddr3-data-micron-v2.txt */ +/* Wed, 16 Apr 2014 16:50:41 +0200 */ +/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ struct ddr3_data { unsigned int magic; /* 0x33524444 */ - unsigned int version; /* 0x56312e34 */ - unsigned short int ddr3_sratio; /* 0x0100 */ - unsigned short int iclkout; /* 0x0001 */ + unsigned int version; /* 0x56312e35 */ + unsigned short int ddr3_sratio; /* 0x0080 */ + unsigned short int iclkout; /* 0x0000 */ unsigned short int dt0rdsratio0; /* 0x003A */ - unsigned short int dt0wdsratio0; /* 0x008A */ - unsigned short int dt0fwsratio0; /* 0x010B */ - unsigned short int dt0wrsratio0; /* 0x00C4 */ + unsigned short int dt0wdsratio0; /* 0x003F */ + unsigned short int dt0fwsratio0; /* 0x009F */ + unsigned short int dt0wrsratio0; /* 0x0079 */ unsigned int sdram_tim1; /* 0x0888A39B */ unsigned int sdram_tim2; /* 0x26247FDA */ unsigned int sdram_tim3; /* 0x501F821F */ unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ - unsigned int sdram_config; /* 0x61C04AB2 */ - unsigned int ref_ctrl; /* 0x00000618 */ - unsigned int ioctr_val; /* 0x0000018B */ + unsigned int sdram_config; /* 0x61A44A32 */ + unsigned int ref_ctrl; /* 0x0000093B */ + unsigned int ioctr_val; /* 0x0000014A */ + char manu_name[32]; /* "default@303MHz \0" */ + char manu_marking[32]; /* "default \0" */ }; struct chip_data { -- cgit v1.1 From 111c8e40934ca8dfc0c7faf7eeb836a823098f0f Mon Sep 17 00:00:00 2001 From: "Egli, Samuel" Date: Thu, 24 Apr 2014 17:57:54 +0200 Subject: siemens: add led cmd for flexible LED control * remove setting LED in user button function. We want to decouple reading user button and setting LED. This two things need to be done independently. * led cmd can be used to control LEDs that are defined in board file having a led cmd, one can easily set LEDs in u-boot shell. For example bootcmd can be extended to disable status LED before loading kernel. Signed-off-by: Samuel Egli Cc: Roger Meier Cc: Heiko Schocher Cc: Wolfgang Denk --- board/siemens/common/board.c | 46 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 7e8731b..2782bcc 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -128,12 +128,6 @@ do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) button = 0; gpio_free(gpio); - if (!button) { - /* LED0 - RED=1: GPIO2_0 2*32 = 64 */ - gpio_request(BOARD_DFU_BUTTON_LED, ""); - gpio_direction_output(BOARD_DFU_BUTTON_LED, 1); - gpio_set_value(BOARD_DFU_BUTTON_LED, 1); - } return button; } @@ -144,6 +138,46 @@ U_BOOT_CMD( "" ); #endif +/* + * This command sets led + * Input - name of led + * value of led + * Returns - 1 if input does not match + * 0 if led was set + */ +static int +do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int gpio = 0; + if (argc != 3) + goto exit; +#if defined(BOARD_STATUS_LED) + if (!strcmp(argv[1], "stat")) + gpio = BOARD_STATUS_LED; +#endif +#if defined(BOARD_DFU_BUTTON_LED) + if (!strcmp(argv[1], "dfu")) + gpio = BOARD_DFU_BUTTON_LED; +#endif + /* If argument does not mach exit */ + if (gpio == 0) + goto exit; + gpio_request(gpio, ""); + gpio_direction_output(gpio, 1); + if (!strcmp(argv[2], "1")) + gpio_set_value(gpio, 1); + else + gpio_set_value(gpio, 0); + return 0; +exit: + return 1; +} + +U_BOOT_CMD( + led, CONFIG_SYS_MAXARGS, 2, do_setled, + "Set led on or off", + "dfu val - set dfu led\nled stat val - set status led" +); static int do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -- cgit v1.1 From 820969f370ac9e0a6cb672ea54a62163bf1d88a3 Mon Sep 17 00:00:00 2001 From: "Egli, Samuel" Date: Mon, 5 May 2014 16:50:43 +0200 Subject: siemens:cosmetic, dxr2: rename dxr2 to draco The actual board name is draco and dxr2 is the target name. In the future we'll have different targets based on draco board. All changes are purely non-functional and basically rename dxr2 to draco. One style fix in board.c that existed already before. Signed-off-by: Samuel Egli Reviewed-by: Roger Meier Cc: Heiko Schocher Cc: Wolfgang Denk --- board/siemens/draco/Makefile | 21 ++++ board/siemens/draco/board.c | 283 ++++++++++++++++++++++++++++++++++++++++++ board/siemens/draco/board.h | 72 +++++++++++ board/siemens/draco/mux.c | 272 +++++++++++++++++++++++++++++++++++++++++ board/siemens/dxr2/Makefile | 21 ---- board/siemens/dxr2/board.c | 284 ------------------------------------------- board/siemens/dxr2/board.h | 72 ----------- board/siemens/dxr2/mux.c | 272 ----------------------------------------- 8 files changed, 648 insertions(+), 649 deletions(-) create mode 100644 board/siemens/draco/Makefile create mode 100644 board/siemens/draco/board.c create mode 100644 board/siemens/draco/board.h create mode 100644 board/siemens/draco/mux.c delete mode 100644 board/siemens/dxr2/Makefile delete mode 100644 board/siemens/dxr2/board.c delete mode 100644 board/siemens/dxr2/board.h delete mode 100644 board/siemens/dxr2/mux.c (limited to 'board') diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile new file mode 100644 index 0000000..f159932 --- /dev/null +++ b/board/siemens/draco/Makefile @@ -0,0 +1,21 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := mux.o +endif + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/factoryset.o +endif diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c new file mode 100644 index 0000000..9be2e34 --- /dev/null +++ b/board/siemens/draco/board.c @@ -0,0 +1,283 @@ +/* + * Board functions for TI AM335X based draco board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * + * Board functions for TI AM335X based boards + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static struct draco_baseboard_id __attribute__((section(".data"))) settings; + +#if DDR_PLL_FREQ == 303 +/* Default@303MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, + 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, + 0x0000093B, 0x0000014A, + "default name @303MHz \0", + "default marking \0", +}; +#elif DDR_PLL_FREQ == 400 +/* Default@400MHz-i0 */ +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, + 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, + 0x00000618, 0x0000014A, + "default name @400MHz \0", + "default marking \0", +}; +#endif + +static void set_default_ddr3_timings(void) +{ + printf("Set default DDR3 settings\n"); + settings.ddr3 = ddr3_default; +} + +static void print_ddr3_timings(void) +{ + printf("\nDDR3\n"); + printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); + printf("device:\t\t%s\n", settings.ddr3.manu_name); + printf("marking:\t%s\n", settings.ddr3.manu_marking); + printf("timing parameters\n"); + printf("diff\teeprom\tdefault\n"); + PRINTARGS(magic); + PRINTARGS(version); + PRINTARGS(ddr3_sratio); + PRINTARGS(iclkout); + + PRINTARGS(dt0rdsratio0); + PRINTARGS(dt0wdsratio0); + PRINTARGS(dt0fwsratio0); + PRINTARGS(dt0wrsratio0); + + PRINTARGS(sdram_tim1); + PRINTARGS(sdram_tim2); + PRINTARGS(sdram_tim3); + + PRINTARGS(emif_ddr_phy_ctlr_1); + + PRINTARGS(sdram_config); + PRINTARGS(ref_ctrl); + PRINTARGS(ioctr_val); +} + +static void print_chip_data(void) +{ + printf("\nCPU BOARD\n"); + printf("device: \t'%s'\n", settings.chip.sdevname); + printf("hw version: \t'%s'\n", settings.chip.shwver); +} +#endif /* CONFIG_SPL_BUILD */ + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + +#ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + + if (ddr3_default.magic == settings.ddr3.magic && + ddr3_default.version == settings.ddr3.version) { + printf("Using DDR3 settings from EEPROM\n"); + } else { + if (ddr3_default.magic != settings.ddr3.magic) + printf("Warning: No valid DDR3 data in eeprom.\n"); + if (ddr3_default.version != settings.ddr3.version) + printf("Warning: DDR3 data version does not match.\n"); + + printf("Using default settings\n"); + set_default_ddr3_timings(); + } + + if (MAGIC_CHIP == settings.chip.magic) + print_chip_data(); + else + printf("Warning: No chip data in eeprom\n"); + + print_ddr3_timings(); +#endif + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs draco_ddr3_emif_reg_data = { + .zq_config = 0x50074BE4, +}; + +struct ddr_data draco_ddr3_data = { +}; + +struct cmd_control draco_ddr3_cmd_ctrl_data = { +}; + +struct ctrl_ioregs draco_ddr3_ioregs = { +}; + + /* pass values from eeprom */ + draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + settings.ddr3.emif_ddr_phy_ctlr_1; + draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data, + &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + + factoryset_setenv(); + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} + +static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + + return 0; +}; + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, + "Reset LAN9303 switch via its reset pin", + "" +); +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#include "../common/board.c" diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h new file mode 100644 index 0000000..ff8ab76 --- /dev/null +++ b/board/siemens/draco/board.h @@ -0,0 +1,72 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ + settings.ddr3.x, ddr3_default.x +#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) +#define MAGIC_CHIP 0x50494843 + +/* Automatic generated definition */ +/* Wed, 16 Apr 2014 16:50:41 +0200 */ +/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ +struct ddr3_data { + unsigned int magic; /* 0x33524444 */ + unsigned int version; /* 0x56312e35 */ + unsigned short int ddr3_sratio; /* 0x0080 */ + unsigned short int iclkout; /* 0x0000 */ + unsigned short int dt0rdsratio0; /* 0x003A */ + unsigned short int dt0wdsratio0; /* 0x003F */ + unsigned short int dt0fwsratio0; /* 0x009F */ + unsigned short int dt0wrsratio0; /* 0x0079 */ + unsigned int sdram_tim1; /* 0x0888A39B */ + unsigned int sdram_tim2; /* 0x26247FDA */ + unsigned int sdram_tim3; /* 0x501F821F */ + unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ + unsigned int sdram_config; /* 0x61A44A32 */ + unsigned int ref_ctrl; /* 0x0000093B */ + unsigned int ioctr_val; /* 0x0000014A */ + char manu_name[32]; /* "default@303MHz \0" */ + char manu_marking[32]; /* "default \0" */ +}; + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; +}; + +struct draco_baseboard_id { + struct ddr3_data ddr3; + struct chip_data chip; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c new file mode 100644 index 0000000..eaa3c70 --- /dev/null +++ b/board/siemens/draco/mux.c @@ -0,0 +1,272 @@ +/* + * pinmux setup for siemens draco board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux gpios_pin_mux[] = { + /* DFU button GPIO0_27*/ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, + {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ + {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ + /* Triacs in HW Rev 2 */ + {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/ + {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ + {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ + /* Triacs initial HW Rev */ + {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */ + {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ + {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ + {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ + {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */ + {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */ + {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */ + {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */ + /* Remaining pins that were not used in this file */ + {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, + {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, + /* nRST for SMSC LAN9303 switch - GPIO2_24 */ + {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */ + {-1}, +}; + +static struct module_pin_mux ethernet_pin_mux[] = { + {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + enable_uart3_pin_mux(); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ethernet_pin_mux); + configure_module_pin_mux(gpios_pin_mux); +} diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile deleted file mode 100644 index f159932..0000000 --- a/board/siemens/dxr2/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Makefile -# -# (C) Copyright 2013 Siemens Schweiz AG -# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# Based on: -# u-boot:/board/ti/am335x/Makefile -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y := mux.o -endif - -obj-y += board.o -ifndef CONFIG_SPL_BUILD -obj-y += ../common/factoryset.o -endif diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c deleted file mode 100644 index e9f157a..0000000 --- a/board/siemens/dxr2/board.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Board functions for TI AM335X based dxr2 board - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * - * Board functions for TI AM335X based boards - * u-boot:/board/ti/am335x/board.c - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "board.h" -#include "../common/factoryset.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SPL_BUILD -static struct dxr2_baseboard_id __attribute__((section(".data"))) settings; - -#if DDR_PLL_FREQ == 303 -/* Default@303MHz-i0 */ -const struct ddr3_data ddr3_default = { - 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F, - 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32, - 0x0000093B, 0x0000014A, - "default name @303MHz \0", - "default marking \0", -}; -#elif DDR_PLL_FREQ == 400 -/* Default@400MHz-i0 */ -const struct ddr3_data ddr3_default = { - 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab, - 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232, - 0x00000618, 0x0000014A, - "default name @400MHz \0", - "default marking \0", -}; -#endif - -static void set_default_ddr3_timings(void) -{ - printf("Set default DDR3 settings\n"); - settings.ddr3 = ddr3_default; -} - -static void print_ddr3_timings(void) -{ - printf("\nDDR3\n"); - printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ); - printf("device:\t\t%s\n", settings.ddr3.manu_name); - printf("marking:\t%s\n", settings.ddr3.manu_marking); - printf("timing parameters\n"); - printf("diff\teeprom\tdefault\n"); - PRINTARGS(magic); - PRINTARGS(version); - PRINTARGS(ddr3_sratio); - PRINTARGS(iclkout); - - PRINTARGS(dt0rdsratio0); - PRINTARGS(dt0wdsratio0); - PRINTARGS(dt0fwsratio0); - PRINTARGS(dt0wrsratio0); - - PRINTARGS(sdram_tim1); - PRINTARGS(sdram_tim2); - PRINTARGS(sdram_tim3); - - PRINTARGS(emif_ddr_phy_ctlr_1); - - PRINTARGS(sdram_config); - PRINTARGS(ref_ctrl); - PRINTARGS(ioctr_val); -} - -static void print_chip_data(void) -{ - printf("\nCPU BOARD\n"); - printf("device: \t'%s'\n", settings.chip.sdevname); - printf("hw version: \t'%s'\n", settings.chip.shwver); -} -#endif /* CONFIG_SPL_BUILD */ - -/* - * Read header information from EEPROM into global structure. - */ -static int read_eeprom(void) -{ - /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { - printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); - return 1; - } - -#ifdef CONFIG_SPL_BUILD - /* Read Siemens eeprom data (DDR3) */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, - (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { - printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); - set_default_ddr3_timings(); - } - /* Read Siemens eeprom data (CHIP) */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, - (uchar *)&settings.chip, sizeof(settings.chip))) - printf("Could not read chip settings\n"); - - if (ddr3_default.magic == settings.ddr3.magic && - ddr3_default.version == settings.ddr3.version) { - printf("Using DDR3 settings from EEPROM\n"); - } else { - if (ddr3_default.magic != settings.ddr3.magic) - printf("Warning: No valid DDR3 data in eeprom.\n"); - if (ddr3_default.version != settings.ddr3.version) - printf("Warning: DDR3 data version does not match.\n"); - - printf("Using default settings\n"); - set_default_ddr3_timings(); - } - - if (MAGIC_CHIP == settings.chip.magic) { - print_chip_data(); - } else { - printf("Warning: No chip data in eeprom\n"); - } - - print_ddr3_timings(); -#endif - return 0; -} - -#ifdef CONFIG_SPL_BUILD -static void board_init_ddr(void) -{ -struct emif_regs dxr2_ddr3_emif_reg_data = { - .zq_config = 0x50074BE4, -}; - -struct ddr_data dxr2_ddr3_data = { -}; - -struct cmd_control dxr2_ddr3_cmd_ctrl_data = { -}; - -struct ctrl_ioregs dxr2_ddr3_ioregs = { -}; - - /* pass values from eeprom */ - dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; - dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; - dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; - dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = - settings.ddr3.emif_ddr_phy_ctlr_1; - dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; - dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; - - dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; - dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; - dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; - dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; - - dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; - dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; - dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; - dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; - dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; - dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; - - dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, - dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, - - config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data, - &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); -} - -static void spl_siemens_board_init(void) -{ - return; -} -#endif /* if def CONFIG_SPL_BUILD */ - -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_MII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 4, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -#if defined(CONFIG_DRIVER_TI_CPSW) || \ - (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) -int board_eth_init(bd_t *bis) -{ - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - int n = 0; - int rv; - - factoryset_setenv(); - - /* Set rgmii mode and enable rmii clock to be sourced from chip */ - writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; - return n; -} - -static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* Reset SMSC LAN9303 switch for default configuration */ - gpio_request(GPIO_LAN9303_NRST, "nRST"); - gpio_direction_output(GPIO_LAN9303_NRST, 0); - /* assert active low reset for 200us */ - udelay(200); - gpio_set_value(GPIO_LAN9303_NRST, 1); - - return 0; -}; - -U_BOOT_CMD( - switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, - "Reset LAN9303 switch via its reset pin", - "" -); -#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ -#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ - -#include "../common/board.c" diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h deleted file mode 100644 index a59ffb0..0000000 --- a/board/siemens/dxr2/board.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * board.h - * - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * TI AM335x boards information header - * u-boot:/board/ti/am335x/board.h - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ - settings.ddr3.x, ddr3_default.x -#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) -#define MAGIC_CHIP 0x50494843 - -/* Automatic generated definition */ -/* Wed, 16 Apr 2014 16:50:41 +0200 */ -/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ -struct ddr3_data { - unsigned int magic; /* 0x33524444 */ - unsigned int version; /* 0x56312e35 */ - unsigned short int ddr3_sratio; /* 0x0080 */ - unsigned short int iclkout; /* 0x0000 */ - unsigned short int dt0rdsratio0; /* 0x003A */ - unsigned short int dt0wdsratio0; /* 0x003F */ - unsigned short int dt0fwsratio0; /* 0x009F */ - unsigned short int dt0wrsratio0; /* 0x0079 */ - unsigned int sdram_tim1; /* 0x0888A39B */ - unsigned int sdram_tim2; /* 0x26247FDA */ - unsigned int sdram_tim3; /* 0x501F821F */ - unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ - unsigned int sdram_config; /* 0x61A44A32 */ - unsigned int ref_ctrl; /* 0x0000093B */ - unsigned int ioctr_val; /* 0x0000014A */ - char manu_name[32]; /* "default@303MHz \0" */ - char manu_marking[32]; /* "default \0" */ -}; - -struct chip_data { - unsigned int magic; - char sdevname[16]; - char shwver[7]; -}; - -struct dxr2_baseboard_id { - struct ddr3_data ddr3; - struct chip_data chip; -}; - -/* - * We have three pin mux functions that must exist. We must be able to enable - * uart0, for initial output and i2c0 to read the main EEPROM. We then have a - * main pinmux function that can be overridden to enable all other pinmux that - * is required on the board. - */ -void enable_uart0_pin_mux(void); -void enable_uart1_pin_mux(void); -void enable_uart2_pin_mux(void); -void enable_uart3_pin_mux(void); -void enable_uart4_pin_mux(void); -void enable_uart5_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(void); -#endif diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c deleted file mode 100644 index f2314b5..0000000 --- a/board/siemens/dxr2/mux.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * pinmux setup for siemens dxr2 board - * - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * u-boot:/board/ti/am335x/mux.c - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "board.h" - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ - {-1}, -}; - -static struct module_pin_mux uart3_pin_mux[] = { - {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ - {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ - {-1}, -}; - -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ - {-1}, -}; - -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; - -static struct module_pin_mux gpios_pin_mux[] = { - /* DFU button GPIO0_27*/ - {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, - {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ - {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ - /* Triacs in HW Rev 2 */ - {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/ - {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/ - {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/ - /* Triacs initial HW Rev */ - {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */ - {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */ - {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */ - {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */ - {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */ - {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */ - {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */ - {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */ - /* Remaining pins that were not used in this file */ - {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS}, - {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS}, - /* nRST for SMSC LAN9303 switch - GPIO2_24 */ - {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */ - {-1}, -}; - -static struct module_pin_mux ethernet_pin_mux[] = { - {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, - {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, - {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, - {OFFSET(mii1_txen), (MODE(1))}, - {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, - {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, - {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, - {OFFSET(mii1_txd1), (MODE(1))}, - {OFFSET(mii1_txd0), (MODE(1))}, - {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, - {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, - {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, - {OFFSET(mii1_rxd2), (MODE(1))}, - {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, - {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, - {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, - {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, - {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, - {-1}, -}; - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_uart3_pin_mux(void) -{ - configure_module_pin_mux(uart3_pin_mux); -} - -void enable_i2c0_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_board_pin_mux(void) -{ - enable_uart3_pin_mux(); - configure_module_pin_mux(nand_pin_mux); - configure_module_pin_mux(ethernet_pin_mux); - configure_module_pin_mux(gpios_pin_mux); -} -- cgit v1.1 From 2d92ba844068a72b50fbedbb17937ed264ef754a Mon Sep 17 00:00:00 2001 From: Ash Charles Date: Wed, 7 May 2014 08:24:11 -0700 Subject: am335x: pepper: Add Gumstix Pepper AM335x-based machine This adds the Gumstix Pepper[1] single-board computer based on the TI AM335x processor. Schematics are available [2]. [1] https://store.gumstix.com/index.php/products/344/ [2] https://pubs.gumstix.com/boards/PEPPER/ Signed-off-by: Ash Charles [trini: Move 'cdev' in board.c down to under #ifdef's where it's used] Signed-off-by: Tom Rini --- board/gumstix/pepper/Makefile | 13 +++ board/gumstix/pepper/board.c | 226 ++++++++++++++++++++++++++++++++++++++++++ board/gumstix/pepper/board.h | 19 ++++ board/gumstix/pepper/mux.c | 78 +++++++++++++++ 4 files changed, 336 insertions(+) create mode 100644 board/gumstix/pepper/Makefile create mode 100644 board/gumstix/pepper/board.c create mode 100644 board/gumstix/pepper/board.h create mode 100644 board/gumstix/pepper/mux.c (limited to 'board') diff --git a/board/gumstix/pepper/Makefile b/board/gumstix/pepper/Makefile new file mode 100644 index 0000000..ecb1d61 --- /dev/null +++ b/board/gumstix/pepper/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += mux.o +endif + +obj-y += board.o diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c new file mode 100644 index 0000000..75aac49 --- /dev/null +++ b/board/gumstix/pepper/board.c @@ -0,0 +1,226 @@ +/* + * Board functions for Gumstix Pepper and AM335x-based boards + * + * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ + * Based on board/ti/am335x/board.c from Texas Instruments, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static const struct ddr_data ddr2_data = { + .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | + (MT47H128M16RT25E_RD_DQS<<20) | + (MT47H128M16RT25E_RD_DQS<<10) | + (MT47H128M16RT25E_RD_DQS<<0)), + .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | + (MT47H128M16RT25E_WR_DQS<<20) | + (MT47H128M16RT25E_WR_DQS<<10) | + (MT47H128M16RT25E_WR_DQS<<0)), + .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | + (MT47H128M16RT25E_PHY_WRLVL<<20) | + (MT47H128M16RT25E_PHY_WRLVL<<10) | + (MT47H128M16RT25E_PHY_WRLVL<<0)), + .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | + (MT47H128M16RT25E_PHY_GATELVL<<20) | + (MT47H128M16RT25E_PHY_GATELVL<<10) | + (MT47H128M16RT25E_PHY_GATELVL<<0)), + .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | + (MT47H128M16RT25E_PHY_FIFO_WE<<20) | + (MT47H128M16RT25E_PHY_FIFO_WE<<10) | + (MT47H128M16RT25E_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | + (MT47H128M16RT25E_PHY_WR_DATA<<20) | + (MT47H128M16RT25E_PHY_WR_DATA<<10) | + (MT47H128M16RT25E_PHY_WR_DATA<<0)), +}; + +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = MT47H128M16RT25E_RATIO, + .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + + .cmd1csratio = MT47H128M16RT25E_RATIO, + .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, + + .cmd2csratio = MT47H128M16RT25E_RATIO, + .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, +}; + +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(266, &ioregs, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); +} +#endif + +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + const char *devname; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the KSZ9021 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the current instance. + */ + devname = miiphy_get_current_dev(); + /* max rx/tx clock delay, min rx/tx control delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8104); + miiphy_write(devname, 0x0, 0xc, 0xa0a0); + + /* min rx data delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8105); + miiphy_write(devname, 0x0, 0x0c, 0x0000); + + /* min tx data delay */ + miiphy_write(devname, 0x0, 0x0b, 0x8106); + miiphy_write(devname, 0x0, 0x0c, 0x0000); + + return n; +} +#endif diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h new file mode 100644 index 0000000..0512735 --- /dev/null +++ b/board/gumstix/pepper/board.h @@ -0,0 +1,19 @@ +/* + * Gumstix Pepper and AM335x-based boards information header + * + * Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * We must be able to enable uart0, for initial output. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c new file mode 100644 index 0000000..50b1266 --- /dev/null +++ b/board/gumstix/pepper/mux.c @@ -0,0 +1,78 @@ +/* + * Muxing for Gumstix Pepper and AM335x-based boards + * + * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */ + {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */ + {OFFSET(xdma_event_intr1), MODE(3)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +/* + * Do board-specific muxes. + */ +void enable_board_pin_mux(void) +{ + /* I2C0 */ + configure_module_pin_mux(i2c0_pin_mux); + /* SD Card */ + configure_module_pin_mux(mmc0_pin_mux); + /* Ethernet pinmux. */ + configure_module_pin_mux(rgmii1_pin_mux); +} -- cgit v1.1