From e76cd5d4cf311da7d40adc5d6e9b425509cf0205 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 23 Oct 2012 19:03:46 -0500 Subject: 8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming Tested-by: Andy Fleming Acked-by: Kim Phillips --- board/exmeritus/hww1u1a/hww1u1a.c | 2 +- board/freescale/mpc8540ads/mpc8540ads.c | 2 +- board/freescale/mpc8560ads/mpc8560ads.c | 2 +- board/freescale/mpc8569mds/mpc8569mds.c | 2 +- board/freescale/p1023rds/p1023rds.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 2 +- board/freescale/p2020ds/p2020ds.c | 2 +- board/sbc8548/ddr.c | 2 +- board/socrates/sdram.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c index 52c22fa..89cfaad 100644 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ b/board/exmeritus/hww1u1a/hww1u1a.c @@ -105,7 +105,7 @@ int checkboard(void) * and delay a while before we continue. */ if (mpc85xx_gpio_get(GPIO_RESETS)) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; puts("Debugger detected... extra device reset enabled!\n"); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a275d3a..418c06b 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -184,7 +184,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 285edbc..a4f48bb 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -389,7 +389,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index d119c65..0d3b418 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -247,7 +247,7 @@ int checkboard (void) #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index eb11f3f..9110767 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -74,7 +74,7 @@ int checkboard(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index d48fb01..09019e9 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; */ static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 3188f59..d4a4451 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -84,7 +84,7 @@ int checkboard(void) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; uint d_init; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 45ec485..9508561 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); out_be32(&ddr->cs0_bnds, 0x0000007f); out_be32(&ddr->cs1_bnds, 0x008000ff); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index c8235f4..8a9ce79 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -41,7 +41,7 @@ */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); /* * Disable memory controller. -- cgit v1.1 From d31e53b42c35a9285c1e688733ceaa995689418b Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 23 Oct 2012 09:40:22 +0000 Subject: powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- board/freescale/common/Makefile | 2 + board/freescale/common/ngpixis.h | 2 +- board/freescale/corenet_ds/Makefile | 2 + board/freescale/corenet_ds/corenet_ds.c | 22 +- board/freescale/corenet_ds/eth_superhydra.c | 722 ++++++++++++++++++++++++++++ board/freescale/corenet_ds/p5040ds_ddr.c | 18 + 6 files changed, 761 insertions(+), 7 deletions(-) create mode 100644 board/freescale/corenet_ds/eth_superhydra.c create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c (limited to 'board') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 36f7c4f..75725b4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o +COBJS-$(CONFIG_P5040DS) += ics307_clk.o COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o # deal with common files for P-series corenet based devices @@ -60,6 +61,7 @@ SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 1d4483d..a239ee3 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -45,7 +45,7 @@ typedef struct ngpixis { struct { u8 sw; u8 en; - } s[8]; + } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */ } __attribute__ ((packed)) ngpixis_t; /* Pointer to the PIXIS register set */ diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 1fdf8b7..d79193a 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -31,9 +31,11 @@ COBJS-y += ddr.o COBJS-$(CONFIG_P3041DS) += eth_hydra.o COBJS-$(CONFIG_P4080DS) += eth_p4080.o COBJS-$(CONFIG_P5020DS) += eth_hydra.o +COBJS-$(CONFIG_P5040DS) += eth_superhydra.o COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o +COBJS-$(CONFIG_P5040DS) += p5040ds_ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index a33c936..21428e3 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -45,6 +45,7 @@ int checkboard (void) struct cpu_type *cpu = gd->cpu; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; + static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", @@ -83,20 +84,28 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { - static const char *freq[] = {"100", "125", "156.25", "212.5" }; unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } +#ifdef CONFIG_P5040DS + /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ + sw = in_8(&PIXIS_SW(9)); + printf("Bank4=%sMhz ", freq[sw & 3]); +#endif puts("\n"); #else sw = in_8(&PIXIS_SW(3)); - printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); - printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); - printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); + /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ + /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ + /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ + printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); + printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); + printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); #endif return 0; @@ -168,7 +177,8 @@ int misc_init_r(void) unsigned int i; u8 sw; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c new file mode 100644 index 0000000..ef9de25 --- /dev/null +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -0,0 +1,722 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Author: Srikanth Srinivasan + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the board muxing between the Fman Ethernet MACs and + * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference + * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are + * provided by the standard Freescale four-port SGMII riser card. The 10Gb + * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans + * and 5 1G interfaces and 10G interface per FMan. Based on the options in + * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. + * + * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control + * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is + * always the same (0). The value for SGMII depends on which slot the riser is + * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, + * the value is based on which slot the XAUI is inserted in. + * + * The SERDES configuration is used to determine where the SGMII and XAUI cards + * exist, and also which Fman's MACs are routed to which PHYs. So for a given + * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed + * to PHYs dynamically. + * + * + * This file also updates the device tree in three ways: + * + * 1) The status of each virtual MDIO node that is referenced by an Ethernet + * node is set to "okay". + * + * 2) The phy-handle property of each active Ethernet MAC node is set to the + * appropriate PHY node. + * + * 3) The "mux value" for each virtual MDIO node is set to the correct value, + * if necessary. Some virtual MDIO nodes do not have configurable mux + * values, so those values are hard-coded in the DTS. On the HYDRA board, + * the virtual MDIO node for the SGMII card needs to be updated. + * + * For all this to work, the device tree needs to have the following: + * + * 1) An alias for each PHY node that an Ethernet node could be routed to. + * + * 2) An alias for each real and virtual MDIO node that is disabled by default + * and might need to be enabled, and also might need to have its mux-value + * updated. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/ngpixis.h" +#include "../common/fman.h" + +#ifdef CONFIG_FMAN_ENET + +#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_SLOT1 0x10 +#define BRDCFG1_EMI1_SEL_SLOT2 0x20 +#define BRDCFG1_EMI1_SEL_SLOT5 0x30 +#define BRDCFG1_EMI1_SEL_SLOT6 0x40 +#define BRDCFG1_EMI1_SEL_SLOT7 0x50 +#define BRDCFG1_EMI1_SEL_SLOT3 0x60 +#define BRDCFG1_EMI1_SEL_RGMII 0x00 +#define BRDCFG1_EMI1_EN 0x08 +#define BRDCFG1_EMI2_SEL_MASK 0x06 +#define BRDCFG1_EMI2_SEL_SLOT1 0x00 +#define BRDCFG1_EMI2_SEL_SLOT2 0x02 + +#define BRDCFG2_REG_GPIO_SEL 0x20 + +/* + * BRDCFG1 mask and value for each MAC + * + * This array contains the BRDCFG1 values (in mask/val format) that route the + * MDIO bus to a particular RGMII or SGMII PHY. + */ +static struct { + u8 mask; + u8 val; +} mdio_mux[NUM_FM_PORTS]; + +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 +}; + +/* + * Set the board muxing for a given MAC + * + * The MDIO layer calls this function every time it wants to talk to a PHY. + */ +void super_hydra_mux_mdio(u8 mask, u8 val) +{ + clrsetbits_8(&pixis->brdcfg1, mask, val); +} + +struct super_hydra_mdio { + u8 mask; + u8 val; + struct mii_dev *realbus; +}; + +static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct super_hydra_mdio *priv = bus->priv; + + super_hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct super_hydra_mdio *priv = bus->priv; + + super_hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int super_hydra_mdio_reset(struct mii_dev *bus) +{ + struct super_hydra_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) +{ + struct mii_dev *bus = miiphy_get_dev_by_name(name); + struct super_hydra_mdio *priv = bus->priv; + + priv->mask = mask; + priv->val = val; +} + +static int super_hydra_mdio_init(char *realbusname, char *fakebusname) +{ + struct super_hydra_mdio *hmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate Hydra MDIO bus\n"); + return -1; + } + + hmdio = malloc(sizeof(*hmdio)); + if (!hmdio) { + printf("Failed to allocate Hydra private data\n"); + free(bus); + return -1; + } + + bus->read = super_hydra_mdio_read; + bus->write = super_hydra_mdio_write; + bus->reset = super_hydra_mdio_reset; + sprintf(bus->name, fakebusname); + + hmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!hmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(hmdio); + return -1; + } + + bus->priv = hmdio; + + return mdio_register(bus); +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. That + * information is stored in mdio_mux[]. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + enum srds_prtcl device; + int lane, slot, phy; + char alias[32]; + + /* RGMII and XGMII are already mapped correctly in the DTS */ + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + device = serdes_device_from_fm_port(port); + lane = serdes_get_first_lane(device); + slot = lane_to_slot[lane]; + phy = fm_info_get_phy_address(port); + + sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + } +} + +#define PIXIS_SW2_LANE_23_SEL 0x80 +#define PIXIS_SW2_LANE_45_SEL 0x40 +#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 +#define PIXIS_SW2_LANE_67_SEL_5 0x00 +#define PIXIS_SW2_LANE_67_SEL_6 0x20 +#define PIXIS_SW2_LANE_67_SEL_7 0x10 +#define PIXIS_SW2_LANE_8_SEL 0x08 +#define PIXIS_SW2_LANE_1617_SEL 0x04 +#define PIXIS_SW11_LANE_9_SEL 0x04 +/* + * Initialize the lane_to_slot[] array. + * + * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board + * slots is hard-coded. On the Hydra board, however, the mapping is controlled + * by board switch SW2, so the lane_to_slot[] array needs to be dynamically + * initialized. + */ +static void initialize_lane_to_slot(void) +{ + u8 sw2 = in_8(&PIXIS_SW(2)); + /* SW11 appears in the programming model as SW9 */ + u8 sw11 = in_8(&PIXIS_SW(9)); + + lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; + lane_to_slot[3] = lane_to_slot[2]; + + lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; + lane_to_slot[5] = lane_to_slot[4]; + + switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { + case PIXIS_SW2_LANE_67_SEL_5: + lane_to_slot[6] = 5; + break; + case PIXIS_SW2_LANE_67_SEL_6: + lane_to_slot[6] = 6; + break; + case PIXIS_SW2_LANE_67_SEL_7: + lane_to_slot[6] = 7; + break; + } + lane_to_slot[7] = lane_to_slot[6]; + + lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; + lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; + + lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; + lane_to_slot[17] = lane_to_slot[16]; +} + +#endif /* #ifdef CONFIG_FMAN_ENET */ + +/* + * Configure the status for the virtual MDIO nodes + * + * Rather than create the virtual MDIO nodes from scratch for each active + * virtual MDIO, we expect the DTS to have the nodes defined already, and we + * only enable the ones that are actually active. + * + * We assume that the DTS already hard-codes the status for all the + * virtual MDIO nodes to "disabled", so all we need to do is enable the + * active ones. + */ +void fdt_fixup_board_enet(void *fdt) +{ +#ifdef CONFIG_FMAN_ENET + enum fm_port i; + int lane, slot; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_sg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", + alias, slot); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_status_okay_by_alias(fdt, "hydra_rg"); + debug("Enabled MDIO node hydra_rg\n"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_xg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", alias, slot); + } + +#if CONFIG_SYS_NUM_FMAN == 2 + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_sg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", + alias, slot); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_status_okay_by_alias(fdt, "hydra_rg"); + debug("Enabled MDIO node hydra_rg\n"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM2); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_xg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", alias, slot); + } +#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CONFIG_FMAN_ENET */ +} + +/* + * Mapping of SerDes Protocol to MDIO MUX value and PHY address. + * + * Fman 1: + * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 + * Mux Phy | Mux Phy | Mux Phy | Mux Phy + * Value Addr | Value Addr | Value Addr | Value Addr + * 0x00 2 1c | 2 1d | 2 1e | 2 1f + * 0x01 | | 6 1c | + * 0x02 | | 3 1c | 3 1d + * 0x03 2 1c | 2 1d | 2 1e | 2 1f + * 0x04 2 1c | 2 1d | 2 1e | 2 1f + * 0x05 | | 3 1c | 3 1d + * 0x06 2 1c | 2 1d | 2 1e | 2 1f + * 0x07 | | 6 1c | + * 0x11 2 1c | 2 1d | 2 1e | 2 1f + * 0x2a 2 | | 2 1e | 2 1f + * 0x34 6 1c | 6 1d | 4 1e | 4 1f + * 0x35 | | 3 1c | 3 1d + * 0x36 6 1c | 6 1d | 4 1e | 4 1f + * | | | + * Fman 2: | | | + * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 + * EMI1 | EMI1 | EMI1 | EMI1 + * Mux Phy | Mux Phy | Mux Phy | Mux Phy + * Value Addr | Value Addr | Value Addr | Value Addr + * 0x00 | | 6 1c | 6 1d + * 0x01 | | | + * 0x02 | | 6 1c | 6 1d + * 0x03 3 1c | 3 1d | 6 1c | 6 1d + * 0x04 3 1c | 3 1d | 6 1c | 6 1d + * 0x05 | | 6 1c | 6 1d + * 0x06 | | 6 1c | 6 1d + * 0x07 | | | + * 0x11 | | | + * 0x2a | | | + * 0x34 | | | + * 0x35 | | | + * 0x36 | | | + */ + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + unsigned int i, slot; + int lane; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ + setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); + + memset(mdio_mux, 0, sizeof(mdio_mux)); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* Register the three virtual MDIO front-ends */ + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_RGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM1_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM2_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, + "SUPER_HYDRA_FM1_TGEC_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, + "SUPER_HYDRA_FM2_TGEC_MDIO"); + + /* + * Program the DTSEC PHY addresses assuming that they are all SGMII. + * For any DTSEC that's RGMII, we'll override its PHY address later. + * We assume that DTSEC5 is only used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); + +#if (CONFIG_SYS_NUM_FMAN == 2) + fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); +#endif + + switch (srds_prtcl) { + case 0: + case 3: + case 4: + case 6: + case 0x11: + case 0x2a: + case 0x34: + case 0x36: + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + break; + case 1: + case 2: + case 5: + case 7: + case 0x35: + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + break; + default: + printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + switch (slot) { + case 1: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 3: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * FM1 DTSEC5 is routed via EC1 to the first on-board + * RGMII port. FM2 DTSEC5 is routed via EC2 to the + * second on-board RGMII port. The other DTSECs cannot + * be routed to RGMII. + */ + debug("FM1@DTSEC%u is RGMII at address %u\n", + idx + 1, 0); + fm_info_set_phy_address(i, 0); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); + mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; + super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + } + + fm_info_set_mdio(FM1_10GEC1, + miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + switch (slot) { + case 1: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 3: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * FM1 DTSEC5 is routed via EC1 to the first on-board + * RGMII port. FM2 DTSEC5 is routed via EC2 to the + * second on-board RGMII port. The other DTSECs cannot + * be routed to RGMII. + */ + debug("FM2@DTSEC%u is RGMII at address %u\n", + idx + 1, 1); + fm_info_set_phy_address(i, 1); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman2: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM2); + if (lane >= 0) { + debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); + mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; + super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + } + + fm_info_set_mdio(FM2_10GEC1, + miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); + +#endif + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c new file mode 100644 index 0000000..e65de36 --- /dev/null +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -0,0 +1,18 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {0, 0, NULL} +}; -- cgit v1.1 From 765ad3cf4d6f60f6104289d05bfa39d562c83859 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 26 Oct 2012 16:40:14 +0000 Subject: powerpc/corenet_ds: Update DDR timing for single-rank DIMMs Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed 800, 900, 1000, 1200, 1300MT/s. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- board/freescale/corenet_ds/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 4a53b8d..da284cd 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = { {2, 1250, 4, 6, 0xff, 2, 0}, {2, 1350, 5, 7, 0xff, 2, 0}, {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, {1, 1666, 4, 8, 0xff, 2, 0}, {} }; -- cgit v1.1