From 89c7784ed90ba50301eec521144f95111e472906 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 8 Feb 2008 13:15:55 -0600 Subject: 83xx: Add Vitesse VSC7385 firmware uploading Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by: Timur Tabi Signed-off-by: Kim Phillips --- board/freescale/mpc8313erdb/mpc8313erdb.c | 21 +++++++++++++++++++++ board/freescale/mpc8349itx/mpc8349itx.c | 15 ++++++++++++++- board/freescale/mpc837xerdb/mpc837xerdb.c | 27 ++++++++++++++++++++++----- 3 files changed, 57 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 42019fb..7cbdb7b 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -28,6 +28,7 @@ #endif #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -98,6 +99,26 @@ void pci_init_board(void) mpc83xx_pci_init(1, reg, warmboot); } +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 972361f..704f963 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -25,6 +25,7 @@ #include #include #include +#include #ifdef CONFIG_PCI #include #include @@ -177,7 +178,7 @@ int checkboard(void) */ int misc_init_f(void) { -#ifdef CONFIG_VSC7385 +#ifdef CONFIG_VSC7385_ENET volatile u32 *vsc7385_cpuctrl; /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -239,6 +240,8 @@ int misc_init_f(void) } /* + * Miscellaneous late-boot configurations + * * Make sure the EEPROM has the HRCW correctly programmed. * Make sure the RTC is correctly programmed. * @@ -250,6 +253,8 @@ int misc_init_f(void) * * This function makes sure that the I2C EEPROM is programmed * correctly. + * + * If a VSC7385 microcode image is present, then upload it. */ int misc_init_r(void) { @@ -375,6 +380,14 @@ int misc_init_r(void) i2c_set_bus_num(orig_bus); #endif +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + return rc; } diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index bed0fc3..a3b20b8 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -16,6 +16,8 @@ #include #include #include +#include + #if defined(CFG_DRAM_TEST) int @@ -56,11 +58,6 @@ testdram(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) void ddr_enable_ecc(unsigned int dram_size); #endif @@ -135,6 +132,26 @@ int checkboard(void) return 0; } +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) -- cgit v1.1