From 762e63754b6417126260dd22631d0e3bda12eb70 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Tue, 1 Nov 2011 00:00:39 +0100 Subject: Fix Stelian's email address Change my old email address which is no longer valid. Signed-off-by: Stelian Pop Signed-off-by: Anatolij Gustschin --- board/afeb9260/Makefile | 2 +- board/afeb9260/afeb9260.c | 2 +- board/atmel/at91sam9260ek/Makefile | 2 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 2 +- board/atmel/at91sam9260ek/led.c | 2 +- board/atmel/at91sam9261ek/Makefile | 2 +- board/atmel/at91sam9261ek/at91sam9261ek.c | 2 +- board/atmel/at91sam9261ek/led.c | 2 +- board/atmel/at91sam9263ek/Makefile | 2 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 2 +- board/atmel/at91sam9263ek/led.c | 2 +- board/atmel/at91sam9m10g45ek/Makefile | 2 +- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +- board/atmel/at91sam9m10g45ek/led.c | 2 +- board/atmel/at91sam9rlek/Makefile | 2 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 2 +- board/atmel/at91sam9rlek/led.c | 2 +- board/calao/sbc35_a9g20/Makefile | 2 +- board/calao/sbc35_a9g20/sbc35_a9g20.c | 2 +- board/calao/tny_a9260/Makefile | 2 +- board/calao/tny_a9260/tny_a9260.c | 2 +- board/emk/top9000/top9000.c | 2 +- board/esd/meesc/Makefile | 2 +- board/esd/meesc/meesc.c | 2 +- board/esd/otc570/Makefile | 2 +- board/esd/otc570/otc570.c | 2 +- board/eukrea/cpu9260/Makefile | 2 +- board/eukrea/cpu9260/cpu9260.c | 2 +- board/ronetix/pm9261/Makefile | 2 +- board/ronetix/pm9261/led.c | 2 +- board/ronetix/pm9261/pm9261.c | 2 +- board/ronetix/pm9263/Makefile | 2 +- board/ronetix/pm9263/led.c | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- board/ronetix/pm9g45/Makefile | 2 +- board/ronetix/pm9g45/pm9g45.c | 2 +- board/syteco/jadecpu/Makefile | 2 +- 37 files changed, 37 insertions(+), 37 deletions(-) (limited to 'board') diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile index 9134856..c56bcf8 100644 --- a/board/afeb9260/Makefile +++ b/board/afeb9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index f0e2e80..dda69e0 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * (C) Copyright 2008 Sergey Lapin * diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile index b9ecc88..66706eb 100644 --- a/board/atmel/at91sam9260ek/Makefile +++ b/board/atmel/at91sam9260ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index b3ed91d..2555672 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index daf81e8..9bdd385 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile index 080f289..f44dcdb 100644 --- a/board/atmel/at91sam9261ek/Makefile +++ b/board/atmel/at91sam9261ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index b6c7d9e..47ab839 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c index 0c2f522..7fa6136 100644 --- a/board/atmel/at91sam9261ek/led.c +++ b/board/atmel/at91sam9261ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index 8493043..af8726d 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 4d2937d..41ec752 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index c44455e..ce3cf09 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile index 6c37827..1915111 100644 --- a/board/atmel/at91sam9m10g45ek/Makefile +++ b/board/atmel/at91sam9m10g45ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 24a8606..5a04274 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index dadbd6a..0fd38f6 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile index 7de8897..36df7af 100644 --- a/board/atmel/at91sam9rlek/Makefile +++ b/board/atmel/at91sam9rlek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index e559084..ef0ddd7 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c index 987e8c0..4a1e8d7 100644 --- a/board/atmel/at91sam9rlek/led.c +++ b/board/atmel/at91sam9rlek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile index 7b7cc29..8a0618e 100644 --- a/board/calao/sbc35_a9g20/Makefile +++ b/board/calao/sbc35_a9g20/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index 5f448d9..4f5cff6 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Copyright (C) 2009 diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile index 1bf21e1..5a6c6b8 100644 --- a/board/calao/tny_a9260/Makefile +++ b/board/calao/tny_a9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index ab51a33..24de177 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * Copyright (C) 2009 diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c index 61dee62..6f5662a 100644 --- a/board/emk/top9000/top9000.c +++ b/board/emk/top9000/top9000.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2010 diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile index 74cfce9..2c95ced 100644 --- a/board/esd/meesc/Makefile +++ b/board/esd/meesc/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index ad43531..4882ffc 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * (C) Copyright 2009-2011 diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile index 1819292..3e94d19 100644 --- a/board/esd/otc570/Makefile +++ b/board/esd/otc570/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 15faa16..5dded41 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -4,7 +4,7 @@ * esd electronic system design gmbh * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile index 897fe3e..2ec6338 100644 --- a/board/eukrea/cpu9260/Makefile +++ b/board/eukrea/cpu9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop # Ilko Iliev # diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 402f19f..ecb0796 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile index 0abca0d..a288b28 100644 --- a/board/ronetix/pm9261/Makefile +++ b/board/ronetix/pm9261/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # Ilko Iliev # diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index f659870..1a2a81d 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index b26e33a..c6b582d 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile index 68baec7..db8de82 100644 --- a/board/ronetix/pm9263/Makefile +++ b/board/ronetix/pm9263/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # Ilko Iliev # diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index d6eb69f..e6883a3 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Ilko Iliev * diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 335efba..59cca87 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile index e586964..bebc5b4 100644 --- a/board/ronetix/pm9g45/Makefile +++ b/board/ronetix/pm9g45/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 961d193..d29d076 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -5,7 +5,7 @@ * Ronetix GmbH * * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile index c99252c..a2951a4 100644 --- a/board/syteco/jadecpu/Makefile +++ b/board/syteco/jadecpu/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop +# Stelian Pop # Lead Tech Design # # See file CREDITS for list of people who contributed to this -- cgit v1.1 From 641483af40915dabdfe7764bb22d7e5103cb636b Mon Sep 17 00:00:00 2001 From: Yan-Pai Chen Date: Mon, 7 Nov 2011 19:40:25 +0000 Subject: arm: a320evb: define mach-type in board config file MACH_TYPE_FARADAY was dropped from mach-types.h. Add it back to board config file. Signed-off-by: Yan-Pai Chen Acked-by: Igor Grinberg --- board/faraday/a320evb/a320evb.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index 2578be4..dfd186b 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_FARADAY; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; ftsmc020_init(); /* initialize Flash */ -- cgit v1.1 From ece91e30265764fe4edd61d8c1852d2248e566be Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sat, 19 Nov 2011 00:45:42 +0000 Subject: davinci_schmoogie: define CONFIG_MACH_TYPE for davinci_schmoogie board This patch fixes the build breakage for the davinci_schmoogie board. Signed-off-by: Christian Riesch Cc: Sergey Kubushyn Cc: Sandeep Paulraj --- board/davinci/schmoogie/schmoogie.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'board') diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 8b615a9..52d00e4 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; - /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; -- cgit v1.1 From f880fe57948907815cccbcbb6cb2f1984254da0d Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sat, 19 Nov 2011 00:45:43 +0000 Subject: davinci_sonata: define CONFIG_MACH_TYPE for davinci_sonata board This patch fixes the build breakage for the davinci_sonata board. Signed-off-by: Christian Riesch Cc: Sergey Kubushyn Cc: Sandeep Paulraj --- board/davinci/sonata/sonata.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'board') diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index c194290..55110fb 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -34,9 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SONATA; - /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; -- cgit v1.1 From e722d5d076539309e4dc6ff718a2d3ba0341a046 Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Sat, 19 Nov 2011 00:45:44 +0000 Subject: hawkboard: Replace HAWKBOARD_KICK{0, 1}_UNLOCK defines This patch replaces the HAWKBOARD_KICK{0,1}_UNLOCK defines by DV_SYSCFG_KICK{0,1}_UNLOCK. The kick register values are not hawkboard specific but may be used for all davinci boards. In commit f3c149d6c6e5ba8dd72baa86fe527837e4fb0e9a new defines for these values wer introduced. Signed-off-by: Christian Riesch Cc: Syed Mohammed Khasim Cc: Sughosh Ganu Cc: Sandeep Paulraj --- board/davinci/da8xxevm/hawkboard.c | 4 ++-- board/davinci/da8xxevm/hawkboard_nand_spl.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c index f34830e..9d4e238 100644 --- a/board/davinci/da8xxevm/hawkboard.c +++ b/board/davinci/da8xxevm/hawkboard.c @@ -47,8 +47,8 @@ int board_early_init_f(void) /* * Kick Registers need to be set to allow access to Pin Mux registers */ - writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); /* set cfgchip3 to select mii */ writel(readl(&davinci_syscfg_regs->cfgchip3) & diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index e5e65e5..32b17ce 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -99,8 +99,8 @@ void board_init_f(ulong bootflag) /* * Kick Registers need to be set to allow access to Pin Mux registers */ - writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & -- cgit v1.1 From 63a90bfb7e2794489acc708835958e1e4a6ea1d6 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:16 +0000 Subject: cosmetic: checkpatch cleanup of board/eNET/*.c Signed-off-by: Graeme Russ --- board/eNET/eNET.c | 8 ++++---- board/eNET/eNET_pci.c | 19 +++++++++---------- 2 files changed, 13 insertions(+), 14 deletions(-) (limited to 'board') diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index c4ed820..429fe1b 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -223,7 +223,7 @@ void setup_pcat_compatibility() * active low polarity on PIC interrupt pins, * active high polarity on all other irq pins */ - writew(0x0000,&sc520_mmcr->intpinpol); + writew(0x0000, &sc520_mmcr->intpinpol); /* * PIT 0 -> IRQ0 @@ -252,7 +252,7 @@ void setup_pcat_compatibility() void enet_timer_isr(void) { - static long enet_ticks = 0; + static long enet_ticks; enet_ticks++; @@ -281,9 +281,9 @@ void hw_watchdog_reset(void) void enet_toggle_run_led(void) { - unsigned char leds_state= inb(LED_LATCH_ADDRESS); + unsigned char leds_state = inb(LED_LATCH_ADDRESS); if (leds_state & LED_RUN_BITMASK) - outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); + outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS); else outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); } diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index 29d13d2..5af4ef7 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -38,7 +38,7 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) CONFIG_SYS_THIRD_PCI_IRQ, CONFIG_SYS_FORTH_PCI_IRQ }; - static int next_irq_index=0; + static int next_irq_index; uchar tmp_pin; int pin; @@ -47,9 +47,8 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) pin = tmp_pin; pin -= 1; /* PCI config space use 1-based numbering */ - if (pin == -1) { + if (pin == -1) return; /* device use no irq */ - } /* map device number + pin to a pin on the sc520 */ switch (PCI_DEV(dev)) { @@ -69,19 +68,19 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) if (sc520_pci_ints[pin] == -1) { /* re-route one interrupt for us */ - if (next_irq_index > 3) { + if (next_irq_index > 3) return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) return; - } + next_irq_index++; } - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + if (-1 != sc520_pci_ints[pin]) + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, sc520_pci_ints[pin]); - } + printf("fixup_irq: device %d pin %c irq %d\n", PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); } -- cgit v1.1 From 311b1a2b38b5317fdff76a5dad9d16fee3f52c79 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Tue, 8 Nov 2011 02:33:18 +0000 Subject: sc520: Create arch asm-offsets Signed-off-by: Graeme Russ --- board/eNET/eNET_start16.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 4241f6e..5e3f44c 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -30,6 +30,7 @@ #include "config.h" #include "hardware.h" #include +#include .text .section .start16, "ax" @@ -46,12 +47,12 @@ board_init16: movw %ax, %ds /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ - movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi + movl $GENERATED_SC520_PAR14, %edi movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax movl %eax, (%di) /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ - movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi + movl $GENERATED_SC520_PAR15, %edi movl $CONFIG_SYS_SC520_LLIO_PAR, %eax movl %eax, (%di) -- cgit v1.1 From ae6b03fefc1a8b27d834ef12e0a586f4237fdb1f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Tue, 22 Nov 2011 16:51:13 +0800 Subject: powerpc/p3060qds: Add board related support for P3060QDS platform The P3060QDS is a Freescale reference board for the six-core P3060 SOC. P3060QDS Board Overview: Memory subsystem: - 2G Bytes unbuffered DDR3 SDRAM SO-DIMM(64bit bus) - 128M Bytes NOR flash single-chip memory - 16M Bytes SPI flash - 8K Bytes AT24C64 I2C EEPROM for RCW Ethernet: - Eight Ethernet controllers (4x1G + 4x1G/2.5G) - Three VSC8641 PHYs on board (2xRGMII + 1xMII) - Suport multiple Vitesse VSC8234 SGMII Cards in Slot1/2/3 PCIe: Two PCI Express 2.0 controllers/ports USB: Two USB2.0, USB1(TYPE-A) and USB2(TYPE-AB) on board I2C: Four I2C controllers UART: Supports two dUARTs up to 115200 bps for console RapidIO: Two RapidIO, sRIO1 and sRIO2 Signed-off-by: Shengzhou Liu Signed-off-by: York Sun Signed-off-by: Kumar Gala --- board/freescale/common/Makefile | 3 + board/freescale/common/ics307_clk.c | 21 +- board/freescale/common/qixis.c | 151 ++++++++++ board/freescale/common/qixis.h | 101 +++++++ board/freescale/p3060qds/Makefile | 54 ++++ board/freescale/p3060qds/ddr.c | 248 +++++++++++++++ board/freescale/p3060qds/eth.c | 482 ++++++++++++++++++++++++++++++ board/freescale/p3060qds/fixed_ddr.c | 214 +++++++++++++ board/freescale/p3060qds/p3060qds.c | 341 +++++++++++++++++++++ board/freescale/p3060qds/p3060qds.h | 30 ++ board/freescale/p3060qds/p3060qds_qixis.h | 74 +++++ 11 files changed, 1711 insertions(+), 8 deletions(-) create mode 100644 board/freescale/common/qixis.c create mode 100644 board/freescale/common/qixis.h create mode 100644 board/freescale/p3060qds/Makefile create mode 100644 board/freescale/p3060qds/ddr.c create mode 100644 board/freescale/p3060qds/eth.c create mode 100644 board/freescale/p3060qds/fixed_ddr.c create mode 100644 board/freescale/p3060qds/p3060qds.c create mode 100644 board/freescale/p3060qds/p3060qds.h create mode 100644 board/freescale/p3060qds/p3060qds_qixis.h (limited to 'board') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 353d3c6..9077aaf 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_FSL_VIA) += cds_via.o COBJS-$(CONFIG_FMAN_ENET) += fman.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +COBJS-$(CONFIG_FSL_QIXIS) += qixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o @@ -50,12 +51,14 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o +COBJS-$(CONFIG_P3060QDS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 6acbc36..95a3cd7 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,10 +25,15 @@ #include "ics307_clk.h" -#ifdef CONFIG_FSL_NGPIXIS +#if defined(CONFIG_FSL_NGPIXIS) #include "ngpixis.h" +#define fpga_reg pixis +#elif defined(CONFIG_FSL_QIXIS) +#include "qixis.h" +#define fpga_reg ((struct qixis *)QIXIS_BASE) #else #include "pixis.h" +#define fpga_reg pixis #endif /* define for SYS CLK or CLK1Frequency */ @@ -143,15 +148,15 @@ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) unsigned long get_board_sys_clk(void) { return ics307_clk_freq( - in_8(&pixis->sclk[0]), - in_8(&pixis->sclk[1]), - in_8(&pixis->sclk[2])); + in_8(&fpga_reg->sclk[0]), + in_8(&fpga_reg->sclk[1]), + in_8(&fpga_reg->sclk[2])); } unsigned long get_board_ddr_clk(void) { return ics307_clk_freq( - in_8(&pixis->dclk[0]), - in_8(&pixis->dclk[1]), - in_8(&pixis->dclk[2])); + in_8(&fpga_reg->dclk[0]), + in_8(&fpga_reg->dclk[1]), + in_8(&fpga_reg->dclk[2])); } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c new file mode 100644 index 0000000..6cd7e51 --- /dev/null +++ b/board/freescale/common/qixis.c @@ -0,0 +1,151 @@ +/* + * Copyright 2011 Freescale Semiconductor + * Author: Shengzhou Liu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the QIXIS of some Freescale reference boards. + * + */ + +#include +#include +#include +#include "qixis.h" + +u8 qixis_read(unsigned int reg) +{ + void *p = (void *)QIXIS_BASE; + + return in_8(p + reg); +} + +void qixis_write(unsigned int reg, u8 value) +{ + void *p = (void *)QIXIS_BASE; + + out_8(p + reg, value); +} + +void qixis_reset(void) +{ + QIXIS_WRITE(rst_ctl, 0x83); +} + +void qixis_bank_reset(void) +{ + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +} + +/* Set the boot bank to the power-on default bank0 */ +void clear_altbank(void) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[0]); + reg = reg & ~QIXIS_LBMAP_MASK; + QIXIS_WRITE(brdcfg[0], reg); +} + +/* Set the boot bank to the alternate bank */ +void set_altbank(void) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK; + QIXIS_WRITE(brdcfg[0], reg); +} + +#ifdef DEBUG +static void qixis_dump_regs(void) +{ + int i; + + printf("id = %02x\n", QIXIS_READ(id)); + printf("arch = %02x\n", QIXIS_READ(arch)); + printf("scver = %02x\n", QIXIS_READ(scver)); + printf("model = %02x\n", QIXIS_READ(model)); + printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); + printf("aux = %02x\n", QIXIS_READ(aux)); + for (i = 0; i < 16; i++) + printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); + for (i = 0; i < 16; i++) + printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); + printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), + QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); + printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), + QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); + printf("aux = %02x\n", QIXIS_READ(aux)); + printf("watch = %02x\n", QIXIS_READ(watch)); + printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); + printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); + printf("present = %02x\n", QIXIS_READ(present)); + printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); + printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); + printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); + printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); + printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2)); +} +#endif + +int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + + if (argc <= 1) { + clear_altbank(); + qixis_reset(); + } else if (strcmp(argv[1], "altbank") == 0) { + set_altbank(); + qixis_bank_reset(); + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[9] = {"2s", "4s", "8s", "16s", "32s", + "1min", "2min", "4min", "8min"}; + u8 rcfg = QIXIS_READ(rcfg_ctl); + + if (argv[2] == NULL) { + printf("qixis watchdog \n"); + return 0; + } + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) { + /* disable watchdog */ + QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08); + QIXIS_WRITE(watch, ((i<<2) - 1)); + QIXIS_WRITE(rcfg_ctl, rcfg); + return 0; + } + } + } + +#ifdef DEBUG + else if (strcmp(argv[1], "dump") == 0) { + qixis_dump_regs(); + return 0; + } +#endif + + else { + printf("Invalid option: %s\n", argv[1]); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, + "Reset the board using the FPGA sequencer", + "- hard reset to default bank\n" + "qixis_reset altbank - reset to alternate bank\n" + "qixis watchdog - set the watchdog period\n" + " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" +#ifdef DEBUG + "qixis_reset dump - display the QIXIS registers\n" +#endif + ); diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h new file mode 100644 index 0000000..7a0268a --- /dev/null +++ b/board/freescale/common/qixis.h @@ -0,0 +1,101 @@ +/* + * Copyright 2011 Freescale Semiconductor + * Author: Shengzhou Liu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the QIXIS of some Freescale reference boards. + */ + +#ifndef __QIXIS_H_ +#define __QIXIS_H_ + +struct qixis { + u8 id; /* ID value uniquely identifying each QDS board type */ + u8 arch; /* Board version information */ + u8 scver; /* QIXIS Version Register */ + u8 model; /* Information of software programming model version */ + u8 tagdata; + u8 ctl_sys; + u8 aux; /* Auxiliary Register,0x06 */ + u8 clk_spd; + u8 stat_dut; + u8 stat_sys; + u8 stat_alrm; + u8 present; + u8 ctl_sys2; + u8 rcw_ctl; + u8 ctl_led; + u8 i2cblk; + u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ + u8 rcfg_st; + u8 dcm_ad; + u8 dcm_da; + u8 dcmd; + u8 dmsg; + u8 gdc; + u8 gdd; /* DCM Debug Data Register,0x17 */ + u8 dmack; + u8 res1[6]; + u8 watch; /* Watchdog Register,0x1F */ + u8 pwr_ctl[2]; /* Power Control Register,0x20 */ + u8 res2[2]; + u8 pwr_stat[4]; /* Power Status Register,0x24 */ + u8 res3[8]; + u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ + u8 res4[2]; + u8 sclk[3]; /* Clock Configuration Registers,0x34 */ + u8 res5; + u8 dclk[3]; + u8 res6; + u8 clk_dspd[3]; + u8 res7; + u8 rst_ctl; /* Reset Control Register,0x40 */ + u8 rst_stat; /* Reset Status Register */ + u8 rst_rsn; /* Reset Reason Register */ + u8 rst_frc[2]; /* Reset Force Registers,0x43 */ + u8 res8[11]; + u8 brdcfg[16]; /* Board Configuration Register,0x50 */ + u8 dutcfg[16]; + u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ + u8 rcw_data; + u8 res9[5]; + u8 post_ctl; + u8 post_stat; + u8 post_dat[2]; + u8 pi_d[4]; + u8 gpio_io[4]; + u8 gpio_dir[4]; + u8 res10[20]; + u8 rjtag_ctl; + u8 rjtag_dat; + u8 res11[2]; + u8 trig_src[4]; + u8 trig_dst[4]; + u8 trig_stat; + u8 res12[3]; + u8 trig_ctr[4]; + u8 res13[48]; + u8 aux2[4]; /* Auxiliary Registers,0xE0 */ + u8 res14[10]; + u8 aux_ad; + u8 aux_da; + u8 res15[16]; +}; + +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 7 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_ALTBANK 0x04 + +u8 qixis_read(unsigned int reg); +void qixis_write(unsigned int reg, u8 value); + +#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) + +#endif diff --git a/board/freescale/p3060qds/Makefile b/board/freescale/p3060qds/Makefile new file mode 100644 index 0000000..ae136f4 --- /dev/null +++ b/board/freescale/p3060qds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += eth.o +COBJS-y += fixed_ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p3060qds/ddr.c b/board/freescale/p3060qds/ddr.c new file mode 100644 index 0000000..9affbf0 --- /dev/null +++ b/board/freescale/p3060qds/ddr.c @@ -0,0 +1,248 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "p3060qds.h" + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } + return ddr_size; +} + +struct board_specific_params { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_params udimm[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 950, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_params rdimm[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_params *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimm; + else + pbsp = udimm; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } + + +found: + + /* + * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered. + * However SPD still claims CL=7 is supported. Extensive tests + * confirmed this board cannot work stably with CL=7 with this + * particular DIMM. + */ + if (ddr_freq >= 800 && ddr_freq < 1066 && \ + !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) { + popts->cas_latency_override = 1; + popts->cas_latency_override_value = 8; + debug("Override CL to 8\n"); + } + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/freescale/p3060qds/eth.c b/board/freescale/p3060qds/eth.c new file mode 100644 index 0000000..3f812db --- /dev/null +++ b/board/freescale/p3060qds/eth.c @@ -0,0 +1,482 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/fman.h" + +#include "p3060qds_qixis.h" + +#define EMI_NONE 0xffffffff +#define EMI1_RGMII1 0 +#define EMI1_SLOT1 1 +#define EMI1_SLOT2 2 +#define EMI1_SLOT3 3 +#define EMI1_RGMII2 4 + +static int mdio_mux[NUM_FM_PORTS]; + +static char *mdio_names[5] = { + "P3060QDS_MDIO0", + "P3060QDS_MDIO1", + "P3060QDS_MDIO2", + "P3060QDS_MDIO3", + "P3060QDS_MDIO4", +}; + +/* + * Mapping of all 18 SERDES lanes to board slots. + * A value of '0' here means that the mapping must be determined + * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug + */ +static u8 lane_to_slot[] = { + 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 +}; + +static char *p3060qds_mdio_name_for_muxval(u32 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u32 muxval) +{ + struct mii_dev *bus; + char *name = p3060qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct p3060qds_mdio { + u32 muxval; + struct mii_dev *realbus; +}; + +static void p3060qds_mux_mdio(u32 muxval) +{ + u8 brdcfg4; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << 4); + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct p3060qds_mdio *priv = bus->priv; + + p3060qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct p3060qds_mdio *priv = bus->priv; + + p3060qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int p3060qds_mdio_reset(struct mii_dev *bus) +{ + struct p3060qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int p3060qds_mdio_init(char *realbusname, u32 muxval) +{ + struct p3060qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate P3060QDS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate P3060QDS private data\n"); + free(bus); + return -1; + } + + bus->read = p3060qds_mdio_read; + bus->write = p3060qds_mdio_write; + bus->reset = p3060qds_mdio_reset; + sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + if (mdio_mux[port] == EMI1_RGMII1) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1"); + + if (mdio_mux[port] == EMI1_RGMII2) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2"); + + if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3) + || (srds_prtcl == 0x6))) { + switch (port) { + case FM2_DTSEC4: + fdt_set_phy_handle(blob, prop, pa, "phy2_slot1"); + break; + case FM1_DTSEC4: + fdt_set_phy_handle(blob, prop, pa, "phy3_slot1"); + break; + default: + break; + } + } + + if (mdio_mux[port] == EMI1_SLOT3) { + switch (port) { + case FM2_DTSEC3: + fdt_set_phy_handle(blob, prop, pa, "phy0_slot3"); + break; + case FM1_DTSEC3: + fdt_set_phy_handle(blob, prop, pa, "phy1_slot3"); + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT1: + if (lane >= 14) { + fdt_status_okay_by_alias(fdt, + "emi1_slot1"); + fdt_status_disabled_by_alias(fdt, + "emi1_slot1_bk1"); + } else { + fdt_status_disabled_by_alias(fdt, + "emi1_slot1"); + fdt_status_okay_by_alias(fdt, + "emi1_slot1_bk1"); + } + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC1) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + + if (i == FM1_DTSEC2) + fdt_status_okay_by_alias(fdt, "emi1_rgmii2"); + break; + default: + break; + } + } +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + idx = i - FM2_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane >= 0) { + switch (mdio_mux[i]) { + case EMI1_SLOT1: + if (lane >= 14) + fdt_status_okay_by_alias(fdt, + "emi1_slot1"); + else + fdt_status_okay_by_alias(fdt, + "emi1_slot1_bk1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, + "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, + "emi1_slot3"); + break; + } + } + break; + default: + break; + } + } +#endif +} + +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int sdprtl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + switch (sdprtl) { + case 0x03: + case 0x06: + lane_to_slot[8] = 1; + lane_to_slot[9] = lane_to_slot[8]; + lane_to_slot[16] = 5; + lane_to_slot[17] = lane_to_slot[16]; + break; + case 0x16: + case 0x19: + case 0x1C: + lane_to_slot[8] = 5; + lane_to_slot[9] = lane_to_slot[8]; + lane_to_slot[16] = 1; + lane_to_slot[17] = lane_to_slot[16]; + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + int i; + struct fsl_pq_mdio_info dtsec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_cfg = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + initialize_lane_to_slot(); + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + /* Register the 5 muxing front-ends to the MDIO buses */ + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + + if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) + fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */ + else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR); + + if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) + fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */ + else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII) + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR); + + switch (srds_cfg) { + case 0x03: + case 0x06: + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x16: + case 0x19: + case 0x1C: + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (QIXIS_READ(present) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC1) { + mdio_mux[i] = EMI1_RGMII1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + } else if (i == FM1_DTSEC2) { + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + } + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (QIXIS_READ(present) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/p3060qds/fixed_ddr.c b/board/freescale/p3060qds/fixed_ddr.c new file mode 100644 index 0000000..125988d --- /dev/null +++ b/board/freescale/p3060qds/fixed_ddr.c @@ -0,0 +1,214 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {850, 950, &ddr_cfg_regs_900}, + {950, 1050, &ddr_cfg_regs_1000}, + {1050, 1250, &ddr_cfg_regs_1200}, + {0, 0, NULL} +}; diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c new file mode 100644 index 0000000..c6c74f2 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds.c @@ -0,0 +1,341 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "p3060qds.h" +#include "p3060qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %s", cpu->name); + puts("QDS, "); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < 3; i++) { + static const char * const freq[] = {"100", "125", "Reserved", + "156.25"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */ + setbits_be32(&gur->ddrclkdr, 0x00030000); + + return 0; +} + +void board_config_serdes_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int cfg = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + switch (cfg) { + case 0x03: + case 0x06: + /* set Lane I,J as SGMII */ + QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A | + BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A); + break; + case 0x16: + case 0x19: + case 0x1c: + /* set Lane I,J as Aurora Debug */ + QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B | + BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B); + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } +} + +void board_config_usb_mux(void) +{ + u8 brdcfg4, brdcfg5, brdcfg7; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1; + u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EC_MODE_MASK; + if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && + (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { + brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && + ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || + (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { + brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && + (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { + brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && + ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || + (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { + brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII; + } else { + brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII; + } + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK); + brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL); + QIXIS_WRITE(brdcfg[5], brdcfg5); + + brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT | + BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1; + QIXIS_WRITE(brdcfg[7], brdcfg7); +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + board_config_serdes_mux(); + board_config_usb_mux(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "150"; + } +} + +#define NUM_SRDS_BANKS 3 + +int misc_init_r(void) +{ + serdes_corenet_t *srds_regs; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 3: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '10' is " + "unsupported\n", i + 1); + break; + } + } + + srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0); + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +/* + * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v, + * 18 means CVDD is 1.8v. + */ +static u8 IO_VSEL[] = { + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 33, 33 +}; + +#define IO_VSEL_MASK 0x1f + +/* + * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD, + * then set status of spi flash nodes to 'disabled' according to CVDD. + * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi + * flash2, CVDD '18' will select spi flash3. + */ +void fdt_fixup_board_spi(void *blob) +{ + u8 sw5 = QIXIS_READ(dutcfg[3]); + + switch (IO_VSEL[sw5 & IO_VSEL_MASK]) { + /* 3.3v */ + case 33: + do_fixup_by_compat(blob, "atmel,at45db081d", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,sst25wf040", "status", + "disabled", strlen("disabled") + 1, 1); + break; + /* 2.5v */ + case 25: + do_fixup_by_compat(blob, "spansion,s25sl12801", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,en25q32", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,sst25wf040", "status", + "disabled", strlen("disabled") + 1, 1); + break; + /* 1.8v */ + case 18: + do_fixup_by_compat(blob, "spansion,s25sl12801", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,en25q32", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "atmel,at45db081d", "status", + "disabled", strlen("disabled") + 1, 1); + break; + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_board_spi(blob); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/p3060qds/p3060qds.h b/board/freescale/p3060qds/p3060qds.h new file mode 100644 index 0000000..3da6815 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds.h @@ -0,0 +1,30 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3060QDS_H__ +#define __P3060QDS_H__ + +#include +#include + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); +extern fixed_ddr_parm_t fixed_ddr_parm_0[]; + +#endif diff --git a/board/freescale/p3060qds/p3060qds_qixis.h b/board/freescale/p3060qds/p3060qds_qixis.h new file mode 100644 index 0000000..4d5d6a2 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds_qixis.h @@ -0,0 +1,74 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3060QDS_QIXIS_H__ +#define __P3060QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for P3060QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EC_MODE_MASK 0x0F +#define BRDCFG4_EC2_MII_EC1_MII 0x00 +#define BRDCFG4_EC2_MII_EC1_USB 0x03 +#define BRDCFG4_EC2_USB_EC1_MII 0x0C +#define BRDCFG4_EC2_USB_EC1_USB 0x0F +#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E +#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B +#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A +#define BRDCFG4_EMISEL_MASK 0xF0 + +#define BRDCFG5_ECLKS_MASK 0x80 +#define BRDCFG5_USB1ID_MASK 0x40 +#define BRDCFG5_USB2ID_MASK 0x20 +#define BRDCFG5_GC2MX_MASK 0x0C +#define BRDCFG5_T15MX_MASK 0x03 +#define BRDCFG5_ECLKS_IEEE1588_CM 0x80 +#define BRDCFG5_USB1ID_CTRL 0x40 +#define BRDCFG5_USB2ID_CTRL 0x20 + +#define BRDCFG6_SD1MX_A 0x01 +#define BRDCFG6_SD1MX_B 0x00 +#define BRDCFG6_SD2MX_A 0x02 +#define BRDCFG6_SD2MX_B 0x00 +#define BRDCFG6_SD3MX_A 0x04 +#define BRDCFG6_SD3MX_B 0x00 +#define BRDCFG6_SD4MX_A 0x08 +#define BRDCFG6_SD4MX_B 0x00 + +#define BRDCFG7_JTAGMX_MASK 0xC0 +#define BRDCFG7_IQ1MX_MASK 0x20 +#define BRDCFG7_G1MX_MASK 0x10 +#define BRDCFG7_D1MX_MASK 0x0C +#define BRDCFG7_I3MX_MASK 0x03 +#define BRDCFG7_JTAGMX_AURORA 0x00 +#define BRDCFG7_JTAGMX_FPGA 0x80 +#define BRDCFG7_JTAGMX_COP_JTAG 0xC0 +#define BRDCFG7_IQ1MX_IRQ_EVT 0x00 +#define BRDCFG7_IQ1MX_USB2 0x20 +#define BRDCFG7_G1MX_USB1 0x00 +#define BRDCFG7_G1MX_TSEC3 0x10 +#define BRDCFG7_D1MX_DMA 0x00 +#define BRDCFG7_D1MX_TSEC3USB 0x04 +#define BRDCFG7_D1MX_HDLC2 0x08 +#define BRDCFG7_I3MX_UART2_I2C34 0x00 +#define BRDCFG7_I3MX_GPIO_EVT 0x01 +#define BRDCFG7_I3MX_USB1 0x02 +#define BRDCFG7_I3MX_TSEC3 0x03 + +#endif -- cgit v1.1 From 9839709ea3df89f6021034508f48b97cab33ebb8 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Wed, 23 Nov 2011 08:25:58 -0800 Subject: mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder Signed-off-by: Kumar Gala --- board/freescale/p2020come/Makefile | 46 ++++++ board/freescale/p2020come/ddr.c | 45 ++++++ board/freescale/p2020come/law.c | 39 +++++ board/freescale/p2020come/p2020come.c | 287 ++++++++++++++++++++++++++++++++++ board/freescale/p2020come/tlb.c | 99 ++++++++++++ 5 files changed, 516 insertions(+) create mode 100644 board/freescale/p2020come/Makefile create mode 100644 board/freescale/p2020come/ddr.c create mode 100644 board/freescale/p2020come/law.c create mode 100644 board/freescale/p2020come/p2020come.c create mode 100644 board/freescale/p2020come/tlb.c (limited to 'board') diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile new file mode 100644 index 0000000..ba87904 --- /dev/null +++ b/board/freescale/p2020come/Makefile @@ -0,0 +1,46 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c new file mode 100644 index 0000000..85f84c6 --- /dev/null +++ b/board/freescale/p2020come/ddr.c @@ -0,0 +1,45 @@ +/* + * Copyright 2009, 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + + if (!pdimm->n_ranks) + return; + + /* + * Set DDR_SDRAM_CLK_CNTL = 0x02800000 + * + * Clock is launched 5/8 applied cycle after address/command + */ + popts->clk_adjust = 5; +} diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c new file mode 100644 index 0000000..20ba36f --- /dev/null +++ b/board/freescale/p2020come/law.c @@ -0,0 +1,39 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Create a dummy LAW entry for the DDR SDRAM which will be replaced when + * the DDR SPD setup code runs. + * + * This table would be empty, except that it is used before the BSS section is + * initialized, and therefore must have at least one entry to push it into + * the DATA section. + */ +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c new file mode 100644 index 0000000..8cf7bee --- /dev/null +++ b/board/freescale/p2020come/p2020come.c @@ -0,0 +1,287 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_PCI) +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void ft_pci_board_setup(void *blob) +{ + FT_FSL_PCI_SETUP; +} +#endif + +#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \ + SGMII_PHY_RST_SET | PCIE_RST_SET | \ + RGMII_PHY_RST_SET) + +#define SYSCLK_MASK 0x00200000 +#define BOARDREV_MASK 0x10100000 +#define BOARDREV_B 0x10100000 +#define BOARDREV_C 0x00100000 +#define BOARDREV_D 0x00000000 + +#define SYSCLK_66 66666666 +#define SYSCLK_50 50000000 +#define SYSCLK_100 100000000 + +unsigned long get_board_sys_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + switch (ddr_ratio) { + case 0x0C: + return SYSCLK_66; + case 0x0A: + case 0x08: + return SYSCLK_100; + default: + puts("ERROR: unknown DDR ratio\n"); + return SYSCLK_100; + } +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + switch (ddr_ratio) { + case 0x0C: + case 0x0A: + return SYSCLK_66; + case 0x08: + return SYSCLK_100; + default: + puts("ERROR: unknown DDR ratio\n"); + return SYSCLK_100; + } +} + +#ifdef CONFIG_MMC +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); + + /* All the device are enable except for SRIO12 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); + return 0; +} +#endif + +#define GPIO_DIR 0x0f3a0000 +#define GPIO_ODR 0x00000000 +#define GPIO_DAT 0x001a0000 + +int checkboard(void) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00); + + /* + * GPIO + * 0 - 3: CarryBoard Input; + * 4 - 7: CarryBoard Output; + * 8 : Mux as SDHC_CD (card detection) + * 9 : Mux as SDHC_WP + * 10 : Clear Watchdog timer + * 11 : LED Input + * 12 : Output to 1 + * 13 : Open Drain + * 14 : LED Output + * 15 : Switch Input + * + * Set GPIOs 11, 12, 14 to 1. + */ + out_be32(&pgpio->gpodr, GPIO_ODR); + mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT); + + puts("Board: Freescale COM Express P2020\n"); + return 0; +} + +#define M41ST85W_I2C_BUS 1 +#define M41ST85W_I2C_ADDR 0x68 +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args) + +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name) +{ + u8 data; + + if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { + M41ST85W_ERROR("unable to read %s bit\n", name); + return; + } + + if (data & mask) { + data &= ~mask; + if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { + M41ST85W_ERROR("unable to clear %s bit\n", name); + return; + } + } +} + +#define M41ST85W_REG_SEC2 0x01 +#define M41ST85W_REG_SEC2_ST 0x80 + +#define M41ST85W_REG_ALHOUR 0x0c +#define M41ST85W_REG_ALHOUR_HT 0x40 + +/* + * The P2020COME board has a STMicro M41ST85W RTC/watchdog + * at i2c bus 1 address 0x68. + */ +static void start_rtc(void) +{ + unsigned int bus = i2c_get_bus_num(); + + if (i2c_set_bus_num(M41ST85W_I2C_BUS)) { + M41ST85W_ERROR("unable to set i2c bus\n"); + goto out; + } + + /* ensure ST (stop) and HT (halt update) bits are cleared */ + m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST"); + m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT"); + +out: + /* reset the i2c bus */ + i2c_set_bus_num(bus); +} + +int board_early_init_r(void) +{ + start_rtc(); + return 0; +} + +#define M41ST85W_REG_WATCHDOG 0x09 +#define M41ST85W_REG_WATCHDOG_WDS 0x80 +#define M41ST85W_REG_WATCHDOG_BMB0 0x04 + +void board_reset(void) +{ + u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0; + + /* set the hardware watchdog timeout to 1/16 second, then hang */ + i2c_set_bus_num(M41ST85W_I2C_BUS); + i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1); + + while (1) + /* hang */; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode."); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + ft_pci_board_setup(blob); +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c new file mode 100644 index 0000000..d787ac3 --- /dev/null +++ b/board/freescale/p2020come/tlb.c @@ -0,0 +1,99 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_PCI) + /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * *I*G* - PCI I/O + * + * PCI3 => 0xFFC10000 + * PCI2 => 0xFFC2,0000 + * PCI1 => 0xFFC3,0000 + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +#endif /* #if defined(CONFIG_PCI) */ + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit v1.1 From 2fe6b7f70f423b66e23ad6fb0848b71252b2b2cd Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 13 Oct 2011 15:12:22 +0200 Subject: ppc4xx: use CONFIG_PCI_BOOTDELAY instead of private implementation This patch switches PMC440 board code to the CONFIG_PCI_BOOTDELAY option instead of using a private implemention. This relies on Anatolji's patch that moves the pcidelay handling behind pci_target_init. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/pmc440/pmc440.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'board') diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 5236f44..0d56064 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -617,21 +617,6 @@ void pci_master_init(struct pci_controller *hose) static void wait_for_pci_ready(void) { - int i; - char *s = getenv("pcidelay"); - /* - * We have our own handling of the pcidelay variable. - * Using CONFIG_PCI_BOOTDELAY enables pausing for host - * and adapter devices. For adapter devices we do not - * want this. - */ - if (s) { - int ms = simple_strtoul(s, NULL, 10); - printf("PCI: Waiting for %d ms\n", ms); - for (i=0; i Date: Thu, 13 Oct 2011 15:12:23 +0200 Subject: ppc4xx: remove invalid access to PCI_BRDGOPT2 register This patch removes an invalid call to pci_write_config_dword to PCI_BRDGOPT2 register. This function must not be used from pci_target_init and is also at the wrong place. The correct call is done later in pci_target_init via pci_hose_write_config_dword. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/pmc440/pmc440.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'board') diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 0d56064..3713e37 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -574,8 +574,6 @@ void pci_target_init(struct pci_controller *hose) /* No error reporting */ pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - if (!is_monarch()) { /* Program the board's subsystem id/classcode */ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, -- cgit v1.1 From a6569c63b368efeff262e11586319b8c8515ca00 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Thu, 24 Nov 2011 16:36:06 +0100 Subject: ppc4xx: fix PMC440 painit command This patch fixes the PMC440 BSP command painit. The implementation was broken since the step to the new environment handling. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/pmc440/cmd_pmc440.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 0202876..f1ffb7b 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -342,7 +342,8 @@ U_BOOT_CMD( #if defined(CONFIG_PRAM) #include -extern env_t *env_ptr; +#include +#include int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -351,6 +352,10 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) u32 param; ulong *lptr; + env_t *envp; + char *res; + int len; + v = getenv("pram"); if (v) pram = simple_strtoul(v, NULL, 10); @@ -384,7 +389,15 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* env is first (4k aligned) */ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + envp = (env_t *)nextbase; + res = (char *)envp->data; + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + envp->crc = crc32(0, envp->data, ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ *(--lptr) = base - nextbase; /* offset | type=0 */ -- cgit v1.1 From 255ef4d9091fe896ff152629a8cb290ee92c9fde Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Thu, 20 Oct 2011 11:12:55 +0200 Subject: ppc4xx: Add Io64 board support Board support for the Guntermann & Drunck Io64. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- board/gdsys/405ex/405ex.c | 250 ++++++++++++++++++++++++++ board/gdsys/405ex/405ex.h | 10 ++ board/gdsys/405ex/Makefile | 53 ++++++ board/gdsys/405ex/chip_config.c | 96 ++++++++++ board/gdsys/405ex/io64.c | 384 ++++++++++++++++++++++++++++++++++++++++ board/gdsys/common/Makefile | 1 + board/gdsys/common/miiphybb.c | 58 +++++- 7 files changed, 844 insertions(+), 8 deletions(-) create mode 100644 board/gdsys/405ex/405ex.c create mode 100644 board/gdsys/405ex/405ex.h create mode 100644 board/gdsys/405ex/Makefile create mode 100644 board/gdsys/405ex/chip_config.c create mode 100644 board/gdsys/405ex/io64.c (limited to 'board') diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c new file mode 100644 index 0000000..0d25214 --- /dev/null +++ b/board/gdsys/405ex/405ex.c @@ -0,0 +1,250 @@ +#include +#include +#include +#include +#include + +#include + +#include "405ex.h" + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +DECLARE_GLOBAL_DATA_PTR; + +int get_fpga_state(unsigned dev) +{ + return gd->fpga_state[dev]; +} + +void print_fpga_state(unsigned dev) +{ + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); +} + +int board_early_init_f(void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* + * Configure PFC (Pin Function Control) registers + */ + val = SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; + + /* + * reset FPGA + */ + gd405ex_init(); + + gd405ex_set_fpga_reset(1); + + gd405ex_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!gd405ex_get_fpga_done(k)) { + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + gd405ex_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI + u16 *reflection_target = &fpga->reflection_low; +#else + u16 *reflection_target = &fpga->reflection_high; +#endif + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + out_le16(&fpga->reflection_low, + REFLECTION_TESTPATTERN); + + if (in_le16(reflection_target) == + REFLECTION_TESTPATTERN_INV) + break; + + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h new file mode 100644 index 0000000..b15623f --- /dev/null +++ b/board/gdsys/405ex/405ex.h @@ -0,0 +1,10 @@ +#ifndef __405EX_H_ +#define __405EX_H_ + +/* functions to be provided by board implementation */ +void gd405ex_init(void); +void gd405ex_set_fpga_reset(unsigned state); +void gd405ex_setup_hw(void); +int gd405ex_get_fpga_done(unsigned fpga); + +#endif /* __405EX_H_ */ diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile new file mode 100644 index 0000000..4549705 --- /dev/null +++ b/board/gdsys/405ex/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-$(CONFIG_IO64) += io64.o + +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o + +COBJS := $(BOARD).o $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c new file mode 100644 index 0000000..12cb3bf --- /dev/null +++ b/board/gdsys/405ex/chip_config.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + +/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ + +struct ppc4xx_config ppc4xx_config_val[] = { + { + "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66", + { + 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, +}; + +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c new file mode 100644 index 0000000..a997571 --- /dev/null +++ b/board/gdsys/405ex/io64.c @@ -0,0 +1,384 @@ +/* + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on kilauea.c + * by Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "405ex.h" +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define PHYREG_CONTROL 0 +#define PHYREG_PAGE_ADDRESS 22 +#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 +#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 +#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17 +#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21 + +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) +#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) + +enum { + UNITTYPE_CCD_SWITCH = 1, +}; + +enum { + HWVER_100 = 0, + HWVER_110 = 1, +}; + +static inline void blank_string(int size) +{ + int i; + + for (i = 0; i < size; i++) + putc('\b'); + for (i = 0; i < size; i++) + putc(' '); + for (i = 0; i < size; i++) + putc('\b'); +} + +/* + * Board early initialization function + */ +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + +#ifdef CONFIG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +static void print_fpga_info(unsigned dev) +{ + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); + int fpga_state = get_fpga_state(dev); + + unsigned unit_type; + unsigned hardware_version; + unsigned feature_channels; + unsigned feature_expansion; + + printf("FPGA%d: ", dev); + if (fpga_state & FPGA_STATE_PLATFORM) + printf("(legacy) "); + + if (fpga_state & FPGA_STATE_DONE_FAILED) { + printf(" done timed out\n"); + return; + } + + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { + printf(" refelectione test failed\n"); + return; + } + + unit_type = (versions & 0xf000) >> 12; + hardware_version = versions & 0x000f; + feature_channels = fpga_features & 0x007f; + feature_expansion = fpga_features & (1<<15); + + switch (unit_type) { + case UNITTYPE_CCD_SWITCH: + printf("CCD-Switch"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00\n"); + break; + + case HWVER_110: + printf(" HW-Ver 1.10\n"); + break; + + default: + printf(" HW-Ver %d(not supported)\n", + hardware_version); + break; + } + + printf(" FPGA V %d.%02d, features:", + fpga_version / 100, fpga_version % 100); + + printf(" %d channel(s)", feature_channels); + + printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: CATCenter Io64\n"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + return 0; +} + +int configure_gbit_phy(char *bus, unsigned char addr) +{ + unsigned short value; + + /* select page 0 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) + goto err_out; + /* switch to powerdown */ + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + &value)) + goto err_out; + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + value | 0x0004)) + goto err_out; + /* select page 2 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) + goto err_out; + /* disable SGMII autonegotiation */ + if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48)) + goto err_out; + /* select page 0 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) + goto err_out; + /* switch from powerdown to normal operation */ + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + &value)) + goto err_out; + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + value & ~0x0004)) + goto err_out; + /* reset phy so settings take effect */ + if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140)) + goto err_out; + + return 0; + +err_out: + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; +} + +int verify_gbit_phy(char *bus, unsigned char addr) +{ + unsigned short value; + + /* select page 2 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) + goto err_out; + /* verify SGMII link status */ + if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) + goto err_out; + if (!(value & (1 << 10))) + return -2; + + return 0; + +err_out: + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; +} + +int last_stage_init(void) +{ + unsigned int k; + unsigned int fpga; + ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1); + int failed = 0; + char str_phys[] = "Setup PHYs -"; + char str_serdes[] = "Start SERDES blocks"; + char str_channels[] = "Start FPGA channels"; + char str_locks[] = "Verify SERDES locks"; + char str_status[] = "Verify PHY status -"; + char slash[] = "\\|/-\\|/-"; + + print_fpga_info(0); + print_fpga_info(1); + + /* setup Gbit PHYs */ + puts("TRANS: "); + puts(str_phys); + miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, + bb_miiphy_read, bb_miiphy_write); + + for (k = 0; k < 32; ++k) { + configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); + putc('\b'); + putc(slash[k % 8]); + } + + miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, + bb_miiphy_read, bb_miiphy_write); + + for (k = 0; k < 32; ++k) { + configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); + putc('\b'); + putc(slash[k % 8]); + } + blank_string(strlen(str_phys)); + + /* take fpga serdes blocks out of reset */ + puts(str_serdes); + udelay(500000); + out_le16(&fpga0->quad_serdes_reset, 0); + out_le16(&fpga1->quad_serdes_reset, 0); + blank_string(strlen(str_serdes)); + + /* take channels out of reset */ + puts(str_channels); + udelay(500000); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; + for (k = 0; k < 32; ++k) + out_le16(ch0_config_int + 4 * k, 0); + } + blank_string(strlen(str_channels)); + + /* verify channels serdes lock */ + puts(str_locks); + udelay(500000); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; + for (k = 0; k < 32; ++k) { + u16 status = in_le16(ch0_status_int + 4*k); + if (!(status & (1 << 4))) { + failed = 1; + printf("fpga %d channel %d: no serdes lock\n", + fpga, k); + } + /* reset events */ + out_le16(ch0_status_int + 4*k, status); + } + } + blank_string(strlen(str_locks)); + + /* verify phy status */ + puts(str_status); + for (k = 0; k < 32; ++k) { + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { + printf("verify baseboard phy %d failed\n", k); + failed = 1; + } + putc('\b'); + putc(slash[k % 8]); + } + for (k = 0; k < 32; ++k) { + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { + printf("verify extensionboard phy %d failed\n", k); + failed = 1; + } + putc('\b'); + putc(slash[k % 8]); + } + blank_string(strlen(str_status)); + + printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); + + return 0; +} + +void gd405ex_init(void) +{ + unsigned int k; + + if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] |= FPGA_STATE_PLATFORM; + } else { + pca9698_direction_output(0x22, 39, 1); + } +} + +void gd405ex_set_fpga_reset(unsigned state) +{ + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) { + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } + } else { + pca9698_set_value(0x22, 39, state ? 0 : 1); + } +} + +void gd405ex_setup_hw(void) +{ + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); +} + +int gd405ex_get_fpga_done(unsigned fpga) +{ + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) + return in_le16((void *)LATCH3_BASE) + & CONFIG_SYS_FPGA_DONE(fpga); + else + return pca9698_get_value(0x22, fpga ? 9 : 8); +} diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 2868cc8..05dd65d 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -30,6 +30,7 @@ endif LIB = $(obj)lib$(VENDOR).o COBJS-$(CONFIG_IO) += miiphybb.o +COBJS-$(CONFIG_IO64) += miiphybb.o COBJS-$(CONFIG_IOCON) += osd.o COBJS-$(CONFIG_DLVISION_10G) += osd.o diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c index e56e966..46f1a1e 100644 --- a/board/gdsys/common/miiphybb.c +++ b/board/gdsys/common/miiphybb.c @@ -26,6 +26,11 @@ #include +struct io_bb_pinset { + int mdio; + int mdc; +}; + static int io_bb_mii_init(struct bb_miiphy_bus *bus) { return 0; @@ -33,47 +38,57 @@ static int io_bb_mii_init(struct bb_miiphy_bus *bus) static int io_bb_mdio_active(struct bb_miiphy_bus *bus) { + struct io_bb_pinset *pins = bus->priv; + out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_TCR) | pins->mdio); return 0; } static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) { + struct io_bb_pinset *pins = bus->priv; + out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_TCR) & ~pins->mdio); return 0; } static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { + struct io_bb_pinset *pins = bus->priv; + if (v) out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_OR) | pins->mdio); else out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_OR) & ~pins->mdio); return 0; } static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { - *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0); + struct io_bb_pinset *pins = bus->priv; + + *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); return 0; } static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { + struct io_bb_pinset *pins = bus->priv; + if (v) out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN); + in_be32((void *)GPIO0_OR) | pins->mdc); else out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN); + in_be32((void *)GPIO0_OR) & ~pins->mdc); return 0; } @@ -85,6 +100,19 @@ static int io_bb_delay(struct bb_miiphy_bus *bus) return 0; } +struct io_bb_pinset io_bb_pinsets[] = { + { + .mdio = CONFIG_SYS_MDIO_PIN, + .mdc = CONFIG_SYS_MDC_PIN, + }, +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME + { + .mdio = CONFIG_SYS_MDIO1_PIN, + .mdc = CONFIG_SYS_MDC1_PIN, + }, +#endif +}; + struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = CONFIG_SYS_GBIT_MII_BUSNAME, @@ -95,7 +123,21 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { .get_mdio = io_bb_get_mdio, .set_mdc = io_bb_set_mdc, .delay = io_bb_delay, - } + .priv = &io_bb_pinsets[0], + }, +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME + { + .name = CONFIG_SYS_GBIT_MII1_BUSNAME, + .init = io_bb_mii_init, + .mdio_active = io_bb_mdio_active, + .mdio_tristate = io_bb_mdio_tristate, + .set_mdio = io_bb_set_mdio, + .get_mdio = io_bb_get_mdio, + .set_mdc = io_bb_set_mdc, + .delay = io_bb_delay, + .priv = &io_bb_pinsets[1], + }, +#endif }; int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / -- cgit v1.1 From bba8f3929e1ae3c09274b8dcdf0ad7b099494f71 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:44 +0000 Subject: alpr board: Fix GCC 4.6 build warnings Fix: fpga.c: In function 'fpga_pre_fn': fpga.c:88:16: warning: variable 'reg' set but not used [-Wunused-but-set-variable] nand.c: In function 'alpr_nand_dev_ready': nand.c:125:18: warning: variable 'val' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese --- board/prodrive/alpr/fpga.c | 3 --- board/prodrive/alpr/nand.c | 4 +--- 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'board') diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index e7686ad..1cce798 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -85,9 +85,6 @@ static unsigned long regval; /* PROGRAM_SEL_DPR = LOW */ int fpga_pre_fn(int cookie) { - unsigned long reg; - - reg = in32(GPIO0_IR); /* Enable the FPGA Chain */ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN); SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN); diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index b18c96b..d35cfed 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -122,12 +122,10 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len static int alpr_nand_dev_ready(struct mtd_info *mtd) { - volatile u_char val; - /* * Blocking read to wait for NAND to be ready */ - val = readb(&(alpr_ndfc->addr_wait)); + (void)readb(&(alpr_ndfc->addr_wait)); /* * Return always true -- cgit v1.1 From 2752a525b8f6f1b591b0a053f284bc51848eb174 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:45 +0000 Subject: board/amirix/ap1000/flash.c: Fix GCC 4.6 build warning Fix: flash.c: In function 'flash_write_cfiword': flash.c:778:11: warning: variable 'ctladdr' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Acked-by: Marek Vasut --- board/amirix/ap1000/flash.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'board') diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c index 1e742e5..bf8877e 100644 --- a/board/amirix/ap1000/flash.c +++ b/board/amirix/ap1000/flash.c @@ -774,12 +774,9 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword) { - - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr (info, 0, 0); cptr.cp = (uchar *) dest; /* Check if Flash is (sufficiently) erased */ -- cgit v1.1 From fc4df325dc90d194428cb188e24abf6aae48dc50 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:47 +0000 Subject: board/cray/L1/flash.c: Fix GCC 4.6 build warning Fix: flash.c: In function 'flash_erase': flash.c:276:24: warning: variable 'l_sect' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Acked-by: Marek Vasut --- board/cray/L1/flash.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'board') diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c index a3d893e..77a2100 100644 --- a/board/cray/L1/flash.c +++ b/board/cray/L1/flash.c @@ -273,7 +273,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -303,16 +303,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; @@ -320,15 +318,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); } } -- cgit v1.1 From 4fcfbec0d74d20dc230a4a4e0e36a9f3bf17ce46 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:48 +0000 Subject: DB64360: Fix GCC 4.6 build warnings Fix: db64360.c: In function 'debug_led': db64360.c:413:6: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_real_open': mv_eth.c:424:6: warning: variable 'port_status' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_stop': mv_eth.c:642:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_xmit': mv_eth.c:718:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_receive': mv_eth.c:803:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_get_stats': mv_eth.c:902:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_update_stat': mv_eth.c:930:24: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c:929:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64360_eth_print_stat': mv_eth.c:1011:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'eth_clear_mib_counters': mv_eth.c:2068:15: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'check_dimm': sdram_init.c:289:50: warning: variable 'trrd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:37: warning: variable 'tras_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:24: warning: variable 'trcd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:8: warning: variable 'trp_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:279:34: warning: variable 'devicesForErrCheck' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'setup_sdram': sdram_init.c:1256:13: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'initdram': sdram_init.c:1735:25: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c:1733:14: warning: variable 's1' set but not used [-Wunused-but-set-variable] sdram_init.c:1733:6: warning: variable 's0' set but not used [-Wunused-but-set-variable] Note: no attempt was make to clean up the mess coding style and other issues in sdram_init.c Signed-off-by: Wolfgang Denk --- board/Marvell/db64360/db64360.c | 3 +- board/Marvell/db64360/mv_eth.c | 33 +-- board/Marvell/db64360/sdram_init.c | 517 ++++++++++++++++++------------------- 3 files changed, 254 insertions(+), 299 deletions(-) (limited to 'board') diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 35b695e..5183466 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include #include +#include #include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index 30304b0..6340585 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -421,7 +421,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data; ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -519,7 +519,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); /* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -637,15 +637,6 @@ static int mv64360_eth_free_rx_rings (struct eth_device *dev) int mv64360_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -715,7 +706,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -724,7 +714,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -800,15 +789,12 @@ int mv64360_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; - ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -899,12 +885,10 @@ static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64360_eth_update_stat (dev); @@ -926,13 +910,10 @@ static void mv64360_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -955,12 +936,12 @@ static void mv64360_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1008,12 +989,10 @@ static void mv64360_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2065,13 +2044,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); return; } diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index d52d3f0..e62ed0c 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -44,15 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG #define MAP_PCI -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64360 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -276,7 +269,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1; #ifdef DEBUG unsigned int k; @@ -286,17 +279,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 1, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); /* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +300,7 @@ return 0; } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -385,48 +378,46 @@ return 0; switch (i) { case 2: /* Memory type (DDR / SDRAM) */ dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif + dimmInfo->slot); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ /*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -552,26 +543,26 @@ return 0; dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n"); #endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1219,11 @@ return 0; cal_val = 2; } - DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1272,13 +1255,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } /* SDRAM configuration */ @@ -1329,12 +1312,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg); /* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg); /* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1344,30 +1327,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64360_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1390,23 +1373,23 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf + debug ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); switch (info->maxClSupported_DDR) { case DDR_CL_3: tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ @@ -1428,18 +1411,18 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ tmp_dunit_control_low = 0x2C1107F2; else tmp_dunit_control_low = 0x3C1107d2; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1449,9 +1432,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1460,9 +1443,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1B1107d2; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1472,9 +1455,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1483,9 +1466,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x3B1107d2; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1495,9 +1478,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1506,9 +1489,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1A1107d2; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1528,8 +1511,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1538,8 +1521,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1549,29 +1532,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */ - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1582,15 +1565,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp); /* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220)); + 0x11511220); GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); @@ -1602,42 +1585,38 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU * Page 426 MV64360 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */ - DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9)); + 0x9); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); - DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - DP (printf - indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *" - + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); /* ------------------------------------------------------------------------------ */ @@ -1647,8 +1626,8 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1656,17 +1635,17 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1712,9 +1691,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2; if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1730,9 +1709,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1747,10 +1725,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2); memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1784,7 +1762,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */ realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; } -- cgit v1.1 From 774b35768571d5b061fc8287dc532c9ea96c443b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:49 +0000 Subject: DB64460: Fix GCC 4.6 build warnings Fix: db64460.c: In function 'debug_led': db64460.c:413:6: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_real_open': mv_eth.c:423:6: warning: variable 'port_status' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_stop': mv_eth.c:641:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_xmit': mv_eth.c:717:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_receive': mv_eth.c:802:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_get_stats': mv_eth.c:901:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_update_stat': mv_eth.c:929:24: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] mv_eth.c:928:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'mv64460_eth_print_stat': mv_eth.c:1010:15: warning: variable 'port_num' set but not used [-Wunused-but-set-variable] mv_eth.c: In function 'eth_clear_mib_counters': mv_eth.c:2067:15: warning: variable 'dummy' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'check_dimm': sdram_init.c:289:50: warning: variable 'trrd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:37: warning: variable 'tras_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:24: warning: variable 'trcd_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:289:8: warning: variable 'trp_clocks' set but not used [-Wunused-but-set-variable] sdram_init.c:279:34: warning: variable 'devicesForErrCheck' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'setup_sdram': sdram_init.c:1255:13: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c: In function 'initdram': sdram_init.c:1744:25: warning: variable 'check' set but not used [-Wunused-but-set-variable] sdram_init.c:1742:14: warning: variable 's1' set but not used [-Wunused-but-set-variable] sdram_init.c:1742:6: warning: variable 's0' set but not used [-Wunused-but-set-variable] Note: no attempt was make to clean up the mess coding style and other issues in sdram_init.c Signed-off-by: Wolfgang Denk --- board/Marvell/db64460/db64460.c | 3 +- board/Marvell/db64460/mv_eth.c | 33 +-- board/Marvell/db64460/sdram_init.c | 515 ++++++++++++++++++------------------- 3 files changed, 255 insertions(+), 296 deletions(-) (limited to 'board') diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c index 14e6355..a7836ed 100644 --- a/board/Marvell/db64460/db64460.c +++ b/board/Marvell/db64460/db64460.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include #include +#include #include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index cd9d5a4..4aefbaf 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -420,7 +420,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data; ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -518,7 +518,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); /* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -636,15 +636,6 @@ static int mv64460_eth_free_rx_rings (struct eth_device *dev) int mv64460_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -714,7 +705,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -723,7 +713,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -799,15 +788,12 @@ int mv64460_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; - ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -898,12 +884,10 @@ static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64460_eth_update_stat (dev); @@ -925,13 +909,10 @@ static void mv64460_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -954,12 +935,12 @@ static void mv64460_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1007,12 +988,10 @@ static void mv64460_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2064,13 +2043,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); return; } diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index e328d8f..6297447 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -44,15 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG #define MAP_PCI -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64460 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -69,14 +62,12 @@ memory_map_bank (unsigned int bankNo, #endif -#ifdef DEBUG if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", + debug("mapping bank %d at %08x - %08x\n", bankNo, bankBase, bankBase + bankLength - 1); } else { - printf ("unmapping bank %d\n", bankNo); + debug("unmapping bank %d\n", bankNo); } -#endif memoryMapBank (bankNo, bankBase, bankLength); @@ -276,7 +267,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1; #ifdef DEBUG unsigned int k; @@ -286,17 +277,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 1, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); /* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +298,7 @@ return 0; } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -387,46 +378,46 @@ return 0; dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; #ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ /*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -552,26 +543,26 @@ return 0; dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n"); #endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1219,11 @@ return 0; cal_val = 2; } - DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1271,13 +1254,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } /* SDRAM configuration */ @@ -1328,12 +1311,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg); /* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg); /* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1343,30 +1326,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64460_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1392,21 +1375,21 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ switch (info->maxClSupported_DDR) { case DDR_CL_3: @@ -1429,9 +1412,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1439,9 +1422,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC5000540; else tmp_dunit_control_low = 0xC4000540; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1451,9 +1434,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1464,9 +1447,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* hang();1 */ } else tmp_dunit_control_low = 0xC4000540; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1476,9 +1459,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1489,9 +1472,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC4000540; } else tmp_dunit_control_low = 0xC3000540;; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1501,9 +1484,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1514,9 +1497,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC4000540; } else tmp_dunit_control_low = 0xC3000540; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1536,8 +1519,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1546,8 +1529,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1557,29 +1540,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */ - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1590,15 +1573,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp); /* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x01501220)); + 0x01501220); /*ronen db64460 */ GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); @@ -1611,10 +1594,10 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU @@ -1624,29 +1607,29 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As 4460 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */ /* ronen db64460 */ - DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0xc)); + 0xc); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); - DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - DP (printf + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); /* ------------------------------------------------------------------------------ */ @@ -1656,8 +1639,8 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1665,17 +1648,17 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1721,9 +1704,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2; if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1739,9 +1722,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1756,10 +1738,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2); memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1793,7 +1775,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */ realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; } -- cgit v1.1 From effa4e30b06e7c4c7d4535bcab8e40652262b13c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:50 +0000 Subject: board/sandburst/common/flash.c: Fix GCC 4.6 build warning Fix: ../common/flash.c: In function 'flash_erase': ../common/flash.c:307:24: warning: variable 'l_sect' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Travis Sawyer Acked-by: Marek Vasut --- board/sandburst/common/flash.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'board') diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c index c65cb96..818a7c3 100644 --- a/board/sandburst/common/flash.c +++ b/board/sandburst/common/flash.c @@ -304,7 +304,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -335,8 +335,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -363,7 +361,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must -- cgit v1.1 From ae5f6b3b2fa26eb82b58bd162535e5a80ebed543 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:53 +0000 Subject: board/mpl/common/flash.c: Fix GCC 4.6 build warning Fix: ../common/flash.c: In function 'flash_init': ../common/flash.c:160:16: warning: variable 'size_b1' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Denis Peter Acked-by: Marek Vasut --- board/mpl/common/flash.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'board') diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 81d7271..d5b63c0 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -157,7 +157,7 @@ unsigned long flash_init (void) int i; #if !defined(CONFIG_PATI) - unsigned long size_b1,flashcr,size_reg; + unsigned long flashcr,size_reg; int mode; extern char version_string; char *p = &version_string; @@ -197,7 +197,6 @@ unsigned long flash_init (void) #if !defined(CONFIG_PATI) /* protect reset vector */ flash_info[0].protect[flash_info[0].sector_count-1] = 1; - size_b1 = 0 ; flash_info[0].size = size_b0; /* set up flash cs according to the size */ size_reg=(flash_info[0].size >>20); -- cgit v1.1 From e38cc2c7713c3a6f25b75317bb4ddcf290d33dfd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:54 +0000 Subject: board/freescale/mpc8610hpcd/mpc8610hpcd.c: Fix GCC 4.6 build warning Fix: mpc8610hpcd.c: In function 'pci_init_board': mpc8610hpcd.c:238:15: warning: variable 'pordevsr' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Cc: Kumar Gala Acked-by: Kumar Gala --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 5b3b560..2bcd5e6 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -235,12 +235,11 @@ void pci_init_board(void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; struct fsl_pci_info pci_info; - u32 devdisr, pordevsr; + u32 devdisr; int first_free_busno; int pci_agent; devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); first_free_busno = fsl_pcie_init_board(0); -- cgit v1.1 From 24b0da3aebb63d945cbdad79a587dc6f90b7bec5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:56 +0000 Subject: board/sbc405/strataflash.c: Fix GCC 4.6 build warning Fix: strataflash.c: In function 'flash_write_cfiword': strataflash.c:673:11: warning: variable 'ctladdr' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk Acked-by: Marek Vasut --- board/sbc405/strataflash.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'board') diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c index e5863d6..b0d3c6c 100644 --- a/board/sbc405/strataflash.c +++ b/board/sbc405/strataflash.c @@ -670,14 +670,11 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr(info, 0, 0); cptr.cp = (uchar *)dest; - /* Check if Flash is (sufficiently) erased */ switch(info->portwidth) { case FLASH_CFI_8BIT: -- cgit v1.1 From f008b17f8c2995996b5d100b71f8851d6f74a136 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 29 Nov 2011 22:17:57 +0000 Subject: board/emk/top860/top860.c: Fix GCC 4.6 build warning Fix: top860.c: In function 'initdram': top860.c:90:11: warning: variable 'j' set but not used [-Wunused-but-set-variable] Note: No attempts were made to convert this file completely to using I/O accessors. This is left as an exercise for the board maintainer. Signed-off-by: Wolfgang Denk Cc: Reinhard Meyer --- board/emk/top860/top860.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c index 76f7a0c..4df7f0e 100644 --- a/board/emk/top860/top860.c +++ b/board/emk/top860/top860.c @@ -34,6 +34,7 @@ #include #include #include +#include /***************************************************************************** * UPM table for 60ns EDO RAM at 25 MHz bus/external clock @@ -87,7 +88,7 @@ phys_size_t initdram (int board_type) */ if ((ulong) initdram & 0xff000000) { volatile uint *addr1, *addr2; - uint i, j; + uint i; upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); @@ -100,8 +101,8 @@ phys_size_t initdram (int board_type) */ addr1 = (volatile uint *) 0; addr2 = (volatile uint *) 0x00400000; - for (i = 0, j = 0; i < 8; i++) - j = addr1[0]; + for (i = 0; i < 8; i++) + in_be32(addr1); /* * Now check whether we got 4MB or 16MB populated -- cgit v1.1