From 76b3f195e9c771f03161616a2f35ab7070be178a Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 17 Aug 2015 19:58:34 +0530 Subject: ARM: k2l: Fix device speeds ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov " for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla --- board/ti/ks2_evm/board_k2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 70e25f1..f35a64f 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -25,7 +25,7 @@ unsigned int external_clk[ext_clk_count] = { static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_799, [SPD1000] = CORE_PLL_1000, - [SPD800] = CORE_PLL_1198, + [SPD1200] = CORE_PLL_1198, }; s16 divn_val[16] = { -- cgit v1.1