From 6d97dc10a81062a787fcf5e5df7b88d1ea122a64 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 12 Aug 2015 17:46:50 +0800 Subject: imx: clock support enet2 anatop clock support To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan Cc: Heiko Schocher Cc: Fabio Estevam Cc: Stefan Roese Cc: Nikolaos Pasaloukos Cc: Stefano Babic Reviewed-by: Stefan Roese --- board/aristainetos/aristainetos-v1.c | 2 +- board/barco/platinum/platinum_picon.c | 2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c index d6a7614..b8fed2e 100644 --- a/board/aristainetos/aristainetos-v1.c +++ b/board/aristainetos/aristainetos-v1.c @@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(ENET_50MHZ); + ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c index b2eab76..0384a26 100644 --- a/board/barco/platinum/platinum_picon.c +++ b/board/barco/platinum/platinum_picon.c @@ -148,7 +148,7 @@ int platinum_setup_enet(void) /* set GPIO_16 as ENET_REF_CLK_OUT */ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } int platinum_setup_i2c(void) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 98602f8..7c0e90a 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -361,7 +361,7 @@ static void setup_fec(void) * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(ENET_125MHZ); + enable_fec_anatop_clock(0, ENET_125MHZ); } setup_iomux_enet(); diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 7c18c90..98e3ef0 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -279,7 +279,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } #endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index d58a79a..ffc0046 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -170,7 +170,7 @@ static int setup_fec(void) reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(ENET_125MHZ); + return enable_fec_anatop_clock(0, ENET_125MHZ); } int board_eth_init(bd_t *bis) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 9b1ecf0..8247e43 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis) struct mii_dev *bus; struct phy_device *phydev; - int ret = enable_fec_anatop_clock(ENET_25MHZ); + int ret = enable_fec_anatop_clock(0, ENET_25MHZ); if (ret) return ret; -- cgit v1.1