From 5de851403b01489b493fa83137ad990b8ce60d1c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Jun 2008 17:36:39 +0200 Subject: ppc4xx: Rework 440GX UIC handling This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese --- board/amcc/ocotea/ocotea.c | 50 +++++++++++++++++++++++-------------- board/amcc/taishan/taishan.c | 50 +++++++++++++++++++++++-------------- board/prodrive/alpr/alpr.c | 50 +++++++++++++++++++++++-------------- board/sandburst/karef/karef.c | 50 +++++++++++++++++++++++-------------- board/sandburst/metrobox/metrobox.c | 50 +++++++++++++++++++++++-------------- board/xpedite1k/xpedite1k.c | 50 +++++++++++++++++++++++-------------- 6 files changed, 186 insertions(+), 114 deletions(-) (limited to 'board') diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index eea1e1e..4d1d093 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -147,36 +147,48 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(sdr_mfr, mfr); */ diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index b6c3065..fdd82e7 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -119,36 +119,48 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ + mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ mfsdr(sdr_pfc0,reg); diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 131a62d..cc491d0 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -48,36 +48,48 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe03); /* per manual */ - mtdcr (uic0tr, 0x01c00000); /* per manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe03); /* per manual */ + mtdcr (uic1tr, 0x01c00000); /* per manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 2d71d3b..72ce976 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -195,36 +195,48 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ * Setup the interrupt controller polarities, triggers, etc. +-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non- critical */ - mtdcr (uic0pr, 0xfffffe03); /* polarity */ - mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc8ff); /* polarity */ - mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1cr, 0x00000000); /* all non- critical */ + mtdcr (uic1pr, 0xfffffe03); /* polarity */ + mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffff83ff); /* polarity */ - mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2pr, 0xffffc8ff); /* polarity */ + mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); - mtdcr (uicb0tr, 0x00000000); - mtdcr (uicb0vr, 0x00000001); + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffff83ff); /* polarity */ + mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); + mtdcr (uic0tr, 0x00000000); + mtdcr (uic0vr, 0x00000001); fpga_init(); diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index 9704901..63c91dc 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -185,36 +185,48 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ * Setup the interrupt controller polarities, triggers, etc. +-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non- critical */ - mtdcr (uic0pr, 0xfffffe03); /* polarity */ - mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc8ff); /* polarity */ - mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1cr, 0x00000000); /* all non- critical */ + mtdcr (uic1pr, 0xfffffe03); /* polarity */ + mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffff83ff); /* polarity */ - mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2pr, 0xffffc8ff); /* polarity */ + mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); - mtdcr (uicb0tr, 0x00000000); - mtdcr (uicb0vr, 0x00000001); + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffff83ff); /* polarity */ + mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); + mtdcr (uic0tr, 0x00000000); + mtdcr (uic0vr, 0x00000001); fpga_init(); diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index bc7e3bd..c94a345 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -59,36 +59,48 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */ + mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ LED0_ON(); -- cgit v1.1