From b5d289fc29842095d5cd0f82cceab1b0b2e824ba Mon Sep 17 00:00:00 2001 From: Asen Dimov Date: Tue, 20 Apr 2010 22:49:04 +0300 Subject: add new board pm9g45 Add the new board PM9G45 from Ronetix GmbH. * AT91SAM9G45 MCU at 400Mhz. * 128MB DDR2 SDRAM * 256MB NAND * 10/100 MBits Ethernet DP83848 * Serial number chip DS2401 The board is made as SODIMM200 module. For more info www.ronatix.at or info@ronetix.at. Signed-off-by: Asen Dimov --- board/ronetix/pm9g45/Makefile | 54 ++++++++++++ board/ronetix/pm9g45/config.mk | 1 + board/ronetix/pm9g45/pm9g45.c | 188 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 243 insertions(+) create mode 100644 board/ronetix/pm9g45/Makefile create mode 100644 board/ronetix/pm9g45/config.mk create mode 100644 board/ronetix/pm9g45/pm9g45.c (limited to 'board') diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile new file mode 100644 index 0000000..dd5b02e --- /dev/null +++ b/board/ronetix/pm9g45/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += pm9g45.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ronetix/pm9g45/config.mk b/board/ronetix/pm9g45/config.mk new file mode 100644 index 0000000..7fe9d03 --- /dev/null +++ b/board/ronetix/pm9g45/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x73f00000 diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c new file mode 100644 index 0000000..3b4d9a3 --- /dev/null +++ b/board/ronetix/pm9g45/pm9g45.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2010 + * Ilko Iliev + * Asen Dimov + * Ronetix GmbH + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void pm9g45_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + /* Enable CS3 */ + csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->ccr[6]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer); + +#ifdef CONFIG_SYS_NAND_READY_PIN + /* Configure RDY/BSY */ + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void pm9g45_macb_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + /* + * PD2 enables the 50MHz oscillator for Ethernet PHY + * 1 - enable + * 0 - disable + */ + at91_set_pio_output(AT91_PIO_PORTD, 2, 1); + at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */ + + /* Enable clock */ + writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0); + + /* Re-enable pull-up */ + at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); + at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + + /* Enable Ctrlc */ + console_init_f(); + + writel((1 << AT91SAM9G45_ID_PIOA) | + (1 << AT91SAM9G45_ID_PIOB) | + (1 << AT91SAM9G45_ID_PIOC) | + (1 << AT91SAM9G45_ID_PIODE), &pmc->pcer); + + /* arch number of AT91SAM9M10G45EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PM9G45; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + pm9g45_nand_hw_init(); +#endif + +#ifdef CONFIG_MACB + pm9g45_macb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); +#endif + return rc; +} -- cgit v1.1 From 04cbc19fedb55265d08cddea294c3b6d9f8b2d18 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 7 Jun 2010 14:13:36 -0400 Subject: TI: TNETV107X EVM initial support TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This patch adds support for the TNETV107X EVM board. Signed-off-by: Cyril Chemparathy Signed-off-by: Sandeep Paulraj --- board/ti/tnetv107xevm/Makefile | 49 +++++++++++++ board/ti/tnetv107xevm/config.mk | 20 +++++ board/ti/tnetv107xevm/sdb_board.c | 149 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+) create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/sdb_board.c (limited to 'board') diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile new file mode 100644 index 0000000..2446c2a --- /dev/null +++ b/board/ti/tnetv107xevm/Makefile @@ -0,0 +1,49 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS += sdb_board.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +.PHONY: all + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk new file mode 100644 index 0000000..d24d49a --- /dev/null +++ b/board/ti/tnetv107xevm/config.mk @@ -0,0 +1,20 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +TEXT_BASE = 0x83FC0000 diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c new file mode 100644 index 0000000..3ed1cfd --- /dev/null +++ b/board/ti/tnetv107xevm/sdb_board.c @@ -0,0 +1,149 @@ +/* + * TNETV107X-EVM: Board initialization + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { + { /* CS0 */ + .mode = ASYNC_EMIF_MODE_NAND, + .wr_setup = 5, + .wr_strobe = 5, + .wr_hold = 2, + .rd_setup = 5, + .rd_strobe = 5, + .rd_hold = 2, + .turn_around = 5, + .width = ASYNC_EMIF_8, + }, + { /* CS1 */ + .mode = ASYNC_EMIF_MODE_NOR, + .wr_setup = 2, + .wr_strobe = 27, + .wr_hold = 4, + .rd_setup = 2, + .rd_strobe = 27, + .rd_hold = 4, + .turn_around = 2, + .width = ASYNC_EMIF_PRESERVE, + }, + { /* CS2 */ + .mode = ASYNC_EMIF_MODE_NOR, + .wr_setup = 2, + .wr_strobe = 27, + .wr_hold = 4, + .rd_setup = 2, + .rd_strobe = 27, + .rd_hold = 4, + .turn_around = 2, + .width = ASYNC_EMIF_PRESERVE, + }, + { /* CS3 */ + .mode = ASYNC_EMIF_MODE_NOR, + .wr_setup = 1, + .wr_strobe = 90, + .wr_hold = 3, + .rd_setup = 1, + .rd_strobe = 26, + .rd_hold = 3, + .turn_around = 1, + .width = ASYNC_EMIF_8, + }, +}; + +static struct pll_init_data pll_config[] = { + { + .pll = ETH_PLL, + .internal_osc = 1, + .pll_freq = 500000000, + .div_freq = { + 5000000, 50000000, 125000000, 250000000, 25000000, + }, + }, +}; + +static const short sdio1_pins[] = { + TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1, + TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1, + TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1, + -1 +}; + +static const short uart1_pins[] = { + TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1 +}; + +static const short ssp_pins[] = { + TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2, + TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2, + TNETV107X_PIN_SSP1_3, -1 +}; + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + __raw_writel(0, INTC_GLB_EN); /* Global disable */ + __raw_writel(0, INTC_HINT_EN); /* Disable host ints */ + __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */ + __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */ + __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */ +#endif + + gd->bd->bi_arch_number = MACH_TYPE_TNETV107X; + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + init_plls(ARRAY_SIZE(pll_config), pll_config); + + init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); + + mux_select_pin(TNETV107X_PIN_ASR_CS3); + mux_select_pins(sdio1_pins); + mux_select_pins(uart1_pins); + mux_select_pins(ssp_pins); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_NAND_DAVINCI +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + + return 0; +} +#endif -- cgit v1.1 From 3d9f0ffddaf1ece95a826785b971860ebdadf424 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 Jun 2010 15:20:43 -0400 Subject: AM35x: Add support for AM3517EVM This patch adds basic support for the AM3517EVM. It includes: - Board files (.c and .h) - Default configuration file - Updates for Makefile Signed-off-by: Vaibhav Hiremath Signed-off-by: Sanjeev Premi Signed-off-by: Sandeep Paulraj --- board/logicpd/am3517evm/Makefile | 46 ++++ board/logicpd/am3517evm/am3517evm.c | 76 ++++++ board/logicpd/am3517evm/am3517evm.h | 445 ++++++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/config.mk | 30 +++ 4 files changed, 597 insertions(+) create mode 100644 board/logicpd/am3517evm/Makefile create mode 100644 board/logicpd/am3517evm/am3517evm.c create mode 100644 board/logicpd/am3517evm/am3517evm.h create mode 100644 board/logicpd/am3517evm/config.mk (limited to 'board') diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile new file mode 100644 index 0000000..3a6b1a1 --- /dev/null +++ b/board/logicpd/am3517evm/Makefile @@ -0,0 +1,46 @@ +# +# Author: Vaibhav Hiremath +# +# Based on ti/evm/Makefile +# +# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := am3517evm.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c new file mode 100644 index 0000000..bbb6e83 --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@ +/* + * am3517evm.c - board file for TI's AM3517 family of devices. + * + * Author: Vaibhav Hiremath + * + * Based on ti/evm/evm.c + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "am3517evm.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Init i2c, ethernet, etc... (done here so udelay works) + */ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_AM3517EVM(); +} diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h new file mode 100644 index 0000000..3d74ef1 --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.h @@ -0,0 +1,445 @@ +/* + * am3517evm.h - Header file for the AM3517 EVM. + * + * Author: Vaibhav Hiremath + * + * Based on ti/evm/evm.h + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "AM3517EVM Board", + "NAND", +}; +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_AM3517EVM() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - ETH_nRESET*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + /* WriteProtect */\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ + /* - LCD_INI*/\ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ + /* - LCD_ENVDD */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ + /* - LCD_QVGA/nVGA */\ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ + /* - LCD_RESB */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ + /* - LAN_INTR*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + /*SYS_nRESWARM */\ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + /* - GPIO30 */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + /* - PEN_IRQ */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk new file mode 100644 index 0000000..f7a35ce --- /dev/null +++ b/board/logicpd/am3517evm/config.mk @@ -0,0 +1,30 @@ +# +# Author: Vaibhav Hiremath +# +# Based on ti/evm/config.mk +# +# Copyright (C) 2010 +# Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 -- cgit v1.1 From 5cc48f7e55df0d74a12d338de2117f05951fc536 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 7 Jun 2010 14:13:36 -0400 Subject: TI: TNETV107X EVM initial support TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This patch adds support for the TNETV107X EVM board. Signed-off-by: Cyril Chemparathy Signed-off-by: Sandeep Paulraj --- board/ti/tnetv107xevm/Makefile | 49 +++++++++++++ board/ti/tnetv107xevm/config.mk | 20 +++++ board/ti/tnetv107xevm/sdb_board.c | 149 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+) create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/sdb_board.c (limited to 'board') diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile new file mode 100644 index 0000000..2446c2a --- /dev/null +++ b/board/ti/tnetv107xevm/Makefile @@ -0,0 +1,49 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS += sdb_board.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +.PHONY: all + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk new file mode 100644 index 0000000..d24d49a --- /dev/null +++ b/board/ti/tnetv107xevm/config.mk @@ -0,0 +1,20 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +TEXT_BASE = 0x83FC0000 diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c new file mode 100644 index 0000000..3ed1cfd --- /dev/null +++ b/board/ti/tnetv107xevm/sdb_board.c @@ -0,0 +1,149 @@ +/* + * TNETV107X-EVM: Board initialization + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { + { /* CS0 */ + .mode = ASYNC_EMIF_MODE_NAND, + .wr_setup = 5, + .wr_strobe = 5, + .wr_hold = 2, + .rd_setup = 5, + .rd_strobe = 5, + .rd_hold = 2, + .turn_around = 5, + .width = ASYNC_EMIF_8, + }, + { /* CS1 */ + .mode = ASYNC_EMIF_MODE_NOR, + .wr_setup = 2, + .wr_strobe = 27, + .wr_hold = 4, + .rd_setup = 2, + .rd_strobe = 27, + .rd_hold = 4, + .turn_around = 2, + .width = ASYNC_EMIF_PRESERVE, + }, + { /* CS2 */ + .mode = ASYNC_EMIF_MODE_NOR, + .wr_setup = 2, + .wr_strobe = 27, + .wr_hold = 4, + .rd_setup = 2, + .rd_strobe = 27, + .rd_hold = 4, + .turn_around = 2, + .width = ASYNC_EMIF_PRESERVE, + }, + { /* CS3 */ + .mode = ASYNC_EMIF_MODE_NOR, + .wr_setup = 1, + .wr_strobe = 90, + .wr_hold = 3, + .rd_setup = 1, + .rd_strobe = 26, + .rd_hold = 3, + .turn_around = 1, + .width = ASYNC_EMIF_8, + }, +}; + +static struct pll_init_data pll_config[] = { + { + .pll = ETH_PLL, + .internal_osc = 1, + .pll_freq = 500000000, + .div_freq = { + 5000000, 50000000, 125000000, 250000000, 25000000, + }, + }, +}; + +static const short sdio1_pins[] = { + TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1, + TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1, + TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1, + -1 +}; + +static const short uart1_pins[] = { + TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1 +}; + +static const short ssp_pins[] = { + TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2, + TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2, + TNETV107X_PIN_SSP1_3, -1 +}; + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + __raw_writel(0, INTC_GLB_EN); /* Global disable */ + __raw_writel(0, INTC_HINT_EN); /* Disable host ints */ + __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */ + __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */ + __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */ +#endif + + gd->bd->bi_arch_number = MACH_TYPE_TNETV107X; + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + init_plls(ARRAY_SIZE(pll_config), pll_config); + + init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); + + mux_select_pin(TNETV107X_PIN_ASR_CS3); + mux_select_pins(sdio1_pins); + mux_select_pins(uart1_pins); + mux_select_pins(ssp_pins); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_NAND_DAVINCI +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + + return 0; +} +#endif -- cgit v1.1 From ed01e45cfa20d60ee83a4ee0128d843730055294 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 7 Jun 2010 15:20:43 -0400 Subject: AM35x: Add support for AM3517EVM This patch adds basic support for the AM3517EVM. It includes: - Board files (.c and .h) - Default configuration file - Updates for Makefile Signed-off-by: Vaibhav Hiremath Signed-off-by: Sanjeev Premi Signed-off-by: Sandeep Paulraj --- board/logicpd/am3517evm/Makefile | 46 ++++ board/logicpd/am3517evm/am3517evm.c | 76 ++++++ board/logicpd/am3517evm/am3517evm.h | 445 ++++++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/config.mk | 30 +++ 4 files changed, 597 insertions(+) create mode 100644 board/logicpd/am3517evm/Makefile create mode 100644 board/logicpd/am3517evm/am3517evm.c create mode 100644 board/logicpd/am3517evm/am3517evm.h create mode 100644 board/logicpd/am3517evm/config.mk (limited to 'board') diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile new file mode 100644 index 0000000..3a6b1a1 --- /dev/null +++ b/board/logicpd/am3517evm/Makefile @@ -0,0 +1,46 @@ +# +# Author: Vaibhav Hiremath +# +# Based on ti/evm/Makefile +# +# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := am3517evm.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c new file mode 100644 index 0000000..bbb6e83 --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@ +/* + * am3517evm.c - board file for TI's AM3517 family of devices. + * + * Author: Vaibhav Hiremath + * + * Based on ti/evm/evm.c + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "am3517evm.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Init i2c, ethernet, etc... (done here so udelay works) + */ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_AM3517EVM(); +} diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h new file mode 100644 index 0000000..3d74ef1 --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.h @@ -0,0 +1,445 @@ +/* + * am3517evm.h - Header file for the AM3517 EVM. + * + * Author: Vaibhav Hiremath + * + * Based on ti/evm/evm.h + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "AM3517EVM Board", + "NAND", +}; +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_AM3517EVM() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - ETH_nRESET*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + /* WriteProtect */\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ + /* - LCD_INI*/\ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ + /* - LCD_ENVDD */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ + /* - LCD_QVGA/nVGA */\ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ + /* - LCD_RESB */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ + /* - LAN_INTR*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + /*SYS_nRESWARM */\ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + /* - GPIO30 */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + /* - PEN_IRQ */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk new file mode 100644 index 0000000..f7a35ce --- /dev/null +++ b/board/logicpd/am3517evm/config.mk @@ -0,0 +1,30 @@ +# +# Author: Vaibhav Hiremath +# +# Based on ti/evm/config.mk +# +# Copyright (C) 2010 +# Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 -- cgit v1.1 From 5246d01edd8935e04cdf79a5b9a03874509a31b1 Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Tue, 8 Jun 2010 17:19:22 -0400 Subject: OMAP3: pandora: enable battery backup capacitor Pandora has a capacitor connected as backup battery, which allows retaining RTC for some time while main battery is removed. Enable backup battery charge function to charge that capacitor. Signed-off-by: Grazvydas Ignotas Signed-off-by: Sandeep Paulraj --- board/pandora/pandora.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board') diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 75e4330..355e9ea 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -37,6 +37,10 @@ #include #include "pandora.h" +#define TWL4030_BB_CFG_BBCHEN (1 << 4) +#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2) +#define TWL4030_BB_CFG_BBISEL_500UA 2 + /* * Routine: board_init * Description: Early hardware init. @@ -78,6 +82,11 @@ int misc_init_r(void) writel(GPIO28, &gpio5_base->setdataout); writel(GPIO4, &gpio6_base->setdataout); + /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, + TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV | + TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG); + dieid_num_r(); return 0; -- cgit v1.1 From 9d79956029ec379e7137948ba3a7debbea61325f Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Mon, 7 Jun 2010 12:39:59 +0530 Subject: da830: Move common code out of da830evm.c file TI's DA850/OMAP-L138 platform is similar to DA830/OMAP-L137 in many aspects. So instead of repeating the same code in multiple files, move the common code to a different file and call those functions from the respective da830/da850 files. Signed-off-by: Sudhakar Rajashekhara Acked-by: Nick Thompson Acked-by: Ben Gardiner Signed-off-by: Sandeep Paulraj --- board/davinci/da830evm/Makefile | 2 +- board/davinci/da830evm/common.c | 55 +++++++++++++++++++++++++++++++++++++++ board/davinci/da830evm/common.h | 30 +++++++++++++++++++++ board/davinci/da830evm/da830evm.c | 29 +++++++++------------ 4 files changed, 98 insertions(+), 18 deletions(-) create mode 100644 board/davinci/da830evm/common.c create mode 100644 board/davinci/da830evm/common.h (limited to 'board') diff --git a/board/davinci/da830evm/Makefile b/board/davinci/da830evm/Makefile index 02636fa..ee00057 100644 --- a/board/davinci/da830evm/Makefile +++ b/board/davinci/da830evm/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := da830evm.o +COBJS := da830evm.o common.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/davinci/da830evm/common.c b/board/davinci/da830evm/common.c new file mode 100644 index 0000000..9cd5204c --- /dev/null +++ b/board/davinci/da830evm/common.c @@ -0,0 +1,55 @@ +/* + * Miscellaneous DA8XX functions. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include "common.h" + +#ifndef CONFIG_USE_IRQ +void irq_init(void) +{ + /* + * Mask all IRQs by clearing the global enable and setting + * the enable clear for all the 90 interrupts. + */ + + writel(0, &davinci_aintc_regs->ger); + + writel(0, &davinci_aintc_regs->hier); + + writel(0xffffffff, &davinci_aintc_regs->ecr1); + writel(0xffffffff, &davinci_aintc_regs->ecr2); + writel(0xffffffff, &davinci_aintc_regs->ecr3); +} +#endif + +/* + * Enable PSC for various peripherals. + */ +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) + lpsc_on(item[i].lpsc_no); + + return 0; +} diff --git a/board/davinci/da830evm/common.h b/board/davinci/da830evm/common.h new file mode 100644 index 0000000..7ae63a6 --- /dev/null +++ b/board/davinci/da830evm/common.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __COMMON_H +#define __COMMON_H + +struct lpsc_resource { + const int lpsc_no; +}; + +void irq_init(void); +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + int n_items); + +#endif /* __COMMON_H */ diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index 6385443..57506d6 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -41,6 +41,7 @@ #include #include #include "../common/misc.h" +#include "common.h" DECLARE_GLOBAL_DATA_PTR; @@ -120,21 +121,18 @@ static const struct pinmux_resource pinmuxes[] = { #endif }; +static const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_SPI0 }, /* Serial Flash */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + int board_init(void) { #ifndef CONFIG_USE_IRQ - /* - * Mask all IRQs by clearing the global enable and setting - * the enable clear for all the 90 interrupts. - */ - - writel(0, &davinci_aintc_regs->ger); - - writel(0, &davinci_aintc_regs->hier); - - writel(0xffffffff, &davinci_aintc_regs->ecr1); - writel(0xffffffff, &davinci_aintc_regs->ecr2); - writel(0xffffffff, &davinci_aintc_regs->ecr3); + irq_init(); #endif #ifdef CONFIG_NAND_DAVINCI @@ -165,11 +163,8 @@ int board_init(void) * assuming here that the DSP bootloader has set the IOPU * such that PSC access is available to ARM */ - lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */ - lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */ - lpsc_on(DAVINCI_LPSC_EMAC); /* image download */ - lpsc_on(DAVINCI_LPSC_UART2); /* console */ - lpsc_on(DAVINCI_LPSC_GPIO); + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & -- cgit v1.1 From 158557001afe167dcb848bb14ba0f2f20aeb25a1 Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Tue, 8 Jun 2010 11:01:58 +0530 Subject: TI: DaVinci: Prepare for da850 support DA850/OMAP-L138 is a new SoC from Texas Instruments (http://focus.ti.com/docs/prod/folders/print/omap-l138.html). This SoC is similar to DA830/OMAP-L137 in many aspects. Hence rename the da830 specific files and folders to da8xx to accommodate DA850/OMAP-L138. Signed-off-by: Sudhakar Rajashekhara Acked-by: Ben Gardiner Reviewed-by: Wolfgang Denk Signed-off-by: Sandeep Paulraj --- board/davinci/da830evm/Makefile | 51 --------- board/davinci/da830evm/common.c | 55 --------- board/davinci/da830evm/common.h | 30 ----- board/davinci/da830evm/config.mk | 43 -------- board/davinci/da830evm/da830evm.c | 227 -------------------------------------- board/davinci/da8xxevm/Makefile | 54 +++++++++ board/davinci/da8xxevm/common.c | 55 +++++++++ board/davinci/da8xxevm/common.h | 30 +++++ board/davinci/da8xxevm/config.mk | 43 ++++++++ board/davinci/da8xxevm/da830evm.c | 227 ++++++++++++++++++++++++++++++++++++++ 10 files changed, 409 insertions(+), 406 deletions(-) delete mode 100644 board/davinci/da830evm/Makefile delete mode 100644 board/davinci/da830evm/common.c delete mode 100644 board/davinci/da830evm/common.h delete mode 100644 board/davinci/da830evm/config.mk delete mode 100644 board/davinci/da830evm/da830evm.c create mode 100644 board/davinci/da8xxevm/Makefile create mode 100644 board/davinci/da8xxevm/common.c create mode 100644 board/davinci/da8xxevm/common.h create mode 100644 board/davinci/da8xxevm/config.mk create mode 100644 board/davinci/da8xxevm/da830evm.c (limited to 'board') diff --git a/board/davinci/da830evm/Makefile b/board/davinci/da830evm/Makefile deleted file mode 100644 index ee00057..0000000 --- a/board/davinci/da830evm/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2007 Sergey Kubushyn -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := da830evm.o common.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak *~ .depend - -######################################################################### -# This is for $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/davinci/da830evm/common.c b/board/davinci/da830evm/common.c deleted file mode 100644 index 9cd5204c..0000000 --- a/board/davinci/da830evm/common.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Miscellaneous DA8XX functions. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include "common.h" - -#ifndef CONFIG_USE_IRQ -void irq_init(void) -{ - /* - * Mask all IRQs by clearing the global enable and setting - * the enable clear for all the 90 interrupts. - */ - - writel(0, &davinci_aintc_regs->ger); - - writel(0, &davinci_aintc_regs->hier); - - writel(0xffffffff, &davinci_aintc_regs->ecr1); - writel(0xffffffff, &davinci_aintc_regs->ecr2); - writel(0xffffffff, &davinci_aintc_regs->ecr3); -} -#endif - -/* - * Enable PSC for various peripherals. - */ -int da8xx_configure_lpsc_items(const struct lpsc_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) - lpsc_on(item[i].lpsc_no); - - return 0; -} diff --git a/board/davinci/da830evm/common.h b/board/davinci/da830evm/common.h deleted file mode 100644 index 7ae63a6..0000000 --- a/board/davinci/da830evm/common.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __COMMON_H -#define __COMMON_H - -struct lpsc_resource { - const int lpsc_no; -}; - -void irq_init(void); -int da8xx_configure_lpsc_items(const struct lpsc_resource *item, - int n_items); - -#endif /* __COMMON_H */ diff --git a/board/davinci/da830evm/config.mk b/board/davinci/da830evm/config.mk deleted file mode 100644 index 6da29a9..0000000 --- a/board/davinci/da830evm/config.mk +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/ -# -# Copyright (C) 2007 Sergey Kubushyn -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Texas Instruments DA8xx EVM board (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips). -# Physical Address: -# C000'0000 to C400'0000 -# -# Linux-Kernel is expected to be at C000'8000, entry C000'8000 -# (mem base + reserved) -# -# we load ourself to C108 '0000 - - -#Provide at least 16MB spacing between us and the Linux Kernel image -TEXT_BASE = 0xC1080000 diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c deleted file mode 100644 index 57506d6..0000000 --- a/board/davinci/da830evm/da830evm.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. - * - * Base on code from TI. Original Notices follow: - * - * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/ - * - * Modified for DA8xx EVM. - * - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts are shamelessly stolen from various TI sources, original copyright - * follows: - * ----------------------------------------------------------------- - * - * Copyright (C) 2004 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * ---------------------------------------------------------------------------- - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/misc.h" -#include "common.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define pinmux &davinci_syscfg_regs->pinmux - -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi0_pins[] = { - { pinmux[7], 1, 3 }, - { pinmux[7], 1, 4 }, - { pinmux[7], 1, 5 }, - { pinmux[7], 1, 6 }, - { pinmux[7], 1, 7 } -}; - -/* EMIF-A bus pins for 8-bit NAND support on CS3 */ -static const struct pinmux_config emifa_nand_pins[] = { - { pinmux[13], 1, 6 }, - { pinmux[13], 1, 7 }, - { pinmux[14], 1, 0 }, - { pinmux[14], 1, 1 }, - { pinmux[14], 1, 2 }, - { pinmux[14], 1, 3 }, - { pinmux[14], 1, 4 }, - { pinmux[14], 1, 5 }, - { pinmux[15], 1, 7 }, - { pinmux[16], 1, 0 }, - { pinmux[18], 1, 1 }, - { pinmux[18], 1, 4 }, - { pinmux[18], 1, 5 }, -}; - -/* EMAC PHY interface pins */ -static const struct pinmux_config emac_pins[] = { - { pinmux[9], 0, 5 }, - { pinmux[10], 2, 1 }, - { pinmux[10], 2, 2 }, - { pinmux[10], 2, 3 }, - { pinmux[10], 2, 4 }, - { pinmux[10], 2, 5 }, - { pinmux[10], 2, 6 }, - { pinmux[10], 2, 7 }, - { pinmux[11], 2, 0 }, - { pinmux[11], 2, 1 }, -}; - -/* UART pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux[8], 2, 7 }, - { pinmux[9], 2, 0 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux[8], 2, 3 }, - { pinmux[8], 2, 4 } -}; - -/* USB0_DRVVBUS pin muxer settings */ -static const struct pinmux_config usb_pins[] = { - { pinmux[9], 1, 1 } -}; - -static const struct pinmux_resource pinmuxes[] = { -#ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi0_pins), -#endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), -#ifdef CONFIG_USB_DA8XX - PINMUX_ITEM(usb_pins), -#endif -#ifdef CONFIG_USE_NAND - PINMUX_ITEM(emifa_nand_pins), -#endif -#if defined(CONFIG_DRIVER_TI_EMAC) - PINMUX_ITEM(emac_pins), -#endif -}; - -static const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_SPI0 }, /* Serial Flash */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_GPIO }, -}; - -int board_init(void) -{ -#ifndef CONFIG_USE_IRQ - irq_init(); -#endif - -#ifdef CONFIG_NAND_DAVINCI - /* EMIFA 100MHz clock select */ - writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2, - &davinci_syscfg_regs->cfgchip3); - /* NAND CS setup */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(2) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(2) | - DAVINCI_ABCR_RHOLD(0) | - DAVINCI_ABCR_TA(2) | - DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->ab2cr); -#endif - - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* - * Power on required peripherals - * ARM does not have access by default to PSC0 and PSC1 - * assuming here that the DSP bootloader has set the IOPU - * such that PSC access is available to ARM - */ - if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) - return 1; - - /* setup the SUSPSRC for ARM to control emulation suspend */ - writel(readl(&davinci_syscfg_regs->suspsrc) & - ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | - DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART2), - &davinci_syscfg_regs->suspsrc); - - /* configure pinmux settings */ - if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) - return 1; - - /* enable the console UART */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart2_ctrl_regs->pwremu_mgmt); - - return(0); -} - -#if defined(CONFIG_DRIVER_TI_EMAC) - -#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */ - -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - u_int8_t mac_addr[6]; - u_int8_t switch_start_cmd[2] = { 0x01, 0x23 }; - - /* Read Ethernet MAC address from EEPROM */ - if (dvevm_read_mac_address(mac_addr)) - /* set address env if not already set */ - dv_configure_mac_address(mac_addr); - - /* read the address back from env */ - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) - return -1; - - /* provide the resulting addr to the driver */ - davinci_eth_set_mac_addr(mac_addr); - - /* enable the Ethernet switch in the 3 port PHY */ - if (i2c_write(PHY_SW_I2C_ADDR, 0, 0, - switch_start_cmd, sizeof(switch_start_cmd))) { - printf("Ethernet switch start failed!\n"); - return -1; - } - - /* finally, initialise the driver */ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - return 0; -} -#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile new file mode 100644 index 0000000..56047dc --- /dev/null +++ b/board/davinci/da8xxevm/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += common.o +COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o + +COBJS := $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/da8xxevm/common.c b/board/davinci/da8xxevm/common.c new file mode 100644 index 0000000..9cd5204c --- /dev/null +++ b/board/davinci/da8xxevm/common.c @@ -0,0 +1,55 @@ +/* + * Miscellaneous DA8XX functions. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include "common.h" + +#ifndef CONFIG_USE_IRQ +void irq_init(void) +{ + /* + * Mask all IRQs by clearing the global enable and setting + * the enable clear for all the 90 interrupts. + */ + + writel(0, &davinci_aintc_regs->ger); + + writel(0, &davinci_aintc_regs->hier); + + writel(0xffffffff, &davinci_aintc_regs->ecr1); + writel(0xffffffff, &davinci_aintc_regs->ecr2); + writel(0xffffffff, &davinci_aintc_regs->ecr3); +} +#endif + +/* + * Enable PSC for various peripherals. + */ +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) + lpsc_on(item[i].lpsc_no); + + return 0; +} diff --git a/board/davinci/da8xxevm/common.h b/board/davinci/da8xxevm/common.h new file mode 100644 index 0000000..7ae63a6 --- /dev/null +++ b/board/davinci/da8xxevm/common.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __COMMON_H +#define __COMMON_H + +struct lpsc_resource { + const int lpsc_no; +}; + +void irq_init(void); +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + int n_items); + +#endif /* __COMMON_H */ diff --git a/board/davinci/da8xxevm/config.mk b/board/davinci/da8xxevm/config.mk new file mode 100644 index 0000000..6da29a9 --- /dev/null +++ b/board/davinci/da8xxevm/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/ +# +# Copyright (C) 2007 Sergey Kubushyn +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Texas Instruments DA8xx EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips). +# Physical Address: +# C000'0000 to C400'0000 +# +# Linux-Kernel is expected to be at C000'8000, entry C000'8000 +# (mem base + reserved) +# +# we load ourself to C108 '0000 + + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0xC1080000 diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c new file mode 100644 index 0000000..57506d6 --- /dev/null +++ b/board/davinci/da8xxevm/da830evm.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. + * + * Base on code from TI. Original Notices follow: + * + * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/ + * + * Modified for DA8xx EVM. + * + * Copyright (C) 2007 Sergey Kubushyn + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/misc.h" +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define pinmux &davinci_syscfg_regs->pinmux + +/* SPI0 pin muxer settings */ +static const struct pinmux_config spi0_pins[] = { + { pinmux[7], 1, 3 }, + { pinmux[7], 1, 4 }, + { pinmux[7], 1, 5 }, + { pinmux[7], 1, 6 }, + { pinmux[7], 1, 7 } +}; + +/* EMIF-A bus pins for 8-bit NAND support on CS3 */ +static const struct pinmux_config emifa_nand_pins[] = { + { pinmux[13], 1, 6 }, + { pinmux[13], 1, 7 }, + { pinmux[14], 1, 0 }, + { pinmux[14], 1, 1 }, + { pinmux[14], 1, 2 }, + { pinmux[14], 1, 3 }, + { pinmux[14], 1, 4 }, + { pinmux[14], 1, 5 }, + { pinmux[15], 1, 7 }, + { pinmux[16], 1, 0 }, + { pinmux[18], 1, 1 }, + { pinmux[18], 1, 4 }, + { pinmux[18], 1, 5 }, +}; + +/* EMAC PHY interface pins */ +static const struct pinmux_config emac_pins[] = { + { pinmux[9], 0, 5 }, + { pinmux[10], 2, 1 }, + { pinmux[10], 2, 2 }, + { pinmux[10], 2, 3 }, + { pinmux[10], 2, 4 }, + { pinmux[10], 2, 5 }, + { pinmux[10], 2, 6 }, + { pinmux[10], 2, 7 }, + { pinmux[11], 2, 0 }, + { pinmux[11], 2, 1 }, +}; + +/* UART pin muxer settings */ +static const struct pinmux_config uart_pins[] = { + { pinmux[8], 2, 7 }, + { pinmux[9], 2, 0 } +}; + +/* I2C pin muxer settings */ +static const struct pinmux_config i2c_pins[] = { + { pinmux[8], 2, 3 }, + { pinmux[8], 2, 4 } +}; + +/* USB0_DRVVBUS pin muxer settings */ +static const struct pinmux_config usb_pins[] = { + { pinmux[9], 1, 1 } +}; + +static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_SPI_FLASH + PINMUX_ITEM(spi0_pins), +#endif + PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), +#ifdef CONFIG_USB_DA8XX + PINMUX_ITEM(usb_pins), +#endif +#ifdef CONFIG_USE_NAND + PINMUX_ITEM(emifa_nand_pins), +#endif +#if defined(CONFIG_DRIVER_TI_EMAC) + PINMUX_ITEM(emac_pins), +#endif +}; + +static const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_SPI0 }, /* Serial Flash */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + +#ifdef CONFIG_NAND_DAVINCI + /* EMIFA 100MHz clock select */ + writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2, + &davinci_syscfg_regs->cfgchip3); + /* NAND CS setup */ + writel((DAVINCI_ABCR_WSETUP(0) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(0) | + DAVINCI_ABCR_RSETUP(0) | + DAVINCI_ABCR_RSTROBE(2) | + DAVINCI_ABCR_RHOLD(0) | + DAVINCI_ABCR_TA(2) | + DAVINCI_ABCR_ASIZE_8BIT), + &davinci_emif_regs->ab2cr); +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart2_ctrl_regs->pwremu_mgmt); + + return(0); +} + +#if defined(CONFIG_DRIVER_TI_EMAC) + +#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */ + +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + u_int8_t mac_addr[6]; + u_int8_t switch_start_cmd[2] = { 0x01, 0x23 }; + + /* Read Ethernet MAC address from EEPROM */ + if (dvevm_read_mac_address(mac_addr)) + /* set address env if not already set */ + dv_configure_mac_address(mac_addr); + + /* read the address back from env */ + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) + return -1; + + /* provide the resulting addr to the driver */ + davinci_eth_set_mac_addr(mac_addr); + + /* enable the Ethernet switch in the 3 port PHY */ + if (i2c_write(PHY_SW_I2C_ADDR, 0, 0, + switch_start_cmd, sizeof(switch_start_cmd))) { + printf("Ethernet switch start failed!\n"); + return -1; + } + + /* finally, initialise the driver */ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ -- cgit v1.1 From 89b765c7f6ddfde07ba673dd4adbeb5da391a81b Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Thu, 10 Jun 2010 15:18:15 +0530 Subject: TI: DaVinci: Add board specific code for da850 EVM Provides initial support for TI OMAP-L138/DA850 SoC devices on a Logic PD EVM board. Provides: Initial boot and configuration. Support for i2c. UART support (console). Signed-off-by: Sudhakar Rajashekhara Acked-by: Ben Gardiner Reviewed-by: Wolfgang Denk Signed-off-by: Sandeep Paulraj --- board/davinci/da8xxevm/Makefile | 1 + board/davinci/da8xxevm/da850evm.c | 111 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) create mode 100644 board/davinci/da8xxevm/da850evm.c (limited to 'board') diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile index 56047dc..17cbe86 100644 --- a/board/davinci/da8xxevm/Makefile +++ b/board/davinci/da8xxevm/Makefile @@ -29,6 +29,7 @@ LIB = $(obj)lib$(BOARD).a COBJS-y += common.o COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o +COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o COBJS := $(COBJS-y) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c new file mode 100644 index 0000000..959b2c6 --- /dev/null +++ b/board/davinci/da8xxevm/da850evm.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include "../common/misc.h" +#include "common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define pinmux (&davinci_syscfg_regs->pinmux) + +/* SPI0 pin muxer settings */ +static const struct pinmux_config spi1_pins[] = { + { pinmux[5], 1, 1 }, + { pinmux[5], 1, 2 }, + { pinmux[5], 1, 4 }, + { pinmux[5], 1, 5 } +}; + +/* UART pin muxer settings */ +static const struct pinmux_config uart_pins[] = { + { pinmux[0], 4, 6 }, + { pinmux[0], 4, 7 }, + { pinmux[4], 2, 4 }, + { pinmux[4], 2, 5 } +}; + +/* I2C pin muxer settings */ +static const struct pinmux_config i2c_pins[] = { + { pinmux[4], 2, 2 }, + { pinmux[4], 2, 3 } +}; + +static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_SPI_FLASH + PINMUX_ITEM(spi1_pins), +#endif + PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), +}; + +static const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart2_ctrl_regs->pwremu_mgmt); + + return 0; +} -- cgit v1.1 From c474a8ebb880e564df0c701c6a8cf73b7779b1d2 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Mon, 31 May 2010 22:02:42 +0900 Subject: s5pc1xx: Add support for Samsung Goni board This patch adds support for the Samsung Goni board (S5PC110 SoC) Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park --- board/samsung/goni/Makefile | 54 ++++ board/samsung/goni/config.mk | 16 + board/samsung/goni/goni.c | 55 ++++ board/samsung/goni/lowlevel_init.S | 585 +++++++++++++++++++++++++++++++++++++ board/samsung/goni/mem_setup.S | 265 +++++++++++++++++ board/samsung/goni/onenand.c | 36 +++ 6 files changed, 1011 insertions(+) create mode 100644 board/samsung/goni/Makefile create mode 100644 board/samsung/goni/config.mk create mode 100644 board/samsung/goni/goni.c create mode 100644 board/samsung/goni/lowlevel_init.S create mode 100644 board/samsung/goni/mem_setup.S create mode 100644 board/samsung/goni/onenand.c (limited to 'board') diff --git a/board/samsung/goni/Makefile b/board/samsung/goni/Makefile new file mode 100644 index 0000000..9b4c886 --- /dev/null +++ b/board/samsung/goni/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := goni.o onenand.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(SOBJS) $(OBJS) + $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/goni/config.mk b/board/samsung/goni/config.mk new file mode 100644 index 0000000..2da9ca1 --- /dev/null +++ b/board/samsung/goni/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2008 # Samsung Elecgtronics +# Kyungmin Park +# + +# On S5PC100 we use the 128 MiB OneDRAM bank at +# +# 0x30000000 to 0x35000000 (80MiB) +# 0x38000000 to 0x40000000 (128MiB) +# +# On S5PC110 we use the 128 MiB OneDRAM bank at +# +# 0x30000000 to 0x35000000 (80MiB) +# 0x40000000 to 0x50000000 (256MiB) +# +TEXT_BASE = 0x34800000 diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c new file mode 100644 index 0000000..e512c59 --- /dev/null +++ b/board/samsung/goni/goni.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2008-2009 Samsung Electronics + * Minkyu Kang + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_GONI; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board:\tGoni\n"); + return 0; +} +#endif diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S new file mode 100644 index 0000000..4b72992 --- /dev/null +++ b/board/samsung/goni/lowlevel_init.S @@ -0,0 +1,585 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * Register usages: + * + * r5 has zero always + * r7 has S5PC100 GPIO base, 0xE0300000 + * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively + * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on + */ + +_TEXT_BASE: + .word TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + mov r11, lr + + /* r5 has always zero */ + mov r5, #0 + + ldr r7, =S5PC100_GPIO_BASE + ldr r8, =S5PC100_GPIO_BASE + /* Read CPU ID */ + ldr r2, =S5PC1XX_PRO_ID + ldr r0, [r2] + mov r1, #0x00010000 + and r0, r0, r1 + cmp r0, r5 + beq 100f + ldr r8, =S5PC110_GPIO_BASE +100: + /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */ + cmp r7, r8 + beq skip_check_didle @ Support C110 only + + ldr r0, =S5PC110_RST_STAT + ldr r1, [r0] + and r1, r1, #0x000D0000 + cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP + beq didle_wakeup + cmp r7, r8 + +skip_check_didle: + addeq r0, r8, #0x280 @ S5PC100_GPIO_J4 + addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4 + ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET + bic r1, r1, #(0xf << 4) @ 1 * 4-bit + orr r1, r1, #(0x1 << 4) + str r1, [r0, #0x0] @ GPIO_CON_OFFSET + + ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET +#ifdef CONFIG_ONENAND_IPL + orr r1, r1, #(1 << 1) @ 1 * 1-bit +#else + bic r1, r1, #(1 << 1) +#endif + str r1, [r0, #0x4] @ GPIO_DAT_OFFSET + + /* Don't setup at s5pc100 */ + beq 100f + + /* + * Initialize Async Register Setting for EVT1 + * Because we are setting EVT1 as the default value of EVT0, + * setting EVT0 as well does not make things worse. + * Thus, for the simplicity, we set for EVT0, too + * + * The "Async Registers" are: + * 0xE0F0_0000 + * 0xE1F0_0000 + * 0xF180_0000 + * 0xF190_0000 + * 0xF1A0_0000 + * 0xF1B0_0000 + * 0xF1C0_0000 + * 0xF1D0_0000 + * 0xF1E0_0000 + * 0xF1F0_0000 + * 0xFAF0_0000 + */ + ldr r0, =0xe0f00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xe1f00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1800000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1900000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1a00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1b00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1c00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1d00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1e00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1f00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xfaf00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + /* + * Diable ABB block to reduce sleep current at low temperature + * Note that it's hidden register setup don't modify it + */ + ldr r0, =0xE010C300 + ldr r1, =0x00800000 + str r1, [r0] + +100: + /* IO retension release */ + ldreq r0, =S5PC100_OTHERS @ 0xE0108200 + ldrne r0, =S5PC110_OTHERS @ 0xE010E000 + ldr r1, [r0] + ldreq r2, =(1 << 31) @ IO_RET_REL + ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) + orr r1, r1, r2 + /* Do not release retention here for S5PC110 */ + streq r1, [r0] + +#ifndef CONFIG_ONENAND_IPL + /* Disable Watchdog */ + ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000 + ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000 + str r5, [r0] + + /* setting SRAM */ + ldreq r0, =S5PC100_SROMC_BASE + ldrne r0, =S5PC110_SROMC_BASE + ldr r1, =0x9 + str r1, [r0] +#endif + + /* S5PC100 has 3 groups of interrupt sources */ + ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000 + ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000 + add r1, r0, #0x00100000 + add r2, r0, #0x00200000 + + /* Disable all interrupts (VIC0, VIC1 and VIC2) */ + mvn r3, #0x0 + str r3, [r0, #0x14] @ INTENCLEAR + str r3, [r1, #0x14] @ INTENCLEAR + str r3, [r2, #0x14] @ INTENCLEAR + +#ifndef CONFIG_ONENAND_IPL + /* Set all interrupts as IRQ */ + str r5, [r0, #0xc] @ INTSELECT + str r5, [r1, #0xc] @ INTSELECT + str r5, [r2, #0xc] @ INTSELECT + + /* Pending Interrupt Clear */ + str r5, [r0, #0xf00] @ INTADDRESS + str r5, [r1, #0xf00] @ INTADDRESS + str r5, [r2, #0xf00] @ INTADDRESS +#endif + +#ifndef CONFIG_ONENAND_IPL + /* for UART */ + bl uart_asm_init + + bl internal_ram_init +#endif + +#ifdef CONFIG_ONENAND_IPL + /* init system clock */ + bl system_clock_init + + /* OneNAND Sync Read Support at S5PC110 only + * RM[15] : Sync Read + * BRWL[14:12] : 7 CLK + * BL[11:9] : Continuous + * VHF[3] : Very High Frequency Enable (Over 83MHz) + * HF[2] : High Frequency Enable (Over 66MHz) + * WM[1] : Sync Write + */ + cmp r7, r8 + ldrne r1, =0xE006 + ldrne r0, =0xB001E442 + strneh r1, [r0] + + /* + * GCE[26] : Gated Clock Enable + * RPE[17] : Enables Read Prefetch + */ + ldrne r1, =((1 << 26) | (1 << 17) | 0xE006) + ldrne r0, =0xB0600000 + strne r1, [r0, #0x100] @ ONENAND_IF_CTRL + ldrne r1, =0x1212 + strne r1, [r0, #0x108] + + /* Board detection to set proper memory configuration */ + cmp r7, r8 + moveq r9, #1 /* r9 has 1Gib default at s5pc100 */ + movne r9, #2 /* r9 has 2Gib default at s5pc110 */ + + ldr r2, =0xE0200200 + ldr r4, [r2, #0x48] + + bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */ + bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */ + bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */ + str r1, [r2, #0x48] + /* For write completion */ + nop + nop + + ldr r3, [r2, #0x44] + and r1, r3, #(0x7 << 2) + mov r1, r1, lsr #2 + cmp r1, #0x5 + moveq r9, #3 + cmp r1, #0x6 + moveq r9, #1 + cmp r1, #0x7 + moveq r9, #2 + and r0, r3, #(0x1 << 1) + mov r0, r0, lsr #1 + orr r1, r1, r0, lsl #3 + cmp r1, #0x8 + moveq r9, #3 + and r1, r3, #(0x7 << 2) + mov r1, r1, lsr #2 + and r0, r3, #(0x1 << 7) + mov r0, r0, lsr #7 + orr r1, r1, r0, lsl #3 + cmp r1, #0x9 + moveq r9, #3 + str r4, [r2, #0x48] /* Restore PULLUP configuration */ + + bl mem_ctrl_asm_init + + /* Wakeup support. Don't know if it's going to be used, untested. */ + ldreq r0, =S5PC100_RST_STAT + ldrne r0, =S5PC110_RST_STAT + ldr r1, [r0] + biceq r1, r1, #0xfffffff7 + moveq r2, #(1 << 3) + bicne r1, r1, #0xfffeffff + movne r2, #(1 << 16) + cmp r1, r2 + bne 1f +wakeup: + /* turn off L2 cache */ + bl l2_cache_disable + + cmp r7, r8 + ldreq r0, =0xC100 + ldrne r0, =0xC110 + + /* invalidate L2 cache also */ + bl invalidate_dcache + + /* turn on L2 cache */ + bl l2_cache_enable + + cmp r7, r8 + /* Load return address and jump to kernel */ + ldreq r0, =S5PC100_INFORM0 + ldrne r0, =S5PC110_INFORM0 + + /* r1 = physical address of s5pc1xx_cpu_resume function */ + ldr r1, [r0] + + /* Jump to kernel (sleep-s5pc1xx.S) */ + mov pc, r1 + nop + nop +#else + cmp r7, r8 + /* Clear wakeup status register */ + ldreq r0, =S5PC100_WAKEUP_STAT + ldrne r0, =S5PC110_WAKEUP_STAT + ldr r1, [r0] + str r1, [r0] + + /* IO retension release */ + ldreq r0, =S5PC100_OTHERS @ 0xE0108200 + ldrne r0, =S5PC110_OTHERS @ 0xE010E000 + ldr r1, [r0] + ldreq r2, =(1 << 31) @ IO_RET_REL + ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) + orr r1, r1, r2 + str r1, [r0] + +#endif + b 1f + +didle_wakeup: + /* Wait when APLL is locked */ + ldr r0, =0xE0100100 @ S5PC110_APLL_CON +lockloop: + ldr r1, [r0] + and r1, r1, #(1 << 29) + cmp r1, #(1 << 29) + bne lockloop + + ldr r0, =S5PC110_INFORM0 + ldr r1, [r0] + mov pc, r1 + nop + nop + nop + nop + nop + +1: + mov lr, r11 + mov pc, lr + +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f +100: + /* Set Lock Time */ + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r0, #0x000] @ S5PC100_APLL_LOCK + str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK + str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK + str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK + + /* S5P_APLL_CON */ + ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz) + str r1, [r0, #0x100] + /* S5P_MPLL_CON */ + ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) + str r1, [r0, #0x104] + /* S5P_EPLL_CON */ + ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) + str r1, [r0, #0x108] + /* S5P_HPLL_CON */ + ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 + str r1, [r0, #0x10C] + + ldr r1, [r0, #0x300] + ldr r2, =0x00003fff + bic r1, r1, r2 + ldr r2, =0x00011301 + + orr r1, r1, r2 + str r1, [r0, #0x300] + ldr r1, [r0, #0x304] + ldr r2, =0x00011110 + orr r1, r1, r2 + str r1, [r0, #0x304] + ldr r1, =0x00000001 + str r1, [r0, #0x308] + + /* Set Source Clock */ + ldr r1, =0x00001111 @ A, M, E, HPLL Muxing + str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 + + b 200f +110: + ldr r0, =0xE010C000 @ S5PC110_PWR_CFG + + /* Set OSC_FREQ value */ + ldr r1, =0xf + str r1, [r0, #0x100] @ S5PC110_OSC_FREQ + + /* Set MTC_STABLE value */ + ldr r1, =0xffffffff + str r1, [r0, #0x110] @ S5PC110_MTC_STABLE + + /* Set CLAMP_STABLE value */ + ldr r1, =0x3ff03ff + str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE + + ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + + /* Set Clock divider */ + ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 + str r1, [r0, #0x300] + ldr r1, =0x11110111 @ UART[3210]: MMC[3210] + str r1, [r0, #0x310] + + /* Set Lock Time */ + ldr r1, =0x2cf @ Locktime : 30us + str r1, [r0, #0x000] @ S5PC110_APLL_LOCK + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK + str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK + str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK + + /* S5PC110_APLL_CON */ + ldr r1, =0x80C80601 @ 800MHz + str r1, [r0, #0x100] + /* S5PC110_MPLL_CON */ + ldr r1, =0x829B0C01 @ 667MHz + str r1, [r0, #0x108] + /* S5PC110_EPLL_CON */ + ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2 + str r1, [r0, #0x110] + /* S5PC110_VPLL_CON */ + ldr r1, =0x806C0603 @ 54MHz + str r1, [r0, #0x120] + + /* Set Source Clock */ + ldr r1, =0x10001111 @ A, M, E, VPLL Muxing + str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 + + /* OneDRAM(DMC0) clock setting */ + ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL + str r1, [r0, #0x218] @ S5PC110_CLK_SRC6 + ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1 + str r1, [r0, #0x318] @ S5PC110_CLK_DIV6 + + /* XCLKOUT = XUSBXTI 24MHz */ + add r2, r0, #0xE000 @ S5PC110_OTHERS + ldr r1, [r2] + orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI + str r1, [r2] + + /* CLK_IP0 */ + ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5] + str r1, [r0, #0x460] @ S5PC110_CLK_IP0 + + /* CLK_IP1 */ + ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16] + @ NANDXL[24] + str r1, [r0, #0x464] @ S5PC110_CLK_IP1 + + /* CLK_IP2 */ + ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9] + @ HOSTIF[10] HSMMC0[16] + @ HSMMC2[18] VIC[27:24] + str r1, [r0, #0x468] @ S5PC110_CLK_IP2 + + /* CLK_IP3 */ + ldr r1, =0x8eff038c @ I2C[8:6] + @ SYSTIMER[16] UART0[17] + @ UART1[18] UART2[19] + @ UART3[20] WDT[22] + @ PWM[23] GPIO[26] SYSCON[27] + str r1, [r0, #0x46c] @ S5PC110_CLK_IP3 + + /* CLK_IP4 */ + ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5] + str r1, [r0, #0x470] @ S5PC110_CLK_IP3 + +200: + /* wait at least 200us to stablize all clock */ + mov r2, #0x10000 +1: subs r2, r2, #1 + bne 1b + + mov pc, lr + +#ifndef CONFIG_ONENAND_IPL +internal_ram_init: + ldreq r0, =0xE3800000 + ldrne r0, =0xF1500000 + ldr r1, =0x0 + str r1, [r0] + + mov pc, lr +#endif + +#ifndef CONFIG_ONENAND_IPL +/* + * uart_asm_init: Initialize UART's pins + */ +uart_asm_init: + /* set GPIO to enable UART0-UART4 */ + mov r0, r8 + ldr r1, =0x22222222 + str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET + ldr r1, =0x00002222 + str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f + + /* UART_SEL GPK0[5] at S5PC100 */ + add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET + ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit + orr r1, r1, #(0x1 << 20) @ Output + str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit + orr r1, r1, #(0x2 << 10) @ Pull-up enabled + str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit + str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET + + b 200f +110: + /* + * Note that the following address + * 0xE020'0360 is reserved address at S5PC100 + */ + /* UART_SEL MP0_5[7] at S5PC110 */ + add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET + ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit + orr r1, r1, #(0x1 << 28) @ Output + str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit + orr r1, r1, #(0x2 << 14) @ Pull-up enabled + str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit + str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET +200: + mov pc, lr +#endif diff --git a/board/samsung/goni/mem_setup.S b/board/samsung/goni/mem_setup.S new file mode 100644 index 0000000..c4d2845 --- /dev/null +++ b/board/samsung/goni/mem_setup.S @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2009 Samsung Electrnoics + * Minkyu Kang + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + .globl mem_ctrl_asm_init +mem_ctrl_asm_init: + cmp r7, r8 + + ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000 + ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000 + ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000 + + /* DLL parameter setting */ + ldr r1, =0x50101000 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + ldr r1, =0x000000f4 + str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET + strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET + ldreq r1, =0x0 + streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET + + /* DLL on */ + ldr r1, =0x50101002 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* DLL start */ + ldr r1, =0x50101003 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + mov r2, #0x4000 +wait: subs r2, r2, #0x1 + cmp r2, #0x0 + bne wait + + cmp r7, r8 + /* Force value locking for DLL off */ + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* DLL off */ + ldr r1, =0x50101009 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* auto refresh off */ + ldr r1, =0xff001010 | (1 << 7) + ldr r2, =0xff001010 | (1 << 7) + str r1, [r0, #0x000] @ CONCONTROL_OFFSET + strne r2, [r6, #0x000] @ CONCONTROL_OFFSET + + /* + * Burst Length 4, 2 chips, 32-bit, LPDDR + * OFF: dynamic self refresh, force precharge, dynamic power down off + */ + ldr r1, =0x00212100 + ldr r2, =0x00212100 + str r1, [r0, #0x004] @ MEMCONTROL_OFFSET + strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET + + /* + * Note: + * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only) + * So finally Bank1 OneDRAM should address start at at 0x3000'0000 + */ + + /* + * DMC0: CS0 : S5PC100/S5PC110 + * 0x30 -> 0x30000000 + * 0xf8 -> 0x37FFFFFF + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits + * [ 7:4 ] 2: 14 bits + * [ 3:0 ] 2: 4 banks + */ + ldr r3, =0x30f80222 + ldr r4, =0x40f00222 +swap_memory: + str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET + str r4, [r0, #0x00C] @ dummy write + + /* + * DMC1: CS0 : S5PC110 + * 0x40 -> 0x40000000 + * 0xf8 -> 0x47FFFFFF (1Gib) + * 0x40 -> 0x40000000 + * 0xf0 -> 0x4FFFFFFF (2Gib) + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits - Col (1Gib) + * [11:8 ] 3: 10 bits - Col (2Gib) + * [ 7:4 ] 2: 14 bits - Row + * [ 3:0 ] 2: 4 banks + */ + /* Default : 2GiB */ + ldr r4, =0x40f01322 @ 2Gib: MCP B + ldr r5, =0x50f81312 @ dummy: MCP D + cmp r9, #1 + ldreq r4, =0x40f81222 @ 1Gib: MCP A + cmp r9, #3 + ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D + cmp r9, #4 + ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E + + cmp r7, r8 + strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET + strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET + + /* + * DMC0: CS1: S5PC100 + * 0x38 -> 0x38000000 + * 0xf8 -> 0x3fFFFFFF + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits + * [ 7:4 ] 2: 14 bits + * [ 3:0 ] 2: 4 banks + */ + eoreq r3, r3, #0x08000000 + streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET + + ldr r1, =0x20000000 + str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET + strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET + strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET + + /* + * S5PC100: + * DMC: CS0: 166MHz + * CS1: 166MHz + * S5PC110: + * DMC0: CS0: 166MHz + * DMC1: CS0: 200MHz + * + * 7.8us * 200MHz %LE %LONG1560(0x618) + * 7.8us * 166MHz %LE %LONG1294(0x50E) + * 7.8us * 133MHz %LE %LONG1038(0x40E), + * 7.8us * 100MHz %LE %LONG780(0x30C), + */ + ldr r1, =0x0000050E + str r1, [r0, #0x030] @ TIMINGAREF_OFFSET + ldrne r1, =0x00000618 + strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET + + ldr r1, =0x14233287 + str r1, [r0, #0x034] @ TIMINGROW_OFFSET + ldrne r1, =0x182332c8 + strne r1, [r6, #0x034] @ TIMINGROW_OFFSET + + ldr r1, =0x12130005 + str r1, [r0, #0x038] @ TIMINGDATA_OFFSET + ldrne r1, =0x13130005 + strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET + + ldr r1, =0x0E140222 + str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET + ldrne r1, =0x0E180222 + strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET + + /* chip0 Deselect */ + ldr r1, =0x07000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 PALL */ + ldr r1, =0x01000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 REFA */ + ldr r1, =0x05000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + /* chip0 REFA */ + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 MRS */ + ldr r1, =0x00000032 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 EMRS */ + ldr r1, =0x00020020 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 Deselect */ + ldr r1, =0x07100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 PALL */ + ldr r1, =0x01100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 REFA */ + ldr r1, =0x05100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + /* chip1 REFA */ + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 MRS */ + ldr r1, =0x00100032 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 EMRS */ + ldr r1, =0x00120020 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* auto refresh on */ + ldr r1, =0xFF002030 | (1 << 7) + str r1, [r0, #0x000] @ CONCONTROL_OFFSET + strne r1, [r6, #0x000] @ CONCONTROL_OFFSET + + /* PwrdnConfig */ + ldr r1, =0x00100002 + str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET + strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET + + ldr r1, =0x00212113 + str r1, [r0, #0x004] @ MEMCONTROL_OFFSET + strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET + + /* Skip when S5PC110 */ + bne 1f + + /* Check OneDRAM access area at s5pc100 */ + ldreq r3, =0x38f80222 + ldreq r1, =0x37ffff00 + str r3, [r1] + ldr r2, [r1] + cmp r2, r3 + beq swap_memory +1: + mov pc, lr + + .ltorg diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c new file mode 100644 index 0000000..8d3769b --- /dev/null +++ b/board/samsung/goni/onenand.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008-2009 Samsung Electronics + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void onenand_board_init(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; +} -- cgit v1.1 From 376e7fadbad3285231e390c6534feb5af86d594b Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Tue, 8 Jun 2010 14:40:47 +0900 Subject: SAMSUNG: goni: add the GPL licence Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park Acked-by: Tom --- board/samsung/goni/config.mk | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/samsung/goni/config.mk b/board/samsung/goni/config.mk index 2da9ca1..0e9dd45 100644 --- a/board/samsung/goni/config.mk +++ b/board/samsung/goni/config.mk @@ -1,7 +1,25 @@ # -# Copyright (C) 2008 # Samsung Elecgtronics +# Copyright (C) 2010 Samsung Electronics # Kyungmin Park # +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# # On S5PC100 we use the 128 MiB OneDRAM bank at # -- cgit v1.1 From ce9c227cc71afc3b4c78dcc0a565c40d4ad943e4 Mon Sep 17 00:00:00 2001 From: Albert Aribaud <[albert.aribaud@free.fr]> Date: Thu, 17 Jun 2010 19:38:21 +0530 Subject: Add support for the LaCie ED Mini V2 board This patch adds support for the LaCie ED Mini V2 product which is based on the Marvell Orion5x SoC. Signed-off-by: Albert Aribaud --- board/LaCie/edminiv2/Makefile | 53 ++++++++++++++++++++++++ board/LaCie/edminiv2/config.mk | 27 ++++++++++++ board/LaCie/edminiv2/edminiv2.c | 92 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c (limited to 'board') diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile new file mode 100644 index 0000000..df542dc --- /dev/null +++ b/board/LaCie/edminiv2/Makefile @@ -0,0 +1,53 @@ +# +# Copyright (C) 2010 Albert ARIBAUD +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := edminiv2.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk new file mode 100644 index 0000000..3dec1aa --- /dev/null +++ b/board/LaCie/edminiv2/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2010 Albert ARIBAUD +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00100000 diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c new file mode 100644 index 0000000..54c0ffe --- /dev/null +++ b/board/LaCie/edminiv2/edminiv2.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2010 Albert ARIBAUD + * + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH + * which CFI does not properly detect, hence the LEGACY config. + */ +#if defined(CONFIG_FLASH_CFI_LEGACY) +#include +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; + int sect; + + if (base != CONFIG_SYS_FLASH_BASE) + return 0; + + info->size = 0; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + /* set each sector's start address and size based */ + for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { + info->start[sect] = base+info->size; + info->size += sectsz[sect]; + } + /* This flash must be accessed in 8-bits mode, no buffer. */ + info->flash_id = 0x01000000; + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->buffer_size = 0; + /* timings are derived from the Macronix datasheet. */ + info->erase_blk_tout = 1000; + info->write_tout = 10; + info->buffer_write_tout = 300; + /* Commands and addresses are for AMD mode 8-bit access. */ + info->vendor = CFI_CMDSET_AMD_LEGACY; + info->cmd_reset = 0xF0; + info->interface = FLASH_CFI_X8; + info->legacy_unlock = 0; + info->ext_addr = 0; + info->addr_unlock1 = 0x00000aaa; + info->addr_unlock2 = 0x00000555; + /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */ + info->manufacturer_id = 0x22; + info->device_id = 0xBA; + info->device_id2 = 0; + info->cfi_version = 0x3133; + info->cfi_offset = 0x0000; + info->name = "MX29LV400CB"; + + return 1; +} +#endif /* CONFIG_SYS_FLASH_CFI */ + +int board_init(void) +{ + /* arch number of board */ + gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; + + /* boot parameter start at 256th byte of RAM base */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} -- cgit v1.1