From 834670eae0ddc3e4a809d05645f12f23ef216a41 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 Dec 2014 16:23:17 -0200 Subject: mx6sxsabresd: Remove unneeded board_late_init() Since commit 1f98e31bc0b2c37a ("imx: mx6sxsabresd: Use the pfuze common init function") board_late_init() became empty, so we can safely remove this unneeded function. Signed-off-by: Fabio Estevam --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5cc58ac..a848f41 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -423,11 +423,6 @@ int board_init(void) return 0; } -int board_late_init(void) -{ - return 0; -} - int checkboard(void) { puts("Board: MX6SX SABRE SDB\n"); -- cgit v1.1 From 5d6050fdb8b0aaf3d3c43b3cad68d6b8f5037f9a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 10 Dec 2014 10:15:23 +0100 Subject: arm: mx6: Add Barco platinum-picon and platinum-titanium This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese Cc: Stefano Babic Cc: Pieter Ronsijn --- board/barco/platinum/Kconfig | 37 +++++ board/barco/platinum/MAINTAINERS | 7 + board/barco/platinum/Makefile | 14 ++ board/barco/platinum/platinum.c | 217 +++++++++++++++++++++++++++ board/barco/platinum/platinum.h | 88 +++++++++++ board/barco/platinum/platinum_picon.c | 244 +++++++++++++++++++++++++++++++ board/barco/platinum/platinum_titanium.c | 209 ++++++++++++++++++++++++++ board/barco/platinum/spl_picon.c | 182 +++++++++++++++++++++++ board/barco/platinum/spl_titanium.c | 185 +++++++++++++++++++++++ 9 files changed, 1183 insertions(+) create mode 100644 board/barco/platinum/Kconfig create mode 100644 board/barco/platinum/MAINTAINERS create mode 100644 board/barco/platinum/Makefile create mode 100644 board/barco/platinum/platinum.c create mode 100644 board/barco/platinum/platinum.h create mode 100644 board/barco/platinum/platinum_picon.c create mode 100644 board/barco/platinum/platinum_titanium.c create mode 100644 board/barco/platinum/spl_picon.c create mode 100644 board/barco/platinum/spl_titanium.c (limited to 'board') diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig new file mode 100644 index 0000000..8bbad24 --- /dev/null +++ b/board/barco/platinum/Kconfig @@ -0,0 +1,37 @@ +if TARGET_PLATINUM_PICON + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_picon" + +endif + +if TARGET_PLATINUM_TITANIUM + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_titanium" + +endif diff --git a/board/barco/platinum/MAINTAINERS b/board/barco/platinum/MAINTAINERS new file mode 100644 index 0000000..a22584b --- /dev/null +++ b/board/barco/platinum/MAINTAINERS @@ -0,0 +1,7 @@ +PLATINUM BOARD +M: Stefan Roese +S: Maintained +F: board/barco/platinum/ +F: include/configs/platinum.h +F: configs/platinum_picon_defconfig +F: configs/platinum_titanium_defconfig diff --git a/board/barco/platinum/Makefile b/board/barco/platinum/Makefile new file mode 100644 index 0000000..abc9419 --- /dev/null +++ b/board/barco/platinum/Makefile @@ -0,0 +1,14 @@ +# +# Copyright (C) 2014, Barco (www.barco.com) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := platinum.o +obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o + +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o +endif diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c new file mode 100644 index 0000000..1485a48 --- /dev/null +++ b/board/barco/platinum/platinum.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC3_BASE_ADDR }, +}; + +void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +int board_ehci_hcd_init(int port) +{ + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { + unsigned sd3_cd = IMX_GPIO_NR(7, 0); + gpio_direction_input(sd3_cd); + return !gpio_get_value(sd3_cd); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +void board_init_gpio(void) +{ + platinum_init_gpio(); +} + +void board_init_gpmi_nand(void) +{ + setup_gpmi_nand(); +} + +void board_init_i2c(void) +{ + platinum_setup_i2c(); +} + +void board_init_spi(void) +{ + platinum_setup_spi(); +} + +void board_init_uart(void) +{ + platinum_setup_uart(); +} + +void board_init_usb(void) +{ + platinum_init_usb(); +} + +void board_init_finished(void) +{ + platinum_init_finished(); +} + +int board_phy_config(struct phy_device *phydev) +{ + return platinum_phy_config(phydev); +} + +int board_eth_init(bd_t *bis) +{ + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + board_init_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + board_init_spi(); + + board_init_i2c(); + + board_init_gpmi_nand(); + + board_init_gpio(); + + board_init_usb(); + + board_init_finished(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_PLATINUM_BOARD "\n"); + return 0; +} + +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; + +int misc_init_r(void) +{ + add_board_boot_modes(board_boot_modes); + + return 0; +} diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h new file mode 100644 index 0000000..8650d6d --- /dev/null +++ b/board/barco/platinum/platinum.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PLATINUM_H_ +#define _PLATINUM_H_ + +#include +#include + +/* Defines */ + +#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) + +/* Prototypes */ + +int platinum_setup_enet(void); +int platinum_setup_i2c(void); +int platinum_setup_spi(void); +int platinum_setup_uart(void); +int platinum_phy_config(struct phy_device *phydev); +int platinum_init_gpio(void); +int platinum_init_usb(void); +int platinum_init_finished(void); + +static inline void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static inline void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +#endif /* _PLATINUM_H_ */ diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c new file mode 100644 index 0000000..b2eab76 --- /dev/null +++ b/board/barco/platinum/platinum_picon.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) +#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) +#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) + +#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) +#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) +#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) + +#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) +#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) +#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) + +#define GPIO_USB_RESET IMX_GPIO_NR(1, 5) + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* PHY nRESET */ +iomux_v3_cfg_t const phy_reset_pad = { + MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c0_mux_pads[] = { + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c2_mux_pads[] = { + MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + unsigned phy_reset = IMX_GPIO_NR(1, 19); + + /* First configure PHY reset GPIO pin */ + imx_iomux_v3_setup_pad(phy_reset_pad); + + /* Reconfigure enet muxing while PHY is in reset */ + gpio_direction_output(phy_reset, 0); + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + mdelay(10); + gpio_set_value(phy_reset, 1); + udelay(100); + + /* set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + return enable_fec_anatop_clock(ENET_50MHZ); +} + +int platinum_setup_i2c(void) +{ + imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, + ARRAY_SIZE(i2c0_mux_pads)); + imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, + ARRAY_SIZE(i2c2_mux_pads)); + + mdelay(10); + + /* Disable i2c mux 0 */ + gpio_direction_output(GPIO_I2C0_SEL0, 0); + gpio_direction_output(GPIO_I2C0_SEL1, 0); + gpio_direction_output(GPIO_I2C0_ENBN, 1); + + /* Disable i2c mux 1 */ + gpio_direction_output(GPIO_I2C2_SEL0, 0); + gpio_direction_output(GPIO_I2C2_SEL1, 0); + gpio_direction_output(GPIO_I2C2_ENBN, 1); + + udelay(10); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + /* Disable all leds */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x55); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* Use generic infrastructure, no specific setup */ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Reset FPGA's */ + gpio_direction_output(GPIO_IP_NCONFIG, 0); + gpio_direction_output(GPIO_HK_NCONFIG, 0); + gpio_direction_output(GPIO_LS_NCONFIG, 0); + udelay(3); + gpio_set_value(GPIO_IP_NCONFIG, 1); + gpio_set_value(GPIO_HK_NCONFIG, 1); + gpio_set_value(GPIO_LS_NCONFIG, 1); + + /* no dmd configuration yet */ + + return 0; +} + +int platinum_init_usb(void) +{ + /* Reset usb hub */ + gpio_direction_output(GPIO_USB_RESET, 0); + udelay(100); + gpio_set_value(GPIO_USB_RESET, 1); + + return 0; +} + +int platinum_init_finished(void) +{ + /* Enable led 0 */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x54); + + return 0; +} diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c new file mode 100644 index 0000000..73a955f --- /dev/null +++ b/board/barco/platinum/platinum_titanium.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + /* non mounted spi nor flash for booting */ + MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + mdelay(10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + udelay(100); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + + return 0; +} + +int platinum_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Default GPIO's */ + /* Toggle CONFIG_n to reset fpga on every boot */ + gpio_direction_output(IMX_GPIO_NR(5, 18), 0); + /* Need delay >=2uS */ + udelay(3); + gpio_set_value(IMX_GPIO_NR(5, 18), 1); + + /* Default pin 1,15 high - DLP_FLASH_WPZ */ + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + + return 0; +} + +int platinum_init_usb(void) +{ + return 0; +} + +int platinum_init_finished(void) +{ + return 0; +} diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c new file mode 100644 index 0000000..f421c21 --- /dev/null +++ b/board/barco/platinum/spl_picon.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41K256M16HA-125 */ +static struct mx6_ddr3_cfg mt41k256m16ha_125 = { + .mem_speed = 1600, + .density = 4, /* 4Gbit */ + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * Values from running the Freescale DDR stress tool via USB + */ +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x0044004E, + .p0_mpwldectrl1 = 0x001F0023, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x02480248, + .p0_mpdgctrl1 = 0x0210021C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x42444444, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36322C32, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c new file mode 100644 index 0000000..26fe26b --- /dev/null +++ b/board/barco/platinum/spl_titanium.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41J128M16JT-125 */ +static struct mx6_ddr3_cfg mt41j128m16jt_125 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* Write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x434b0350, + .p0_mpdgctrl1 = 0x034c0359, + .p1_mpdgctrl0 = 0x434b0350, + .p1_mpdgctrl1 = 0x03650348, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4436383b, + .p1_mprddlctl = 0x39393341, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254a36, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} -- cgit v1.1 From 1565d54a7671a139e225327dd2dc6871c590ac91 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 30 Dec 2014 17:24:03 +0800 Subject: imx:mx6sxsabresd board spl support Add board level spl support for mx6sxsabresd board. Signed-off-by: Peng Fan --- board/freescale/mx6sxsabresd/MAINTAINERS | 1 + board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 ++++++++++++++++++++++++++++ 2 files changed, 169 insertions(+) (limited to 'board') diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS index f52f300..c0f5d9c 100644 --- a/board/freescale/mx6sxsabresd/MAINTAINERS +++ b/board/freescale/mx6sxsabresd/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mx6sxsabresd/ F: include/configs/mx6sxsabresd.h F: configs/mx6sxsabresd_defconfig +F: configs/mx6sxsabresd_spl_defconfig diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index a848f41..a2c9aae 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { +#ifndef CONFIG_SPL_BUILD int i, ret; /* @@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis) } return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + break; + case 3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #ifdef CONFIG_FSL_QSPI @@ -429,3 +471,129 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include + +const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00290025, + .p0_mpwldectrl1 = 0x00220022, + .p0_mpdgctrl0 = 0x41480144, + .p0_mpdgctrl1 = 0x01340130, + .p0_mprddlctl = 0x3C3E4244, + .p0_mpwrdlctl = 0x34363638, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width/32, + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif -- cgit v1.1 From 5ba49e75afa9c9f6a6de478f519dd5c284f260cc Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 22 Jan 2015 10:09:00 +0100 Subject: mx6: fix warning in platinum board Fix warning due to missing prototype for writel Signed-off-by: Stefano Babic Acked-by: Stefan Roese --- board/barco/platinum/platinum.h | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h index 8650d6d..d3ea8bd 100644 --- a/board/barco/platinum/platinum.h +++ b/board/barco/platinum/platinum.h @@ -9,6 +9,7 @@ #include #include +#include /* Defines */ -- cgit v1.1 From f77dd6d7dbe42cee2b03d1b4c8b34ceb15643174 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 19 Jan 2015 17:26:45 +0100 Subject: ot1200: make use of imx_ddr_size(..) To support different ddr3 memory sizes we should start using imx_ddr_size(..) instead of the define PHYS_SDRAM_SIZE. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 93f3d65..039e858 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } -- cgit v1.1 From 84c5dd16a45cc6502bf622ea33543a53102d681f Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 19 Jan 2015 17:26:46 +0100 Subject: ot1200: move ccgr and gpr init to c functions We need this way for SPL boot. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/mx6q_4x_mt41j128.cfg | 14 -------------- board/bachmann/ot1200/ot1200.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 14 deletions(-) (limited to 'board') diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg index bb6c60b..c25f99d 100644 --- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg +++ b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg @@ -142,20 +142,6 @@ DATA 4 0x021b48b8 0x00000800 DATA 4 0x021b001c 0x00000000 DATA 4 0x021b0404 0x00011006 -/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F /* * Setup CCM_CCOSR register as follows: diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 039e858..6b6c1a3 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -119,8 +120,35 @@ static void setup_iomux_features(void) ARRAY_SIZE(feature_pads)); } +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + int board_early_init_f(void) { + ccgr_init(); + gpr_init(); + setup_iomux_uart(); setup_iomux_spi(); setup_iomux_features(); -- cgit v1.1 From e88b83575a94b76a57161d98ec659460cb83ffab Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 19 Jan 2015 17:26:47 +0100 Subject: ot1200: enable spi clock directly in ccgr_init(..) Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/ot1200.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'board') diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 6b6c1a3..e434ed9 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -125,7 +125,7 @@ static void ccgr_init(void) struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); + writel(0x0030FC33, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); writel(0x00FFF300, &ccm->CCGR4); @@ -319,9 +319,6 @@ int board_init(void) leds_on(); - /* enable ecspi3 clocks */ - enable_cspi_clock(1, 2); - #ifdef CONFIG_CMD_SATA setup_sata(); #endif -- cgit v1.1 From 532491712610ef903e5f53b1da799fc0011829e0 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 19 Jan 2015 17:26:49 +0100 Subject: ot1200: add basic SPL support Currently we only support the Micron MT41K128M16JT-125 ddr3 chip. Signed-off-by: Christian Gmeiner --- board/bachmann/ot1200/Makefile | 4 + board/bachmann/ot1200/ot1200_spl.c | 162 +++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 board/bachmann/ot1200/ot1200_spl.c (limited to 'board') diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile index 1bd42e8..9e50bfe 100644 --- a/board/bachmann/ot1200/Makefile +++ b/board/bachmann/ot1200/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y := ot1200.o ot1200_spl.o +else obj-y := ot1200.o +endif diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c new file mode 100644 index 0000000..9c77fd3 --- /dev/null +++ b/board/bachmann/ot1200/ot1200_spl.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2015, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */ + .dram_sdclk_0 = 0x00000028, + .dram_sdclk_1 = 0x00000028, + .dram_cas = 0x00000028, + .dram_ras = 0x00000028, + .dram_reset = 0x00000028, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 48 ohm */ + .dram_sdodt0 = 0x00000028, + .dram_sdodt1 = 0x00000028, + /* SDQS[0:7]: Differential input, 48 ohm */ + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_sdqs4 = 0x00000028, + .dram_sdqs5 = 0x00000028, + .dram_sdqs6 = 0x00000028, + .dram_sdqs7 = 0x00000028, + /* DQM[0:7]: Differential input, 48 ohm */ + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_dqm4 = 0x00000028, + .dram_dqm5 = 0x00000028, + .dram_dqm6 = 0x00000028, + .dram_dqm7 = 0x00000028, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* Disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 48 ohm */ + .grp_addds = 0x00000028, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */ + .grp_ctlds = 0x00000028, + /* DATA[00:63]: Differential input, 48 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_b4ds = 0x00000028, + .grp_b5ds = 0x00000028, + .grp_b6ds = 0x00000028, + .grp_b7ds = 0x00000028, +}; + +static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { + /* Width of data bus: 0=16, 1=32, 2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* Single chip select */ + .ncs = 1, + .cs1_mirror = 0, /* war 0 */ + .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg micron_2gib_1600 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, +}; + +static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00260025, + .p0_mpwldectrl1 = 0x00270021, + .p1_mpwldectrl0 = 0x00180034, + .p1_mpwldectrl1 = 0x00180024, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x04380344, + .p0_mpdgctrl1 = 0x0330032C, + .p1_mpdgctrl0 = 0x0338033C, + .p1_mpdgctrl1 = 0x032C0300, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C2E3238, + .p1_mprddlctl = 0x3A2E303C, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36384036, + .p1_mpwrdlctl = 0x442E4438, +}; + +static void ot1200_spl_dram_init(void) +{ + mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs); + mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib, + µn_2gib_1600); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* configure MMDC for SDRAM width/size and per-model calibration */ + ot1200_spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} -- cgit v1.1 From cc67f4a63ff3c6ed0b8fab35ce4af6e683296e47 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:42 +0200 Subject: arm: mx6: cm-fx6: change dtb node for ethaddr When passing eth address to Linux via dtb, the "local-mac-address" property should be set for "/soc/aips-bus@02100000/ethernet@02188000", not "/fec". Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 84e3643..5ddf8c6 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -464,8 +464,9 @@ int ft_board_setup(void *blob, bd_t *bd) /* MAC addr */ if (eth_getenv_enetaddr("ethaddr", enetaddr)) { - fdt_find_and_setprop(blob, "/fec", "local-mac-address", - enetaddr, 6, 1); + fdt_find_and_setprop(blob, + "/soc/aips-bus@02100000/ethernet@02188000", + "local-mac-address", enetaddr, 6, 1); } return 0; -- cgit v1.1 From e7a2447ba2d8483b7d029e77c59b0ee26eeabe88 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:43 +0200 Subject: compulab: eeprom: allow reading mac address from multiple eeproms Implement the option to select the eeprom i2c bus when reading mac address. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Cc: Ilya Ledvich Cc: Dmitry Lifshitz Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 2 +- board/compulab/cm_t335/cm_t335.c | 2 +- board/compulab/cm_t35/cm_t35.c | 2 +- board/compulab/cm_t3517/cm_t3517.c | 2 +- board/compulab/cm_t54/cm_t54.c | 2 +- board/compulab/common/eeprom.c | 20 +++++++++++++------- board/compulab/common/eeprom.h | 4 ++-- 7 files changed, 20 insertions(+), 14 deletions(-) (limited to 'board') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 5ddf8c6..32f4434 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -354,7 +354,7 @@ static int handle_mac_address(void) if (rc) return 0; - rc = cl_eeprom_read_mac_addr(enetaddr); + rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (rc) return rc; diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 9583149..592ef3d 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -110,7 +110,7 @@ static int handle_mac_address(void) if (rv) return 0; - rv = cl_eeprom_read_mac_addr(enetaddr); + rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (rv) get_efuse_mac_addr(enetaddr); diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 43463d5..9a3b2ee 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -429,7 +429,7 @@ static int handle_mac_address(void) if (rc) return 0; - rc = cl_eeprom_read_mac_addr(enetaddr); + rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (rc) return rc; diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c index cac1ad9..624cf4c 100644 --- a/board/compulab/cm_t3517/cm_t3517.c +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -163,7 +163,7 @@ static int cm_t3517_handle_mac_address(void) if (ret) return 0; - ret = cl_eeprom_read_mac_addr(enetaddr); + ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (ret) { ret = am3517_get_efuse_enetaddr(enetaddr); if (ret) diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 2c2530a..fdea909 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -165,7 +165,7 @@ static int handle_mac_address(void) if (ret) return 0; - ret = cl_eeprom_read_mac_addr(enetaddr); + ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (ret || !is_valid_ether_addr(enetaddr)) generate_mac_addr(enetaddr); diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index a45e7be..77bcea4 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -31,6 +31,7 @@ #define LAYOUT_INVALID 0 #define LAYOUT_LEGACY 0xff +static int cl_eeprom_bus; static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ static int cl_eeprom_read(uint offset, uchar *buf, int len) @@ -38,7 +39,7 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len) int res; unsigned int current_i2c_bus = i2c_get_bus_num(); - res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); + res = i2c_set_bus_num(cl_eeprom_bus); if (res < 0) return res; @@ -50,13 +51,18 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len) return res; } -static int cl_eeprom_setup_layout(void) +static int cl_eeprom_setup(uint eeprom_bus) { int res; - if (cl_eeprom_layout != LAYOUT_INVALID) + /* + * We know the setup was already done when the layout is set to a valid + * value and we're using the same bus as before. + */ + if (cl_eeprom_layout != LAYOUT_INVALID && eeprom_bus == cl_eeprom_bus) return 0; + cl_eeprom_bus = eeprom_bus; res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, (uchar *)&cl_eeprom_layout, 1); if (res) { @@ -77,7 +83,7 @@ void get_board_serial(struct tag_serialnr *serialnr) memset(serialnr, 0, sizeof(*serialnr)); - if (cl_eeprom_setup_layout()) + if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS)) return; offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? @@ -96,11 +102,11 @@ void get_board_serial(struct tag_serialnr *serialnr) * Routine: cl_eeprom_read_mac_addr * Description: read mac address and store it in buf. */ -int cl_eeprom_read_mac_addr(uchar *buf) +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) { uint offset; - if (cl_eeprom_setup_layout()) + if (cl_eeprom_setup(eeprom_bus)) return 0; offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? @@ -123,7 +129,7 @@ u32 cl_eeprom_get_board_rev(void) if (board_rev) return board_rev; - if (cl_eeprom_setup_layout()) + if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS)) return 0; if (cl_eeprom_layout != LAYOUT_LEGACY) diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index 85d5bf0..50c6b02 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -11,10 +11,10 @@ #define _EEPROM_ #ifdef CONFIG_SYS_I2C -int cl_eeprom_read_mac_addr(uchar *buf); +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); u32 cl_eeprom_get_board_rev(void); #else -static inline int cl_eeprom_read_mac_addr(uchar *buf) +static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) { return 1; } -- cgit v1.1 From eab29802d6211aeb9cd521a51d22a43c8fb4f94d Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:44 +0200 Subject: arm: mx6: cm-fx6: pass 2nd nic mac addr to Linux Obtain 2nd NIC MAC address from baseboard EEPROM and pass it to Linux. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 32f4434..eb18dfc 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -345,32 +345,36 @@ static iomux_v3_cfg_t const enet_pads[] = { MUX_PAD_CTRL(ENET_PAD_CTRL)), }; -static int handle_mac_address(void) +static int handle_mac_address(char *env_var, uint eeprom_bus) { unsigned char enetaddr[6]; int rc; - rc = eth_getenv_enetaddr("ethaddr", enetaddr); + rc = eth_getenv_enetaddr(env_var, enetaddr); if (rc) return 0; - rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); + rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); if (rc) return rc; if (!is_valid_ether_addr(enetaddr)) return -1; - return eth_setenv_enetaddr("ethaddr", enetaddr); + return eth_setenv_enetaddr(env_var, enetaddr); } +#define SB_FX6_I2C_EEPROM_BUS 0 +#define NO_MAC_ADDR "No MAC address found for %s\n" int board_eth_init(bd_t *bis) { int err; - err = handle_mac_address(); - if (err) - puts("No MAC address found\n"); + if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) + printf(NO_MAC_ADDR, "primary NIC"); + + if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) + printf(NO_MAC_ADDR, "secondary NIC"); SETUP_IOMUX_PADS(enet_pads); /* phy reset */ @@ -469,6 +473,11 @@ int ft_board_setup(void *blob, bd_t *bd) "local-mac-address", enetaddr, 6, 1); } + if (eth_getenv_enetaddr("eth1addr", enetaddr)) { + fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", + enetaddr, 6, 1); + } + return 0; } #endif -- cgit v1.1 From deb94d6192e7507d743aefa69a86954c0c26be82 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:46 +0200 Subject: arm: mx6: cm-fx6: add hdmi console support Add support for hdmi console. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 51 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'board') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index eb18dfc..b31e1f5 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -18,8 +18,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -28,6 +30,53 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_IMX_HDMI +static void cm_fx6_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = cm_fx6_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 40385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + } + }, +}; +size_t display_count = ARRAY_SIZE(displays); + +static void cm_fx6_setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); +} +#else +static inline void cm_fx6_setup_display(void) {} +#endif /* CONFIG_VIDEO_IPUV3 */ + #ifdef CONFIG_DWC_AHSATA static int cm_fx6_issd_gpios[] = { /* The order of the GPIOs in the array is important! */ @@ -516,6 +565,8 @@ int board_init(void) if (ret) printf("Warning: I2C setup failed: %d\n", ret); + cm_fx6_setup_display(); + return 0; } -- cgit v1.1 From 6947e3f56f265c9bb1f3832c74630adf6286987d Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:49 +0200 Subject: compulab: splash: use errno values Use errno values to improve return reporting. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/common/splash.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c index 49ed49b..33b2f9f 100644 --- a/board/compulab/common/splash.c +++ b/board/compulab/common/splash.c @@ -8,6 +8,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -44,12 +45,12 @@ splash_address_too_high: printf("Error: splashimage address too high. Data overwrites U-Boot " "and/or placed beyond DRAM boundaries.\n"); - return -1; + return -EFAULT; } #else static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) { - return -1; + return -ENOSYS; } #endif /* CONFIG_CMD_NAND */ @@ -60,12 +61,12 @@ int cl_splash_screen_prepare(int nand_offset) env_splashimage_value = getenv("splashimage"); if (env_splashimage_value == NULL) - return -1; + return -ENOENT; bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); if (bmp_load_addr == 0) { printf("Error: bad splashimage address specified\n"); - return -1; + return -EFAULT; } return splash_load_from_nand(bmp_load_addr, nand_offset); -- cgit v1.1 From 7be4cd2cc54fc494dd550b9893e784bf1f9a31b5 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:50 +0200 Subject: compulab: splash: refactor splash.c Move storage device specific code into its own function instead of calling it directly from an otherwise storage device independent function (cl_splash_screen_prepare). This is a preparation for supporting multiple splash locations. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/common/common.h | 4 ++-- board/compulab/common/splash.c | 43 +++++++++++++++++++++++++----------------- 2 files changed, 28 insertions(+), 19 deletions(-) (limited to 'board') diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index 68ffb11..80753b4 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -25,9 +25,9 @@ static inline void cl_usb_hub_deinit(int gpio) {} #endif /* CONFIG_CMD_USB */ #ifdef CONFIG_SPLASH_SCREEN -int cl_splash_screen_prepare(int nand_offset); +int cl_splash_screen_prepare(int offset); #else /* !CONFIG_SPLASH_SCREEN */ -static inline int cl_splash_screen_prepare(int nand_offset) +static inline int cl_splash_screen_prepare(int offset) { return -ENOSYS; } diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c index 33b2f9f..09a0755 100644 --- a/board/compulab/common/splash.c +++ b/board/compulab/common/splash.c @@ -10,11 +10,32 @@ #include #include #include +#include "common.h" DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND -static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + return nand_read_skip_bad(&nand_info[nand_curr_device], offset, + &read_size, NULL, + nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); +} +#else +static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + debug("%s: nand support not available\n", __func__); + return -ENOSYS; +} +#endif + +static int splash_storage_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + return splash_nand_read(bmp_load_addr, offset, read_size); +} + +static int splash_load_raw(u32 bmp_load_addr, int offset) { struct bmp_header *bmp_hdr; int res; @@ -23,10 +44,7 @@ static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) goto splash_address_too_high; - res = nand_read_skip_bad(&nand_info[nand_curr_device], - nand_offset, &bmp_header_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); + res = splash_storage_read(bmp_load_addr, offset, bmp_header_size); if (res < 0) return res; @@ -36,10 +54,7 @@ static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) if (bmp_load_addr + bmp_size >= gd->start_addr_sp) goto splash_address_too_high; - return nand_read_skip_bad(&nand_info[nand_curr_device], - nand_offset, &bmp_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); + return splash_storage_read(bmp_load_addr, offset, bmp_size); splash_address_too_high: printf("Error: splashimage address too high. Data overwrites U-Boot " @@ -47,14 +62,8 @@ splash_address_too_high: return -EFAULT; } -#else -static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) -{ - return -ENOSYS; -} -#endif /* CONFIG_CMD_NAND */ -int cl_splash_screen_prepare(int nand_offset) +int cl_splash_screen_prepare(int offset) { char *env_splashimage_value; u32 bmp_load_addr; @@ -69,5 +78,5 @@ int cl_splash_screen_prepare(int nand_offset) return -EFAULT; } - return splash_load_from_nand(bmp_load_addr, nand_offset); + return splash_load_raw(bmp_load_addr, offset); } -- cgit v1.1 From fd29dd554af6e88ff6d794886e5ab7ba176ace17 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:51 +0200 Subject: compulab: splash: support multiple splash sources Define a generic way for boards to define splash image locations: - introduce struct splash_location - introduce enum splash_storage - update cl_splash_screen_prepare() to take an array of above struct and select the appropriate one based on the splashsource environment variable (if it is not defined- use the first splash location as default). cm-t35 is updated to work with the new interface. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Igor Grinberg Acked-by: Igor Grinberg --- board/compulab/cm_t35/cm_t35.c | 11 +++++-- board/compulab/common/common.h | 15 +++++++-- board/compulab/common/splash.c | 70 +++++++++++++++++++++++++++++++++++++----- 3 files changed, 85 insertions(+), 11 deletions(-) (limited to 'board') diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 9a3b2ee..8143c05 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -59,11 +59,18 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) } #endif -#define CM_T35_SPLASH_NAND_OFFSET 0x100000 +struct splash_location splash_locations[] = { + { + .name = "nand", + .storage = SPLASH_STORAGE_NAND, + .offset = 0x100000, + }, +}; int splash_screen_prepare(void) { - return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET); + return cl_splash_screen_prepare(splash_locations, + ARRAY_SIZE(splash_locations)); } /* diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index 80753b4..09b4de6 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -24,10 +24,21 @@ static inline int cl_usb_hub_init(int gpio, const char *label) static inline void cl_usb_hub_deinit(int gpio) {} #endif /* CONFIG_CMD_USB */ +enum splash_storage { + SPLASH_STORAGE_NAND, +}; + +struct splash_location { + char *name; + enum splash_storage storage; + u32 offset; /* offset from start of storage */ +}; + #ifdef CONFIG_SPLASH_SCREEN -int cl_splash_screen_prepare(int offset); +int cl_splash_screen_prepare(struct splash_location *locations, uint size); #else /* !CONFIG_SPLASH_SCREEN */ -static inline int cl_splash_screen_prepare(int offset) +static inline int cl_splash_screen_prepare(struct splash_location *locations, + uint size) { return -ENOSYS; } diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c index 09a0755..f230d6d 100644 --- a/board/compulab/common/splash.c +++ b/board/compulab/common/splash.c @@ -30,12 +30,26 @@ static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) } #endif -static int splash_storage_read(u32 bmp_load_addr, int offset, size_t read_size) +static int splash_storage_read(struct splash_location *location, + u32 bmp_load_addr, size_t read_size) { - return splash_nand_read(bmp_load_addr, offset, read_size); + u32 offset; + + if (!location) + return -EINVAL; + + offset = location->offset; + switch (location->storage) { + case SPLASH_STORAGE_NAND: + return splash_nand_read(bmp_load_addr, offset, read_size); + default: + printf("Unknown splash location\n"); + } + + return -EINVAL; } -static int splash_load_raw(u32 bmp_load_addr, int offset) +static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr) { struct bmp_header *bmp_hdr; int res; @@ -44,7 +58,7 @@ static int splash_load_raw(u32 bmp_load_addr, int offset) if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) goto splash_address_too_high; - res = splash_storage_read(bmp_load_addr, offset, bmp_header_size); + res = splash_storage_read(location, bmp_load_addr, bmp_header_size); if (res < 0) return res; @@ -54,7 +68,7 @@ static int splash_load_raw(u32 bmp_load_addr, int offset) if (bmp_load_addr + bmp_size >= gd->start_addr_sp) goto splash_address_too_high; - return splash_storage_read(bmp_load_addr, offset, bmp_size); + return splash_storage_read(location, bmp_load_addr, bmp_size); splash_address_too_high: printf("Error: splashimage address too high. Data overwrites U-Boot " @@ -63,8 +77,46 @@ splash_address_too_high: return -EFAULT; } -int cl_splash_screen_prepare(int offset) +/** + * select_splash_location - return the splash location based on board support + * and env variable "splashsource". + * + * @locations: An array of supported splash locations. + * @size: Size of splash_locations array. + * + * @return: If a null set of splash locations is given, or + * splashsource env variable is set to unsupported value + * return NULL. + * If splashsource env variable is not defined + * return the first entry in splash_locations as default. + * If splashsource env variable contains a supported value + * return the location selected by splashsource. + */ +static struct splash_location *select_splash_location( + struct splash_location *locations, uint size) +{ + int i; + char *env_splashsource; + + if (!locations || size == 0) + return NULL; + + env_splashsource = getenv("splashsource"); + if (env_splashsource == NULL) + return &locations[0]; + + for (i = 0; i < size; i++) { + if (!strcmp(locations[i].name, env_splashsource)) + return &locations[i]; + } + + printf("splashsource env variable set to unsupported value\n"); + return NULL; +} + +int cl_splash_screen_prepare(struct splash_location *locations, uint size) { + struct splash_location *splash_location; char *env_splashimage_value; u32 bmp_load_addr; @@ -78,5 +130,9 @@ int cl_splash_screen_prepare(int offset) return -EFAULT; } - return splash_load_raw(bmp_load_addr, offset); + splash_location = select_splash_location(locations, size); + if (!splash_location) + return -EINVAL; + + return splash_load_raw(splash_location, bmp_load_addr); } -- cgit v1.1 From 7e8d7f2ac2035efa04382bbeede1b4fbe1c66987 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:52 +0200 Subject: compulab: splash: support loading splash from sf Add support for loading splash from sf. Signed-off-by: Nikita Kiryanov [grinberg@compulab.co.il: staticize the sf global variable] Signed-off-by: Igor Grinberg Cc: Stefano Babic Cc: Igor Grinberg --- board/compulab/common/common.h | 1 + board/compulab/common/splash.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'board') diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index 09b4de6..b992965 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -26,6 +26,7 @@ static inline void cl_usb_hub_deinit(int gpio) {} enum splash_storage { SPLASH_STORAGE_NAND, + SPLASH_STORAGE_SF, }; struct splash_location { diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c index f230d6d..16c315c 100644 --- a/board/compulab/common/splash.c +++ b/board/compulab/common/splash.c @@ -9,11 +9,36 @@ #include #include #include +#include +#include #include #include "common.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPI_FLASH +static struct spi_flash *sf; +static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + if (!sf) { + sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!sf) + return -ENODEV; + } + + return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr); +} +#else +static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) +{ + debug("%s: sf support not available\n", __func__); + return -ENOSYS; +} +#endif + #ifdef CONFIG_CMD_NAND static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) { @@ -42,6 +67,8 @@ static int splash_storage_read(struct splash_location *location, switch (location->storage) { case SPLASH_STORAGE_NAND: return splash_nand_read(bmp_load_addr, offset, read_size); + case SPLASH_STORAGE_SF: + return splash_sf_read(bmp_load_addr, offset, read_size); default: printf("Unknown splash location\n"); } -- cgit v1.1 From 3a236a356397449bf3ad1e72221053b5a3d87b80 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:53 +0200 Subject: arm: mx6: cm-fx6: add splash screen support Add support for splash screen. The splash screen is loaded from the SPI flash and is displayed on the HDMI display. Signed-off-by: Nikita Kiryanov [grinberg@compulab.co.il: minor code and commit message updates] Signed-off-by: Igor Grinberg Cc: Stefano Babic Cc: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'board') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b31e1f5..b5c3ea1 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -27,9 +27,26 @@ #include #include "common.h" #include "../common/eeprom.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location cm_fx6_splash_locations[] = { + { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .offset = 0x100000, + }, +}; + +int splash_screen_prepare(void) +{ + return cl_splash_screen_prepare(cm_fx6_splash_locations, + ARRAY_SIZE(cm_fx6_splash_locations)); +} +#endif + #ifdef CONFIG_IMX_HDMI static void cm_fx6_enable_hdmi(struct display_info_t const *dev) { -- cgit v1.1 From f82eb2fa5df86b7180ea355a3cb98482f7c27269 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 14 Jan 2015 10:42:54 +0200 Subject: common: convert compulab splash load code to common code Move board/compulab/common/splash.c code to common/splash_source.c to make it available for everybody. This move renames cl_splash_screen_prepare() to splash_source_load(), and the compilation of this code is conditional on CONFIG_SPLASH_SOURCE. splash_source features: * Provide a standardized way for declaring board specific splash screen locations * Provide existing routines for auto loading the splash image from the locations as declared by the board * Introduce the "splashsource" environment variable, which makes it possible to select the splash image source. cm-t35 and cm-fx6 are updated to use the modified version. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic Cc: Tom Rini Cc: Igor Grinberg Cc: Anatolij Gustschin Reviewed-by: Tom Rini Acked-by: Igor Grinberg --- board/compulab/cm_fx6/cm_fx6.c | 5 +- board/compulab/cm_t35/cm_t35.c | 5 +- board/compulab/common/Makefile | 1 - board/compulab/common/common.h | 21 ------ board/compulab/common/splash.c | 165 ----------------------------------------- 5 files changed, 6 insertions(+), 191 deletions(-) delete mode 100644 board/compulab/common/splash.c (limited to 'board') diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index b5c3ea1..ae6945b 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -42,8 +43,8 @@ static struct splash_location cm_fx6_splash_locations[] = { int splash_screen_prepare(void) { - return cl_splash_screen_prepare(cm_fx6_splash_locations, - ARRAY_SIZE(cm_fx6_splash_locations)); + return splash_source_load(cm_fx6_splash_locations, + ARRAY_SIZE(cm_fx6_splash_locations)); } #endif diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 8143c05..c4ea8ea 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -69,8 +70,8 @@ struct splash_location splash_locations[] = { int splash_screen_prepare(void) { - return cl_splash_screen_prepare(splash_locations, - ARRAY_SIZE(splash_locations)); + return splash_source_load(splash_locations, + ARRAY_SIZE(splash_locations)); } /* diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index dbf0009..286f327 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -9,5 +9,4 @@ obj-y += common.o obj-$(CONFIG_SYS_I2C) += eeprom.o obj-$(CONFIG_LCD) += omap3_display.o -obj-$(CONFIG_SPLASH_SCREEN) += splash.o obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index b992965..8f38b79 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -24,27 +24,6 @@ static inline int cl_usb_hub_init(int gpio, const char *label) static inline void cl_usb_hub_deinit(int gpio) {} #endif /* CONFIG_CMD_USB */ -enum splash_storage { - SPLASH_STORAGE_NAND, - SPLASH_STORAGE_SF, -}; - -struct splash_location { - char *name; - enum splash_storage storage; - u32 offset; /* offset from start of storage */ -}; - -#ifdef CONFIG_SPLASH_SCREEN -int cl_splash_screen_prepare(struct splash_location *locations, uint size); -#else /* !CONFIG_SPLASH_SCREEN */ -static inline int cl_splash_screen_prepare(struct splash_location *locations, - uint size) -{ - return -ENOSYS; -} -#endif /* CONFIG_SPLASH_SCREEN */ - #ifdef CONFIG_SMC911X int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, int (*reset)(int), int rst_gpio); diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c deleted file mode 100644 index 16c315c..0000000 --- a/board/compulab/common/splash.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2014 CompuLab, Ltd. - * - * Authors: Igor Grinberg - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "common.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SPI_FLASH -static struct spi_flash *sf; -static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - if (!sf) { - sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, - CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, - CONFIG_SF_DEFAULT_MODE); - if (!sf) - return -ENODEV; - } - - return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr); -} -#else -static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - debug("%s: sf support not available\n", __func__); - return -ENOSYS; -} -#endif - -#ifdef CONFIG_CMD_NAND -static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - return nand_read_skip_bad(&nand_info[nand_curr_device], offset, - &read_size, NULL, - nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); -} -#else -static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) -{ - debug("%s: nand support not available\n", __func__); - return -ENOSYS; -} -#endif - -static int splash_storage_read(struct splash_location *location, - u32 bmp_load_addr, size_t read_size) -{ - u32 offset; - - if (!location) - return -EINVAL; - - offset = location->offset; - switch (location->storage) { - case SPLASH_STORAGE_NAND: - return splash_nand_read(bmp_load_addr, offset, read_size); - case SPLASH_STORAGE_SF: - return splash_sf_read(bmp_load_addr, offset, read_size); - default: - printf("Unknown splash location\n"); - } - - return -EINVAL; -} - -static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr) -{ - struct bmp_header *bmp_hdr; - int res; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = splash_storage_read(location, bmp_load_addr, bmp_header_size); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return splash_storage_read(location, bmp_load_addr, bmp_size); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -EFAULT; -} - -/** - * select_splash_location - return the splash location based on board support - * and env variable "splashsource". - * - * @locations: An array of supported splash locations. - * @size: Size of splash_locations array. - * - * @return: If a null set of splash locations is given, or - * splashsource env variable is set to unsupported value - * return NULL. - * If splashsource env variable is not defined - * return the first entry in splash_locations as default. - * If splashsource env variable contains a supported value - * return the location selected by splashsource. - */ -static struct splash_location *select_splash_location( - struct splash_location *locations, uint size) -{ - int i; - char *env_splashsource; - - if (!locations || size == 0) - return NULL; - - env_splashsource = getenv("splashsource"); - if (env_splashsource == NULL) - return &locations[0]; - - for (i = 0; i < size; i++) { - if (!strcmp(locations[i].name, env_splashsource)) - return &locations[i]; - } - - printf("splashsource env variable set to unsupported value\n"); - return NULL; -} - -int cl_splash_screen_prepare(struct splash_location *locations, uint size) -{ - struct splash_location *splash_location; - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -ENOENT; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -EFAULT; - } - - splash_location = select_splash_location(locations, size); - if (!splash_location) - return -EINVAL; - - return splash_load_raw(splash_location, bmp_load_addr); -} -- cgit v1.1 From b4b39a7e54fa6f4aa016cf98744aa5659db75d33 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 20 Jan 2015 10:06:18 +0100 Subject: arm, imx6, aristainetos: board updates - use linux display timing settings - change backlight duty cycle 500ns - some defaultenvironment changes - change fit_addr_r to 0x14000000 as needed if MAX_LOCKDEP_SUBCLASSES in linux gets increased. - Environment now at 0xd0000 in nand flash Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 67ac260..8330bb6 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -321,8 +321,8 @@ static void enable_lvds(struct display_info_t const *dev) /* enable backlight PWM 3 */ if (pwm_init(2, 0, 0)) goto error; - /* duty cycle 200ns, period: 3000ns */ - if (pwm_config(2, 200, 3000)) + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(2, 500, 3000)) goto error; if (pwm_enable(2)) goto error; @@ -350,8 +350,8 @@ struct display_info_t const displays[] = { .right_margin = 88, .upper_margin = 10, .lower_margin = 10, - .hsync_len = 25, - .vsync_len = 1, + .hsync_len = 80, + .vsync_len = 25, .sync = 0, .vmode = FB_VMODE_NONINTERLACED } -- cgit v1.1 From 5f22d88f82082019ce631bb7cb635bb075170c9c Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Mon, 12 Jan 2015 17:37:13 +0800 Subject: imx: mx6qsabreauto: Change to use common GPMI IO clock function Since a clock function setup_gpmi_io_clk is implemented for GPMI IO clock settings, change to use this common function in GPMI setup. Signed-off-by: Ye.Li Acked-by: Stefano Babic --- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 59387ff..a90360f 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -311,30 +311,9 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - clrbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -- cgit v1.1 From aee0013e53b339a573e2a8d66062fe87765aa3bd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 9 Feb 2015 07:29:33 -0200 Subject: mx53loco: Fix boot hang during reboot stress test Currently by running the following test: => setenv bootcmd reset => save => reset , we observe a hang after approximately 20-30 minutes of stress reboot test. Investigation of this issue revealed that when a single DDR chip select is used, the hang does not happen. It only happens when the two chip selects are active. MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence": "The controller must keep the memory lines quiet (except for CK) for the ZQ calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256 for other ZQCL and 64 for ZQCS)." According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL: "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines. Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)" So make sure to activate one chip select at time (CS0 first and then CS1 later), so that the required JEDEC delay is respected for each chip select. With this change applied the board has gone through three days of reboot stress test without any hang. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic --- board/freescale/mx53loco/imximage.cfg | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg index d1c1931..a5f1d98 100644 --- a/board/freescale/mx53loco/imximage.cfg +++ b/board/freescale/mx53loco/imximage.cfg @@ -59,7 +59,7 @@ DATA 4 0x63fd9090 0x4d444c44 DATA 4 0x63fd907c 0x01370138 DATA 4 0x63fd9080 0x013b013c DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd9000 0x83190000 DATA 4 0x63fd900c 0x9f5152e3 DATA 4 0x63fd9010 0xb68e8a63 DATA 4 0x63fd9014 0x01ff00db @@ -72,6 +72,7 @@ DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd9000 0xc3190000 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -- cgit v1.1