From 32f4d729e775e707d3ef11ef320d83aaa1ef6afb Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 19 Nov 2013 11:02:18 +0530 Subject: board/ti/am335x/README: update for NAND boot NAND boot mode on AM335x EVM has been verified, and steps to use it has been documented and update in this README Signed-off-by: Pekon Gupta Acked-by: Peter Korsgaard Acked-by: Tom Rini --- board/ti/am335x/README | 53 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 17 deletions(-) (limited to 'board') diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 2a30ab8..947305b 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -46,23 +46,42 @@ NAND The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In this example to program the NAND we assume that an SD card has been inserted with the files to write in the first SD slot and that mtdparts -have been configured correctly for the board. As a time saving measure we -load MLO into memory in one location, copy it into the three locatations -that the ROM checks for additional valid copies, then load U-Boot into -memory. We then write that whole section of memory to NAND. - -U-Boot # mmc rescan -U-Boot # env default -f -a -U-Boot # nand erase.chip -U-Boot # saveenv -U-Boot # load mmc 0 81000000 MLO -U-Boot # cp.b 81000000 81020000 20000 -U-Boot # cp.b 81000000 81040000 20000 -U-Boot # cp.b 81000000 81060000 20000 -U-Boot # load mmc 0 81080000 u-boot.img -U-Boot # nand write 81000000 0 260000 -U-Boot # load mmc 0 ${loadaddr} uImage -U-Boot # nand write ${loadaddr} kernel 500000 +have been configured correctly for the board. All images are first loaded +into memory, then written to NAND. + +Step-1: Building u-boot for NAND boot + Set following CONFIGxx options for NAND device. + CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page + CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page + CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block + CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) + +Step-2: Flashing NAND via MMC/SD + # select BOOTSEL to MMC/SD boot and boot from MMC/SD card + U-Boot # mmc rescan + # erase flash + U-Boot # nand erase.chip + U-Boot # env default -f -a + U-Boot # saveenv + # flash MLO. Redundant copies of MLO are kept for failsafe + U-Boot # load mmc 0 0x82000000 MLO + U-Boot # nand write 0x82000000 0x00000 0x20000 + U-Boot # nand write 0x82000000 0x20000 0x20000 + U-Boot # nand write 0x82000000 0x40000 0x20000 + U-Boot # nand write 0x82000000 0x60000 0x20000 + # flash u-boot.img + U-Boot # load mmc 0 0x82000000 u-boot.img + U-Boot # nand write 0x82000000 0x80000 0x60000 + # flash kernel image + U-Boot # load mmc 0 0x82000000 uImage + U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} + # flash filesystem image + U-Boot # load mmc 0 0x82000000 filesystem.img + U-Boot # nand write 0x82000000 ${loadaddress} 0x300000 + +Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. + The device should boot from images flashed on NAND device. NOR === -- cgit v1.1 From 9e0e37accde19e513caaddb18ad22a573910dbe7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Feb 2014 11:16:32 +0100 Subject: zynq: Add OF ram initialization support Read ram size directly from DTB. Signed-off-by: Michal Simek --- board/xilinx/zynq/board.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 82f2345..485a5e4 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -134,8 +135,27 @@ int board_mmc_init(bd_t *bd) int dram_init(void) { +#ifdef CONFIG_OF_CONTROL + int node; + fdt_addr_t addr; + fdt_size_t size; + const void *blob = gd->fdt_blob; + + node = fdt_node_offset_by_prop_value(blob, -1, "device_type", + "memory", 7); + if (node == -FDT_ERR_NOTFOUND) { + debug("ZYNQ DRAM: Can't get memory node\n"); + return -1; + } + addr = fdtdec_get_addr_size(blob, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE || size == 0) { + debug("ZYNQ DRAM: Can't get base address or size\n"); + return -1; + } + gd->ram_size = size; +#else gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - +#endif zynq_ddrc_init(); return 0; -- cgit v1.1 From 9c366881d70ec09ddb8830daaf3f5cd07f9aac15 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 26 Feb 2014 14:51:00 +0900 Subject: nand_spl: simpc8313: move config.mk used only for nand_spl board/sheldon/simpc8313/config.mk is used only for nand_spl. So it should go into nand_spl/board/sheldon/simpc8313/. Signed-off-by: Masahiro Yamada --- board/sheldon/simpc8313/config.mk | 5 ----- 1 file changed, 5 deletions(-) delete mode 100644 board/sheldon/simpc8313/config.mk (limited to 'board') diff --git a/board/sheldon/simpc8313/config.mk b/board/sheldon/simpc8313/config.mk deleted file mode 100644 index d1b4e2e..0000000 --- a/board/sheldon/simpc8313/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_LP -PAD_TO = 0xFFF20000 -else -PAD_TO = 0xFFF04000 -endif -- cgit v1.1 From 1ace4022394eacbdae12e7275c445699f8ad4833 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 26 Feb 2014 17:47:58 +0400 Subject: sizes.h - consolidate for all architectures Copied from Linux sources "include/linux/sizes.h" commit 413541dd66d51f791a0b169d9b9014e4f56be13c Signed-off-by: Alexey Brodkin Cc: Vineet Gupta Cc: Tom Rini Cc: Stefan Roese Cc: Albert Aribaud Acked-by: Tom Rini Acked-by: Stefan Roese [trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini --- board/BuS/vl_ma2sc/vl_ma2sc.c | 2 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 2 +- board/compulab/cm_t335/spl.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/highbank/highbank.c | 2 +- board/ronetix/pm9261/pm9261.c | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- board/ronetix/pm9g45/pm9g45.c | 2 +- board/samsung/common/misc.c | 2 +- board/wandboard/wandboard.c | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) (limited to 'board') diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c index 63f7ad9..da39c86 100644 --- a/board/BuS/vl_ma2sc/vl_ma2sc.c +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include #include diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index d42a173..7784cd7 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -7,7 +7,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index b3b150a..d574364 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include const struct ctrl_ioregs ioregs = { .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index c496254..aadad32 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 4b272c7..371b0a2 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #define HB_AHCI_BASE 0xffe08000 diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index a634383..ec3ac89 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 3cedeef..3aaffa8 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index c9f2747..15aa4ac 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index eb15739..3ff4289 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 72e9bb2..0508457 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.1 From e2d8a714a7e6047124581b93d1cfe9c7702cedd4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 26 Feb 2014 15:59:25 -0700 Subject: sandbox: Convert GPIOs to use driver model Convert sandbox over to use driver model GPIOs. Signed-off-by: Simon Glass --- board/sandbox/sandbox/sandbox.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 95efaff..2f90df5 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -4,7 +4,7 @@ */ #include - +#include #include /* @@ -14,6 +14,11 @@ */ gd_t *gd; +/* Add a simple GPIO device */ +U_BOOT_DEVICE(gpio_sandbox) = { + .name = "gpio_sandbox", +}; + void flush_cache(unsigned long start, unsigned long size) { } -- cgit v1.1 From de1931460f6755e5cd04d38108a797a22cb8ea4d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 28 Feb 2014 19:42:26 +0900 Subject: board: gaisler: delete unnecessary include path The same outputs are generated with or without -I$(TOPDIR)/board. I cannot understand why it is necessary. Remove. Signed-off-by: Masahiro Yamada Cc: Daniel Hellstrom --- board/gaisler/gr_cpci_ax2000/config.mk | 2 -- board/gaisler/gr_ep2s60/config.mk | 2 -- board/gaisler/gr_xc3s_1500/config.mk | 2 -- board/gaisler/grsim/config.mk | 2 -- board/gaisler/grsim_leon2/config.mk | 2 -- 5 files changed, 10 deletions(-) (limited to 'board') diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk index 309c879..731a539 100644 --- a/board/gaisler/gr_cpci_ax2000/config.mk +++ b/board/gaisler/gr_cpci_ax2000/config.mk @@ -17,5 +17,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN SDRAM #CONFIG_SYS_TEXT_BASE = 0x60000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk index d57efae..6e01f07 100644 --- a/board/gaisler/gr_ep2s60/config.mk +++ b/board/gaisler/gr_ep2s60/config.mk @@ -15,5 +15,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN SDRAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk index e87320b..e4a66cb 100644 --- a/board/gaisler/gr_xc3s_1500/config.mk +++ b/board/gaisler/gr_xc3s_1500/config.mk @@ -14,5 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk index df26f82..d1f61da 100644 --- a/board/gaisler/grsim/config.mk +++ b/board/gaisler/grsim/config.mk @@ -14,5 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk index 99f9a68..f98b23b 100644 --- a/board/gaisler/grsim_leon2/config.mk +++ b/board/gaisler/grsim_leon2/config.mk @@ -14,5 +14,3 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # RUN U-BOOT FROM RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 - -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board -- cgit v1.1 From 1900d3cfaddc81f990aaf50eb3707540bf353b43 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 28 Feb 2014 19:59:16 +0900 Subject: board: .gitignore: ignore board-specific generated files Ignore - board/cray/L1/bootscript.{c|image} - board/matrix_vision/mvblm7/bootscript.img - board/maxtir_vision/mvsmr/bootscript.img Signed-off-by: Masahiro Yamada Cc: Andre Schwarz --- board/cray/L1/.gitignore | 2 ++ board/matrix_vision/mvblm7/.gitignore | 1 + board/matrix_vision/mvsmr/.gitignore | 1 + 3 files changed, 4 insertions(+) create mode 100644 board/cray/L1/.gitignore create mode 100644 board/matrix_vision/mvblm7/.gitignore create mode 100644 board/matrix_vision/mvsmr/.gitignore (limited to 'board') diff --git a/board/cray/L1/.gitignore b/board/cray/L1/.gitignore new file mode 100644 index 0000000..cd76d66 --- /dev/null +++ b/board/cray/L1/.gitignore @@ -0,0 +1,2 @@ +bootscript.c +bootscript.image diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore new file mode 100644 index 0000000..469f1bc --- /dev/null +++ b/board/matrix_vision/mvblm7/.gitignore @@ -0,0 +1 @@ +bootscript.img diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore new file mode 100644 index 0000000..469f1bc --- /dev/null +++ b/board/matrix_vision/mvsmr/.gitignore @@ -0,0 +1 @@ +bootscript.img -- cgit v1.1 From e0708fb539b9b6eddba2c66ce7ff7fa3810aa04d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 28 Feb 2014 20:12:34 +0900 Subject: board: config.mk: delete unused sinclude directive config.tmp is not there. Signed-off-by: Masahiro Yamada --- board/freescale/m54418twr/config.mk | 2 -- board/micronas/vct/config.mk | 2 -- 2 files changed, 4 deletions(-) (limited to 'board') diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk index b306d03..07f52e0 100644 --- a/board/freescale/m54418twr/config.mk +++ b/board/freescale/m54418twr/config.mk @@ -4,6 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk index 0f004e0..354d918 100644 --- a/board/micronas/vct/config.mk +++ b/board/micronas/vct/config.mk @@ -8,8 +8,6 @@ # vct_xxx boards with MIPS 4Kc CPU core # -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp - ifndef CONFIG_SYS_TEXT_BASE CONFIG_SYS_TEXT_BASE = 0x87000000 endif -- cgit v1.1 From 50a91dacb04053426497adca67901b54f92fae48 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 3 Mar 2014 19:03:18 +0900 Subject: arc: arcangel4: set board entry to fix a build error There are no source files in board/synopsys/arcangel4/ directory. Signed-off-by: Masahiro Yamada Cc: Alexey Brodkin --- board/synopsys/arcangel4/Makefile | 11 ----------- 1 file changed, 11 deletions(-) delete mode 100644 board/synopsys/arcangel4/Makefile (limited to 'board') diff --git a/board/synopsys/arcangel4/Makefile b/board/synopsys/arcangel4/Makefile deleted file mode 100644 index 575e58f..0000000 --- a/board/synopsys/arcangel4/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# This board is mostly used for debugging U-Boot in simulation (ISS). -# The only peripheral which is used on this board is a serial port which -# requires no initialization except those in "include/configs/arcangel4.h". -# And now there's no specific initializations for this board. -# So this Makefile is only required for satisfaction of U-Boot build system. -- cgit v1.1 From 6aff05098864233caf9d24cb020e67b00ada4e3e Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 22 Nov 2013 16:53:29 +0530 Subject: mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nand omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta --- board/isee/igep00x0/igep00x0.c | 1 - board/overo/overo.c | 1 - 2 files changed, 2 deletions(-) (limited to 'board') diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 7a7500b..3b2b1f1 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/board/overo/overo.c b/board/overo/overo.c index 9ac35d2..1192d02 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include "overo.h" -- cgit v1.1 From 4b75fd510076f2261c5e21b9b8cf75c9f01ded3c Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Thu, 6 Mar 2014 07:03:24 +0100 Subject: board/BuR/common: fix phy addresses B&R boards are using Phy Addresses 'one' and 'two', prior this was defined through #define PHYADDR 1 within a header file. Now this is addresses are given with device-driver structure. Signed-off-by: Hannes Petermaier --- board/BuR/common/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 04f3f1f..4c926ce 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -141,12 +141,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_addr = 0, + .phy_addr = 1, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, + .phy_addr = 2, }, }; -- cgit v1.1 From cbac2a6e49d396048bae2c97954e213fb3d2fcb0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 4 Mar 2014 11:36:51 +0900 Subject: xilinx: delete meaningless .gitignore files config.tmp is never generated Signed-off-by: Masahiro Yamada Cc: Michal Simek Acked-by: Michal Simek --- board/avnet/fx12mm/.gitignore | 1 - board/avnet/v5fx30teval/.gitignore | 1 - board/xilinx/ml507/.gitignore | 1 - board/xilinx/ppc405-generic/.gitignore | 1 - board/xilinx/ppc440-generic/.gitignore | 1 - 5 files changed, 5 deletions(-) delete mode 100644 board/avnet/fx12mm/.gitignore delete mode 100644 board/avnet/v5fx30teval/.gitignore delete mode 100644 board/xilinx/ml507/.gitignore delete mode 100644 board/xilinx/ppc405-generic/.gitignore delete mode 100644 board/xilinx/ppc440-generic/.gitignore (limited to 'board') diff --git a/board/avnet/fx12mm/.gitignore b/board/avnet/fx12mm/.gitignore deleted file mode 100644 index b644f59..0000000 --- a/board/avnet/fx12mm/.gitignore +++ /dev/null @@ -1 +0,0 @@ -config.tmp diff --git a/board/avnet/v5fx30teval/.gitignore b/board/avnet/v5fx30teval/.gitignore deleted file mode 100644 index f6418a0..0000000 --- a/board/avnet/v5fx30teval/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/config.tmp diff --git a/board/xilinx/ml507/.gitignore b/board/xilinx/ml507/.gitignore deleted file mode 100644 index f6418a0..0000000 --- a/board/xilinx/ml507/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/config.tmp diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore deleted file mode 100644 index b644f59..0000000 --- a/board/xilinx/ppc405-generic/.gitignore +++ /dev/null @@ -1 +0,0 @@ -config.tmp diff --git a/board/xilinx/ppc440-generic/.gitignore b/board/xilinx/ppc440-generic/.gitignore deleted file mode 100644 index f6418a0..0000000 --- a/board/xilinx/ppc440-generic/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/config.tmp -- cgit v1.1 From 345b77bacabb84a00c7508471ab560b452910240 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 4 Mar 2014 15:34:35 +0100 Subject: ppc4xx: Remove 4xx NAND booting support As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese Cc: Wolfgang Denk Cc: Tirumala Marri Cc: Matthias Fuchs Cc: Masahiro Yamada Cc: Tom Rini Tested-by: Matthias Fuchs --- board/amcc/acadia/memory.c | 13 ----------- board/amcc/acadia/pll.c | 42 ------------------------------------ board/amcc/bamboo/bamboo.c | 17 --------------- board/amcc/bamboo/init.S | 33 ---------------------------- board/amcc/canyonlands/canyonlands.c | 4 ---- board/amcc/canyonlands/init.S | 34 ----------------------------- board/amcc/sequoia/init.S | 32 --------------------------- board/amcc/sequoia/sdram.c | 13 ++--------- board/amcc/sequoia/sequoia.c | 10 ++++----- board/esd/pmc440/init.S | 32 --------------------------- board/esd/pmc440/pmc440.c | 8 ------- 11 files changed, 6 insertions(+), 232 deletions(-) (limited to 'board') diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 61bfea3..9673118 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -17,7 +17,6 @@ extern void board_pll_init_f(void); -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val) return; } -#endif phys_size_t initdram(int board_type) { -#if defined(CONFIG_NAND_SPL) - u32 reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); -#endif - -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; @@ -88,7 +76,6 @@ phys_size_t initdram(int board_type) /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) ; -#endif return (CONFIG_SYS_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index d74b725..d868582 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -135,45 +135,3 @@ void board_pll_init_f(void) mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU__405EZ */ - -#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) -/* - * Get timebase clock frequency - */ -unsigned long get_tbclk(void) -{ - unsigned long cpr_plld; - unsigned long cpr_primad; - unsigned long primad_cpudv; - unsigned long pllFbkDiv; - unsigned long freqProcessor; - - /* - * Read PLL Mode registers - */ - mfcpr(CPR0_PLLD, cpr_plld); - - /* - * Read CPR_PRIMAD register - */ - mfcpr(CPR0_PRIMAD, cpr_primad); - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - /* - * Determine FBK_DIV. - */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; - - freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; - - return (freqProcessor); -} -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 84bbacf..c8d0963 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) /************************************************************************* * * Bamboo has one bank onboard sdram (plus DIMM) @@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0, 0 }; -#endif #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ @@ -440,15 +438,11 @@ int checkboard(void) phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) long dram_size; dram_size = spd_sdram(); return dram_size; -#else - return CONFIG_SYS_MBYTES_SDRAM << 20; -#endif } /*----------------------------------------------------------------------------+ @@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { update_ndfc_ios(gpio_tab); - -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); -#else - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN0 | - SDR0_CUST0_CHIPSELGAT_EN2); -#endif - ndfc_selection_in_fpga(); } else diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index 48dbcbe..5c7c839 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -32,12 +32,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) -#endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) @@ -58,31 +53,3 @@ tlbtab: tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 2b5f1a6..79d4bab 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -379,11 +379,7 @@ int board_early_init_r (void) */ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); -#else mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); -#endif /* Remove TLB entry of boot EBC mapping */ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index d83cd6e..bf00bd6 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -31,13 +31,7 @@ tlbtab: * use the speed up boot process. It is patched after relocation to * enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) - tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG) -#endif /* * TLB entries for SDRAM are not needed on this platform. @@ -95,31 +89,3 @@ tlbtab: #endif tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index b31e9db..f876639 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -48,11 +48,7 @@ tlbtab: /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ @@ -81,31 +77,3 @@ tlbtab: tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 2c5a218..67640d7 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -26,14 +26,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); -#if defined(CONFIG_NAND_SPL) -/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133333333 -#endif - /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void); ************************************************************************/ phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \ - defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_SYS_RAMBOOT) ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); @@ -81,7 +72,7 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ +#endif /* #ifndef CONFIG_SYS_RAMBOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 73c65c5..53f9b34 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -142,8 +142,7 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -151,8 +150,7 @@ int misc_init_r(void) pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ - defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -360,7 +358,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) } #endif -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) /* * On NAND-booting sequoia, we need to patch the chips select numbers * in the dtb (CS0 - NAND, CS3 - NOR) @@ -411,4 +409,4 @@ void ft_board_setup(void *blob, bd_t *bd) return; } } -#endif /* CONFIG_NAND_U_BOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index cc8030b..1f26fad 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -27,11 +27,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif /* TLB entries for DDR2 SDRAM are generated dynamically */ @@ -71,31 +67,3 @@ tlbtab: /* TODO: what about high IO space */ tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 88fc5f7..e86996c 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -229,19 +229,11 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(EBC0_CFGADDR, PB2CR); -#else mtdcr(EBC0_CFGADDR, PB0CR); -#endif pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(EBC0_CFGADDR, PB2CR); -#else mtdcr(EBC0_CFGADDR, PB0CR); -#endif mtdcr(EBC0_CFGDATA, pbcr); /* -- cgit v1.1 From e91df49fbb56858003ebe61191ae07b223a7b866 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 5 Mar 2014 16:59:37 +0900 Subject: kbuild, blackfin: Add CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED Many (but not all) of Blackfin boards give -O2 option to compile under lib/ directory. That means lib/ should be speed-optimized, whereas other parts should be size-optimized. We want to keep the same behavior, but do not want to parse board/*/config.mk again and again. We've got no choice but to invent a new method. CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED, if it is enabled, gives -O2 flag only for building under lib/ directory. Dirty codes which I had marked as "FIX ME" in board/${BOARD}/config.mk have been deleted. Instead, CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED has been defined in include/configs/${BOARD}.h. Signed-off-by: Masahiro Yamada Cc: Sonic Zhang --- board/bct-brettl2/config.mk | 13 ------------- board/bf518f-ezbrd/config.mk | 13 ------------- board/bf526-ezbrd/config.mk | 13 ------------- board/bf527-ad7160-eval/config.mk | 13 ------------- board/bf527-ezkit/config.mk | 13 ------------- board/bf527-sdp/config.mk | 5 ----- board/bf533-ezkit/config.mk | 5 ----- board/bf533-stamp/config.mk | 5 ----- board/bf537-stamp/config.mk | 5 ----- board/bf538f-ezkit/config.mk | 5 ----- board/bf548-ezkit/config.mk | 5 ----- board/bf561-acvilon/config.mk | 5 ----- board/bf561-ezkit/config.mk | 5 ----- board/br4/config.mk | 15 --------------- board/cm-bf527/config.mk | 13 ------------- board/cm-bf533/config.mk | 5 ----- board/cm-bf537e/config.mk | 5 ----- board/cm-bf537u/config.mk | 5 ----- board/cm-bf548/config.mk | 5 ----- board/cm-bf561/config.mk | 5 ----- board/ip04/config.mk | 5 ----- board/pr1/config.mk | 15 --------------- board/tcm-bf518/config.mk | 13 ------------- board/tcm-bf537/config.mk | 5 ----- 24 files changed, 196 deletions(-) delete mode 100644 board/bct-brettl2/config.mk delete mode 100644 board/bf518f-ezbrd/config.mk delete mode 100644 board/bf526-ezbrd/config.mk delete mode 100644 board/bf527-ad7160-eval/config.mk delete mode 100644 board/bf527-ezkit/config.mk delete mode 100644 board/br4/config.mk delete mode 100644 board/cm-bf527/config.mk delete mode 100644 board/pr1/config.mk delete mode 100644 board/tcm-bf518/config.mk (limited to 'board') diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/bct-brettl2/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/bf518f-ezbrd/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/bf526-ezbrd/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/bf527-ad7160-eval/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/bf527-ezkit/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk index af299f5..1d46cfc 100644 --- a/board/bf527-sdp/config.mk +++ b/board/bf527-sdp/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index 97eaafe..7f9138b 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index 97eaafe..7f9138b 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index bc0e747..ab0fbec 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -7,11 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index 97eaafe..7f9138b 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index 8d2c60f..7bb8e9c 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -7,11 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index ce94715..854d7db 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index ce94715..854d7db 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/br4/config.mk b/board/br4/config.mk deleted file mode 100644 index 2436ec0..0000000 --- a/board/br4/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) Switchfin Org. -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/cm-bf527/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index 97eaafe..7f9138b 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index 97eaafe..7f9138b 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index 97eaafe..7f9138b 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index 289c8a4..beb9834 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -7,11 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1 diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index ce94715..854d7db 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/ip04/config.mk b/board/ip04/config.mk index bc0e747..ab0fbec 100644 --- a/board/ip04/config.mk +++ b/board/ip04/config.mk @@ -7,11 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/pr1/config.mk b/board/pr1/config.mk deleted file mode 100644 index 2436ec0..0000000 --- a/board/pr1/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) Switchfin Org. -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk deleted file mode 100644 index 0d3df2d..0000000 --- a/board/tcm-bf518/config.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index 97eaafe..7f9138b 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -7,10 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# FIX ME -ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) -ccflags-y := -O2 -endif - # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 -- cgit v1.1 From 58dac32764728f2f621377442d785936ec6925e8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 5 Mar 2014 17:40:10 +0900 Subject: powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260 Before this commit, CONFIG_MPC8260 and CONFIG_8260 were used mixed-up. All boards with mpc8260 cpu defined both of them: - CONFIG_MPC8260 was defined in board config headers and include/common.h - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk We do not need to have both of them. This commit keeps only CONFIG_MPC8260. This commit does: - Delete CONFIG_8260 and CONFIG_MPC8260 definition in config headers and include/common.h - Rename CONFIG_8260 to CONFIG_MPC8260 in arch/powerpc/cpu/mpc8260/config.mk. - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260 Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk --- board/cogent/mb.c | 4 ++-- board/cogent/serial.c | 2 +- board/hymod/hymod.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/cogent/mb.c b/board/cogent/mb.c index 3eea47d..c025643 100644 --- a/board/cogent/mb.c +++ b/board/cogent/mb.c @@ -14,7 +14,7 @@ /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_8260) +#if defined(CONFIG_MPC8260) #include @@ -186,7 +186,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -#endif /* CONFIG_8260 */ +#endif /* CONFIG_MPC8260 */ /* ------------------------------------------------------------------------- */ diff --git a/board/cogent/serial.c b/board/cogent/serial.c index f0d6b22..95c8120 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) #if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \ - (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE)) + (defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE)) #if CONFIG_CONS_INDEX == 1 #define CMA_MB_SERIAL_BASE CMA_MB_SERIALA_BASE diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h index 3ab3794..7024d8a 100644 --- a/board/hymod/hymod.h +++ b/board/hymod/hymod.h @@ -8,7 +8,7 @@ #ifndef _HYMOD_H_ #define _HYMOD_H_ -#ifdef CONFIG_8260 +#ifdef CONFIG_MPC8260 #include #endif -- cgit v1.1 From 5e5097c110ab5d6bda7f18b7a795d17f27ac3d36 Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 26 Feb 2014 16:06:30 +0530 Subject: board/b4860qds: Add support to make Aurora work on B4860QDS 1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha Reviewed-by: York Sun --- board/freescale/b4860qds/b4860qds.c | 75 ++++++++++++++++++++++-- board/freescale/b4860qds/b4860qds_crossbar_con.h | 8 +++ 2 files changed, 79 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index f6b012d..f6faa24 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -151,6 +151,53 @@ int configure_vsc3316_3308(void) } break; + case 0x02: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x30: + case 0x32: + case 0x33: + case 0x34: + case 0x39: + case 0x3A: + case 0x3C: + case 0x3D: + case 0x5C: + case 0x5D: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B: AURORA + * Lanes: C,d: SGMII + * Lanes: E,F,G,H: CPRI + */ + debug("Configuring crossbar for Aurora, SGMII 3 and 4," + " and CPRI. srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sfp_sgmii_aurora, + num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sfp_sgmii_aurora, + num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + #ifdef CONFIG_PPC_B4420 case 0x18: /* @@ -245,7 +292,7 @@ int config_serdes1_refclks(void) serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 serdes1_prtcl, lane; - unsigned int flag_sgmii_prtcl = 0; + unsigned int flag_sgmii_aurora_prtcl = 0; int ret, i; serdes1_prtcl = in_be32(&gur->rcwsr[4]) & @@ -270,6 +317,25 @@ int config_serdes1_refclks(void) case 0x2C: case 0x2D: case 0x2E: + case 0x02: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x30: + case 0x32: + case 0x33: + case 0x34: + case 0x39: + case 0x3A: + case 0x3C: + case 0x3D: + case 0x5C: + case 0x5D: debug("Configuring idt8t49n222a for CPRI SerDes clks:" " for srds_prctl:%x\n", serdes1_prtcl); ret = select_i2c_ch_pca(I2C_CH_IDT); @@ -288,7 +354,7 @@ int config_serdes1_refclks(void) select_i2c_ch_pca(I2C_CH_DEFAULT); /* Change SerDes1's Refclk1 to 125MHz for on board - * SGMIIs to work + * SGMIIs or Aurora to work */ for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl @@ -300,14 +366,15 @@ int config_serdes1_refclks(void) case SGMII_FM1_DTSEC4: case SGMII_FM1_DTSEC5: case SGMII_FM1_DTSEC6: - flag_sgmii_prtcl++; + case AURORA: + flag_sgmii_aurora_prtcl++; break; default: break; } } - if (flag_sgmii_prtcl) + if (flag_sgmii_aurora_prtcl) QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); /* Steps For SerDes PLLs reset and reconfiguration after diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index db0cf28..fcccb8f 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -24,6 +24,10 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {5, 14}, {4, 15}, {-1, -1}, {-1, -1} }; +static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {5, 14}, + {4, 15}, {2, 12}, {12, 13} }; + #ifdef CONFIG_PPC_B4420 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; @@ -46,6 +50,10 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 11}, {15, 10}, {-1, -1}, {-1, -1} }; +static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 11}, + {15, 10}, {13, 3}, {12, 12} }; + #ifdef CONFIG_PPC_B4420 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -- cgit v1.1 From fb07c0a16dce007208d58c673aacc649703f18fd Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 26 Feb 2014 16:06:56 +0530 Subject: board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha Reviewed-by: York Sun --- board/freescale/b4860qds/b4860qds.c | 119 +++++++++++++++++++++++++++++++++--- 1 file changed, 110 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index f6faa24..9d51864 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -293,7 +294,8 @@ int config_serdes1_refclks(void) (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 serdes1_prtcl, lane; unsigned int flag_sgmii_aurora_prtcl = 0; - int ret, i; + int i; + int ret = 0; serdes1_prtcl = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -304,10 +306,12 @@ int config_serdes1_refclks(void) serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); - /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks + /* To prevent generation of reset request from SerDes + * while changing the refclks, By setting SRDS_RST_MSK bit, + * SerDes reset event cannot cause a reset request */ - for (i = 0; i < PLL_NUM; i++) - clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST); + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + /* Reconfigure IDT idt8t49n222a device for CPRI to work * For this SerDes1's Refclk1 and refclk2 need to be set * to 122.88MHz @@ -345,11 +349,11 @@ int config_serdes1_refclks(void) SERDES_REFCLK_122_88, 0); if (ret) { printf("IDT8T49N222A configuration failed.\n"); - return ret; + goto out; } else - printf("IDT8T49N222A configured.\n"); + debug("IDT8T49N222A configured.\n"); } else { - return ret; + goto out; } select_i2c_ch_pca(I2C_CH_DEFAULT); @@ -400,16 +404,99 @@ int config_serdes1_refclks(void) printf("WARNING:IDT8T49N222A configuration not" " supported for:%x SerDes1 Protocol.\n", serdes1_prtcl); - return -1; } - return 0; +out: + /* Clearing SRDS_RST_MSK bit as now + * SerDes reset event can cause a reset request + */ + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + return ret; +} + +int config_serdes2_refclks(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds2_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + u32 serdes2_prtcl; + int ret = 0; + int i; + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + debug("SERDES2 is not enabled\n"); + return -ENODEV; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + /* To prevent generation of reset request from SerDes + * while changing the refclks, By setting SRDS_RST_MSK bit, + * SerDes reset event cannot cause a reset request + */ + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + + /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work + * For this SerDes2's Refclk1 need to be set to 100MHz + */ + switch (serdes2_prtcl) { + case 0x9E: + case 0x9A: + case 0xb2: + debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", + serdes2_prtcl); + ret = select_i2c_ch_pca(I2C_CH_IDT); + if (!ret) { + ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, + SERDES_REFCLK_100, + SERDES_REFCLK_100, 0); + if (ret) { + printf("IDT8T49N222A configuration failed.\n"); + goto out; + } else + debug("IDT8T49N222A configured.\n"); + } else { + goto out; + } + select_i2c_ch_pca(I2C_CH_DEFAULT); + + /* Steps For SerDes PLLs reset and reconfiguration after + * changing SerDes's refclks + */ + for (i = 0; i < PLL_NUM; i++) { + clrbits_be32(&srds2_regs->bank[i].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds2_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds2_regs->bank[i].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds2_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + } + break; + default: + printf("IDT configuration not supported for:%x S2 Protocol.\n", + serdes2_prtcl); + } + +out: + /* Clearing SRDS_RST_MSK bit as now + * SerDes reset event can cause a reset request + */ + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); + return ret; } int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int ret; /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -442,6 +529,20 @@ int board_early_init_r(void) else printf("SerDes1 Refclks have been set.\n"); + /* SerDes2 refclks need to be set again, as default clks + * are not suitable for PCIe SATA to work + * This function will set SerDes2's Refclk1 and refclk2 + * for SerDes2 protocols having PCIe in them + * for PCIe SATA to work + */ + ret = config_serdes2_refclks(); + if (!ret) + printf("SerDes2 Refclks have been set.\n"); + else if (ret == -ENODEV) + printf("SerDes disable, Refclks couldn't change.\n"); + else + printf("SerDes2 Refclk reconfiguring failed.\n"); + /* Configure VSC3316 and VSC3308 crossbar switches */ if (configure_vsc3316_3308()) printf("VSC:failed to configure VSC3316/3308.\n"); -- cgit v1.1 From c7d506d4ee477368d54f226065416648be08a60d Mon Sep 17 00:00:00 2001 From: poonam aggrwal Date: Mon, 17 Feb 2014 08:38:58 +0530 Subject: 85xx/b4860: Alternate serdes protocols for B4860/B4420 On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- board/freescale/b4860qds/b4860qds.c | 2 ++ board/freescale/b4860qds/eth_b4860qds.c | 5 +++++ 2 files changed, 7 insertions(+) (limited to 'board') diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 9d51864..25b3be8 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -121,6 +121,7 @@ int configure_vsc3316_3308(void) debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); switch (serdes1_prtcl) { + case 0x29: case 0x2a: case 0x2C: case 0x2D: @@ -200,6 +201,7 @@ int configure_vsc3316_3308(void) break; #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* * Configuration: diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index a8fc845..12df9a8 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -66,6 +66,7 @@ static void initialize_lane_to_slot(void) serdes2_prtcl); switch (serdes2_prtcl) { + case 0x17: case 0x18: /* * Configuration: @@ -198,6 +199,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); switch (serdes1_prtcl) { + case 0x29: case 0x2a: /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ debug("Setting phy addresses for FM1_DTSEC5: %x and" @@ -209,6 +211,7 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); break; #ifdef CONFIG_PPC_B4420 + case 0x17: case 0x18: /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ debug("Setting phy addresses for FM1_DTSEC3: %x and" @@ -228,6 +231,7 @@ int board_eth_init(bd_t *bis) break; } switch (serdes2_prtcl) { + case 0x17: case 0x18: debug("Setting phy addresses on SGMII Riser card for" "FM1_DTSEC ports: \n"); @@ -240,6 +244,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); break; + case 0x48: case 0x49: debug("Setting phy addresses on SGMII Riser card for" "FM1_DTSEC ports: \n"); -- cgit v1.1 From c4930b1a0ee5a35c49de10e0289f9c8253e78848 Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 26 Feb 2014 16:07:51 +0530 Subject: B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work Change setting of SerDes2 refclk2 to have the default value as it is coming on board that is 156.25MHz, for XFI to work. Also change PLL_NUM variable to the one defined in config_mpc85xx.h for B4860 and B4420. Signed-off-by: Shaveta Leekha Reviewed-by: York Sun --- board/freescale/b4860qds/b4860qds.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 25b3be8..24a709e 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -29,7 +29,6 @@ #define CLK_MUX_SEL_MASK 0x4 #define ETH_PHY_CLK_OUT 0x4 -#define PLL_NUM 2 DECLARE_GLOBAL_DATA_PTR; @@ -386,7 +385,7 @@ int config_serdes1_refclks(void) /* Steps For SerDes PLLs reset and reconfiguration after * changing SerDes's refclks */ - for (i = 0; i < PLL_NUM; i++) { + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { debug("For PLL%d reset and reconfiguration after" " changing refclks\n", i+1); clrbits_be32(&srds_regs->bank[i].rstctl, @@ -453,7 +452,7 @@ int config_serdes2_refclks(void) if (!ret) { ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, SERDES_REFCLK_100, - SERDES_REFCLK_100, 0); + SERDES_REFCLK_156_25, 0); if (ret) { printf("IDT8T49N222A configuration failed.\n"); goto out; @@ -467,7 +466,7 @@ int config_serdes2_refclks(void) /* Steps For SerDes PLLs reset and reconfiguration after * changing SerDes's refclks */ - for (i = 0; i < PLL_NUM; i++) { + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { clrbits_be32(&srds2_regs->bank[i].rstctl, SRDS_RSTCTL_SDRST_B); udelay(10); -- cgit v1.1 From 7af9a07403e80415d097b4175616c7a7686b7deb Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 26 Feb 2014 16:08:22 +0530 Subject: powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha Reviewed-by: York Sun --- board/freescale/b4860qds/b4860qds.c | 193 ++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) (limited to 'board') diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 24a709e..d9c88a0 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -288,6 +288,182 @@ int configure_vsc3316_3308(void) return 0; } +static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num) +{ + u32 rst_err; + + /* Steps For SerDes PLLs reset and reconfiguration + * or PLL power-up procedure + */ + debug("CALIBRATE PLL:%d\n", pll_num); + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds_regs->bank[pll_num].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + + udelay(20); + + /* Check whether PLL has been locked or not */ + rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & + SRDS_RSTCTL_RSTERR; + rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT; + debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err); + if (rst_err) + return rst_err; + + return rst_err; +} + +static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num) +{ + int ret = 0; + u32 fcap, dcbias, bcap, pllcr1, pllcr0; + + if (calibrate_pll(srds_regs, pll_num)) { + /* STEP 1 */ + /* Read fcap, dcbias and bcap value */ + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_FCAP; + fcap >>= SRDS_PLLSR2_FCAP_SHIFT; + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_BCAP_EN; + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; + setbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_DCBIAS; + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; + debug("values of bcap:%x, fcap:%x and dcbias:%x\n", + bcap, fcap, dcbias); + if (fcap == 0 && bcap == 1) { + /* Step 3 */ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + if (calibrate_pll(srds_regs, pll_num)) { + /*save the fcap, dcbias and bcap values*/ + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) + & SRDS_PLLSR2_FCAP; + fcap >>= SRDS_PLLSR2_FCAP_SHIFT; + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) + & SRDS_PLLSR2_BCAP_EN; + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; + setbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OUT_EN); + dcbias = in_be32 + (&srds_regs->bank[pll_num].pllsr2) & + SRDS_PLLSR2_DCBIAS; + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; + + /* Step 4*/ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BYP_CAL); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + /* change the fcap and dcbias to the saved + * values from Step 3 */ + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_PLL_FCAP); + pllcr1 = (in_be32 + (&srds_regs->bank[pll_num].pllcr1)| + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + pllcr1); + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OVRD); + pllcr0 = (in_be32 + (&srds_regs->bank[pll_num].pllcr0)| + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pllcr0); + ret = calibrate_pll(srds_regs, pll_num); + if (ret) + return ret; + } else { + goto out; + } + } else { /* Step 5 */ + clrbits_be32(&srds_regs->bank[pll_num].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + udelay(10); + /* Change the fcap, dcbias, and bcap to the + * values from Step 1 */ + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BYP_CAL); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_PLL_FCAP); + pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr1, + pllcr1); + clrbits_be32(&srds_regs->bank[pll_num].pllcr0, + SRDS_PLLCR0_DCBIAS_OVRD); + pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); + out_be32(&srds_regs->bank[pll_num].pllcr0, + pllcr0); + clrbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_EN); + setbits_be32(&srds_regs->bank[pll_num].pllcr1, + SRDS_PLLCR1_BCAP_OVD); + ret = calibrate_pll(srds_regs, pll_num); + if (ret) + return ret; + } + } +out: + return 0; +} + +static int check_serdes_pll_locks(void) +{ + serdes_corenet_t *srds1_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds2_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + int i, ret1, ret2; + + debug("\nSerDes1 Lock check\n"); + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + ret1 = check_pll_locks(srds1_regs, i); + if (ret1) { + printf("SerDes1, PLL:%d didnt lock\n", i); + return ret1; + } + } + debug("\nSerDes2 Lock check\n"); + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { + ret2 = check_pll_locks(srds2_regs, i); + if (ret2) { + printf("SerDes2, PLL:%d didnt lock\n", i); + return ret2; + } + } + + return 0; +} + int config_serdes1_refclks(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -478,6 +654,8 @@ int config_serdes2_refclks(void) setbits_be32(&srds2_regs->bank[i].rstctl, (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B | SRDS_RSTCTL_SDRST_B)); + + udelay(10); } break; default: @@ -544,6 +722,21 @@ int board_early_init_r(void) else printf("SerDes2 Refclk reconfiguring failed.\n"); +#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A006475) + /* Rechecking the SerDes locks after all SerDes configurations + * are done, As SerDes PLLs may not lock reliably at 5 G VCO + * and at cold temperatures. + * Following sequence ensure the proper locking of SerDes PLLs. + */ + if (SVR_MAJ(get_svr()) == 1) { + if (check_serdes_pll_locks()) + printf("SerDes plls still not locked properly.\n"); + else + printf("SerDes plls have been locked well.\n"); + } +#endif + /* Configure VSC3316 and VSC3308 crossbar switches */ if (configure_vsc3316_3308()) printf("VSC:failed to configure VSC3316/3308.\n"); -- cgit v1.1 From 6b7679c8d2b92cd7e4e8dad6f2ff84ce36ec2c5e Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 6 Mar 2014 15:07:39 +0800 Subject: powerpc/t208xqds: fixup for t208xqds Change QIXIS timing parameter CONFIG_SYS_CS3_FTIM2 to 8 from 0. Fix EMI2 for t2080qds, which was caused by adding t2081qds. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t208xqds/eth_t208xqds.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 7d8411b..d7a804d 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -36,14 +36,15 @@ #define EMI1_SLOT3 3 #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 +#define EMI2 7 #elif defined(CONFIG_T2081QDS) #define EMI1_SLOT2 3 #define EMI1_SLOT3 4 #define EMI1_SLOT5 5 #define EMI1_SLOT6 6 #define EMI1_SLOT7 7 -#endif #define EMI2 8 +#endif static int mdio_mux[NUM_FM_PORTS]; -- cgit v1.1 From 8d67c3685e3b4bea8524e2e25b1443b62a69352b Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 5 Mar 2014 15:04:48 +0800 Subject: powerpc/t2080rdb: Add T2080PCIe-RDB board support T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/t208xrdb/Makefile | 13 ++ board/freescale/t208xrdb/README | 208 ++++++++++++++++++++++++++++++++ board/freescale/t208xrdb/cpld.c | 71 +++++++++++ board/freescale/t208xrdb/cpld.h | 42 +++++++ board/freescale/t208xrdb/ddr.c | 112 +++++++++++++++++ board/freescale/t208xrdb/ddr.h | 47 ++++++++ board/freescale/t208xrdb/eth_t208xrdb.c | 106 ++++++++++++++++ board/freescale/t208xrdb/law.c | 34 ++++++ board/freescale/t208xrdb/pci.c | 23 ++++ board/freescale/t208xrdb/t2080_pbi.cfg | 41 +++++++ board/freescale/t208xrdb/t2080_rcw.cfg | 8 ++ board/freescale/t208xrdb/t208xrdb.c | 124 +++++++++++++++++++ board/freescale/t208xrdb/t208xrdb.h | 13 ++ board/freescale/t208xrdb/tlb.c | 151 +++++++++++++++++++++++ 14 files changed, 993 insertions(+) create mode 100644 board/freescale/t208xrdb/Makefile create mode 100644 board/freescale/t208xrdb/README create mode 100644 board/freescale/t208xrdb/cpld.c create mode 100644 board/freescale/t208xrdb/cpld.h create mode 100644 board/freescale/t208xrdb/ddr.c create mode 100644 board/freescale/t208xrdb/ddr.h create mode 100644 board/freescale/t208xrdb/eth_t208xrdb.c create mode 100644 board/freescale/t208xrdb/law.c create mode 100644 board/freescale/t208xrdb/pci.c create mode 100644 board/freescale/t208xrdb/t2080_pbi.cfg create mode 100644 board/freescale/t208xrdb/t2080_rcw.cfg create mode 100644 board/freescale/t208xrdb/t208xrdb.c create mode 100644 board/freescale/t208xrdb/t208xrdb.h create mode 100644 board/freescale/t208xrdb/tlb.c (limited to 'board') diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile new file mode 100644 index 0000000..092c9ff --- /dev/null +++ b/board/freescale/t208xrdb/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T2080RDB) += t208xrdb.o +obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o +obj-$(CONFIG_T2080RDB) += cpld.o +obj-$(CONFIG_PCI) += pci.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README new file mode 100644 index 0000000..0012c6c --- /dev/null +++ b/board/freescale/t208xrdb/README @@ -0,0 +1,208 @@ +T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. +It can work in two mode: standalone mode and PCIe endpoint mode. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080PCIe-RDB board Overview +---------------------------- + - SERDES Configuration + - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) + - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) + - SerDes-2 Lane G-H: to SATA1 & SATA2 + - Ethernet + - Two on-board 10M/100M/1G RGMII ethernet ports + - Two on-board 10Gbps XFI fiber ports + - Two on-board 10Gbps Base-T copper ports + - DDR Memory + - Supports 72bit 4GB DDR3-LP SODIMM + - PCIe + - One PCIe x4 gold-finger + - One PCIe x4 connector + - One PCIe x2 end-point device (C293 Crypto co-processor) + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 512MB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - SATA + - Two SATA 2.0 onnectors on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one TF-card connector on-board + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +System Memory map +----------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T2080PCIe-RDB Ethernet Port Map +------------------------------- +Label In Uboot In Linux FMan Address Comments PHY +ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) +ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) +ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) +ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) +ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) +ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) + + +T2080PCIe-RDB Default DIP-Switch setting +---------------------------------------- +SW1[1:8] = '00010011' +SW2[1:8] = '10111111' +SW3[1:8] = '11100001' + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080RDB + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank and alternate bank on NOR flash + To change boot source to vbank4: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '011' + + To change boot source to vbank0: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '111' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080RDB_NAND_config + $ make u-boot.pbl + b. program u-boot.pbl to NAND flash + => tftp 1000000 u-boot.pbl + => nand erase 0 d0000 + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080RDB_SPIFLASH_config + $ make u-boot.pbl + b. program u-boot.pbl to SPI flash + => tftp 1000000 u-boot.pbl + => sf probe 0 + => sf erase 0 d0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080RDB_SDCARD_config + $ make u-boot.pbl + b. program u-boot.pbl to TF card + => tftp 1000000 u-boot.pbl + => mmc write 1000000 8 1650 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +How to update the ucode of Cortina CS4315/CS4340 10G PHY +-------------------------------------------------------- +=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt +=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080PCIe-RDB User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c new file mode 100644 index 0000000..4aa126b --- /dev/null +++ b/board/freescale/t208xrdb/cpld.c @@ -0,0 +1,71 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale T2080RDB board-specific CPLD controlling supports. + */ + +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" +); diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h new file mode 100644 index 0000000..4cee4e5 --- /dev/null +++ b/board/freescale/t208xrdb/cpld.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CPLD register set of T2080RDB board-specific. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - Chip ID1 register */ + u8 chip_id2; /* 0x01 - Chip ID2 register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl; /* 0x10 - Reset control Register */ + u8 flash_csr; /* 0x11 - Flash control and status register */ + u8 thermal_csr; /* 0x12 - Thermal control and status register */ + u8 led_csr; /* 0x13 - LED control and status register */ + u8 sfp_csr; /* 0x14 - SFP+ control and status register */ + u8 misc_csr; /* 0x15 - Misc control and status register */ + u8 boot_or; /* 0x16 - Boot config override register */ + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ +} cpld_data_t; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c new file mode 100644 index 0000000..01e9173 --- /dev/null +++ b/board/freescale/t208xrdb/ddr.c @@ -0,0 +1,112 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h new file mode 100644 index 0000000..b6d4062 --- /dev/null +++ b/board/freescale/t208xrdb/ddr.h @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c new file mode 100644 index 0000000..cbbc625 --- /dev/null +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -0,0 +1,106 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x66: + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); + fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); + fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); + break; + default: + printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c new file mode 100644 index 0000000..eb82431 --- /dev/null +++ b/board/freescale/t208xrdb/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c new file mode 100644 index 0000000..ba7041a --- /dev/null +++ b/board/freescale/t208xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg new file mode 100644 index 0000000..e200d92 --- /dev/null +++ b/board/freescale/t208xrdb/t2080_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg new file mode 100644 index 0000000..cd62cc8 --- /dev/null +++ b/board/freescale/t208xrdb/t2080_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T2080RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x66_0x16 +#Core/DDR: 1533Mhz/1600MT/s +120c0017 15000000 00000000 00000000 +66160002 00008400 ec104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c new file mode 100644 index 0000000..f3fec2a --- /dev/null +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -0,0 +1,124 @@ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "t208xrdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", ~reg & 0x7); + } +#endif + + puts("SERDES Reference Clocks:\n"); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h new file mode 100644 index 0000000..13380d0 --- /dev/null +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c new file mode 100644 index 0000000..085d9f5 --- /dev/null +++ b/board/freescale/t208xrdb/tlb.c @@ -0,0 +1,151 @@ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit v1.1 From 337b0c52b3296f371d04aef71a833e09110e0e6b Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 26 Feb 2014 16:11:53 +0530 Subject: powerpc/t1040qds: Add Video - HDMI support T1040 has internal display interface unit (DIU) for driving video. T1040QDS supports video mode via -LCD using TI enconder -HDMI type interface via HDMI encoder Chrontel, CH7301C encoder which is I2C programmable is used as HDMI connector on T1040QDS. This patch add support to -enable Video interface for T1040QDS -route qixis multiplexing to enable DIU-HDMI interface on board -program DIU pixel clock gerenartor for T1040 -program HDMI encoder via I2C on board Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- board/freescale/t1040qds/Makefile | 1 + board/freescale/t1040qds/diu.c | 215 ++++++++++++++++++++++++++++++ board/freescale/t1040qds/t1040qds.h | 1 + board/freescale/t1040qds/t1040qds_qixis.h | 12 ++ 4 files changed, 229 insertions(+) create mode 100644 board/freescale/t1040qds/diu.c (limited to 'board') diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index c7470d7..19ed21b 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o obj-y += eth.o +obj-y += diu.o diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c new file mode 100644 index 0000000..ffd074b --- /dev/null +++ b/board/freescale/t1040qds/diu.c @@ -0,0 +1,215 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Author: Priyanka Jain + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t1040qds.h" +#include "t1040qds_qixis.h" +#include + + +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 +#define I2C_DVI_PLL_DIVIDER_REG 0x34 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 +#define I2C_DVI_PLL_FILTER_REG 0x36 +#define I2C_DVI_TEST_PATTERN_REG 0x48 +#define I2C_DVI_POWER_MGMT_REG 0x49 +#define I2C_DVI_LOCK_STATE_REG 0x4D +#define I2C_DVI_SYNC_POLARITY_REG 0x56 + +/* + * Set VSYNC/HSYNC to active high. This is polarity of sync signals + * from DIU->DVI. The DIU default is active igh, so DVI is set to + * active high. + */ +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 + +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 + +/* Clear test pattern */ +#define I2C_DVI_TEST_PATTERN_VAL 0x18 +/* Exit Power-down mode */ +#define I2C_DVI_POWER_MGMT_VAL 0xC0 + +/* Monitor polarity is handled via DVI Sync Polarity Register */ +#define I2C_DVI_SYNC_POLARITY_VAL 0x00 + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +/* Programming of HDMI Chrontel CH7301 connector */ +int diu_set_dvi_encoder(unsigned int pixclock) +{ + int ret; + u8 temp; + select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + + temp = I2C_DVI_TEST_PATTERN_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select proper dvi test pattern\n"); + return ret; + } + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, + 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi input data format\n"); + return ret; + } + + /* Set Sync polarity register */ + temp = I2C_DVI_SYNC_POLARITY_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi syc polarity\n"); + return ret; + } + + /* Set PLL registers based on pixel clock rate*/ + if (pixclock > 65000000) { + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } else { + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll charge_cntl\n"); + return ret; + } + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll divider\n"); + return ret; + } + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); + if (ret) { + puts("I2C: failed to select dvi pll filter\n"); + return ret; + } + } + + temp = I2C_DVI_POWER_MGMT_VAL; + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, + &temp, 1); + if (ret) { + puts("I2C: failed to select dvi power mgmt\n"); + return ret; + } + + udelay(500); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; +} + +void diu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long speed_ccb, temp; + u32 pixval; + int ret = 0; + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + + /* Program HDMI encoder */ + ret = diu_set_dvi_encoder(temp); + if (ret) { + puts("Failed to set DVI encoder\n"); + return; + } + + /* Program pixel clock */ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, + ((pixval << PXCK_BITS_START) & PXCK_MASK)); + /* enable clock*/ + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | + ((pixval << PXCK_BITS_START) & PXCK_MASK)); +} + +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) +{ + u32 pixel_format; + u8 sw; + + /*Route I2C4 to DIU system as HSYNC/VSYNC*/ + sw = QIXIS_READ(brdcfg[5]); + QIXIS_WRITE(brdcfg[5], + ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); + + /*Configure Display ouput port as HDMI*/ + sw = QIXIS_READ(brdcfg[15]); + QIXIS_WRITE(brdcfg[15], + ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) + | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); + + + return fsl_diu_init(xres, yres, pixel_format, 0); +} diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h index 79bdeda..5041f37 100644 --- a/board/freescale/t1040qds/t1040qds.h +++ b/board/freescale/t1040qds/t1040qds.h @@ -9,5 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); +int select_i2c_ch_pca9547(u8 ch); #endif diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h index 2ce8795..98d2d39 100644 --- a/board/freescale/t1040qds/t1040qds_qixis.h +++ b/board/freescale/t1040qds/t1040qds_qixis.h @@ -13,6 +13,18 @@ #define BRDCFG4_EMISEL_MASK 0xE0 #define BRDCFG4_EMISEL_SHIFT 5 +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ +#define BRDCFG5_IMX_MASK 0xC0 +#define BRDCFG5_IMX_DIU 0x80 + +/* BRDCFG15[3] controls LCD Panel Powerdown*/ +#define BRDCFG15_LCDPD_MASK 0x10 +#define BRDCFG15_LCDPD_ENABLED 0x00 + +/* BRDCFG15[6:7] controls DIU MUX selction*/ +#define BRDCFG15_DIUSEL_MASK 0x03 +#define BRDCFG15_DIUSEL_HDMI 0x00 + /* SYSCLK */ #define QIXIS_SYSCLK_66 0x0 #define QIXIS_SYSCLK_83 0x1 -- cgit v1.1 From 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Wed, 26 Feb 2014 09:38:37 +0530 Subject: powerpc/t104xrdb: Update DDR initialization related settings Update following DDR related settings for T1040RDB, T1042RDB_PI -Correct number of chip selects to two as t1040 supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Update ddr_raw_timing sructure corresponding to DIMM. -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm, but on T104xRDB, on setting this , DDR instability is observed. Board-level debugging is in progress. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s. Signed-off-by: Priyanka Jain Signed-off-by: York Sun --- board/freescale/t104xrdb/ddr.c | 13 +++---------- board/freescale/t104xrdb/ddr.h | 38 ++++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 28 deletions(-) (limited to 'board') diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 9009afa..57d0f9c 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -46,7 +46,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp = udimms[0]; - /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr + /* Get clk_adjust according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -54,14 +54,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -74,13 +70,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -112,8 +105,8 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); } phys_size_t initdram(int board_type) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index 9276b59..09b30b9 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -6,7 +6,6 @@ #ifndef __DDR_H__ #define __DDR_H__ - dimm_params_t ddr_raw_timing = { .n_ranks = 2, .rank_density = 2147483648u, @@ -14,22 +13,21 @@ dimm_params_t ddr_raw_timing = { .primary_sdram_width = 64, .ec_sdram_width = 8, .registered_dimm = 0, - .mirrored_dimm = 1, + .mirrored_dimm = 0, .n_row_addr = 15, .n_col_addr = 10, .n_banks_per_sdram_device = 8, .edc_config = 2, /* ECC */ .burst_lengths_bitmask = 0x0c, - .tckmin_x_ps = 1071, - .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ - .taa_ps = 13910, + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */ + .taa_ps = 13125, .twr_ps = 15000, - .trcd_ps = 13910, + .trcd_ps = 13125, .trrd_ps = 6000, - .trp_ps = 13910, + .trp_ps = 13125, .tras_ps = 34000, - .trc_ps = 48910, + .trc_ps = 48125, .trfc_ps = 260000, .twtr_ps = 7500, .trtp_ps = 7500, @@ -45,9 +43,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -59,14 +54,21 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 */ - {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0}, - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, {} }; -- cgit v1.1 From 81724e09a018cf002be1bbb1a89b4b25e5b6f5c4 Mon Sep 17 00:00:00 2001 From: Andreas Henriksson Date: Mon, 27 Jan 2014 19:18:59 +0100 Subject: at91sam9263ek: add mmc support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for using the Atmel MCI driver on at91sam9263ek. This change is modeled after the existing at91sam9260ek support. Please note that this hooks up slot1 (MCI1) for SD. Not both. Tested with at91bootstrap and u-boot on dataflash in slot 0 and fat-formatted 8GB SDHC in slot 1 on first revision at91sam9263ek (which must use dataflash in slot0 to boot). CONFIG_ATMEL_MCI_PORTB not tested. Signed-off-by: Andreas Henriksson [remove empty line] Signed-off-by: Andreas Bießmann --- board/atmel/at91sam9263ek/at91sam9263ek.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board') diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index d42a173..4b14554 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -24,6 +24,7 @@ #include #endif #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -214,6 +215,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif + int board_early_init_f(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; -- cgit v1.1 From 7ca6f363251a36622c6561c968bc0989f96457b1 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Sun, 9 Feb 2014 15:52:39 +0800 Subject: ARM: atmel: add sama5d3 Xplained board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC. Now it supports boot from NAND flash and SD/MMC card. Features support: - NAND flash - SD/MMC card - Two USB hosts - Ethernet (one GMAC, one EMAC) Signed-off-by: Bo Shen [reorder boards.cfg] Signed-off-by: Andreas Bießmann --- board/atmel/sama5d3_xplained/Makefile | 15 +++ board/atmel/sama5d3_xplained/sama5d3_xplained.c | 130 ++++++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 board/atmel/sama5d3_xplained/Makefile create mode 100644 board/atmel/sama5d3_xplained/sama5d3_xplained.c (limited to 'board') diff --git a/board/atmel/sama5d3_xplained/Makefile b/board/atmel/sama5d3_xplained/Makefile new file mode 100644 index 0000000..ec82b06 --- /dev/null +++ b/board/atmel/sama5d3_xplained/Makefile @@ -0,0 +1,15 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# (C) Copyright 2014 +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d3_xplained.o diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c new file mode 100644 index 0000000..39f2dc6 --- /dev/null +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2014 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_ATMEL +void sama5d3_xplained_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | + AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | + AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); +} +#endif + +#ifdef CONFIG_CMD_USB +static void sama5d3_xplained_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTE, 3, 0); + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +static void sama5d3_xplained_mci0_hw_init(void) +{ + at91_mci_hw_init(); + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ +} +#endif + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + sama5d3_xplained_nand_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + sama5d3_xplained_usb_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + sama5d3_xplained_mci0_hw_init(); +#endif +#ifdef CONFIG_MACB + at91_gmac_hw_init(); + at91_macb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_MACB + macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); + macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return 0; +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + atmel_mci_init((void *)ATMEL_BASE_MCI0); + + return 0; +} +#endif -- cgit v1.1 From 8a45b0ba87649b1bad459fb235a843f5588a8251 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 3 Mar 2014 14:47:15 +0800 Subject: arm: atmel: sama5d3: add spi spl boot support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SPI SPL boot support for sama5d3xek board. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- board/atmel/sama5d3xek/sama5d3xek.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index eff94a4..8a214de 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -307,6 +307,8 @@ void spl_board_init(void) { #ifdef CONFIG_SYS_USE_MMC sama5d3xek_mci_hw_init(); +#elif CONFIG_SYS_USE_SERIALFLASH + at91_spi0_hw_init(1 << 0); #endif } -- cgit v1.1 From 27019e4a949fc3be2e895ac20839c4d4d119f902 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 3 Mar 2014 14:47:17 +0800 Subject: arm: atmel: sama5d3: add nand spl boot support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add NAND SPL boot support with hardware PMECC. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- board/atmel/sama5d3xek/sama5d3xek.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 8a214de..c835c12 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -307,6 +307,8 @@ void spl_board_init(void) { #ifdef CONFIG_SYS_USE_MMC sama5d3xek_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3xek_nand_hw_init(); #elif CONFIG_SYS_USE_SERIALFLASH at91_spi0_hw_init(1 << 0); #endif -- cgit v1.1 From ba650e9b5263bfc7579e6775676441eeeca2edc4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 21 Feb 2014 09:55:16 +0900 Subject: m68k: Remove M5271EVB and idmr board support CONFIG_SYS_HZ must be always 1000, but M5271EVB.h defines it as 1000000 and idmr.h defines it as (50000000 / 64). When compiling these two boards, a warning message is displayed: time.c:14:2: warning: #warning "CONFIG_SYS_HZ must be 1000 and should not be defined by platforms" [-Wcpp] There are no board maintainers for them so this commit just deletes them. Signed-off-by: Masahiro Yamada Cc: Jason Jin --- board/freescale/m5271evb/Makefile | 8 - board/freescale/m5271evb/config.mk | 9 - board/freescale/m5271evb/m5271evb.c | 115 ------------ board/freescale/m5271evb/u-boot.lds | 85 --------- board/idmr/Makefile | 8 - board/idmr/config.mk | 9 - board/idmr/flash.c | 342 ------------------------------------ board/idmr/idmr.c | 152 ---------------- board/idmr/u-boot.lds | 82 --------- 9 files changed, 810 deletions(-) delete mode 100644 board/freescale/m5271evb/Makefile delete mode 100644 board/freescale/m5271evb/config.mk delete mode 100644 board/freescale/m5271evb/m5271evb.c delete mode 100644 board/freescale/m5271evb/u-boot.lds delete mode 100644 board/idmr/Makefile delete mode 100644 board/idmr/config.mk delete mode 100644 board/idmr/flash.c delete mode 100644 board/idmr/idmr.c delete mode 100644 board/idmr/u-boot.lds (limited to 'board') diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile deleted file mode 100644 index 77138c6..0000000 --- a/board/freescale/m5271evb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = m5271evb.o diff --git a/board/freescale/m5271evb/config.mk b/board/freescale/m5271evb/config.mk deleted file mode 100644 index 957f584..0000000 --- a/board/freescale/m5271evb/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xffe00000 diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c deleted file mode 100644 index 5981a27..0000000 --- a/board/freescale/m5271evb/m5271evb.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int checkboard (void) { - puts ("Board: Freescale M5271EVB\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - - int i; - - /* Enable Address lines 23-21 and lower 16bits of data path */ - mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | - MCF_GPIO_AD_DATAL); - - /* Set CS2 pin to be SD_CS0 */ - mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) - | MCF_GPIO_PAR_CS_PAR_CS2); - - /* Configure SDRAM Control Pin Assignemnt Register */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | - MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_11); - asm(" nop"); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(2) - | MCF_SDRAMC_DCR_RC(0x2E)); - asm(" nop"); - - /* - * Initialize DACR0 - * - * CASL: 01 - * CBM: cmd at A20, bank select bits 21 and up - * PS: 32bit port size - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) - | MCF_SDRAMC_DACRn_CASL(1) - | MCF_SDRAMC_DACRn_CBM(3) - | MCF_SDRAMC_DACRn_PS(0)); - asm(" nop"); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M - | MCF_SDRAMC_DMRn_V); - asm(" nop"); - - /* Set IP bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_IP); - asm(" nop"); - - /* Wait at least 20ns to allow banks to precharge */ - for (i = 0; i < 5; i++) - asm(" nop"); - - /* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; - asm(" nop"); - - /* Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_RE); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) - | MCF_SDRAMC_DACRn_MRS); - asm(" nop"); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 2 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; - asm(" nop"); - } - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds deleted file mode 100644 index 3defcd2..0000000 --- a/board/freescale/m5271evb/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/idmr/Makefile b/board/idmr/Makefile deleted file mode 100644 index 67c2384..0000000 --- a/board/idmr/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = idmr.o flash.o diff --git a/board/idmr/config.mk b/board/idmr/config.mk deleted file mode 100644 index 840a37e..0000000 --- a/board/idmr/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0xff800000 diff --git a/board/idmr/flash.c b/board/idmr/flash.c deleted file mode 100644 index 52eb105..0000000 --- a/board/idmr/flash.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE 0x800000 -#define EN29LV640 0x227e227e - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (EN29LV640 & FLASH_TYPEMASK): - printf ("EN29LV640 (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (EN29LV640 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + 0x10000 * j; - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, prot, sect; - int rc = ERR_OK; - int chip1; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - printf("Waiting 10 ms..."); - udelay (10000); - -/* for (i = 0; i < 10 * 1000 * 1000; ++i) - asm(" nop"); -*/ - - printf("done\n"); - if (iflag) - enable_interrupts (); - - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - int chip1; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c deleted file mode 100644 index 73660d8..0000000 --- a/board/idmr/idmr.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -int checkboard (void) { - puts ("Board: iDMR\n"); - return 0; -}; - -phys_size_t initdram (int board_type) { - int i; - - /* - * After reset, CS0 is configured to cover entire address space. We - * need to configure it to its proper values, so that writes to - * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do - * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). - */ - - /* Flash chipselect, CS0 */ - /* ;CSAR0: Flash at 0xFF800000 */ - mbar_writeShort(0x0080, 0xFF80); - - /* CSCR0: Flash 6 waits, 16bit */ - mbar_writeShort(0x008A, 0x1980); - - /* CSMR0: Flash 8MB, R/W, valid */ - mbar_writeLong(0x0084, 0x007F0001); - - - /* - * SDRAM configuration proper - */ - - /* - * Address/Data Pin Assignment Reg.: enable address lines 23-21; do - * not enable data pins D[15:0], as we have 16 bit port to SDRAM - */ - mbar_writeByte(MCF_GPIO_PAR_AD, - MCF_GPIO_AD_ADDR23 | - MCF_GPIO_AD_ADDR22 | - MCF_GPIO_AD_ADDR21); - - /* No need to configure BS pins - reset values are OK */ - - /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */ - mbar_writeByte(MCF_GPIO_PAR_CS, 0x00); - - /* SDRAM Control Pin Assignment Reg. */ - mbar_writeByte(MCF_GPIO_PAR_SDRAM, - MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */ - MCF_GPIO_SDRAM_SDWE | - MCF_GPIO_SDRAM_SCAS | - MCF_GPIO_SDRAM_SRAS | - MCF_GPIO_SDRAM_SCKE | - MCF_GPIO_SDRAM_SDCS_01); - - /* - * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5 - * iterations will do, but we do 10 just to be safe. - */ - for (i = 0; i < 10; ++i) - asm(" nop"); - - - /* 1. Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */ - MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */ - - - /* - * 2. Initialize DACR0 - * - * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1) - * CBM: cmd at A20, bank select bits 21 and up - * PS: 16 bit - */ - mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | - MCF_SDRAMC_DACRn_BA(0x00) | - MCF_SDRAMC_DACRn_CASL(0x03) | - MCF_SDRAMC_DACRn_CBM(0x03) | - MCF_SDRAMC_DACRn_PS(0x03)); - - /* Initialize DMR0 */ - mbar_writeLong(MCF_SDRAMC_DMR0, - MCF_SDRAMC_DMRn_BAM_16M | - MCF_SDRAMC_DMRn_V); - - - /* 3. Set IP bit in DACR to initiate PALL command */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_IP); - - /* Write to this block to initiate precharge */ - *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; - - /* - * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We - * wait a wee longer, just to be safe. - */ - for (i = 0; i < 5; ++i) - asm(" nop"); - - - /* 4. Set RE bit in DACR */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_RE); - - /* - * Wait for at least 8 auto refresh cycles to occur, i.e. at least - * 781 bus cycles. - */ - for (i = 0; i < 1000; ++i) - asm(" nop"); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCF_SDRAMC_DACR0, - mbar_readLong(MCF_SDRAMC_DACR0) | - MCF_SDRAMC_DACRn_MRS); - - /* - * Write to the SDRAM Mode Register A0-A11 = 0x400 - * - * Write Burst Mode = Programmed Burst Length - * Op Mode = Standard Op - * CAS Latency = 3 - * Burst Type = Sequential - * Burst Length = 1 - */ - *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -}; - - -int testdram (void) { - - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds deleted file mode 100644 index 4071f70..0000000 --- a/board/idmr/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(m68k) - -SECTIONS -{ - .text : - { - arch/m68k/cpu/mcf52x2/start.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - - .reloc : - { - __got_start = .; - KEEP(*(.got)) - __got_end = .; - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - _sbss = .; - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - _ebss = .; - } - __bss_end = . ; - PROVIDE (end = .); -} -- cgit v1.1 From b946322670ca8eda2d41c854a00a863076df6446 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 7 Mar 2014 01:20:57 +0000 Subject: highbank: use scsi_init hook Signed-off-by: Ian Campbell Acked-by: Rob Herring --- board/highbank/highbank.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 371b0a2..a1b6749 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -51,17 +51,23 @@ int board_eth_init(bd_t *bis) return rc; } -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) { - char envbuffer[16]; - u32 boot_choice; u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); if (reg & PWRDOM_STAT_SATA) { ahci_init(HB_AHCI_BASE); scsi_scan(1); } +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char envbuffer[16]; + u32 boot_choice; boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; sprintf(envbuffer, "bootcmd%d", boot_choice); -- cgit v1.1 From eb838e7d84a5211ccca0662297b4dfd1cc29e9df Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 13 Feb 2014 21:15:18 -0700 Subject: usb: create common header virtual root hub descriptors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange Cc: Shinya Kuribayashi Cc: Gary Jennejohn Cc: Wolfgang Denk Cc: Eric Millbrandt Cc: Pierre Aubert Cc: Stefan Roese Cc: Daniel Hellstrom Cc: Denis Peter Cc: Rodolfo Giometti Cc: Zhang Wei Cc: Mateusz Zalega Cc: Remy Bohmer Cc: Markus Klotzbuecher Cc: Minkyu Kang Cc: Gary Jennejohn Cc: C Nauman Cc: David Müller Cc: Yoshihiro Shimoda Cc: Nobuhiro Iwamatsu Cc: Thomas Abraham Cc: Tom Rini Cc: Andrew Murray Cc: Matej Frančeškin Cc: Cliff Cai Cc: Bryan Wu Signed-off-by: Stephen Warren --- board/mpl/common/usb_uhci.c | 115 ++------------------------------------------ 1 file changed, 3 insertions(+), 112 deletions(-) (limited to 'board') diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 6bbb527..5590be1 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -640,118 +640,9 @@ static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} static void usb_display_Req(unsigned short req) {} #endif -static unsigned char root_hub_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x00, /* __u16 bcdUSB; v1.0 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x01, /* __u8 iManufacturer; */ - 0x00, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - - -/* Configuration descriptor */ -static unsigned char root_hub_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - - -static unsigned char root_hub_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x02, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -static unsigned char root_hub_str_index0[] = -{ - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = -{ - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'U', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - +#define WANT_USB_ROOT_HUB_HUB_DES +#include +#undef WANT_USB_ROOT_HUB_HUB_DES /* * Root Hub Control Pipe (interrupt Pipes are not supported) -- cgit v1.1 From 4c1dd998523633c8649c6e322ffe6f625dcc234e Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:42 +0100 Subject: board:samsung: move checkboard to common file The checkboard function's implementation is common for all DT supporting boards and should be placed in the board common file. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Chander Kashyap Cc: Rajeshwari S Shinde Cc: Amar Acked-by: Rajeshwari Shinde Signed-off-by: Minkyu Kang --- board/samsung/common/board.c | 12 ++++++++++++ board/samsung/smdk5250/exynos5-dt.c | 15 --------------- board/samsung/smdk5420/smdk5420.c | 15 --------------- 3 files changed, 12 insertions(+), 30 deletions(-) (limited to 'board') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index cd873bc..f8562b2 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -377,7 +377,19 @@ int board_mmc_init(bd_t *bis) return ret; } #endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_name; + + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Board: %s\n", board_name ? board_name : "unknown"); + + return 0; +} #endif +#endif /* CONFIG_OF_CONTROL */ #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 5fb8664..b22fba5 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -45,21 +45,6 @@ int exynos_init(void) return 0; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); - - return 0; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 3ad2ad0..e4606ec 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -142,18 +142,3 @@ int board_get_revision(void) { return 0; } - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); - - return 0; -} -#endif -- cgit v1.1 From 8e5e1e6a92acfa465d993ab099ca1c54c4cadc8d Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:43 +0100 Subject: arm:exynos: add common DTS file for exynos 4 This patch adds common dtsi file and config header for all Exynos 4 based boards. Patch additionaly adds board specific (weak) functions for board_early_init_f and board_power_init functions. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- board/samsung/common/board.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index f8562b2..cf78d36 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -33,6 +33,20 @@ struct local_info { static struct local_info local; +int __exynos_early_init_f(void) +{ + return 0; +} +int exynos_early_init_f(void) + __attribute__((weak, alias("__exynos_early_init_f"))); + +int __exynos_power_init(void) +{ + return 0; +} +int exynos_power_init(void) + __attribute__((weak, alias("__exynos_power_init"))); + #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ static void boot_temp_check(void) @@ -140,7 +154,7 @@ int board_early_init_f(void) board_i2c_init(gd->fdt_blob); #endif - return err; + return exynos_early_init_f(); } #endif @@ -284,7 +298,7 @@ int power_init_board(void) ret = max77686_init(); #endif - return ret; + return exynos_power_init(); } #endif -- cgit v1.1 From d31b3888597f0b0b32363ed6693436b41827c865 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:44 +0100 Subject: board:samsung:common: move max77686 init function This patch moves board specific max77686 init function from common board to smdk5250 board file. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Rajeshwari S Shinde Cc: Rajeshwari Birje Signed-off-by: Minkyu Kang --- board/samsung/common/board.c | 120 ------------------------------------ board/samsung/smdk5250/smdk5250.c | 125 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 120 deletions(-) (limited to 'board') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index cf78d36..a74b044 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -22,7 +22,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -175,129 +174,10 @@ static int board_init_cros_ec_devices(const void *blob) #endif #if defined(CONFIG_POWER) -#ifdef CONFIG_POWER_MAX77686 -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -static int max77686_init(void) -{ - struct pmic *p; - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - int power_init_board(void) { - int ret = 0; - set_ps_hold_ctrl(); -#ifdef CONFIG_POWER_MAX77686 - ret = max77686_init(); -#endif - return exynos_power_init(); } #endif diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index a69f73d..28a6d9e 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -147,6 +147,131 @@ void board_i2c_init(const void *blob) } } +#if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +static int max77686_init(void) +{ + struct pmic *p; + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif /* CONFIG_POWER_MAX77686 */ + +int exynos_power_init(void) +{ + int ret = 0; + +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); +#endif + return ret; +} +#endif /* CONFIG_POWER */ + #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { -- cgit v1.1 From 431a1c569c56ee8f4c0c78015b1a53b64784ff53 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:45 +0100 Subject: arm:exynos: enable sdhci and misc_init to common board This patch enables sdhci initialisation and misc_init_r in common board file for all exynos 4 based boards. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- board/samsung/common/board.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'board') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index a74b044..e95e9c4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -183,6 +185,7 @@ int power_init_board(void) #endif #ifdef CONFIG_OF_CONTROL +#ifdef CONFIG_SMC911X static int decode_sromc(const void *blob, struct fdt_sromc *config) { int err; @@ -206,6 +209,7 @@ static int decode_sromc(const void *blob, struct fdt_sromc *config) } return 0; } +#endif int board_eth_init(bd_t *bis) { @@ -263,10 +267,18 @@ int board_mmc_init(bd_t *bis) { int ret; +#ifdef CONFIG_SDHCI + /* mmc initializattion for available channels */ + ret = exynos_mmc_init(gd->fdt_blob); + if (ret) + debug("mmc init failed\n"); +#endif +#ifdef CONFIG_DWMMC /* dwmmc initializattion for available channels */ ret = exynos_dwmmc_init(gd->fdt_blob); if (ret) debug("dwmmc init failed\n"); +#endif return ret; } @@ -315,3 +327,21 @@ int arch_early_init_r(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif -- cgit v1.1 From bf7716d6a35aceb5cc92330aeed31594aea06d59 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:46 +0100 Subject: board:origen: Enable device tree on Origen This patch enables to run Origen board on device tree. Uart, DRAM and MMC init functions are removed as their generic replacements form the common board file are used. The config file is modified to contain only board specific options. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Cc: Chander Kashyap Signed-off-by: Minkyu Kang --- board/samsung/origen/origen.c | 112 ++++-------------------------------------- 1 file changed, 9 insertions(+), 103 deletions(-) (limited to 'board') diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index 15f77ca..d502f02 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -11,129 +11,35 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; -int board_init(void) +u32 get_board_rev(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } -static int board_uart_init(void) +int exynos_init(void) { - int err; - - err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); - if (err) { - debug("UART0 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); - if (err) { - debug("UART1 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); - if (err) { - debug("UART2 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - if (err) { - debug("UART3 not configured\n"); - return err; - } - return 0; } -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - return err; -} -#endif - -int dram_init(void) +int board_usb_init(int index, enum usb_init_type init) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) - + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) - + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ - PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ - PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ - PHYS_SDRAM_4_SIZE); -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) +#ifdef CONFIG_USB_CABLE_CHECK +int usb_cable_connected(void) { - printf("\nBoard: ORIGEN\n"); return 0; } #endif -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) +#ifdef CONFIG_BOARD_EARLY_INIT_F +int exynos_early_init_f(void) { - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); - - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); - } - - err = s5p_mmc_init(2, 4); - return err; + return 0; } #endif -- cgit v1.1 From 3f41ffe4b5b544acaa43aca52ea22a0ce76680b5 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:47 +0100 Subject: board:universal: Enable device tree on Universal This patch enables to run Universal board on device tree. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Acked-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/universal_c210/universal.c | 204 ++++++++----------------------- 1 file changed, 53 insertions(+), 151 deletions(-) (limited to 'board') diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 96da7e0..f9d71b6 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -13,16 +13,17 @@ #include #include #include -#include #include #include -#include #include #include +#include #include #include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -42,7 +43,7 @@ static int get_hwrev(void) static void init_pmic_lcd(void); -int power_init_board(void) +int exynos_power_init(void) { int ret; @@ -59,22 +60,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -} - static unsigned short get_adc_value(int channel) { struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); @@ -159,71 +144,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tUniversal C210\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err; - - switch (get_hwrev()) { - case 0: - /* - * Set the low to enable LDO_EN - * But when you use the test board for eMMC booting - * you should set it HIGH since it removes the inverter - */ - /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); - break; - default: - /* - * Default reset state is High and there's no inverter - * But set it as HIGH to ensure - */ - /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); - break; - } - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; - -} -#endif - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -271,7 +191,20 @@ struct s3c_plat_otg_data s5pc210_otg_data = { }; #endif -int board_early_init_f(void) +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); +} + +#ifdef CONFIG_USB_CABLE_CHECK +int usb_cable_connected(void) +{ + return 0; +} +#endif + +int exynos_early_init_f(void) { wdt_stop(); @@ -412,6 +345,11 @@ void exynos_cfg_lcd_gpio(void) spi_init(); } +int mipi_power(void) +{ + return 0; +} + void exynos_reset_lcd(void) { s5p_gpio_set_value(&gpio2->y4, 5, 1); @@ -436,39 +374,6 @@ void exynos_lcd_power_on(void) pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 480, - .vl_row = 800, - .vl_width = 480, - .vl_height = 800, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - - .vl_bpix = 4, /* Bits per pixel */ - - /* LD9040 LCD Panel */ - .vl_hspw = 2, - .vl_hbpd = 16, - .vl_hfpd = 16, - - .vl_vspw = 2, - .vl_vbpd = 8, - .vl_vfpd = 8, - .vl_cmd_allow_len = 0xf, - - .win_id = 0, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 10000, - .reset_delay = 10000, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 0, -}; - void exynos_cfg_ldo(void) { ld9040_cfg_ldo(); @@ -479,30 +384,32 @@ void exynos_enable_ldo(unsigned int onoff) ld9040_enable_ldo(onoff); } -void init_panel_info(vidinfo_t *vid) -{ - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; - -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif - - /* for LD9040. */ - vid->pclk_name = 1; /* MPLL */ - vid->sclk_div = 1; - - setenv("lcdinfo", "lcd=ld9040"); -} - -int board_init(void) +int exynos_init(void) { gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + switch (get_hwrev()) { + case 0: + /* + * Set the low to enable LDO_EN + * But when you use the test board for eMMC booting + * you should set it HIGH since it removes the inverter + */ + /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ + s5p_gpio_direction_output(&gpio1->e3, 6, 0); + break; + default: + /* + * Default reset state is High and there's no inverter + * But set it as HIGH to ensure + */ + /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ + s5p_gpio_direction_output(&gpio1->e1, 3, 1); + break; + } #ifdef CONFIG_SOFT_SPI soft_spi_init(); @@ -513,20 +420,15 @@ int board_init(void) return 0; } -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) +void exynos_lcd_misc_init(vidinfo_t *vid) { -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); -#endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); +#ifdef CONFIG_TIZEN + get_tizen_logo_info(vid); #endif - return 0; + + /* for LD9040. */ + vid->pclk_name = 1; /* MPLL */ + vid->sclk_div = 1; + + setenv("lcdinfo", "lcd=ld9040"); } -#endif -- cgit v1.1 From fe60164792e56aba74a2c4b8170612806a50f552 Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:48 +0100 Subject: board:trats: Enable device tree on Trats This patch enables to run Trats board on device tree. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park CC: Lukasz Majewski Signed-off-by: Minkyu Kang --- board/samsung/trats/trats.c | 213 +++----------------------------------------- 1 file changed, 10 insertions(+), 203 deletions(-) (limited to 'board') diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index b725505..7c79e7b 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -12,23 +12,20 @@ #include #include #include -#include #include #include -#include #include #include #include #include #include #include -#include #include #include #include +#include #include #include -#include #include "setup.h" @@ -46,10 +43,8 @@ u32 get_board_rev(void) static void check_hw_revision(void); struct s3c_plat_otg_data s5pc210_otg_data; -int board_init(void) +int exynos_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; - check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); @@ -281,7 +276,7 @@ static int pmic_init_max8997(void) return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg, ret; struct power_battery *pb; @@ -350,28 +345,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - static unsigned int get_hw_revision(void) { struct exynos4_gpio_part1 *gpio = @@ -404,55 +377,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int err; - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio->k0, 2, 1); - s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; -} -#endif #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) @@ -599,38 +523,22 @@ static void board_power_init(void) writel(0, (unsigned int)&pwr->arm_core1_configuration); } -static void board_uart_init(void) +static void exynos_uart_init(void) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int i; - - /* - * UART2 GPIOs - * GPA1CON[0] = UART_2_RXD(2) - * GPA1CON[1] = UART_2_TXD(2) - * GPA1CON[2] = I2C_3_SDA (3) - * GPA1CON[3] = I2C_3_SCL (3) - */ - - for (i = 0; i < 4; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); - } /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); s5p_gpio_direction_output(&gpio2->y4, 7, 1); } -int board_early_init_f(void) +int exynos_early_init_f(void) { wdt_stop(); pmic_reset(); board_clock_init(); - board_uart_init(); + exynos_uart_init(); board_power_init(); return 0; @@ -648,7 +556,7 @@ void exynos_reset_lcd(void) s5p_gpio_direction_output(&gpio2->y4, 5, 1); } -static int lcd_power(void) +int lcd_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -671,46 +579,7 @@ static int lcd_power(void) return 0; } -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&s6e8ax0_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -733,75 +602,13 @@ static int mipi_power(void) return 0; } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 1, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1, - vid->resolution = HD_RESOLUTION, - vid->rgb_mode = MODE_RGB_P, - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - mipi_lcd_device.reverse_panel = 1; - - strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); - s6e8ax0_platform_data.lcd_power = lcd_power; - s6e8ax0_platform_data.mipi_power = mipi_power; - s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; - s6e8ax0_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - exynos_set_dsim_platform_data(&s6e8ax0_platform_data); - setenv("lcdinfo", "lcd=s6e8ax0"); -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); #endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); -#endif - return 0; } -#endif -- cgit v1.1 From 1ecab0f30f9051821fdb5ec1c689b7c531b4feda Mon Sep 17 00:00:00 2001 From: Piotr Wilczek Date: Fri, 7 Mar 2014 14:59:49 +0100 Subject: board:trats2: Enable device tree on Trats2 This patch enables to run Trats2 board on device tree. Signed-off-by: Piotr Wilczek Signed-off-by: Kyungmin Park Signed-off-by: Minkyu Kang --- board/samsung/trats2/trats2.c | 233 ++---------------------------------------- 1 file changed, 10 insertions(+), 223 deletions(-) (limited to 'board') diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index c17c24d..2a6c9f9 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -8,15 +8,9 @@ #include #include -#include -#include -#include -#include -#include -#include -#include #include #include +#include #include #include #include @@ -28,7 +22,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -69,16 +62,6 @@ static void check_hw_revision(void) board_rev = modelrev << 8; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS2\n"); - printf("HW Revision:\t0x%04x\n", board_rev); - - return 0; -} -#endif - u32 get_board_rev(void) { return board_rev; @@ -156,33 +139,24 @@ int get_soft_i2c_sda_pin(void) } #endif -int board_early_init_f(void) +int exynos_early_init_f(void) { - check_hw_revision(); board_external_gpio_init(); - gd->flags |= GD_FLG_DISABLE_CONSOLE; - return 0; } static int pmic_init_max77686(void); -int board_init(void) +int exynos_init(void) { - struct exynos4_power *pwr = - (struct exynos4_power *)samsung_get_base_power(); - - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - /* workaround: clear INFORM4..5 */ - writel(0, (unsigned int)&pwr->inform4); - writel(0, (unsigned int)&pwr->inform5); + check_hw_revision(); + printf("HW Revision:\t0x%04x\n", board_rev); return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg; struct power_battery *pb; @@ -248,90 +222,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - u32 size_mb; - - size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20; - - gd->ram_size = size_mb << 20; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - -int board_mmc_init(bd_t *bis) -{ - int err0, err2 = 0; - - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio2->k0, 2, 1); - s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); - - /* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) - */ - - err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - if (err0) - debug("SDMMC0 not configured\n"); - else - err0 = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err2) - debug("SDMMC2 not configured\n"); - else - err2 = s5p_mmc_init(2, 4); - } - - return err0 & err2; -} - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -479,46 +369,7 @@ static int pmic_init_max77686(void) */ #ifdef CONFIG_LCD -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim dsim_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&dsim_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { struct pmic *p = pmic_get("MAX77686_PMIC"); @@ -556,77 +407,13 @@ void exynos_reset_lcd(void) s5p_gpio_set_value(&gpio1->f2, 1, 1); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - .mipi_enabled = 1, - - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 25, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; - - vid->power_on_delay = 30; - - mipi_lcd_device.reverse_panel = 1; - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - - strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name); - dsim_platform_data.mipi_power = mipi_power; - dsim_platform_data.phy_enable = set_mipi_phy_ctrl; - dsim_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); - +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - - exynos_set_dsim_platform_data(&dsim_platform_data); -} -#endif /* LCD */ - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); #endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); -#endif - return 0; } -#endif +#endif /* LCD */ -- cgit v1.1 From ec716e33d6ce46c9b60db4cf35af81d8812b414e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 12 Mar 2014 10:45:41 +0100 Subject: arm: am335x: DXR2: Move unconditional LAN9303 reset into command The switch HW reset results in a disconnection of the switch port daisy- chain for a few seconds. This is not desired in the normal field use case. So lets remove this switch reset from the normal bootup sequence and move it into a board specific command. This way it can be executed in the development environment when really needed. Signed-off-by: Stefan Roese Cc: Roger Meier Cc: Lukas Stockmann Cc: Tom Rini --- board/siemens/dxr2/board.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 2172379..38ac93d 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -232,13 +232,6 @@ int board_eth_init(bd_t *bis) factoryset_setenv(); - /* Reset SMSC LAN9303 switch for default configuration */ - gpio_request(GPIO_LAN9303_NRST, "nRST"); - gpio_direction_output(GPIO_LAN9303_NRST, 0); - /* assert active low reset for 200us */ - udelay(200); - gpio_set_value(GPIO_LAN9303_NRST, 1); - /* Set rgmii mode and enable rmii clock to be sourced from chip */ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); @@ -249,6 +242,25 @@ int board_eth_init(bd_t *bis) n += rv; return n; } + +static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + + return 0; +}; + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, + "Reset LAN9303 switch via its reset pin", + "" +); #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ -- cgit v1.1 From aadf3192f83a55dbbdb0d395ee5af88b6560edcb Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Sat, 8 Mar 2014 19:09:32 +0100 Subject: board/BuR/kwb: fix usage of 'i2c_set_bus_speed' - fix: return-value of 'i2c_set_bus_speed' was interpreted wrong Signed-off-by: Hannes Petermaier --- board/BuR/kwb/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 8aa16bc..804765a 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -120,7 +120,7 @@ void am33xx_spl_board_init(void) /* power-ON 3V3 via Resetcontroller */ oldspeed = i2c_get_bus_speed(); - if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) { + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { buf = RSTCTRL_FORCE_PWR_NEN; i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, (uint8_t *)&buf, sizeof(buf)); @@ -221,7 +221,7 @@ int board_late_init(void) TPS65217_WLEDCTRL1, 0x09, 0xFF); /* write bootinfo into scratchregister of resetcontroller */ oldspeed = i2c_get_bus_speed(); - if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) { + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, (uint8_t *)&buf, sizeof(buf)); i2c_set_bus_speed(oldspeed); -- cgit v1.1 From 22dbf14f5dfcc7295f8e562898a49ffb3608d08c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 11 Mar 2014 11:05:12 +0900 Subject: kbuild: use short logs for some board specific make rules Signed-off-by: Masahiro Yamada Cc: David Updegraff Cc: Andre Schwarz --- board/cray/L1/Makefile | 15 ++++++++++++--- board/matrix_vision/mvblm7/Makefile | 8 +++++++- board/matrix_vision/mvsmr/Makefile | 8 +++++++- 3 files changed, 26 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index 63f43da..655f530 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -9,10 +9,19 @@ obj-y = L1.o flash.o obj-y += init.o obj-y += bootscript.o -$(obj)/bootscript.c: $(obj)/bootscript.image - od -t x1 -v -A x $^ | awk -f $(srctree)/$(src)/x2c.awk > $@ +quiet_cmd_awk = AWK $@ + cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@ +$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk + $(call cmd,awk) + +quiet_cmd_mkimage = UIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \ + -a 0 -e 0 -n bootscript $(obj)/bootscript.image: $(src)/bootscript.hush - -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $< $@ + $(call cmd,mkimage) clean-files := bootscript.c bootscript.image \ No newline at end of file diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index 1bc1d61..b5987fd 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -8,5 +8,11 @@ obj-y := mvblm7.o pci.o fpga.o extra-y := bootscript.img +quiet_cmd_mkimage = UIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script + $(obj)/bootscript.img: $(src)/bootscript - @mkimage -T script -C none -n M7_script -d $< $@ + $(call cmd,mkimage) diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index 9454259..fae7ec2 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -12,5 +12,11 @@ obj-y := mvsmr.o fpga.o extra-y := bootscript.img +quiet_cmd_mkimage = UIMAGE $@ +cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script + $(obj)/bootscript.img: $(src)/bootscript - @mkimage -T script -C none -n mvSMR_Script -d $< $@ + $(call cmd,mkimage) -- cgit v1.1 From 4379ac614809da2128f8bc1f62e3dde4daaf7deb Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 11 Mar 2014 11:05:19 +0900 Subject: kbuild: rename TOPDIR to stctree Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for pointing to the top of source directory. (No difference between the two.) In Kbuild style, $(srctree) is used instead. This commit renames TOPDIR to srctree and delete the defition of TOPDIR. Signed-off-by: Masahiro Yamada --- board/hymod/config.mk | 2 +- board/korat/config.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/hymod/config.mk b/board/hymod/config.mk index ee15890..2eeea50 100644 --- a/board/hymod/config.mk +++ b/board/hymod/config.mk @@ -9,6 +9,6 @@ # HYMOD boards # -PLATFORM_CPPFLAGS += -I$(TOPDIR) +PLATFORM_CPPFLAGS += -I$(srctree) OBJCOPYFLAGS = --remove-section=.ppcenv diff --git a/board/korat/config.mk b/board/korat/config.mk index f8dba2b..42e0060 100644 --- a/board/korat/config.mk +++ b/board/korat/config.mk @@ -23,5 +23,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000 endif ifndef CONFIG_KORAT_PERMANENT -LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds +LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds endif -- cgit v1.1 From 01286329b27b27eaeda045b469d41b1d9fce545a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 11 Mar 2014 11:05:20 +0900 Subject: kbuild: rename SRCTREE to srctree Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for pointing to the top of source directory. (No difference between the two.) In Kbuild style, $(srctree) is used for instead. This commit renames SRCTREE to srctree and deletes the defition of SRCTREE. Note that SRCTREE in scripts/kernel-doc, scripts/docproc.c, doc/DocBook/Makefile should be keep. Signed-off-by: Masahiro Yamada --- board/ait/cam_enc_4xx/config.mk | 2 +- board/avnet/fx12mm/Makefile | 2 +- board/avnet/v5fx30teval/Makefile | 2 +- board/xilinx/ml507/Makefile | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk index c7cfaca..2022151 100644 --- a/board/ait/cam_enc_4xx/config.mk +++ b/board/ait/cam_enc_4xx/config.mk @@ -7,7 +7,7 @@ # (mem base + reserved) # -UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg +UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg ifndef CONFIG_SPL_BUILD ALL-y += u-boot.ubl else diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile index 37fb02f..618b42f 100644 --- a/board/avnet/fx12mm/Makefile +++ b/board/avnet/fx12mm/Makefile @@ -8,4 +8,4 @@ obj-y += fx12mm.o -include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile +include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile index f7d0417..8c41af0 100644 --- a/board/avnet/v5fx30teval/Makefile +++ b/board/avnet/v5fx30teval/Makefile @@ -8,4 +8,4 @@ obj-y += v5fx30teval.o -include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile +include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile index 3c84651..9a3809f 100644 --- a/board/xilinx/ml507/Makefile +++ b/board/xilinx/ml507/Makefile @@ -8,4 +8,4 @@ obj-y += ml507.o -include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile +include $(srctree)/board/xilinx/ppc440-generic/Makefile -- cgit v1.1 From 194ba5d4ecb2ad1195333cc7453f291e5b316479 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 10 Mar 2014 15:09:34 +0200 Subject: sh: ecovec: correct romImage address in comment romImage is set by CONFIG_ECOVEC_ROMIMAGE_ADDR to 0xA0040000. Signed-off-by: Baruch Siach Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/ecovec/lowlevel_init.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S index eeebdd2..e4c40c8 100644 --- a/board/renesas/ecovec/lowlevel_init.S +++ b/board/renesas/ecovec/lowlevel_init.S @@ -20,7 +20,7 @@ lowlevel_init: - /* jump to 0xA0020000 if bit 1 of PVDR_A */ + /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */ mov.l PVDR_A, r1 mov.l PVDR_D, r2 mov.b @r1, r0 -- cgit v1.1 From 41364f0fbe1e550a3326dd4310e41adec5ce30d7 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Thu, 27 Feb 2014 13:26:02 -0700 Subject: cros_ec: Move EC interface into common library Add a common library for obtaining access to the Chrome OS EC. This is used by boards which need to talk to the EC. Reviewed-by: Vadim Bendebury Tested-by: Vadim Bendebury Signed-off-by: Vadim Bendebury Signed-off-by: Simon Glass --- board/samsung/common/board.c | 29 +++-------------------------- board/samsung/smdk5250/exynos5-dt.c | 1 - 2 files changed, 3 insertions(+), 27 deletions(-) (limited to 'board') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index cd873bc..3866495 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -26,13 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct local_info { - struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ - int cros_ec_err; /* Error for cros_ec, 0 if ok */ -}; - -static struct local_info local; - #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ static void boot_temp_check(void) @@ -144,22 +137,6 @@ int board_early_init_f(void) } #endif -struct cros_ec_dev *board_get_cros_ec_dev(void) -{ - return local.cros_ec_dev; -} - -#ifdef CONFIG_CROS_EC -static int board_init_cros_ec_devices(const void *blob) -{ - local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); - if (local.cros_ec_err) - return -1; /* Will report in board_late_init() */ - - return 0; -} -#endif - #if defined(CONFIG_POWER) #ifdef CONFIG_POWER_MAX77686 static int pmic_reg_update(struct pmic *p, int reg, uint regval) @@ -384,12 +361,12 @@ int board_late_init(void) { stdio_print_current_devices(); - if (local.cros_ec_err) { + if (cros_ec_get_error()) { /* Force console on */ gd->flags &= ~GD_FLG_SILENT; printf("cros-ec communications failure %d\n", - local.cros_ec_err); + cros_ec_get_error()); puts("\nPlease reset with Power+Refresh\n\n"); panic("Cannot init cros-ec device"); return -1; @@ -401,7 +378,7 @@ int board_late_init(void) int arch_early_init_r(void) { #ifdef CONFIG_CROS_EC - if (board_init_cros_ec_devices(gd->fdt_blob)) { + if (cros_ec_board_init()) { printf("%s: Failed to init EC\n", __func__); return 0; } diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 5fb8664..c83b034 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include -- cgit v1.1 From 86bf601d0414541d210d31fe44d44c85c5d0fee0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 27 Feb 2014 13:26:13 -0700 Subject: sandbox: Plumb in Chrome OS EC emulation Add board code to set up the Chrome OS EC on startup. Signed-off-by: Simon Glass --- board/sandbox/sandbox/sandbox.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'board') diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 2f90df5..402afea 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -4,6 +4,7 @@ */ #include +#include #include #include @@ -33,3 +34,32 @@ int dram_init(void) gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } + +int arch_early_init_r(void) +{ +#ifdef CONFIG_CROS_EC + if (cros_ec_board_init()) { + printf("%s: Failed to init EC\n", __func__); + return 0; + } +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + if (cros_ec_get_error()) { + /* Force console on */ + gd->flags &= ~GD_FLG_SILENT; + + printf("cros-ec communications failure %d\n", + cros_ec_get_error()); + puts("\nPlease reset with Power+Refresh\n\n"); + panic("Cannot init cros-ec device"); + return -1; + } + return 0; +} +#endif -- cgit v1.1 From 7d95f2a329c964b54cf505503a61e8fd4f12e2a3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 27 Feb 2014 13:26:19 -0700 Subject: sandbox: Add LCD driver Add a simple LCD driver which uses SDL to display the image. We update the image regularly, while still providing for reasonable performance. Adjust the common lcd code to support sandbox. For command-line runs we do not want the LCD to be displayed, so add a --show_lcd option to enable it. Tested-by: Che-Liang Chiou Signed-off-by: Simon Glass --- board/sandbox/sandbox/sandbox.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'board') diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 402afea..e4d4e02 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -7,6 +7,7 @@ #include #include #include +#include /* * Pointer to initial global data area @@ -35,6 +36,23 @@ int dram_init(void) return 0; } +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_VIDEO_SANDBOX_SDL + int ret; + + ret = sandbox_lcd_sdl_early_init(); + if (ret) { + puts("Could not init sandbox LCD emulation\n"); + return ret; + } +#endif + + return 0; +} +#endif + int arch_early_init_r(void) { #ifdef CONFIG_CROS_EC -- cgit v1.1 From 352580870ca64b23a485a6b2ba6febc240b10904 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 12 Mar 2014 13:10:44 -0600 Subject: ARM: tegra: make all I2C ports open-drain I2C protocol requires open-drain IOs. Fix the Dalmore and Venice2 pinmux tables to configure the IOs correctly. Without this, Tegra may actively drive the lines high while an external device is actively driving the lines low, which can only lead to bad things. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- board/nvidia/dalmore/pinmux-config-dalmore.h | 16 ++++++++-------- board/nvidia/venice2/pinmux-config-venice2.h | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'board') diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 8c05a15..9dcd5e4 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -132,8 +132,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* VI pinmux */ VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), @@ -145,8 +145,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTD pinmux */ DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), @@ -224,8 +224,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* SYSCLK pinmux */ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), @@ -252,8 +252,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTB pinmux */ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index 50868e6..b3d68d5 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -124,12 +124,12 @@ static struct pingroup_config tegra124_pinmux_common[] = { DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT), /* I2C3 (TPM) pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTD pinmux (UART4 on Servo board, unused) */ DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), @@ -198,8 +198,8 @@ static struct pingroup_config tegra124_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* RTCK pinmux */ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), @@ -223,8 +223,8 @@ static struct pingroup_config tegra124_pinmux_common[] = { DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTB, GPS */ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), -- cgit v1.1