From a65c5768e5537530bd1780af3d3fddc3113a163c Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 2 Apr 2007 10:09:30 +0200 Subject: ppc4xx: Change SysACE address on Katmai With this new base address of the Xilinx SystemACE controller the Linux driver will be easier to adapt, since it can now be mapped via the "normal" ioremap() call. Signed-off-by: Stefan Roese --- board/amcc/katmai/init.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 6b024ee..5202ae6 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -103,7 +103,7 @@ tlbtabB: tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) -- cgit v1.1 From d3832e8fe1b214ec62424eac36cfda9fc56d21b3 Mon Sep 17 00:00:00 2001 From: Domen Puncer Date: Mon, 16 Apr 2007 14:00:13 +0200 Subject: [PATCH] icecube/lite5200b: wakeup from low-power support U-Boot part of Lite5200b low power mode support. Puts SDRAM out of self-refresh and transfers control to address saved at physical 0x0. Signed-off-by: Domen Puncer Acked-by: Grant Likely --- board/icecube/icecube.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'board') diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 700c9d9..2960998 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -42,6 +42,53 @@ #include "mt48lc16m16a2-75.h" # endif #endif + +#ifdef CONFIG_LITE5200B_PM +/* u-boot part of low-power mode implementation */ +#define SAVED_ADDR (*(void **)0x00000000) +#define PSC2_4 0x02 + +void lite5200b_wakeup(void) +{ + unsigned char wakeup_pin; + void (*linux_wakeup)(void); + + /* check PSC2_4, if it's down "QT" is signaling we have a wakeup + * from low power mode */ + *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; + __asm__ volatile ("sync"); + + wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; + if (wakeup_pin & PSC2_4) + return; + + /* acknowledge to "QT" + * by holding pin at 1 for 10 uS */ + *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; + __asm__ volatile ("sync"); + *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; + __asm__ volatile ("sync"); + udelay(10); + + /* put ram out of self-refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ + __asm__ volatile ("sync"); + *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ + __asm__ volatile ("sync"); + udelay(10); /* wait a bit */ + + /* jump back to linux kernel code */ + linux_wakeup = SAVED_ADDR; + printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", + linux_wakeup); + linux_wakeup(); +} +#else +#define lite5200b_wakeup() +#endif + #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -208,6 +255,8 @@ long int initdram (int board_type) __asm__ volatile ("sync"); } + lite5200b_wakeup(); + return dramsize + dramsize2; } -- cgit v1.1 From e673226ff9d6aa91b47ceac74b8c13770b06bb37 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Apr 2007 12:07:47 +0200 Subject: ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM Signed-off-by: Stefan Roese --- board/amcc/acadia/acadia.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 7d0046a..baf598c 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -26,7 +26,7 @@ extern void board_pll_init_f(void); -void liveoak_gpio_init(void) +static void acadia_gpio_init(void) { /* * GPIO0 setup (select GPIO or alternate function) @@ -55,8 +55,12 @@ int board_early_init_f(void) { unsigned int reg; - board_pll_init_f(); - liveoak_gpio_init(); + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) + board_pll_init_f(); + + acadia_gpio_init(); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); -- cgit v1.1