From 0d1d042ec0016e40d3a2dbd35278b1456f04c9cb Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Tue, 3 Jun 2014 16:44:18 +0800 Subject: ENGR00315894-9 i.mx6q/dl/solo:sabreauto: Add the WEIM-NOR support Add the WEIM-NOR support Signed-off-by: Jason Liu Signed-off-by: Ye.Li --- board/freescale/mx6qsabreauto/mx6dl.cfg | 18 +++++-- board/freescale/mx6qsabreauto/mx6q.cfg | 18 +++++-- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 77 +++++++++++++++++++++++++++ board/freescale/mx6qsabreauto/mx6solo.cfg | 15 ++++-- 4 files changed, 119 insertions(+), 9 deletions(-) (limited to 'board') diff --git a/board/freescale/mx6qsabreauto/mx6dl.cfg b/board/freescale/mx6qsabreauto/mx6dl.cfg index 1688610..45f0a5d 100644 --- a/board/freescale/mx6qsabreauto/mx6dl.cfg +++ b/board/freescale/mx6qsabreauto/mx6dl.cfg @@ -27,13 +27,25 @@ */ /* image version */ +#define __ASSEMBLY__ +#include + IMAGE_VERSION 2 /* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 */ + +#if defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ BOOT_FROM sd +#endif /* * Device Configuration Data (DCD) @@ -137,7 +149,7 @@ DATA 4, 0x020c4070, 0x0FFFC000 DATA 4, 0x020c4074, 0x3FF00000 DATA 4, 0x020c4078, 0x00FFF300 DATA 4, 0x020c407c, 0x0F0000C3 -DATA 4, 0x020c4080, 0x000003FF +DATA 4, 0x020c4080, 0x00000FFF /* enable AXI cache for VDOA/VPU/IPU */ DATA 4, 0x020e0010, 0xF00000CF diff --git a/board/freescale/mx6qsabreauto/mx6q.cfg b/board/freescale/mx6qsabreauto/mx6q.cfg index c05d1df..ce02f92 100644 --- a/board/freescale/mx6qsabreauto/mx6q.cfg +++ b/board/freescale/mx6qsabreauto/mx6q.cfg @@ -10,13 +10,25 @@ */ /* image version */ +#define __ASSEMBLY__ +#include + IMAGE_VERSION 2 /* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 */ + +#if defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ BOOT_FROM sd +#endif /* * Device Configuration Data (DCD) @@ -120,7 +132,7 @@ DATA 4, 0x020c4070, 0x0FFFC000 DATA 4, 0x020c4074, 0x3FF00000 DATA 4, 0x020c4078, 0x00FFF300 DATA 4, 0x020c407c, 0x0F0000C3 -DATA 4, 0x020c4080, 0x000003FF +DATA 4, 0x020c4080, 0x00000FFF /* enable AXI cache for VDOA/VPU/IPU */ DATA 4, 0x020e0010, 0xF00000CF diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 2bf0c74..5232df7 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -61,6 +61,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); @@ -382,6 +386,75 @@ void setup_spinor(void) } #endif +#ifdef CONFIG_SYS_USE_EIMNOR +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Steer logic */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00020181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + imx_iomux_v3_setup_multiple_pads(eimnor_pads, + ARRAY_SIZE(eimnor_pads)); + + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + + eimnor_cs_setup(); +} +#endif + int mx6_rgmii_rework(struct phy_device *phydev) { unsigned short val; @@ -466,6 +539,10 @@ int board_early_init_f(void) #ifdef CONFIG_SYS_USE_SPINOR setup_spinor(); #endif + +#ifdef CONFIG_SYS_USE_EIMNOR + setup_eimnor(); +#endif return 0; } diff --git a/board/freescale/mx6qsabreauto/mx6solo.cfg b/board/freescale/mx6qsabreauto/mx6solo.cfg index b25d4a7..f085c7f 100644 --- a/board/freescale/mx6qsabreauto/mx6solo.cfg +++ b/board/freescale/mx6qsabreauto/mx6solo.cfg @@ -30,10 +30,19 @@ IMAGE_VERSION 2 /* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 */ + +#if defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ BOOT_FROM sd +#endif /* * Device Configuration Data (DCD) @@ -113,7 +122,7 @@ DATA 4, 0x020c4070, 0x0FFFC000 DATA 4, 0x020c4074, 0x3FF00000 DATA 4, 0x020c4078, 0x00FFF300 DATA 4, 0x020c407c, 0x0F0000C3 -DATA 4, 0x020c4080, 0x000003FF +DATA 4, 0x020c4080, 0x00000FFF /* enable AXI cache for VDOA/VPU/IPU */ DATA 4, 0x020e0010, 0xF00000CF -- cgit v1.1