From 9617c8d49a21703eaf13a4033ab1a56eecc033cc Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 6 Jun 2008 13:12:18 -0500 Subject: FSL DDR: Convert MPC8540ADS to new DDR code. Signed-off-by: Kumar Gala --- board/freescale/mpc8540ads/Makefile | 13 +++--- board/freescale/mpc8540ads/ddr.c | 70 +++++++++++++++++++++++++++++++++ board/freescale/mpc8540ads/mpc8540ads.c | 14 ++++--- 3 files changed, 87 insertions(+), 10 deletions(-) create mode 100644 board/freescale/mpc8540ads/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile index 2d71cbc..4c6da4d 100644 --- a/board/freescale/mpc8540ads/Makefile +++ b/board/freescale/mpc8540ads/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/freescale/mpc8540ads/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 4f068cc..005e4d9 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -1,4 +1,4 @@ - /* +/* * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002,2003, Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) @@ -28,8 +28,9 @@ #include #include #include +#include #include -#include +#include #include #include @@ -82,10 +83,13 @@ initdram(int board_type) } #endif -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; #else - dram_size = fixed_sdram (); + dram_size = fixed_sdram(); #endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -- cgit v1.1 From 8b625114e8bc5a6b436181167a6e7fcd3303dd2c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 18 Mar 2008 11:12:44 -0500 Subject: FSL DDR: Convert MPC8560ADS to new DDR code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- board/freescale/mpc8560ads/Makefile | 13 +++--- board/freescale/mpc8560ads/ddr.c | 70 +++++++++++++++++++++++++++++++++ board/freescale/mpc8560ads/mpc8560ads.c | 11 ++++-- 3 files changed, 86 insertions(+), 8 deletions(-) create mode 100644 board/freescale/mpc8560ads/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile index 2d71cbc..67dbdeb 100644 --- a/board/freescale/mpc8560ads/Makefile +++ b/board/freescale/mpc8560ads/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/freescale/mpc8560ads/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 2c14a88..851fc57 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -28,7 +28,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -285,10 +287,13 @@ initdram(int board_type) } #endif -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; #else - dram_size = fixed_sdram (); + dram_size = fixed_sdram(); #endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -- cgit v1.1 From 2b40edb10d81da7bba724edbccd7f53777112579 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 18 Mar 2008 11:12:42 -0500 Subject: FSL DDR: Convert MPC8555ADS to new DDR code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- board/freescale/mpc8555cds/Makefile | 1 + board/freescale/mpc8555cds/ddr.c | 79 +++++++++++++++++++++++++++++++++ board/freescale/mpc8555cds/mpc8555cds.c | 8 +++- 3 files changed, 87 insertions(+), 1 deletion(-) create mode 100644 board/freescale/mpc8555cds/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile index 98f1530..c19a527 100644 --- a/board/freescale/mpc8555cds/Makefile +++ b/board/freescale/mpc8555cds/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o +COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c new file mode 100644 index 0000000..11ce57d --- /dev/null +++ b/board/freescale/mpc8555cds/ddr.c @@ -0,0 +1,79 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 6; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 9a65101..826056a 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -23,7 +23,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -261,7 +263,10 @@ initdram(int board_type) udelay(200); } #endif - dram_size = spd_sdram(); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -269,6 +274,7 @@ initdram(int board_type) */ ddr_enable_ecc(dram_size); #endif + /* * SDRAM Initialization */ -- cgit v1.1 From aa11d85cf318b961e029fe50d68ca47d004bce93 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 17 Mar 2008 15:48:18 -0500 Subject: FSL DDR: Convert MPC8541CDS to new DDR code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- board/freescale/mpc8541cds/Makefile | 1 + board/freescale/mpc8541cds/ddr.c | 79 +++++++++++++++++++++++++++++++++ board/freescale/mpc8541cds/mpc8541cds.c | 6 ++- 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 board/freescale/mpc8541cds/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile index 98f1530..c19a527 100644 --- a/board/freescale/mpc8541cds/Makefile +++ b/board/freescale/mpc8541cds/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o +COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c new file mode 100644 index 0000000..11ce57d --- /dev/null +++ b/board/freescale/mpc8541cds/ddr.c @@ -0,0 +1,79 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 6; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 3669ba9..de3a791 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -25,7 +25,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -263,7 +265,9 @@ initdram(int board_type) udelay(200); } #endif - dram_size = spd_sdram(); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* -- cgit v1.1 From e31d2c1e2bc954dc32e33bb2076139f85b95f8e6 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 18 Mar 2008 13:51:06 -0500 Subject: FSL DDR: Convert MPC8548CDS to new DDR code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- board/freescale/mpc8548cds/Makefile | 1 + board/freescale/mpc8548cds/ddr.c | 80 +++++++++++++++++++++++++++++++++ board/freescale/mpc8548cds/mpc8548cds.c | 8 +++- 3 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 board/freescale/mpc8548cds/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile index 98f1530..c19a527 100644 --- a/board/freescale/mpc8548cds/Makefile +++ b/board/freescale/mpc8548cds/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o +COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c new file mode 100644 index 0000000..f07d746 --- /dev/null +++ b/board/freescale/mpc8548cds/ddr.c @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 0b037cc..84d3850 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -25,8 +25,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -111,7 +113,10 @@ initdram(int board_type) udelay(200); } #endif - dram_size = spd_sdram(); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -119,6 +124,7 @@ initdram(int board_type) */ ddr_enable_ecc(dram_size); #endif + /* * SDRAM Initialization */ -- cgit v1.1 From e6f5b35b41ddbd637bb9ca4ad985b1e0b07dae0e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 18 Mar 2008 13:51:05 -0500 Subject: FSL DDR: Convert MPC8568MDS to new DDR code. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- board/freescale/mpc8568mds/Makefile | 14 ++++-- board/freescale/mpc8568mds/ddr.c | 81 +++++++++++++++++++++++++++++++++ board/freescale/mpc8568mds/mpc8568mds.c | 8 +++- 3 files changed, 97 insertions(+), 6 deletions(-) create mode 100644 board/freescale/mpc8568mds/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile index ecdc4d3..d499fb3 100644 --- a/board/freescale/mpc8568mds/Makefile +++ b/board/freescale/mpc8568mds/Makefile @@ -26,11 +26,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o bcsr.o law.o tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +COBJS-y += $(BOARD).o +COBJS-y += bcsr.o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c new file mode 100644 index 0000000..1b8ecec --- /dev/null +++ b/board/freescale/mpc8568mds/ddr.c @@ -0,0 +1,81 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 6; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 2ccff7d..f9e35cc 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -25,8 +25,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -163,7 +165,10 @@ initdram(int board_type) udelay(200); } #endif - dram_size = spd_sdram(); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -171,6 +176,7 @@ initdram(int board_type) */ ddr_enable_ecc(dram_size); #endif + /* * SDRAM Initialization */ -- cgit v1.1 From 1167a2fd56138b716e01370c4267f3b70bf9ffa0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 08:02:30 -0500 Subject: FSL DDR: Convert MPC8544DS to new DDR code. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/Makefile | 9 ++-- board/freescale/mpc8544ds/ddr.c | 80 +++++++++++++++++++++++++++++++++++ board/freescale/mpc8544ds/mpc8544ds.c | 11 +++-- 3 files changed, 93 insertions(+), 7 deletions(-) create mode 100644 board/freescale/mpc8544ds/ddr.c (limited to 'board') diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 3a5ea00..3997994 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -26,10 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c new file mode 100644 index 0000000..bbb5ee2 --- /dev/null +++ b/board/freescale/mpc8544ds/ddr.c @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index c39ce11..4e976b7 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -24,10 +24,11 @@ #include #include #include +#include #include #include +#include #include -#include #include #include #include @@ -38,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif -void sdram_init(void); - int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); @@ -69,7 +68,11 @@ initdram(int board_type) puts("Initializing\n"); - dram_size = spd_sdram(); + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* -- cgit v1.1 From be0bd8234b9777ecd63c4c686f72af070d886517 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 22:56:56 -0500 Subject: FSL DDR: Convert socrates to new DDR code. Signed-off-by: Kumar Gala --- board/socrates/Makefile | 13 +++++--- board/socrates/ddr.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++ board/socrates/sdram.c | 5 +++- 3 files changed, 93 insertions(+), 5 deletions(-) create mode 100644 board/socrates/ddr.c (limited to 'board') diff --git a/board/socrates/Makefile b/board/socrates/Makefile index a41fead..6fae601 100644 --- a/board/socrates/Makefile +++ b/board/socrates/Makefile @@ -28,10 +28,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a # -COBJS := $(BOARD).o law.o tlb.o sdram.o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-y += nand.o +COBJS-y += sdram.o +COBJS-$(CONFIG_FSL_DDR2) += ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c new file mode 100644 index 0000000..bbb5ee2 --- /dev/null +++ b/board/socrates/ddr.c @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 768fe05..12d1b8a 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -80,7 +81,9 @@ phys_size_t initdram (int board_type) { long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); #endif -- cgit v1.1 From a947e4c7eb15cea1d9fb633955c516aab5ad35dd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 23:14:14 -0500 Subject: FSL DDR: Convert atum8548 to new DDR code. Signed-off-by: Kumar Gala --- board/atum8548/Makefile | 9 ++++-- board/atum8548/atum8548.c | 8 +++-- board/atum8548/ddr.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+), 5 deletions(-) create mode 100644 board/atum8548/ddr.c (limited to 'board') diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile index d2e689f1..b991308 100644 --- a/board/atum8548/Makefile +++ b/board/atum8548/Makefile @@ -29,10 +29,13 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DDR2) += ddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 34f4599..337cf31 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -29,7 +29,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -106,8 +108,10 @@ initdram(int board_type) puts("Initializing\n"); #if defined(CONFIG_SPD_EEPROM) - puts("spd_sdram\n"); - dram_size = spd_sdram (); + puts("fsl_ddr_sdram\n"); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else puts("fixed_sdram\n"); dram_size = fixed_sdram (); diff --git a/board/atum8548/ddr.c b/board/atum8548/ddr.c new file mode 100644 index 0000000..f07d746 --- /dev/null +++ b/board/atum8548/ddr.c @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} -- cgit v1.1 From 33b9079ba20926f14238fff863b68a98e938948e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 23:15:28 -0500 Subject: FSL DDR: Convert sbc8548 to new DDR code. Signed-off-by: Kumar Gala --- board/sbc8548/Makefile | 9 ++++-- board/sbc8548/ddr.c | 80 +++++++++++++++++++++++++++++++++++++++++++++++++ board/sbc8548/sbc8548.c | 5 +++- 3 files changed, 90 insertions(+), 4 deletions(-) create mode 100644 board/sbc8548/ddr.c (limited to 'board') diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index bb96d95..9919a6e 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -28,10 +28,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DDR2) += ddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c new file mode 100644 index 0000000..f07d746 --- /dev/null +++ b/board/sbc8548/ddr.c @@ -0,0 +1,80 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 91b40e5..f31d7d6 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -106,7 +107,9 @@ initdram(int board_type) #endif #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif -- cgit v1.1 From d53bd3e17bd4f460257c19255569ea6dcfaae817 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 23:51:49 -0500 Subject: FSL DDR: Convert PM854 to new DDR code. Signed-off-by: Kumar Gala --- board/pm854/Makefile | 9 ++++--- board/pm854/ddr.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++ board/pm854/pm854.c | 6 ++++- 3 files changed, 81 insertions(+), 4 deletions(-) create mode 100644 board/pm854/ddr.c (limited to 'board') diff --git a/board/pm854/Makefile b/board/pm854/Makefile index 2d71cbc..52a756c 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DDR1) += ddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/pm854/ddr.c b/board/pm854/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/pm854/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 555f6c0..7dbafb9 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -28,7 +28,9 @@ #include #include #include +#include #include +#include #include #if defined(CONFIG_DDR_ECC) @@ -105,7 +107,9 @@ initdram(int board_type) #endif #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif -- cgit v1.1 From 6bfa8f723cfd82c55e3ef5620ade396916470a70 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 23:52:07 -0500 Subject: FSL DDR: Convert PM856 to new DDR code. Signed-off-by: Kumar Gala --- board/pm856/Makefile | 9 ++++--- board/pm856/ddr.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++ board/pm856/pm856.c | 6 ++++- 3 files changed, 81 insertions(+), 4 deletions(-) create mode 100644 board/pm856/ddr.c (limited to 'board') diff --git a/board/pm856/Makefile b/board/pm856/Makefile index 2d71cbc..52a756c 100644 --- a/board/pm856/Makefile +++ b/board/pm856/Makefile @@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DDR1) += ddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/pm856/ddr.c b/board/pm856/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/pm856/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index bf325f8..bd4c065 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -28,7 +28,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -260,7 +262,9 @@ initdram(int board_type) #endif #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif -- cgit v1.1 From 9658bec2e8f55d56ca1be70090ce5a348be4980f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 23:52:32 -0500 Subject: FSL DDR: Convert MPC8540EVAL to new DDR code. Signed-off-by: Kumar Gala --- board/mpc8540eval/Makefile | 12 ++++--- board/mpc8540eval/ddr.c | 70 +++++++++++++++++++++++++++++++++++++++++ board/mpc8540eval/mpc8540eval.c | 6 +++- 3 files changed, 83 insertions(+), 5 deletions(-) create mode 100644 board/mpc8540eval/ddr.c (limited to 'board') diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile index 325d6d5..5a68f11 100644 --- a/board/mpc8540eval/Makefile +++ b/board/mpc8540eval/Makefile @@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o law.o tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-y += flash.o +COBJS-$(CONFIG_FSL_DDR1) += ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/mpc8540eval/ddr.c b/board/mpc8540eval/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/mpc8540eval/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 1ac333c..7c54458 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -25,7 +25,9 @@ #include #include +#include #include +#include #include long int fixed_sdram (void); @@ -84,7 +86,9 @@ phys_size_t initdram (int board_type) #endif #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif -- cgit v1.1 From 8e55313b7ae12352a343f9b9962e662dbd897187 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 26 Aug 2008 23:52:58 -0500 Subject: FSL DDR: Convert SBC8560 to new DDR code. Signed-off-by: Kumar Gala --- board/sbc8560/Makefile | 9 ++++--- board/sbc8560/ddr.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++ board/sbc8560/sbc8560.c | 6 ++++- board/sbc8560/u-boot.lds | 1 - 4 files changed, 81 insertions(+), 5 deletions(-) create mode 100644 board/sbc8560/ddr.c (limited to 'board') diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile index bb96d95..6399734 100644 --- a/board/sbc8560/Makefile +++ b/board/sbc8560/Makefile @@ -28,10 +28,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DDR1) += ddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/sbc8560/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index d9e598c..dc66170 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -29,7 +29,9 @@ #include #include +#include #include +#include #include #include #include @@ -283,7 +285,9 @@ phys_size_t initdram (int board_type) #endif #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index ba5ce0b..237a3b6 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -74,7 +74,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) -- cgit v1.1 From c360d9b970fbb9c13744c355879671165bbb9b9e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 27 Aug 2008 01:03:42 -0500 Subject: FSL DDR: Convert STXGP3 to new DDR code. Signed-off-by: Kumar Gala --- board/stxgp3/Makefile | 12 ++++++--- board/stxgp3/ddr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++ board/stxgp3/stxgp3.c | 6 ++++- board/stxgp3/u-boot.lds | 1 - 4 files changed, 83 insertions(+), 6 deletions(-) create mode 100644 board/stxgp3/ddr.c (limited to 'board') diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile index 325d6d5..5a68f11 100644 --- a/board/stxgp3/Makefile +++ b/board/stxgp3/Makefile @@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o law.o tlb.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-y += flash.o +COBJS-$(CONFIG_FSL_DDR1) += ddr.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/stxgp3/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index 218e805..c80f1b3 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -32,7 +32,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -292,7 +294,9 @@ initdram (int board_type) } #endif - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) /* Initialize and enable DDR ECC. diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 9cc4997..d5363be 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -76,7 +76,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) -- cgit v1.1 From 0e7927db138976469e7257e29c1338050a50fcd9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 27 Aug 2008 01:04:07 -0500 Subject: FSL DDR: Convert STXSSA to new DDR code. Signed-off-by: Kumar Gala --- board/stxssa/Makefile | 9 ++++--- board/stxssa/ddr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++ board/stxssa/stxssa.c | 6 ++++- board/stxssa/u-boot.lds | 1 - 4 files changed, 81 insertions(+), 5 deletions(-) create mode 100644 board/stxssa/ddr.c (limited to 'board') diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile index e29cf95..9ab41ec 100644 --- a/board/stxssa/Makefile +++ b/board/stxssa/Makefile @@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DDR1) += ddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c new file mode 100644 index 0000000..45372f4 --- /dev/null +++ b/board/stxssa/ddr.c @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void +get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +} + + +unsigned int +fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + + +void +fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 0; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 2c4b546..124e123 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -32,7 +32,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -308,7 +310,9 @@ initdram (int board_type) } #endif - dram_size = spd_sdram (); + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) /* Initialize and enable DDR ECC. diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds index b0a9d68..93bedda 100644 --- a/board/stxssa/u-boot.lds +++ b/board/stxssa/u-boot.lds @@ -76,7 +76,6 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) - cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) -- cgit v1.1 From 129ba616b3813dde861f25f3d8a3c47c5c36ad5f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 12 Aug 2008 11:13:08 -0500 Subject: mpc85xx: Add support for the MPC8572DS reference board Signed-off-by: Kumar Gala --- board/freescale/mpc8572ds/Makefile | 54 ++++ board/freescale/mpc8572ds/config.mk | 32 ++ board/freescale/mpc8572ds/ddr.c | 81 +++++ board/freescale/mpc8572ds/law.c | 41 +++ board/freescale/mpc8572ds/mpc8572ds.c | 573 ++++++++++++++++++++++++++++++++++ board/freescale/mpc8572ds/tlb.c | 85 +++++ board/freescale/mpc8572ds/u-boot.lds | 145 +++++++++ 7 files changed, 1011 insertions(+) create mode 100644 board/freescale/mpc8572ds/Makefile create mode 100644 board/freescale/mpc8572ds/config.mk create mode 100644 board/freescale/mpc8572ds/ddr.c create mode 100644 board/freescale/mpc8572ds/law.c create mode 100644 board/freescale/mpc8572ds/mpc8572ds.c create mode 100644 board/freescale/mpc8572ds/tlb.c create mode 100644 board/freescale/mpc8572ds/u-boot.lds (limited to 'board') diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile new file mode 100644 index 0000000..3e82bbf --- /dev/null +++ b/board/freescale/mpc8572ds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk new file mode 100644 index 0000000..5b32186 --- /dev/null +++ b/board/freescale/mpc8572ds/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8572ds board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c new file mode 100644 index 0000000..5f8c555 --- /dev/null +++ b/board/freescale/mpc8572ds/ddr.c @@ -0,0 +1,81 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS1; + } + if (ctrl_num == 1 && i == 0) { + i2c_address = SPD_EEPROM_ADDRESS2; + } + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 5; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c new file mode 100644 index 0000000..d69b593 --- /dev/null +++ b/board/freescale/mpc8572ds/law.c @@ -0,0 +1,41 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), + SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c new file mode 100644 index 0000000..70b548b --- /dev/null +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -0,0 +1,573 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/pixis.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +long int fixed_sdram(void); + +int checkboard (void) +{ + printf ("Board: MPC8572DS, System ID: 0x%02x, " + "System Version: 0x%02x, FPGA Version: 0x%02x\n", + in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), + in8(PIXIS_BASE + PIXIS_PVER)); + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + puts(" DDR: "); + return dram_size; +} + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + uint d_init; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; + +#if defined (CONFIG_DDR_ECC) + ddr->err_int_en = CFG_DDR_ERR_INT_EN; + ddr->err_disable = CFG_DDR_ERR_DIS; + ddr->err_sbe = CFG_DDR_SBE; +#endif + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CFG_DDR_CONTROL; + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + return 512 * 1024 * 1024; +} + +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno=0; +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + printf (" eTSEC1 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + printf (" eTSEC2 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + printf (" eTSEC3 is in sgmii mode.\n"); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + printf (" eTSEC4 is in sgmii mode.\n"); + + +#ifdef CONFIG_PCIE3 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie3_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 3) || + (host_agent == 5) || (host_agent == 6); + int pcie_configured = io_sel >= 1; + u32 temp32; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE3 connected to ULI as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE3_MEM_BASE, + CFG_PCIE3_MEM_PHYS, + CFG_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE3_IO_BASE, + CFG_PCIE3_IO_PHYS, + CFG_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCIE3 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + * Device 1d has the first on-board memory BAR. + */ + + pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), + PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CFG_PCIE3_MEM_PHYS) { + debug(" uli1572 read to %x\n", temp32); + in_be32((unsigned *)temp32); + } + } else { + printf (" PCIE3: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + int pcie_ep = (host_agent == 2) || (host_agent == 4) || + (host_agent == 6); + int pcie_configured = io_sel & 4; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf (" PCIE2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE2: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 1) || (host_agent == 4) || + (host_agent == 5); + int pcie_configured = io_sel & 6; + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + hose->first_busno=first_free_busno; + + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE1: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif +} +#endif + +int board_early_init_r(void) +{ + unsigned int i; + const unsigned int flashbase = CFG_FLASH_BASE; + const u8 flash_esel = 2; + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Invalidate any remaining lines of the flash from caches. */ + for (i = 0; i < 256*1024*1024; i+=32) { + asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); + asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); + } + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ + + return 0; +} + +#ifdef CONFIG_GET_CLK_FROM_ICS307 +/* decode S[0-2] to Output Divider (OD) */ +static unsigned char ics307_S_to_OD[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. */ +/* XXX: This function should probably go into a common library */ +static unsigned long +ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) +{ + const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ; + unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long RDW = cw2 & 0x7F; + unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; + unsigned long freq; + + /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ + + /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + */ + + /* Adding 1 to get a "nicely" rounded number, but this needs + * more tweaking to get a "properly" rounded number. */ + + freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long get_board_sys_clk(ulong dummy) +{ + return ics307_clk_freq ( + in8(PIXIS_BASE + PIXIS_VSYSCLK0), + in8(PIXIS_BASE + PIXIS_VSYSCLK1), + in8(PIXIS_BASE + PIXIS_VSYSCLK2) + ); +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + return ics307_clk_freq ( + in8(PIXIS_BASE + PIXIS_VDDRCLK0), + in8(PIXIS_BASE + PIXIS_VDDRCLK1), + in8(PIXIS_BASE + PIXIS_VDDRCLK2) + ); +} +#else +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x07; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + + return val; +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x38; + i >>= 3; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + return val; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + ulong base, size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCIE3 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE2 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE1 + path = fdt_getprop(blob, node, "pci2", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c new file mode 100644 index 0000000..965356a --- /dev/null +++ b/board/freescale/mpc8572ds/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS, CFG_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x40000000, CFG_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x50000000, CFG_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8572ds/u-boot.lds b/board/freescale/mpc8572ds/u-boot.lds new file mode 100644 index 0000000..a05ece5 --- /dev/null +++ b/board/freescale/mpc8572ds/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1 From 9490a7f1a9484617bad75c60807ce02c8a3a6d56 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 25 Jul 2008 13:31:05 -0500 Subject: mpc85xx: Add support for the MPC8536DS reference board Signed-off-by: Kumar Gala Signed-off-by: Srikanth Srinivasan Signed-off-by: Dejan Minic Signed-off-by: Jason Jin Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- board/freescale/mpc8536ds/Makefile | 54 +++ board/freescale/mpc8536ds/config.mk | 32 ++ board/freescale/mpc8536ds/ddr.c | 79 ++++ board/freescale/mpc8536ds/law.c | 43 +++ board/freescale/mpc8536ds/mpc8536ds.c | 653 ++++++++++++++++++++++++++++++++++ board/freescale/mpc8536ds/tlb.c | 71 ++++ board/freescale/mpc8536ds/u-boot.lds | 145 ++++++++ 7 files changed, 1077 insertions(+) create mode 100644 board/freescale/mpc8536ds/Makefile create mode 100644 board/freescale/mpc8536ds/config.mk create mode 100644 board/freescale/mpc8536ds/ddr.c create mode 100644 board/freescale/mpc8536ds/law.c create mode 100644 board/freescale/mpc8536ds/mpc8536ds.c create mode 100644 board/freescale/mpc8536ds/tlb.c create mode 100644 board/freescale/mpc8536ds/u-boot.lds (limited to 'board') diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile new file mode 100644 index 0000000..7fcbdaa --- /dev/null +++ b/board/freescale/mpc8536ds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2008 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk new file mode 100644 index 0000000..9775ff4 --- /dev/null +++ b/board/freescale/mpc8536ds/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2008 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8536ds board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8536=1 diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c new file mode 100644 index 0000000..2e88c79 --- /dev/null +++ b/board/freescale/mpc8536ds/ddr.c @@ -0,0 +1,79 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); + } +} + +void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c new file mode 100644 index 0000000..cdf5215 --- /dev/null +++ b/board/freescale/mpc8536ds/law.c @@ -0,0 +1,43 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), + SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), + SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c new file mode 100644 index 0000000..8216c70 --- /dev/null +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -0,0 +1,653 @@ +/* + * Copyright 2008 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/pixis.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +phys_size_t fixed_sdram(void); + +int checkboard (void) +{ + printf ("Board: MPC8536DS, System ID: 0x%02x, " + "System Version: 0x%02x, FPGA Version: 0x%02x\n", + in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), + in8(PIXIS_BASE + PIXIS_PVER)); + return 0; +} + +phys_size_t +initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + +#ifdef CONFIG_SPD_EEPROM + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + puts(" DDR: "); + return dram_size; +} + +#if !defined(CONFIG_SPD_EEPROM) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + uint d_init; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; + +#if defined (CONFIG_DDR_ECC) + ddr->err_int_en = CFG_DDR_ERR_INT_EN; + ddr->err_disable = CFG_DDR_ERR_DIS; + ddr->err_sbe = CFG_DDR_SBE; +#endif + asm("sync;isync"); + + udelay(500); + + ddr->sdram_cfg = CFG_DDR_CONTROL; + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + d_init = 1; + debug("DDR - 1st controller: memory initializing\n"); + /* + * Poll until memory is initialized. + * 512 Meg at 400 might hit this 200 times or so. + */ + while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { + udelay(1000); + } + debug("DDR: memory initialized\n\n"); + asm("sync; isync"); + udelay(500); +#endif + + return 512 * 1024 * 1024; +} + +#endif + +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +int first_free_busno=0; + +void +pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint sdrs2_io_sel = + (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + + debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ + host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); + + if (sdrs2_io_sel == 7) + printf(" Serdes2 disalbed\n"); + else if (sdrs2_io_sel == 4) { + printf(" eTSEC1 is in sgmii mode.\n"); + printf(" eTSEC3 is in sgmii mode.\n"); + } else if (sdrs2_io_sel == 6) + printf(" eTSEC1 is in sgmii mode.\n"); + +#ifdef CONFIG_PCIE3 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie3_hose; + int pcie_ep = (host_agent == 1); + int pcie_configured = (io_sel == 7); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE3_MEM_BASE, + CFG_PCIE3_MEM_PHYS, + CFG_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE3_IO_BASE, + CFG_PCIE3_IO_PHYS, + CFG_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCIE3 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + } else { + printf (" PCIE3: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif + +#ifdef CONFIG_PCIE1 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 5); + int pcie_configured = (io_sel == 2 || io_sel == 3 + || io_sel == 5 || io_sel == 7); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE1_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE1_MEM_BASE2, + CFG_PCIE1_MEM_PHYS2, + CFG_PCIE1_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE1: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + { + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie2_hose; + int pcie_ep = (host_agent == 3); + int pcie_configured = (io_sel == 5 || io_sel == 7); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE2_MEM_BASE, + CFG_PCIE2_MEM_PHYS, + CFG_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE2_IO_BASE, + CFG_PCIE2_IO_PHYS, + CFG_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; +#ifdef CFG_PCIE2_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCIE2_MEM_BASE2, + CFG_PCIE2_MEM_PHYS2, + CFG_PCIE2_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf (" PCIE2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + } else { + printf (" PCIE2: disabled\n"); + } + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif + + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + uint pci_agent = (host_agent == 6); + uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ + uint pci_32 = 1; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter", + (uint)pci + ); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 3; +#ifdef CFG_PCI1_MEM_BASE2 + /* outbound memory */ + pci_set_region(hose->regions + 3, + CFG_PCI1_MEM_BASE2, + CFG_PCI1_MEM_PHYS2, + CFG_PCI1_MEM_SIZE2, + PCI_REGION_MEM); + hose->region_count++; +#endif + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif +} + + +int board_early_init_r(void) +{ + unsigned int i; + const unsigned int flashbase = CFG_FLASH_BASE; + const u8 flash_esel = 1; + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Invalidate any remaining lines of the flash from caches. */ + for (i = 0; i < 256*1024*1024; i+=32) { + asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); + asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); + } + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ + + return 0; +} + +#ifdef CONFIG_GET_CLK_FROM_ICS307 +/* decode S[0-2] to Output Divider (OD) */ +static unsigned char +ics307_S_to_OD[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. */ +/* XXX: This function should probably go into a common library */ +static unsigned long +ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) +{ + const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; + unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long RDW = cw2 & 0x7F; + unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; + unsigned long freq; + + /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ + + /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + */ + + /* Adding 1 to get a "nicely" rounded number, but this needs + * more tweaking to get a "properly" rounded number. */ + + freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long +get_board_sys_clk(ulong dummy) +{ + return ics307_clk_freq ( + in8(PIXIS_BASE + PIXIS_VSYSCLK0), + in8(PIXIS_BASE + PIXIS_VSYSCLK1), + in8(PIXIS_BASE + PIXIS_VSYSCLK2) + ); +} + +unsigned long +get_board_ddr_clk(ulong dummy) +{ + return ics307_clk_freq ( + in8(PIXIS_BASE + PIXIS_VDDRCLK0), + in8(PIXIS_BASE + PIXIS_VDDRCLK1), + in8(PIXIS_BASE + PIXIS_VDDRCLK2) + ); +} +#else +unsigned long +get_board_sys_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x07; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + + return val; +} + +unsigned long +get_board_ddr_clk(ulong dummy) +{ + u8 i; + ulong val = 0; + + i = in8(PIXIS_BASE + PIXIS_SPD); + i &= 0x38; + i >>= 3; + + switch (i) { + case 0: + val = 33333333; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66666666; + break; + case 4: + val = 83333333; + break; + case 5: + val = 100000000; + break; + case 6: + val = 133333333; + break; + case 7: + val = 166666666; + break; + } + return val; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + ft_cpu_setup(blob, bd); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI1 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE2 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE1 + path = fdt_getprop(blob, node, "pci2", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE3 + path = fdt_getprop(blob, node, "pci3", NULL); + if (path) { + tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c new file mode 100644 index 0000000..28a9fa8 --- /dev/null +++ b/board/freescale/mpc8536ds/tlb.c @@ -0,0 +1,71 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8536ds/u-boot.lds b/board/freescale/mpc8536ds/u-boot.lds new file mode 100644 index 0000000..901f633 --- /dev/null +++ b/board/freescale/mpc8536ds/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} -- cgit v1.1