From 2a523f524090d7fc5600ece9f12d7c955db567d7 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 14 Oct 2011 16:26:05 +0800 Subject: fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers Add common function fdt_set_node_status() to assist in various locations that we set a nodes status. This function utilizes the status values that are part of the EPAPR spec (on power.org). fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an alias string to identify the node to update. We also add some shortcut functions to help the common cases of setting "okay" and "disabled": fdt_status_okay() fdt_status_disabled() fdt_status_okay_by_alias() fdt_status_disabled_by_alias() Finally, we fixup the corenet_ds ethernet code which previously had a function by the same name that can be replaced with the new helpers. Signed-off-by: Shengzhou Liu Signed-off-by: Kumar Gala Acked-by: Gerald Van Baren --- board/freescale/corenet_ds/eth_hydra.c | 26 ++++-------------------- board/freescale/corenet_ds/eth_p4080.c | 36 ++++++++++------------------------ 2 files changed, 14 insertions(+), 48 deletions(-) (limited to 'board') diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 91b3408..a7a5e13 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -70,6 +70,7 @@ #include #include #include +#include #include #include "../common/ngpixis.h" @@ -200,25 +201,6 @@ static int hydra_mdio_init(char *realbusname, char *fakebusname) } /* - * Given an alias or a path for a node, set the status of that node. - * - * If 'alias' is not a valid alias, then it is treated as a full path to the - * node. No error checking is performed. - * - * This function is normally called to set the status for a virtual MDIO node. - */ -static void fdt_set_node_status(void *fdt, const char *alias, - const char *status) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); -} - -/* * Given an alias or a path for a node, set the mux value of that node. * * If 'alias' is not a valid alias, then it is treated as a full path to the @@ -372,14 +354,14 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane >= 0) { - fdt_set_node_status(fdt, "emi1_sgmii", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_sgmii"); /* Also set the MUX value */ fdt_set_mdio_mux(fdt, "emi1_sgmii", mdio_mux[i].val); } break; case PHY_INTERFACE_MODE_RGMII: - fdt_set_node_status(fdt, "emi1_rgmii", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: break; @@ -388,7 +370,7 @@ void fdt_fixup_board_enet(void *fdt) lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) - fdt_set_node_status(fdt, "emi2_xgmii", "okay"); + fdt_status_okay_by_alias(fdt, "emi2_xgmii"); #endif } diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index d4657f7..00dfa9a 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -199,22 +199,6 @@ static int p4080ds_mdio_init(char *realbusname, u32 muxval) return mdio_register(bus); } -/* - * Sets the specified node's status to the value contained in "status" - * If the first character of the specified path is "/" then we use - * alias as a path. Otherwise, we look for an alias of that name - */ -static void fdt_set_node_status(void *fdt, const char *alias, - const char *status) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); -} - void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { @@ -255,28 +239,28 @@ void fdt_fixup_board_enet(void *fdt) */ /* We've got six MDIO nodes that may or may not need to exist */ - fdt_set_node_status(fdt, "emi1_slot3", "disabled"); - fdt_set_node_status(fdt, "emi1_slot4", "disabled"); - fdt_set_node_status(fdt, "emi1_slot5", "disabled"); - fdt_set_node_status(fdt, "emi2_slot4", "disabled"); - fdt_set_node_status(fdt, "emi2_slot5", "disabled"); + fdt_status_disabled_by_alias(fdt, "emi1_slot3"); + fdt_status_disabled_by_alias(fdt, "emi1_slot4"); + fdt_status_disabled_by_alias(fdt, "emi1_slot5"); + fdt_status_disabled_by_alias(fdt, "emi2_slot4"); + fdt_status_disabled_by_alias(fdt, "emi2_slot5"); for (i = 0; i < NUM_FM_PORTS; i++) { switch (mdio_mux[i]) { case EMI1_SLOT3: - fdt_set_node_status(fdt, "emi1_slot3", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); break; case EMI1_SLOT4: - fdt_set_node_status(fdt, "emi1_slot4", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_slot4"); break; case EMI1_SLOT5: - fdt_set_node_status(fdt, "emi1_slot5", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_slot5"); break; case EMI2_SLOT4: - fdt_set_node_status(fdt, "emi2_slot4", "okay"); + fdt_status_okay_by_alias(fdt, "emi2_slot4"); break; case EMI2_SLOT5: - fdt_set_node_status(fdt, "emi2_slot5", "okay"); + fdt_status_okay_by_alias(fdt, "emi2_slot5"); break; } } -- cgit v1.1 From 3b001ad26d6e03ebe2510ec8506a8425392adcf8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 18 Oct 2011 01:31:08 -0500 Subject: powerpc/85xx: Fix P2020DS booting The following commit removed the code that set odt_rd_cfg and odt_wr_cfg. With out this code P2020DS board will not boot: commit 712cf7ab0b58e51a69e339397457d3591b6b650e Author: York Sun Date: Mon Oct 3 09:19:53 2011 -0700 powerpc/mpc8xxx: Merge entries in DDR speed table Signed-off-by: Kumar Gala --- board/freescale/p2020ds/ddr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'board') diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index c43f874..59034f9 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -57,6 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; + int i; if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); @@ -65,6 +66,17 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (!pdimm->n_ranks) return; + /* + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + pbsp = dimm0; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr -- cgit v1.1 From a836626cc4ddae53bfa46195a39194f21ad157af Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 18 Oct 2011 18:44:34 -0500 Subject: powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- board/freescale/corenet_ds/eth_p4080.c | 38 +++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 00dfa9a..7ff00d1 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -93,21 +93,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval) return bus; } -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) int board_phy_config(struct phy_device *phydev) { - /* - * If this is the 10G PHY, and we switched it to fiber, - * we need to reset the serdes link for SERDES9 - */ - if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) { + if (phydev->drv->uid == PHY_UID_TN2020) { + unsigned long timeout = 1 * 1000; /* 1 seconds */ enum srds_prtcl device; + /* + * Wait for the XAUI to come out of reset. This is when it + * starts transmitting alignment signals. + */ + while (--timeout) { + int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); + if (reg < 0) { + printf("TN2020: Error reading from PHY at " + "address %u\n", phydev->addr); + break; + } + /* + * Note that we've never actually seen + * MDIO_CTRL1_RESET set to 1. + */ + if ((reg & MDIO_CTRL1_RESET) == 0) + break; + udelay(1000); + } + + if (!timeout) { + printf("TN2020: Timeout waiting for PHY at address %u " + " to reset.\n", phydev->addr); + } + switch (phydev->addr) { - case 4: + case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: device = XAUI_FM1; break; - case 0: + case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: device = XAUI_FM2; break; default: -- cgit v1.1