From 4579dc37c3cce36d9521c26c6e82881393ec769e Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Tue, 17 Feb 2015 10:42:46 -0200 Subject: warp: Add initial WaRP Board support The WaRP Board is a Wearable Reference Plaform. The board features: - Freescale i.MX6 SoloLite processor with 512MB of RAM - Freescale FXOS8700CQ 6-axis Xtrinsic sensor - Freescale Kinetis KL16 MCU - Freescale Xtrinsic MMA955xL intelligent motion sensing platform The board implements a hybrid architecture to address the evolving needs of the wearables market. The platform consists of a main board and an example daughtercard with the ability to add additional daughtercards for different usage models. For more information about the project, visit: http://www.warpboard.org/ Signed-off-by: Otavio Salvador Reviewed-by: Marek Vasut Acked-by: Stefano Babic --- board/warp/warp.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 board/warp/warp.c (limited to 'board/warp/warp.c') diff --git a/board/warp/warp.c b/board/warp/warp.c new file mode 100644 index 0000000..3b275c2 --- /dev/null +++ b/board/warp/warp.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2014, 2015 O.S. Systems Software LTDA. + * Copyright (C) 2014 Kynetics LLC. + * Copyright (C) 2014 Revolution Robotics, Inc. + * + * Author: Otavio Salvador + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ + PAD_CTL_LVE) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ + PAD_CTL_LVE) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} + +int board_mmc_init(bd_t *bis) +{ + static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: WaRP Board\n"); + + return 0; +} -- cgit v1.1