From 19403633dd70333893c2da7926a1d0dcd6dab7d8 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sun, 31 Aug 2008 10:03:22 -0700 Subject: Moved initialization of NS8382X Ethernet controller to board_eth_init() Affected boards: bc3450 cpci5200 mecp5200 pf2000 icecube o2dnt pm520 sandpoint8245 total5200 tqm5200 Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren --- board/tqc/tqm5200/tqm5200.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board/tqc') diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index 8b8e461..d75aa9b 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_VIDEO_SM501 #include @@ -749,3 +750,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} -- cgit v1.1 From e1d7480b5de1fd4830bf7cf5e2237d3b0846d08d Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sun, 31 Aug 2008 10:39:12 -0700 Subject: Moved initialization of MPC5xxx_FEC Ethernet driver to CPU directory Modified board_eth_init() functions of boards that have this FEC in addition to other Ethernet controllers. Affected boards: bc3450 icecube mvbc_p o2dnt pm520 total5200 tq5200 Removed initialization of controller from net/eth.c Signed-off-by: Ben Warren --- board/tqc/tqm5200/tqm5200.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board/tqc') diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index d75aa9b..5152331 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -753,5 +753,6 @@ void ft_board_setup(void *blob, bd_t *bd) int board_eth_init(bd_t *bis) { + cpu_eth_init(bis); /* Built in FEC comes first */ return pci_eth_init(bis); } -- cgit v1.1 From 10efa024b8ffd9e6aaca63da8bddfdffdc672274 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sun, 31 Aug 2008 20:37:00 -0700 Subject: Moved initialization of EEPRO100 Ethernet controller to board_eth_init() Affected boards: db64360 db64460 katmai taihu taishan yucca cpc45 cpu87 eXalion elppc debris kvme080 mpc8315erdb integratorap ixdp425 oxc pm826 pm828 pm854 pm856 ppmc7xx sc3 sc520_spunk sorcery tqm8272 tqm85xx utx8245 Removed initialization of the driver from net/eth.c Also, wrapped contents of pci_eth_init() by CONFIG_PCI. Signed-off-by: Ben Warren --- board/tqc/tqm8272/tqm8272.c | 6 ++++++ board/tqc/tqm85xx/tqm85xx.c | 7 +++++++ 2 files changed, 13 insertions(+) (limited to 'board/tqc') diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index a0ec254..3a2376c 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -26,6 +26,7 @@ #include #include +#include #ifdef CONFIG_PCI #include #include @@ -1226,3 +1227,8 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index ae3c245..0e5bc2f 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -42,6 +42,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -743,3 +744,9 @@ int board_early_init_r (void) return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Intialize TSECs first */ + return pci_eth_init(bis); +} -- cgit v1.1 From 584f979f7ee914e32d408739cbdd2c4457ec18b8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 28 Aug 2008 13:48:36 +0200 Subject: TQM8272: Fix compiling error for the TQM8272 board. Fix compile problems caused by commit cfa460adfdefcc30d104e1a9ee44994ee349bb7b Signed-off-by: Heiko Schocher --- board/tqc/tqm8272/tqm8272.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index 3a2376c..0da16e7 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -1069,10 +1069,22 @@ int update_flash_size (int flash_size) static u8 hwctl = 0; -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + if (hwctl & 0x1) { + WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); + } else if (hwctl & 0x2) { + WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); + } else { + WRITE_NAND(byte, base); + } +} + +static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) hwctl |= 0x1; @@ -1084,21 +1096,7 @@ static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) hwctl &= ~0x2; } if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } + upmnand_write_byte (mtd, cmd); } static u_char upmnand_read_byte(struct mtd_info *mtdinfo) @@ -1191,7 +1189,6 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = upmnand_hwcontrol; nand->read_byte = upmnand_read_byte; - nand->write_byte = upmnand_write_byte; nand->dev_ready = tqm8272_dev_ready; #ifndef CONFIG_NAND_SPL -- cgit v1.1 From a6f2e455b774d0c5d56e44e5661df9adb69b6e07 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 28 Aug 2008 13:50:42 +0200 Subject: TQM8272: move NAND part in seperate File I didn't try to use drivers/mtd/nand/fsl_upm.c for the NAND driver, because I have no longer access to the hardware. Signed-off-by: Heiko Schocher --- board/tqc/tqm8272/Makefile | 2 +- board/tqc/tqm8272/nand.c | 276 ++++++++++++++++++++++++++++++++++++++++++++ board/tqc/tqm8272/tqm8272.c | 276 +------------------------------------------- board/tqc/tqm8272/tqm8272.h | 53 +++++++++ 4 files changed, 331 insertions(+), 276 deletions(-) create mode 100644 board/tqc/tqm8272/nand.c create mode 100644 board/tqc/tqm8272/tqm8272.h (limited to 'board/tqc') diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile index 6730263..c97fe14 100644 --- a/board/tqc/tqm8272/Makefile +++ b/board/tqc/tqm8272/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o +COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c new file mode 100644 index 0000000..b988ffa --- /dev/null +++ b/board/tqc/tqm8272/nand.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include "tqm8272.h" + +/* UPM pattern for bus clock = 66.7 MHz */ +static const uint upmTable67[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 100 MHz */ +static const uint upmTable100[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 133.3 MHz */ +static const uint upmTable133[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, + /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +static int chipsel = 0; + +#if defined(CONFIG_CMD_NAND) + +#include +#include + +static u8 hwctl = 0; + +static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + + if (hwctl & 0x1) { + WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); + } else if (hwctl & 0x2) { + WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); + } else { + WRITE_NAND(byte, base); + } +} + +static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + if ( ctrl & NAND_CLE ) + hwctl |= 0x1; + else + hwctl &= ~0x1; + if ( ctrl & NAND_ALE ) + hwctl |= 0x2; + else + hwctl &= ~0x2; + } + if (cmd != NAND_CMD_NONE) + upmnand_write_byte (mtd, cmd); +} + +static u_char upmnand_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + + return READ_NAND(base); +} + +static int tqm8272_dev_ready(struct mtd_info *mtdinfo) +{ + /* constant delay (see also tR in the datasheet) */ + udelay(12); \ + return 1; +} + +#ifndef CONFIG_NAND_SPL +static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + int i; + + for (i = 0; i< len; i++) + buf[i] = *base; +} + +static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + int i; + + for (i = 0; i< len; i++) + *base = buf[i]; +} + +static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + int i; + + for (i = 0; i < len; i++) + if (buf[i] != *base) + return -1; + return 0; +} +#endif /* #ifndef CONFIG_NAND_SPL */ + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + chipsel = chip; +} + +int board_nand_init(struct nand_chip *nand) +{ + static int UpmInit = 0; + volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + + if (hwinf.nand == 0) return -1; + + /* Setup the UPM */ + if (UpmInit == 0) { + switch (hwinf.busclk_real) { + case 100000000: + upmconfig (UPMB, (uint *) upmTable100, + sizeof (upmTable100) / sizeof (uint)); + break; + case 133333333: + upmconfig (UPMB, (uint *) upmTable133, + sizeof (upmTable133) / sizeof (uint)); + break; + default: + upmconfig (UPMB, (uint *) upmTable67, + sizeof (upmTable67) / sizeof (uint)); + break; + } + UpmInit = 1; + } + + /* Setup the memctrl */ + memctl->memc_or3 = CFG_NAND_OR; + memctl->memc_br3 = CFG_NAND_BR; + memctl->memc_mbmr = (MxMR_OP_NORM); + + nand->ecc.mode = NAND_ECC_SOFT; + + nand->cmd_ctrl = upmnand_hwcontrol; + nand->read_byte = upmnand_read_byte; + nand->dev_ready = tqm8272_dev_ready; + +#ifndef CONFIG_NAND_SPL + nand->write_buf = tqm8272_write_buf; + nand->read_buf = tqm8272_read_buf; + nand->verify_buf = tqm8272_verify_buf; +#endif + + /* + * Select required NAND chip + */ + board_nand_select_device(nand, 0); + return 0; +} + +#endif diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index 0da16e7..fc0a29c 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -31,6 +31,7 @@ #include #include #endif +#include "tqm8272.h" #if 0 #define deb_printf(fmt,arg...) \ @@ -208,112 +209,6 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -#define _NOT_USED_ 0xFFFFFFFF - -/* UPM pattern for bus clock = 66.7 MHz */ -static const uint upmTable67[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const uint upmTable100[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const uint upmTable133[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static int chipsel = 0; - /* UPM pattern for slow init */ static const uint upmTableSlow[] = { @@ -616,31 +511,6 @@ static inline int scanChar (char *p, int len, unsigned long *number) return akt; } -typedef struct{ - int Bus; - int flash; - int flash_nr; - int ram; - int ram_cs; - int nand; - int nand_cs; - int eeprom; - int can; - unsigned long cpunr; - unsigned long option; - int SecEng; - int cpucl; - int cpmcl; - int buscl; - int busclk_real_ok; - int busclk_real; - unsigned char OK; - unsigned char ethaddr[20]; -} HWIB_INFO; - -HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, - 0, 0, 0, 0, 0, 0}; - static int dump_hwib(void) { HWIB_INFO *hw = &hwinf; @@ -1062,150 +932,6 @@ int update_flash_size (int flash_size) } #endif -#if defined(CONFIG_CMD_NAND) - -#include -#include - -static u8 hwctl = 0; - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } -} - -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - } - if (cmd != NAND_CMD_NONE) - upmnand_write_byte (mtd, cmd); -} - -static u_char upmnand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - - return READ_NAND(base); -} - -static int tqm8272_dev_ready(struct mtd_info *mtdinfo) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); \ - return 1; -} - -#ifndef CONFIG_NAND_SPL -static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - buf[i] = *base; -} - -static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - *base = buf[i]; -} - -static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - int i; - - for (i = 0; i < len; i++) - if (buf[i] != *base) - return -1; - return 0; -} -#endif /* #ifndef CONFIG_NAND_SPL */ - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - chipsel = chip; -} - -int board_nand_init(struct nand_chip *nand) -{ - static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - if (hwinf.nand == 0) return -1; - - /* Setup the UPM */ - if (UpmInit == 0) { - switch (hwinf.busclk_real) { - case 100000000: - upmconfig (UPMB, (uint *) upmTable100, - sizeof (upmTable100) / sizeof (uint)); - break; - case 133333333: - upmconfig (UPMB, (uint *) upmTable133, - sizeof (upmTable133) / sizeof (uint)); - break; - default: - upmconfig (UPMB, (uint *) upmTable67, - sizeof (upmTable67) / sizeof (uint)); - break; - } - UpmInit = 1; - } - - /* Setup the memctrl */ - memctl->memc_or3 = CFG_NAND_OR; - memctl->memc_br3 = CFG_NAND_BR; - memctl->memc_mbmr = (MxMR_OP_NORM); - - nand->ecc.mode = NAND_ECC_SOFT; - - nand->cmd_ctrl = upmnand_hwcontrol; - nand->read_byte = upmnand_read_byte; - nand->dev_ready = tqm8272_dev_ready; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = tqm8272_write_buf; - nand->read_buf = tqm8272_read_buf; - nand->verify_buf = tqm8272_verify_buf; -#endif - - /* - * Select required NAND chip - */ - board_nand_select_device(nand, 0); - return 0; -} - -#endif - #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h new file mode 100644 index 0000000..6d558ec --- /dev/null +++ b/board/tqc/tqm8272/tqm8272.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TQM8272_HEADER_H +#define _TQM8272_HEADER_H + +#define _NOT_USED_ 0xFFFFFFFF + +typedef struct{ + int Bus; + int flash; + int flash_nr; + int ram; + int ram_cs; + int nand; + int nand_cs; + int eeprom; + int can; + unsigned long cpunr; + unsigned long option; + int SecEng; + int cpucl; + int cpmcl; + int buscl; + int busclk_real_ok; + int busclk_real; + unsigned char OK; + unsigned char ethaddr[20]; +} HWIB_INFO; + +static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, + 0, 0, 0, 0, 0, 0}; +#endif -- cgit v1.1 From 0cf4fd3cf8d0e00605bec5fc56f89c6415015a46 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:01 +0200 Subject: rename environment.c in env_embedded.c to reflect is functionality Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/tqc/tqm8xx/u-boot.lds | 2 +- board/tqc/tqm8xx/u-boot.lds.debug | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 8c46e46..26aa5d6 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) diff --git a/board/tqc/tqm8xx/u-boot.lds.debug b/board/tqc/tqm8xx/u-boot.lds.debug index c33581d..ea85389 100644 --- a/board/tqc/tqm8xx/u-boot.lds.debug +++ b/board/tqc/tqm8xx/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) -- cgit v1.1 From 7d9b5bae5ba558c7464d89d033aca04acaf01172 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:03 +0200 Subject: cleanup use of CFG_ENV_IS_IN_FLASH - #if CFG_ENV_IS_IN_FLASH - #if (CFG_ENV_IS_IN_FLASH == 1) - #define CFG_ENV_IS_IN_FLASH 0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/tqc/tqm8260/flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 056fe81..063972d 100644 --- a/board/tqc/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c @@ -207,7 +207,7 @@ unsigned long flash_init (void) CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR) # ifndef CFG_ENV_SIZE # define CFG_ENV_SIZE CFG_ENV_SECT_SIZE # endif -- cgit v1.1 From 5a1aceb0689e2f731491838970884a673ef7e7d3 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:04 +0200 Subject: rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/tqc/tqm5200/cam5200_flash.c | 2 +- board/tqc/tqm8260/flash.c | 2 +- board/tqc/tqm8xx/flash.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index b3f095d..bb12aae 100644 --- a/board/tqc/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -768,7 +768,7 @@ unsigned long flash_init(void) (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) +#if defined(CONFIG_ENV_IS_IN_FLASH) (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, &flash_info[i]); diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 063972d..815f023 100644 --- a/board/tqc/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c @@ -207,7 +207,7 @@ unsigned long flash_init (void) CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR) # ifndef CFG_ENV_SIZE # define CFG_ENV_SIZE CFG_ENV_SECT_SIZE # endif diff --git a/board/tqc/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c index 1231c7c..f9078cf 100644 --- a/board/tqc/tqm8xx/flash.c +++ b/board/tqc/tqm8xx/flash.c @@ -176,7 +176,7 @@ unsigned long flash_init (void) &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ # ifdef CFG_ENV_ADDR_REDUND debug ("Protect primary environment: %08lx ... %08lx\n", @@ -229,7 +229,7 @@ unsigned long flash_init (void) &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, -- cgit v1.1 From 0e8d158664a913392cb01fb11a948d83f72e105e Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:06 +0200 Subject: rename CFG_ENV macros to CONFIG_ENV Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/tqc/tqm5200/cam5200_flash.c | 10 +++++----- board/tqc/tqm8260/flash.c | 10 +++++----- board/tqc/tqm85xx/tqm85xx.c | 10 +++++----- board/tqc/tqm8xx/flash.c | 32 ++++++++++++++++---------------- 4 files changed, 31 insertions(+), 31 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index bb12aae..4fc4dc6 100644 --- a/board/tqc/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -769,12 +769,12 @@ unsigned long flash_init(void) CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, &flash_info[i]); #if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); -#if defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); #endif #endif diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 815f023..500af92 100644 --- a/board/tqc/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c @@ -207,13 +207,13 @@ unsigned long flash_init (void) CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return (size_b0); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 0e5bc2f..5314d33 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -321,15 +321,15 @@ int misc_init_r (void) /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); #endif diff --git a/board/tqc/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c index f9078cf..ca35e91 100644 --- a/board/tqc/tqm8xx/flash.c +++ b/board/tqc/tqm8xx/flash.c @@ -43,8 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET) #endif flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -178,30 +178,30 @@ unsigned long flash_init (void) #ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ -# ifdef CFG_ENV_ADDR_REDUND +# ifdef CONFIG_ENV_ADDR_REDUND debug ("Protect primary environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR, - (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); + (ulong)CONFIG_ENV_ADDR, + (ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1); # else debug ("Protect environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR, - (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); + (ulong)CONFIG_ENV_ADDR, + (ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1); # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND debug ("Protect redundand environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR_REDUND, - (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1); + (ulong)CONFIG_ENV_ADDR_REDUND, + (ulong)CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -232,8 +232,8 @@ unsigned long flash_init (void) #ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[1]); #endif } else { -- cgit v1.1 From 7c803be2eb3cae245dedda438776e08fb122250f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Sep 2008 18:02:19 +0200 Subject: TQM8xx: Fix CFI flash driver support for all TQM8xx based boards After switching to using the CFI flash driver, the correct remapping of the flash banks was forgotten. Also, some boards were not adapted, and the old legacy flash driver was not removed yet. Signed-off-by: Wolfgang Denk --- board/tqc/tqm8xx/Makefile | 2 +- board/tqc/tqm8xx/flash.c | 834 ---------------------------------------------- board/tqc/tqm8xx/tqm8xx.c | 123 +++++-- 3 files changed, 93 insertions(+), 866 deletions(-) delete mode 100644 board/tqc/tqm8xx/flash.c (limited to 'board/tqc') diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile index b48934b..280982d 100644 --- a/board/tqc/tqm8xx/Makefile +++ b/board/tqc/tqm8xx/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o load_sernum_ethaddr.o +COBJS = $(BOARD).o load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqc/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c deleted file mode 100644 index ca35e91..0000000 --- a/board/tqc/tqm8xx/flash.c +++ /dev/null @@ -1,834 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if 0 -#define DEBUG -#endif - -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */ - -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) -# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ -# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -# endif -#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else - trlx = 0; - - /* We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); -#endif - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - debug ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); -#else - memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); -#endif - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - debug ("Protect monitor: %08lx ... %08lx\n", - (ulong)CFG_MONITOR_BASE, - (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1); - - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ -# ifdef CONFIG_ENV_ADDR_REDUND - debug ("Protect primary environment: %08lx ... %08lx\n", - (ulong)CONFIG_ENV_ADDR, - (ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1); -# else - debug ("Protect environment: %08lx ... %08lx\n", - (ulong)CONFIG_ENV_ADDR, - (ulong)CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1); -# endif - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - debug ("Protect redundand environment: %08lx ... %08lx\n", - (ulong)CONFIG_ENV_ADDR_REDUND, - (ulong)CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - if (size_b1) { -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#else - memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000); -#endif - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } - - debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n"); - break; -# else /* ! TQM8xxM */ - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; -#endif /* TQM8xxM */ - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - debug ("Manufacturer: AMD\n"); - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - debug ("Manufacturer: FUJITSU\n"); - info->flash_id = FLASH_MAN_FUJ; - break; - default: - debug ("Manufacturer: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case AMD_ID_MIRROR: - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - /* Special case for AMLV320MH/L */ - if ((addr[14] & 0x00ff00ff) == 0x001d001d && - (addr[15] & 0x00ff00ff) == 0x00000000) { - debug ("Chip: AMLV320MH/L\n"); - info->flash_id += FLASH_AMLV320U; - info->sector_count = 64; - info->size = 0x00800000; /* => 8 MB */ - break; - } - switch(addr[14]) { - case AMD_ID_LV128U_2: - if (addr[15] != AMD_ID_LV128U_3) { - debug ("Chip: AMLV128U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV128U\n"); - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x02000000; - } - break; /* => 32 MB */ - case AMD_ID_LV640U_2: - if (addr[15] != AMD_ID_LV640U_3) { - debug ("Chip: AMLV640U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV640U\n"); - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x01000000; - } - break; /* => 16 MB */ - case AMD_ID_LV320B_2: - if (addr[15] != AMD_ID_LV320B_3) { - debug ("Chip: AMLV320B -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV320B\n"); - info->flash_id += FLASH_AMLV320B; - info->sector_count = 71; - info->size = 0x00800000; - } - break; /* => 8 MB */ - default: - debug ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - break; - } - break; -# else /* ! TQM8xxM */ - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* TQM8xxM */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_DL163B: - info->flash_id += FLASH_AMDL163B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case AMD_ID_MIRROR: - switch (info->flash_id & FLASH_TYPEMASK) { - /* only known types here - no default */ - case FLASH_AMLV128U: - case FLASH_AMLV640U: - case FLASH_AMLV320U: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x20000; - } - break; - case FLASH_AMLV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - } - break; -# else /* ! TQM8xxM */ - case AMD_ID_LV400B: - case AMD_ID_LV800B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV400T: - case AMD_ID_LV800T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_LV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - case AMD_ID_LV320T: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The last 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < (info->sector_count - 8)) - ? 2 * (64 << 10) - : 2 * ( 8 << 10); - } - break; -#endif /* TQM8xxM */ - case AMD_ID_LV160B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV160T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_DL163B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - default: - return (0); - break; - } - -#if 0 - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } -#endif - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */ diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 96b6103..59bbdbc 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -21,16 +21,14 @@ * MA 02111-1307 USA */ -#if 0 -#define DEBUG -#endif - #include #include #ifdef CONFIG_PS2MULT #include #endif +extern flash_info_t flash_info[]; /* FLASH chips info */ + DECLARE_GLOBAL_DATA_PTR; static long int dram_size (long int, long int *, long int); @@ -451,24 +449,107 @@ int board_early_init_r (void) #endif /* CONFIG_PS2MULT */ -/* ---------------------------------------------------------------------------- */ -/* HMI10 specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_HMI10 +#ifdef CONFIG_MISC_INIT_R int misc_init_r (void) { -# ifdef CONFIG_IDE_LED - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + +#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ + int scy, trlx, flash_or_timing, clk_diff; + + scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + trlx = OR_TRLX; + scy *= 2; + } else + trlx = 0; + + /* + * We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ + clk_diff = (gd->bus_clk / 1000000) - 50; + + /* + * We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ + if (clk_diff >= 0) + scy += (clk_diff + 5) / 10; + else + scy += (clk_diff - 5) / 10; + + /* + * For bus frequencies above 50MHz, we want to use relaxed timing + * (OR_TRLX). + */ + if (gd->bus_clk >= 50000000) + trlx = OR_TRLX; + else + trlx = 0; + + if (trlx) + scy /= 2; + + if (scy > 0xf) + scy = 0xf; + if (scy < 1) + scy = 1; + + flash_or_timing = (scy << 4) | trlx | + (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); + + memctl->memc_or0 = flash_or_timing | (-flash_info[0].size & OR_AM_MSK); +#else + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); +#endif + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + if (flash_info[1].size) { +#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or1 = flash_or_timing | + (-flash_info[1].size & 0xFFFF8000); +#else + memctl->memc_or1 = CFG_OR_TIMING_FLASH | + (-flash_info[1].size & 0xFFFF8000); +#endif + memctl->memc_br1 = ((CFG_FLASH_BASE + flash_info[0].size) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + debug ("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } + +# ifdef CONFIG_IDE_LED /* Configure PA15 as output port */ immap->im_ioport.iop_padir |= 0x0001; immap->im_ioport.iop_paodr |= 0x0001; immap->im_ioport.iop_papar &= ~0x0001; immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ # endif + +#ifdef CONFIG_NSCU + /* wake up ethernet module */ + immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ + immap->im_ioport.iop_pcdir |= 0x0004; /* output */ + immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ + immap->im_ioport.iop_pcdat |= 0x0004; /* enable */ +#endif /* CONFIG_NSCU */ + return (0); } +#endif /* CONFIG_MISC_INIT_R */ + # ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) @@ -483,26 +564,6 @@ void ide_led (uchar led, uchar status) } } # endif -#endif /* CONFIG_HMI10 */ - -/* ---------------------------------------------------------------------------- */ -/* NSCU specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_NSCU - -int misc_init_r (void) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* wake up ethernet module */ - immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immr->im_ioport.iop_pcdir |= 0x0004; /* output */ - immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ - - return (0); -} -#endif /* CONFIG_NSCU */ /* ---------------------------------------------------------------------------- */ /* TK885D specific initializaion */ -- cgit v1.1 From 87b4ef560cf2da4ccc9e59711ad1ff7fafe96670 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 17 Sep 2008 10:17:55 +0200 Subject: Coding style cleanup; update CHANEGLOG Signed-off-by: Wolfgang Denk --- board/tqc/tqm8xx/tqm8xx.c | 70 +++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 35 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 59bbdbc..5537d04 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -400,8 +400,6 @@ phys_size_t initdram (int board_type) memctl->memc_or5 = CFG_OR5_ISP1362; memctl->memc_br5 = CFG_BR5_ISP1362; #endif /* CONFIG_ISP1362_USB */ - - return (size_b0 + size_b1); } @@ -453,7 +451,7 @@ int board_early_init_r (void) #ifdef CONFIG_MISC_INIT_R int misc_init_r (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; #ifdef CFG_OR_TIMING_FLASH_AT_50MHZ @@ -463,28 +461,29 @@ int misc_init_r (void) if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { trlx = OR_TRLX; scy *= 2; - } else + } else { trlx = 0; + } - /* - * We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ + /* + * We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ clk_diff = (gd->bus_clk / 1000000) - 50; - /* - * We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ + /* + * We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ if (clk_diff >= 0) scy += (clk_diff + 5) / 10; else scy += (clk_diff - 5) / 10; - /* - * For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ + /* + * For bus frequencies above 50MHz, we want to use relaxed timing + * (OR_TRLX). + */ if (gd->bus_clk >= 50000000) trlx = OR_TRLX; else @@ -499,35 +498,39 @@ int misc_init_r (void) scy = 1; flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); + (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); - memctl->memc_or0 = flash_or_timing | (-flash_info[0].size & OR_AM_MSK); + memctl->memc_or0 = + flash_or_timing | (-flash_info[0].size & OR_AM_MSK); #else - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); + memctl->memc_or0 = + CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); #endif memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); + memctl->memc_br0, memctl->memc_or0); if (flash_info[1].size) { #ifdef CFG_OR_TIMING_FLASH_AT_50MHZ memctl->memc_or1 = flash_or_timing | - (-flash_info[1].size & 0xFFFF8000); + (-flash_info[1].size & 0xFFFF8000); #else memctl->memc_or1 = CFG_OR_TIMING_FLASH | - (-flash_info[1].size & 0xFFFF8000); + (-flash_info[1].size & 0xFFFF8000); #endif - memctl->memc_br1 = ((CFG_FLASH_BASE + flash_info[0].size) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; + memctl->memc_br1 = + ((CFG_FLASH_BASE + + flash_info[0]. + size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); + memctl->memc_br1, memctl->memc_or1); } else { - memctl->memc_br1 = 0; /* invalidate bank */ + memctl->memc_br1 = 0; /* invalidate bank */ debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); + memctl->memc_br1, memctl->memc_or1); } # ifdef CONFIG_IDE_LED @@ -540,11 +543,11 @@ int misc_init_r (void) #ifdef CONFIG_NSCU /* wake up ethernet module */ - immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immap->im_ioport.iop_pcdir |= 0x0004; /* output */ - immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immap->im_ioport.iop_pcdat |= 0x0004; /* enable */ -#endif /* CONFIG_NSCU */ + immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ + immap->im_ioport.iop_pcdir |= 0x0004; /* output */ + immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ + immap->im_ioport.iop_pcdat |= 0x0004; /* enable */ +#endif /* CONFIG_NSCU */ return (0); } @@ -609,7 +612,4 @@ int last_stage_init(void) return 0; } - #endif - -/* ------------------------------------------------------------------------- */ -- cgit v1.1 From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/tqc/tqm5200/cam5200_flash.c | 176 ++++++++++++++++----------------- board/tqc/tqm5200/cmd_stk52xx.c | 12 +-- board/tqc/tqm5200/tqm5200.c | 58 +++++------ board/tqc/tqm8260/config.mk | 2 +- board/tqc/tqm8260/flash.c | 16 +-- board/tqc/tqm8260/tqm8260.c | 46 ++++----- board/tqc/tqm8272/config.mk | 2 +- board/tqc/tqm8272/nand.c | 20 ++-- board/tqc/tqm8272/tqm8272.c | 66 ++++++------- board/tqc/tqm834x/pci.c | 34 +++---- board/tqc/tqm834x/tqm834x.c | 22 ++--- board/tqc/tqm85xx/law.c | 16 +-- board/tqc/tqm85xx/nand.c | 14 +-- board/tqc/tqm85xx/sdram.c | 12 +-- board/tqc/tqm85xx/tlb.c | 82 +++++++-------- board/tqc/tqm85xx/tqm85xx.c | 92 ++++++++--------- board/tqc/tqm8xx/load_sernum_ethaddr.c | 10 +- board/tqc/tqm8xx/tqm8xx.c | 82 +++++++-------- 18 files changed, 381 insertions(+), 381 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index 4fc4dc6..124b47d 100644 --- a/board/tqc/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -35,7 +35,7 @@ #define swap16(x) __swab16(x) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * CAM5200 is a TQM5200B based board. Additionally it also features @@ -51,15 +51,15 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle * specifics of both flashes. */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { - {CFG_BOOTCS_START, CFG_CS5_START | 1} +static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { + {CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1} }; /*----------------------------------------------------------------------- * Functions */ static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word_32(flash_info_t * info, ulong dest, ulong data); static int write_word_16(flash_info_t * info, ulong dest, ulong data); static int flash_erase_32(flash_info_t * info, int s_first, int s_last); @@ -145,7 +145,7 @@ void flash_print_info(flash_info_t * info) /* * The following code cannot be run from FLASH! */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static ulong flash_get_size(vu_long * addr, flash_info_t * info) { @@ -164,23 +164,23 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) #endif { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; default: @@ -228,13 +228,13 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr2[2] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -242,14 +242,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_32(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -262,7 +262,7 @@ static int wait_for_DQ7_32(flash_info_t * info, int sect) return 0; } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV int flash_erase(flash_info_t * info, int s_first, int s_last) { if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { @@ -277,8 +277,8 @@ static int flash_erase_32(flash_info_t * info, int s_first, int s_last) int flash_erase(flash_info_t * info, int s_first, int s_last) #endif { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; if ((s_first < 0) || (s_first > s_last)) { @@ -313,14 +313,14 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ l_sect = sect; /* @@ -342,8 +342,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -423,7 +423,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word(flash_info_t * info, ulong dest, ulong data) { if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { @@ -438,9 +438,9 @@ static int write_word_32(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data) #endif { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i, flag; @@ -448,13 +448,13 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) if ((*((vu_long *)dest) & data) != data) return (2); - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -464,10 +464,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } @@ -475,10 +475,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return (0); } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short +#undef CONFIG_SYS_FLASH_WORD_SIZE +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* * The following code cannot be run from FLASH! @@ -486,29 +486,29 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr); /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000; udelay(1000); value = swap16(addr2[0]); DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; default: @@ -522,12 +522,12 @@ static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; @@ -569,13 +569,13 @@ static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr2[2] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; return (info->size); } @@ -583,14 +583,14 @@ static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_16(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) != - (CFG_FLASH_WORD_SIZE) 0x80008000) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -605,8 +605,8 @@ static int wait_for_DQ7_16(flash_info_t * info, int sect) static int flash_erase_16(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; if ((s_first < 0) || (s_first > s_last)) { @@ -641,14 +641,14 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ l_sect = sect; /* @@ -670,8 +670,8 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ printf(" done\n"); return 0; @@ -679,27 +679,27 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) static int write_word_16(flash_info_t * info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; /* Check if Flash is (sufficiently) erased */ - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { if ((dest2[i] & swap16(data2[i])) != swap16(data2[i])) return (2); } - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000; dest2[i] = swap16(data2[i]); @@ -709,10 +709,10 @@ static int write_word_16(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) != - (swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != + (swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -720,7 +720,7 @@ static int write_word_16(flash_info_t * info, ulong dest, ulong data) return (0); } -#endif /* CFG_FLASH_2ND_16BIT_DEV */ +#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ /*----------------------------------------------------------------------- * Functions @@ -734,7 +734,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; @@ -742,7 +742,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -765,8 +765,8 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); #if defined(CONFIG_ENV_IS_IN_FLASH) (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index fd1e68b..5483fca 100644 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -165,9 +165,9 @@ static void i2s_init(void) psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); psc->sicr = 0x22E00000; /* 16 bit data; I2S */ - *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK + *(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK * 5.617 MHz */ - *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable + *(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable * register */ psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ psc->ctur = 0x0F; /* 16 bit frame width */ @@ -751,9 +751,9 @@ int can_init(void) static int init_done = 0; int i; struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); /* GPIO configuration of the CAN pins is done in TQM5200.h */ @@ -896,9 +896,9 @@ int do_can(char *argv[]) { int i; struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); /* send a message on CAN1 */ can1->cantbsel = 0x01; diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index 5152331..faa2e02 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; void ps2mult_early_init(void); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -101,7 +101,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -111,7 +111,7 @@ phys_size_t initdram (int board_type) ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -132,9 +132,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -161,10 +161,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); } if (test1 > test2) { sdram_start(0); @@ -186,7 +186,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -203,7 +203,7 @@ phys_size_t initdram (int board_type) } else { dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -406,7 +406,7 @@ int board_early_init_r (void) ps2mult_early_init(); #endif /* CONFIG_PS2MULT */ -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) /* Low level USB init, required for proper kernel operation */ usb_cpu_init(); #endif @@ -464,34 +464,34 @@ int last_stage_init (void) */ /* save original SRAM content */ - save = *(volatile u16 *)CFG_CS2_START; + save = *(volatile u16 *)CONFIG_SYS_CS2_START; restore = 1; /* write test pattern to SRAM */ - *(volatile u16 *)CFG_CS2_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in SRAM detection\n"); - if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { /* no SRAM at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; restore = 0; __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { /* make sure that we access a mirrored address */ - *(volatile u16 *)CFG_CS2_START = 0x1111; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; __asm__ volatile ("sync"); - if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, 0x80000); __asm__ volatile ("sync"); puts ("SRAM: 512 kB\n"); @@ -503,7 +503,7 @@ int last_stage_init (void) } /* restore origianl SRAM content */ if (restore) { - *(volatile u16 *)CFG_CS2_START = save; + *(volatile u16 *)CONFIG_SYS_CS2_START = save; __asm__ volatile ("sync"); } @@ -513,21 +513,21 @@ int last_stage_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; @@ -539,7 +539,7 @@ int last_stage_init (void) } /* restore origianl FB content */ if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } @@ -679,21 +679,21 @@ unsigned int board_video_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller found */ restore = 0; ret = 0; @@ -702,7 +702,7 @@ unsigned int board_video_init (void) } if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } return ret; diff --git a/board/tqc/tqm8260/config.mk b/board/tqc/tqm8260/config.mk index 1fe9952..3ecfc48 100644 --- a/board/tqc/tqm8260/config.mk +++ b/board/tqc/tqm8260/config.mk @@ -25,7 +25,7 @@ # TQM8260 boards # -# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 500af92..4a6d538 100644 --- a/board/tqc/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c @@ -31,7 +31,7 @@ #define V_BYTE(a) (*(volatile unsigned char *)( a )) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -185,13 +185,13 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); @@ -201,10 +201,10 @@ unsigned long flash_init (void) * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) @@ -364,7 +364,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -480,7 +480,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) start = get_timer (0); while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c index f201045..3039999 100644 --- a/board/tqc/tqm8260/tqm8260.c +++ b/board/tqc/tqm8260/tqm8260.c @@ -236,7 +236,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; @@ -261,7 +261,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -272,7 +272,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -285,10 +285,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif long psize, lsize; @@ -296,8 +296,8 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; #if 0 /* Just for debugging */ #define prt_br_or(brX,orX) do { \ @@ -315,37 +315,37 @@ phys_size_t initdram (int board_type) prt_br_or (br3, or3); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL - %ld MB, ", psize >> 20); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL - %ld MB, ", psize >> 20); } /* Local SDRAM setup: */ -#ifdef CFG_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CFG_LSRT; - size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, +#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CONFIG_SYS_LSRT; + size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, (uchar *) SDRAM_BASE2_PRELIM); if (size8 < size9) { lsize = size9; printf ("Local:9COL - %ld MB) using ", lsize >> 20); } else { - lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); printf ("Local:8COL - %ld MB) using ", lsize >> 20); } @@ -354,11 +354,11 @@ phys_size_t initdram (int board_type) /* Set up BR2 so that the local SDRAM goes * right after the 60x SDRAM */ - memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | - (CFG_SDRAM_BASE + psize); + memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | + (CONFIG_SYS_SDRAM_BASE + psize); #endif -#endif /* CFG_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); diff --git a/board/tqc/tqm8272/config.mk b/board/tqc/tqm8272/config.mk index af7a81e..05c5f0c 100644 --- a/board/tqc/tqm8272/config.mk +++ b/board/tqc/tqm8272/config.mk @@ -25,7 +25,7 @@ # TQM8272 boards # -# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c index b988ffa..8c8341b 100644 --- a/board/tqc/tqm8272/nand.c +++ b/board/tqc/tqm8272/nand.c @@ -141,12 +141,12 @@ static u8 hwctl = 0; static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); + WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); + WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); } else { WRITE_NAND(byte, base); } @@ -171,7 +171,7 @@ static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) static u_char upmnand_read_byte(struct mtd_info *mtdinfo) { struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); return READ_NAND(base); } @@ -187,7 +187,7 @@ static int tqm8272_dev_ready(struct mtd_info *mtdinfo) static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); int i; for (i = 0; i< len; i++) @@ -197,7 +197,7 @@ static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); int i; for (i = 0; i< len; i++) @@ -207,7 +207,7 @@ static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); int i; for (i = 0; i < len; i++) @@ -225,7 +225,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip) int board_nand_init(struct nand_chip *nand) { static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; if (hwinf.nand == 0) return -1; @@ -250,8 +250,8 @@ int board_nand_init(struct nand_chip *nand) } /* Setup the memctrl */ - memctl->memc_or3 = CFG_NAND_OR; - memctl->memc_br3 = CFG_NAND_BR; + memctl->memc_or3 = CONFIG_SYS_NAND_OR; + memctl->memc_br3 = CONFIG_SYS_NAND_BR; memctl->memc_mbmr = (MxMR_OP_NORM); nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index fc0a29c..5d0741d 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -287,7 +287,7 @@ int checkboard (void) char *p = (char *) HWIB_INFO_START_ADDR; puts ("Board: "); - if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { puts (p); } else { puts ("No HWIB assuming TQM8272"); @@ -327,7 +327,7 @@ static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) { #if defined(CONFIG_BOARD_GET_CPU_CLK_F) int clk = board_get_cpu_clk_f (); - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); int cas; @@ -404,7 +404,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; @@ -429,7 +429,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -440,7 +440,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -453,10 +453,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif long psize, lsize; @@ -464,27 +464,27 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE, 8); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE, 9); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE, 8); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE, 9); if (size8 < size9) { psize = size9; printf ("(60x:9COL - %ld MB, ", psize >> 20); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE, 8); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE, 8); printf ("(60x:8COL - %ld MB, ", psize >> 20); } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -514,7 +514,7 @@ static inline int scanChar (char *p, int len, unsigned long *number) static int dump_hwib(void) { HWIB_INFO *hw = &hwinf; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; char *s = getenv("serial#"); if (hw->OK) { @@ -607,7 +607,7 @@ int analyse_hwib (void) deb_printf(" %s pointer: %p\n", __FUNCTION__, p); /* Head = TQM */ - if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { deb_printf("No HWIB\n"); return -1; } @@ -704,7 +704,7 @@ int analyse_hwib (void) hw->OK = 1; /* search MAC Address */ - while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) { + while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { if (*p < ' ' || *p > '~') { /* ASCII strings! */ return 0; } @@ -744,7 +744,7 @@ char get_cpu_str_f (char *buf) buf[i++] = 'M'; buf[i++] = 'P'; buf[i++] = 'C'; - if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { buf[i++] = *&p[3]; buf[i++] = *&p[4]; buf[i++] = *&p[5]; @@ -767,7 +767,7 @@ unsigned long board_get_cpu_clk_f (void) char *p = (char *) HWIB_INFO_START_ADDR; int i = 0; - if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { if (search_real_busclk (&i)) return i; } @@ -779,7 +779,7 @@ unsigned long board_get_cpu_clk_f (void) static int can_test (unsigned long off) { - volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off); + volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); *(base + 0x17) = 'T'; *(base + 0x18) = 'Q'; @@ -794,9 +794,9 @@ static int can_test (unsigned long off) static int can_config_one (unsigned long off) { - volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off); - volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02); - volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f); + volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); + volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); + volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); unsigned char temp; *cpu_if = 0x45; @@ -825,13 +825,13 @@ static int can_config (void) static int init_can (void) { - volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; int count = 0; if ((hwinf.OK) && (hwinf.can)) { - memctl->memc_or4 = CFG_CAN_OR; - memctl->memc_br4 = CFG_CAN_BR; + memctl->memc_or4 = CONFIG_SYS_CAN_OR; + memctl->memc_br4 = CONFIG_SYS_CAN_BR; /* upm Init */ upmconfig (UPMC, (uint *) upmTableFast, sizeof (upmTableFast) / sizeof (uint)); @@ -842,7 +842,7 @@ static int init_can (void) MxMR_OP_NORM); /* can configure */ count = can_config (); - printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE); + printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); if (hwinf.can != count) printf("!!! difference to HWIB\n"); } else { printf ("CAN: No\n"); @@ -870,7 +870,7 @@ U_BOOT_CMD( "\n" ); -#ifdef CFG_UPDATE_FLASH_SIZE +#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE static int get_flash_timing (void) { /* get it from the option -tf in CIB */ @@ -915,7 +915,7 @@ static int get_flash_timing (void) /* Update the Flash_Size and the Flash Timing */ int update_flash_size (int flash_size) { - volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; unsigned long reg; unsigned long tim; @@ -937,7 +937,7 @@ struct pci_controller hose; int board_early_init_f (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; return 0; diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index e3d0309..0eedf4a 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -29,8 +29,8 @@ #ifdef CONFIG_PCI /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) #ifndef CONFIG_PCI_PNP @@ -78,7 +78,7 @@ pci_init_board(void) u32 reg32; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -128,10 +128,10 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; /* @@ -139,13 +139,13 @@ pci_init_board(void) */ /* PCI1 mem space */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); /* @@ -164,16 +164,16 @@ pci_init_board(void) /* PCI memory space */ pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -186,8 +186,8 @@ pci_init_board(void) hose->region_count = 3; pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); + (CONFIG_SYS_IMMR+0x8300), + (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 278780d..106cac2 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -67,7 +67,7 @@ static void set_cs_config(short cs, long config); static void set_ddr_config(void); /* Local variable */ -static volatile immap_t *im = (immap_t *)CFG_IMMR; +static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; /************************************************************************** * Board initialzation after relocation to RAM. Used to detect the number @@ -92,13 +92,13 @@ phys_size_t initdram (int board_type) int cs; /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); /* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS); set_cs_config(cs, INITIAL_CS_CONFIG); @@ -122,7 +122,7 @@ phys_size_t initdram (int board_type) debug("\nDetecting Bank%d\n", cs); bank_size = get_ddr_bank_size(cs, - (volatile long*)(CFG_DDR_BASE + size)); + (volatile long*)(CONFIG_SYS_DDR_BASE + size)); size += bank_size; debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20); @@ -145,7 +145,7 @@ int checkboard (void) volatile immap_t * immr; u32 w, f; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { printf("PCI: NOT in host mode..?!\n"); return 0; @@ -193,9 +193,9 @@ static int detect_num_flash_banks(void) tqm834x_num_flash_banks = 2; /* assume two banks */ /* Get bank 1 and 2 information */ - bank1_size = flash_get_size(CFG_FLASH_BASE, 0); + bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0); debug("Bank1 size: %lu\n", bank1_size); - bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1); + bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1); debug("Bank2 size: %lu\n", bank2_size); total_size = bank1_size + bank2_size; @@ -203,8 +203,8 @@ static int detect_num_flash_banks(void) /* Seems like we've got bank 2, but maybe it's mirrored 1 */ /* Set the base addresses */ - bank1_base = (FPWV *) (CFG_FLASH_BASE); - bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size); + bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE); + bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size); /* Put bank 2 into CFI command mode and read */ bank2_base[0x55] = 0x00980098; @@ -253,9 +253,9 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); /* set OR0 and BR0 */ - im->lbus.bank[0].or = CFG_OR_TIMING_FLASH | + im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH | (-(total_size) & OR_GPCM_AM); - im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) | + im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) | (BR_MS_GPCM | BR_PS_32 | BR_V); return (0); diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index de3ea00..fc92cd8 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -66,20 +66,20 @@ #endif struct law_entry law_table[] = { - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #ifdef CONFIG_PCIE1 - SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), #else /* !CONFIG_PCIE1 */ - SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) - SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ #ifdef CONFIG_PCIE1 - SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), #endif /* CONFIG_PCIE */ }; diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c index 9c5c12c..dea652d 100644 --- a/board/tqc/tqm85xx/nand.c +++ b/board/tqc/tqm85xx/nand.c @@ -41,10 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; extern uint get_lbc_clock (void); /* index of UPM RAM array run pattern for NAND command cycle */ -#define CFG_NAN_UPM_WRITE_CMD_OFS 0x08 +#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08 /* index of UPM RAM array run pattern for NAND address cycle */ -#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10 +#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10 /* Structure for table with supported UPM timings */ struct upm_freq { @@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt; */ static void upmb_write (u_char addr, ulong val) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); out_be32 (&lbc->mdr, val); @@ -385,7 +385,7 @@ static void upmb_write (u_char addr, ulong val) MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ - out_8 ((void __iomem *)CFG_NAND0_BASE, 0); + out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0); clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); } @@ -396,11 +396,11 @@ static void upmb_write (u_char addr, ulong val) static void nand_upm_setup (volatile ccsr_lbc_t *lbc) { uint i; - uint or3 = CFG_OR3_PRELIM; + uint or3 = CONFIG_SYS_OR3_PRELIM; uint clock = get_lbc_clock (); out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ - out_be32 (&lbc->br3, CFG_BR3_PRELIM); + out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM); /* * Search appropriate UPM table for bus clock. @@ -455,7 +455,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip) int board_nand_init (struct nand_chip *nand) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); if (!nand_upm_patt) nand_upm_setup (lbc); diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 33bc407..783b280 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -66,9 +66,9 @@ int cas_latency (void); long int sdram_setup (int casl) { int i; - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); #ifdef CONFIG_TQM8548 - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #else /* !CONFIG_TQM8548 */ unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; @@ -296,7 +296,7 @@ phys_size_t initdram (int board_type) * This DLL-Override only used on TQM8540 and TQM8560 */ { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int i, x; x = 10; @@ -336,11 +336,11 @@ phys_size_t initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf ("SDRAM test phase 1:\n"); diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 380448a..16b102d 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -28,19 +28,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024, - CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024, - CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024, - CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -50,11 +50,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf8000000 128M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000, - CFG_FLASH_BASE + 0x4000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000, + CONFIG_SYS_FLASH_BASE + 0x4000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,8 +70,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, - CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M PCI express MEM First half */ - SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M PCI express MEM Second half */ - SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000, - CFG_PCIE1_MEM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000, + CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), #else /* !CONFIG_PCIE */ @@ -97,7 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -105,8 +105,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000, - CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), #endif /* CONFIG_PCIE */ @@ -117,7 +117,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe2000000 16M PCI1 IO * 0xe3000000 16M CAN and NAND Flash */ - SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, - CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), @@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 9: 16M Non-cacheable, guarded * 0xef000000 16M PCI express IO */ - SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif /* CONFIG_PCIE */ @@ -154,19 +154,19 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xc0000000 1G FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000, - CFG_FLASH_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000, + CONFIG_SYS_FLASH_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000, - CFG_FLASH_BASE + 0x20000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000, + CONFIG_SYS_FLASH_BASE + 0x20000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000, - CFG_FLASH_BASE + 0x30000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000, + CONFIG_SYS_FLASH_BASE + 0x30000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 0, BOOKE_PAGESZ_256M, 1), @@ -174,7 +174,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -182,8 +182,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, - CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), @@ -192,7 +192,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 256M Non-cacheable, guarded * 0xc0000000 256M PCI express MEM First half */ - SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), #else /* !CONFIG_PCIE */ @@ -200,7 +200,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 256M Non-cacheable, guarded * 0xb0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), @@ -212,7 +212,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xa2000000 16M PCI1 IO * 0xa3000000 16M CAN and NAND Flash */ - SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1), @@ -223,12 +223,12 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, - CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_256M, 1), @@ -237,7 +237,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 10: 16M Non-cacheable, guarded * 0xaf000000 16M PCI express IO */ - SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif /* CONFIG_PCIE */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 5314d33..f69de95 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -269,7 +269,7 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -282,9 +282,9 @@ int misc_init_r (void) */ if (flash_info[0].size > 0) { memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | - (CFG_OR1_PRELIM & 0x00007fff); + (CONFIG_SYS_OR1_PRELIM & 0x00007fff); memctl->br1 = gd->bd->bi_flashstart | - (CFG_BR1_PRELIM & 0x00007fff); + (CONFIG_SYS_BR1_PRELIM & 0x00007fff); /* * Re-check to get correct base address for bank 1 */ @@ -298,9 +298,9 @@ int misc_init_r (void) * If bank 1 is equipped, bank 0 is mapped after bank 1 */ memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | - (CFG_OR0_PRELIM & 0x00007fff); + (CONFIG_SYS_OR0_PRELIM & 0x00007fff); memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | - (CFG_BR0_PRELIM & 0x00007fff); + (CONFIG_SYS_BR0_PRELIM & 0x00007fff); /* * Re-check to get correct base address for bank 0 */ @@ -311,26 +311,26 @@ int misc_init_r (void) */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); #ifdef CONFIG_ENV_ADDR_REDUND /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); #endif return 0; @@ -342,7 +342,7 @@ int misc_init_r (void) */ static void upmc_write (u_char addr, uint val) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); out_be32 (&lbc->mdr, val); @@ -350,7 +350,7 @@ static void upmc_write (u_char addr, uint val) MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ - out_8 ((void __iomem *)CFG_CAN_BASE, 0); + out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); /* normal operation */ clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); @@ -359,7 +359,7 @@ static void upmc_write (u_char addr, uint val) uint get_lbc_clock (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; ulong clkdiv = lbc->lcrr & 0x0f; @@ -376,7 +376,7 @@ uint get_lbc_clock (void) return sys_info.freqSystemBus / clkdiv; } - puts("Invalid clock divider value in CFG_LBC_LCRR\n"); + puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n"); return 0; } @@ -386,8 +386,8 @@ uint get_lbc_clock (void) */ void local_bus_init (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 @@ -418,7 +418,7 @@ void local_bus_init (void) gur->lbiuiplldcr1 = dummy; } - lcrr = CFG_LBC_LCRR; + lcrr = CONFIG_SYS_LBC_LCRR; /* * Local Bus Clock > 83.3 MHz. According to timing @@ -464,12 +464,12 @@ void local_bus_init (void) */ if (lbc_mhz < 66) { - lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ } else if (lbc_mhz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -484,7 +484,7 @@ void local_bus_init (void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay (200); /* @@ -503,10 +503,10 @@ void local_bus_init (void) * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) - out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD); + out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else - out_be32 (&lbc->or2, CFG_OR2_CAN); - out_be32 (&lbc->br2, CFG_BR2_CAN); + out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); + out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); @@ -548,10 +548,10 @@ static struct pci_controller pcie1_hose; static inline void init_pci1(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci1_hose; @@ -579,24 +579,24 @@ static inline void init_pci1(void) /* inbound */ pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region (hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region (hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; @@ -636,11 +636,11 @@ static inline void init_pci1(void) static inline void init_pcie1(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || @@ -661,23 +661,23 @@ static inline void init_pcie1(void) /* inbound */ pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region (hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region (hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c index 143f368..d269902 100644 --- a/board/tqc/tqm8xx/load_sernum_ethaddr.c +++ b/board/tqc/tqm8xx/load_sernum_ethaddr.c @@ -52,21 +52,21 @@ void load_sernum_ethaddr (void) { unsigned char *hwi; - unsigned char serial [CFG_HWINFO_SIZE]; - unsigned char ethaddr[CFG_HWINFO_SIZE]; + unsigned char serial [CONFIG_SYS_HWINFO_SIZE]; + unsigned char ethaddr[CONFIG_SYS_HWINFO_SIZE]; unsigned short ih, is, ie, part; - hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET); + hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); ih = is = ie = 0; - if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { return; } part = 1; /* copy serial # / MAC address */ - while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) { + while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) { if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ return; } diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 5537d04..9a0f3a0 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -139,7 +139,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9, size10; long int size_b0 = 0; @@ -154,7 +154,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; /* * The following value is used as an address (i.e. opcode) for @@ -176,19 +176,19 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; } #endif /* CONFIG_CAN_DRIVER */ - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -219,7 +219,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); udelay (1000); @@ -227,30 +227,30 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); udelay(1000); -#if defined(CFG_MAMR_10COL) +#if defined(CONFIG_SYS_MAMR_10COL) /* * try 10 column mode */ - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); #else size10 = 0; -#endif /* CFG_MAMR_10COL */ +#endif /* CONFIG_SYS_MAMR_10COL */ if ((size8 < size10) && (size9 < size10)) { size_b0 = size10; } else if ((size8 < size9) && (size10 < size9)) { size_b0 = size9; - memctl->memc_mamr = CFG_MAMR_9COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; udelay (500); } else { size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); } debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); @@ -281,7 +281,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -290,15 +290,15 @@ phys_size_t initdram (int board_type) */ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* * Position Bank 0 immediately above Bank 1 */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { unsigned long reg; @@ -312,24 +312,24 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* * Position Bank 1 immediately above Bank 0 */ memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { unsigned long reg; @@ -345,7 +345,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -356,8 +356,8 @@ phys_size_t initdram (int board_type) /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; /* Initialize MBMR */ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ @@ -397,8 +397,8 @@ phys_size_t initdram (int board_type) #ifdef CONFIG_ISP1362_USB /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CFG_OR5_ISP1362; - memctl->memc_br5 = CFG_BR5_ISP1362; + memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362; + memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362; #endif /* CONFIG_ISP1362_USB */ return (size_b0 + size_b1); } @@ -415,7 +415,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -451,14 +451,14 @@ int board_early_init_r (void) #ifdef CONFIG_MISC_INIT_R int misc_init_r (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ int scy, trlx, flash_or_timing, clk_diff; - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { trlx = OR_TRLX; scy *= 2; } else { @@ -498,29 +498,29 @@ int misc_init_r (void) scy = 1; flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); + (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); memctl->memc_or0 = flash_or_timing | (-flash_info[0].size & OR_AM_MSK); #else memctl->memc_or0 = - CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); + CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); #endif - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; debug ("## BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); if (flash_info[1].size) { -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ memctl->memc_or1 = flash_or_timing | (-flash_info[1].size & 0xFFFF8000); #else - memctl->memc_or1 = CFG_OR_TIMING_FLASH | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[1].size & 0xFFFF8000); #endif memctl->memc_br1 = - ((CFG_FLASH_BASE + + ((CONFIG_SYS_FLASH_BASE + flash_info[0]. size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; @@ -557,7 +557,7 @@ int misc_init_r (void) # ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* We have one led for both pcmcia slots */ if (status) { /* led on */ -- cgit v1.1 From 8ed44d91c8122d00368523b0b746691c895d3b3c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Oct 2008 02:35:50 +0200 Subject: Cleanup: fix "MHz" spelling Signed-off-by: Wolfgang Denk --- board/tqc/tqm85xx/tqm85xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index f69de95..1f309bb 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -458,8 +458,8 @@ void local_bus_init (void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ -- cgit v1.1 From 055b12f2ffd7c34eea7e983a0588b24f2e69e0e3 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Oct 2008 21:54:30 +0200 Subject: TQM8260: environment in flash instead EEPROM, baudrate 115k Several customers have reported problems with the environment in EEPROM, including corrupted content after board reset. Probably the code to prevent I2C Enge Conditions is not working sufficiently. We move the environment to flash now, which allows to have a backup copy plus gives much faster boot times. Also, change the default console initialization to 115200 bps as used on most other boards. Signed-off-by: Wolfgang Denk --- board/tqc/tqm8260/flash.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c index 4a6d538..cabc818 100644 --- a/board/tqc/tqm8260/flash.c +++ b/board/tqc/tqm8260/flash.c @@ -204,7 +204,8 @@ unsigned long flash_init (void) #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) @@ -213,7 +214,15 @@ unsigned long flash_init (void) # endif flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, + &flash_info[0]); +#endif + +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND) + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + &flash_info[0]); #endif return (size_b0); -- cgit v1.1 From 2dba0dea98c0dee1799ffd6fd6eb541645dbbd98 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 21 Oct 2008 08:28:33 -0500 Subject: 85xx: Convert all fsl_pci_init users to new APIs Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala Signed-off-by: Andrew Fleming-AFLEMING --- board/tqc/tqm85xx/tqm85xx.c | 58 ++++++++++++++++----------------------------- 1 file changed, 20 insertions(+), 38 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 1f309bb..97d49ea 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -538,6 +538,9 @@ void local_bus_init (void) */ static int first_free_busno; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) static struct pci_controller pci1_hose; #endif /* CONFIG_PCI || CONFIG_PCI1 */ @@ -552,8 +555,8 @@ static inline void init_pci1(void) #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; /* PORDEVSR[15] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; @@ -578,28 +581,23 @@ static inline void init_pci1(void) /* inbound */ - pci_set_region (hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region (hose->regions + 1, + pci_set_region (r++, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region (hose->regions + 2, + pci_set_region (r++, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect (hose, (int)&pci->cfg_addr, @@ -641,10 +639,10 @@ static inline void init_pcie1(void) uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; @@ -660,27 +658,23 @@ static inline void init_pcie1(void) puts ("\n"); /* inbound */ - pci_set_region (hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region (hose->regions + 1, + pci_set_region (r++, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region (hose->regions + 2, + pci_set_region (r++, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, @@ -707,31 +701,19 @@ void pci_init_board (void) } #ifdef CONFIG_OF_BOARD_SETUP +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + void ft_board_setup (void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup (blob, bd); - node = fdt_path_offset (blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) - path = fdt_getprop (blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); - } -#endif /* CONFIG_PCI || CONFIG_PCI1 */ + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif #ifdef CONFIG_PCIE1 - path = fdt_getprop (blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); - } -#endif /* CONFIG_PCIE1 */ - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); +#endif } #endif /* CONFIG_OF_BOARD_SETUP */ -- cgit v1.1 From 6b59e03e0237a40a2305ea385defdfd92000978b Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 1 Sep 2008 16:21:22 +0200 Subject: lcd: Let the board code show board-specific info The information displayed when CONFIG_LCD_INFO is set is inherently board-specific, so it should be done by the board code. The current code dealing with this only handles two cases, and is already a horrible mess of #ifdeffery. Yes, this duplicates some code, but it also allows boards to print more board-specific information; this used to be very difficult. Signed-off-by: Haavard Skinnemoen Signed-off-by: Anatolij Gustschin --- board/tqc/tqm8xx/tqm8xx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'board/tqc') diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 9a0f3a0..928afed 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -568,6 +568,32 @@ void ide_led (uchar led, uchar status) } # endif +#ifdef CONFIG_LCD_INFO +#include + +void lcd_show_board_info(void) +{ + lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, __DATE__, __TIME__); + lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); + lcd_printf (" Wolfgang DENK, wd@denx.de\n"); +#ifdef CONFIG_LCD_INFO_BELOW_LOGO + lcd_printf ("MPC823 CPU at %s MHz\n", + strmhz(temp, gd->cpu_clk)); + lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3, + info, strlen(info)); + lcd_printf (" %ld MB RAM, %ld MB Flash\n", + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#else + /* leave one blank line */ + lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", + strmhz(temp, gd->cpu_clk), + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ +} +#endif /* CONFIG_LCD_INFO */ + /* ---------------------------------------------------------------------------- */ /* TK885D specific initializaion */ /* ---------------------------------------------------------------------------- */ -- cgit v1.1 From 3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 2 Nov 2008 16:14:22 +0100 Subject: Coding Style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk --- board/tqc/tqm85xx/tqm85xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 97d49ea..3a828ed 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -23,7 +23,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -702,7 +702,7 @@ void pci_init_board (void) #ifdef CONFIG_OF_BOARD_SETUP extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose); + struct pci_controller *hose); void ft_board_setup (void *blob, bd_t *bd) { -- cgit v1.1 From 60c68d9c1c6d18ce02c862a05718fd94f97c13d0 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 31 Oct 2008 01:13:37 +0100 Subject: TQM8260: use CFI flash driver instead of custom driver. Signed-off-by: Wolfgang Denk --- board/tqc/tqm8260/Makefile | 2 +- board/tqc/tqm8260/flash.c | 497 --------------------------------------------- 2 files changed, 1 insertion(+), 498 deletions(-) delete mode 100644 board/tqc/tqm8260/flash.c (limited to 'board/tqc') diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile index 61221fd..94ba1e9 100644 --- a/board/tqc/tqm8260/Makefile +++ b/board/tqc/tqm8260/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o +COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c deleted file mode 100644 index cabc818..0000000 --- a/board/tqc/tqm8260/flash.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD devices on the TQM8260 board - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - V_ULONG (flash_info[0].start[0]) = 0x00F000F0; - V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG (baseaddr + 4); - - switch ((int) flashtest_h) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG (baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - } else { - switch (flashtest_h) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; /* 4 * 8 MB = 32 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* no or unknown flash */ - } - } - - if (flashtest_h == AMD_ID_LV640U) { - - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - - } else if (info->flash_id & FLASH_BTYPE) { - - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - - } else { - - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG (info->start[i] + 16) & 0x00010001) || - (V_ULONG (info->start[i] + 20) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, - &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG (info->start[sect]) = 0x00300030; - V_ULONG (info->start[sect] + 4) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || - (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start, cl, ch; - int flag, i; - - for (ch = 0, i = 0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl = 0, i = 0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & ch) != ch - || (*((vu_long *) (dest + 4)) & cl) != cl) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest) = ch; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest + 4) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} -- cgit v1.1 From 9b827cf1720acda2473afa516956eab6f7cca9a1 Mon Sep 17 00:00:00 2001 From: Selvamuthukumar Date: Thu, 16 Oct 2008 22:54:03 +0530 Subject: Align end of bss by 4 bytes Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar Signed-off-by: Wolfgang Denk --- board/tqc/tqm85xx/u-boot.lds | 1 + board/tqc/tqm8xx/u-boot.lds | 1 + 2 files changed, 2 insertions(+) (limited to 'board/tqc') diff --git a/board/tqc/tqm85xx/u-boot.lds b/board/tqc/tqm85xx/u-boot.lds index 8cb551a..b1637a5 100644 --- a/board/tqc/tqm85xx/u-boot.lds +++ b/board/tqc/tqm85xx/u-boot.lds @@ -141,6 +141,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 26aa5d6..5af36c9 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); -- cgit v1.1 From 9427ccde0355a2ebf47454e8e1be59f5b9864e08 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 1 Dec 2008 13:47:12 -0600 Subject: 85xx: Add PORDEVSR_PCI1 define Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser Signed-off-by: Andy Fleming --- board/tqc/tqm85xx/tqm85xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 3a828ed..73f1d01 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -610,7 +610,7 @@ static inline void init_pci1(void) first_free_busno = hose->last_busno + 1; #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; -- cgit v1.1 From 1450c4a6682378567030414a9f1198c39b7730c7 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 3 Nov 2008 15:30:34 +0100 Subject: lwmon, tqm8xx: Fix build errors Commit 6b59e03e0237a40a2305ea385defdfd92000978b lcd: Let the board code show board-specific info introduced some bugs which prevent U-Boot building for lwmon board if CONFIG_LCD_INFO_BELOW_LOGO will be defined in the board configuration. Also "LCD enabled" building for TQM823L doesn't work since this commit. This patch fixes above-mentioned issues. Signed-off-by: Anatolij Gustschin --- board/tqc/tqm8xx/tqm8xx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 928afed..d8a19a4 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -570,17 +570,18 @@ void ide_led (uchar led, uchar status) #ifdef CONFIG_LCD_INFO #include +#include void lcd_show_board_info(void) { + char temp[32]; + lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, __DATE__, __TIME__); lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); lcd_printf (" Wolfgang DENK, wd@denx.de\n"); #ifdef CONFIG_LCD_INFO_BELOW_LOGO lcd_printf ("MPC823 CPU at %s MHz\n", strmhz(temp, gd->cpu_clk)); - lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3, - info, strlen(info)); lcd_printf (" %ld MB RAM, %ld MB Flash\n", gd->ram_size >> 20, gd->bd->bi_flashsize >> 20 ); -- cgit v1.1 From 561858ee7d0274c3e89dc98d4d0698cb6fcf6fd9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 3 Nov 2008 09:30:59 -0600 Subject: Update U-Boot's build timestamp on every compile Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser --- board/tqc/tqm8xx/tqm8xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board/tqc') diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index d8a19a4..e065d69 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -571,12 +571,13 @@ void ide_led (uchar led, uchar status) #ifdef CONFIG_LCD_INFO #include #include +#include void lcd_show_board_info(void) { char temp[32]; - lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, __DATE__, __TIME__); + lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); lcd_printf (" Wolfgang DENK, wd@denx.de\n"); #ifdef CONFIG_LCD_INFO_BELOW_LOGO -- cgit v1.1